Renesas HD49335HNP, HD49335NP User Manual

HD49335NP/HNP

CDS/PGA & 10-bit A/D TG Converter

REJ03F0097-0100Z

Rev.1.0

Feb.12.2004

Description

The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip.

There are address map and timing generator charts besides this specification. May be contacted to our sales department
if examining the details.

Functions

• Correlated double sampling

• PGA

• Serial interface control

• 10-bit ADC

• Timing gener at or

• Operates using only the 3 V voltage

• Corresponds to switching mode of power dissipation and operating frequency

Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HNP)
Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335NP)

• ADC direct input mode

• QFN 64-pin package

Features

• Suppresses low-frequency noise, which output from CCD by the correlated double sampling.

• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and

registers.

• High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.

• PGA, pulse timing, standby mode, etc., is achieved via a serial interface.

• High precision is provided by a 10-bit-resolution A/D converter.

• Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization

(wave pattern). It is patented by Renesas.

• Timing gene rator generates the all of pulse which are needed for CCD driving.

Rev.1.0, Feb.12.2004, page 1 of 29

HD49335NP/HNP

Pin Arrangement

VRM

VRT

VRB

BIAS

ADC_in

3

SS

AVSSDV

STROB

SUB_PD

SUB_SW

XSUB

CH4

CH3

CH2

CH1

XV4

Pin Description

AV

DD

BLKC

CDS_in

AV

DD

BLKFB

BLKSH

AV

SS

Test2
Test1

DLL_C

DV

DD

MON

41cont

CS

SDATA

SCK

48 47 3946 45 44 43 42 41 40 38 36 35 3437

49
50
51
52
53
54
55
56
57
58

1

59
60
61
62
63
64

12 103 4 5 6 7 8 9 11 12 13 14 15

ID

D0D1D2D3D4D5D6D7D8

1,2

SS

DV

(Top view)

D9

2

DD

DV

3

SS

DV

33

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

16

HD_in

CLK_in

XV3
XV2
XV1

3

DV

DD

4

DV

DD

1/4clk_o
H2A

4

DV

SS

4

DV

SS

1/2clk_o
H1A

4

DV

DD

3

DV

DD

RG
Reset
VD_in

Pin No. Symbol Description

1 ID Odd/even number line detecting pulse output pin O D 2 mA/10 pF
2 DVSS1,2 CDS Digital ground + ADC output buffer ground (0 V) — D
3 to 12 D0 to D9 Digital output (D0; LSB, D9; MSB) O D 2 mA/10 pF
13 DVDD2 ADC output buffer power supply (3 V) — D
14 DVSS3 General ground for TG (0 V) — D
15 CLK_in CLK input (max 72 MHz) I D
16 HD_in HD input I/O D
17 VD_in VD input I/O D
18 Reset Hardware reset (for DLL reset) I D Schmitt trigger
19 RG Reset gate pulse output O D 3 mA/10 pF
20 DVDD3 General power supply for TG (3 V) — D
21 DVDD4 H1 buffer power supply (3 V) — D
22 H1A H.CCD transfer pulse output-1A O D 30 mA/165 pF
23 1/2clk_o CLK_in 2 divided output. 3 divided out put at 3 divided m ode O D 2 mA/10 pF
24 DVSS4 H1 buffer ground (0 V) — D
25 DVSS4 H1 buffer ground (0 V) — D
26 H2A H.CCD transfer pulse output-2A O D 30 mA/165 pF
27 1/4clk_o CLK_in 4 divided output. 6 divided out put at 3 divided m ode O D 2 mA/10 pF
28 DVDD4 H2 buffer power supply (3 V) — D
29 DVDD3 General power supply for TG (3 V) — D

I/O

Analog(A) or
Digital(D)

Remarks

Rev.1.0, Feb.12.2004, page 2 of 29

HD49335NP/HNP

Pin Description (cont.)

Pin No. Symbol Description

30 XV1 V.CCD transfer pulse output-1 O D 2 mA/10 pF
31 XV2 V.CCD transfer pulse output-2 O D 2 mA/10 pF
32 XV3 V.CCD transfer pulse output-3 O D 2 mA/10 pF
33 XV4 V.CCD transfer pulse output-4 O D 2 mA/10 pF
34 CH1 Read out pulse output-1 O D 2 mA/10 pF
35 CH2 Read out pulse output-2 O D 2 mA/10 pF
36 CH3 Read out pulse output-3 O D 2 mA/10 pF
37 CH4 Read out pulse output-4/XV6 at stripe mode O D 2 mA/10 pF
38 XSUB Pulse output for electronic shutter O D 2 mA/10 pF
39 SUB_SW SUB voltage control output-1. ADCK input I/O D 2 mA/10 pF
40 SUB_PD SUB voltage control output-2/ XV5 at stripe mode O D 2 mA/10 pF
41 STROB Flash control output. Input Vgate at Hi of pin 61 I/O D 2 mA/10 pF
42 DVSS3 General ground for TG (0 V) — D
43 AVSS Analog ground (0 V) — A
44 ADC_in AD converter input pin I A
45 BIAS Bias standard resistance — A
46 VRB ADC bottom standard voltage (0.1 µF for GND) — A
47 VRT ADC top standard voltage (0.1 µF for GND) — A
48 VRM ADC middle standard voltage (0.1 µF for GND) — A
49 AVDD Analog power supply (3 V) — A
50 BLKC Black level C pin (1000 pF for GND) — A
51 CDS_in CDS input pin I A
52 AVDD Analog power supply (3 V) — A
53 BLKFB Black level FB pin (1 µF between BLKFB and BLKSH) I A
54 BLKSH Black level S/H pin O A
55 AVSS Analog ground (0 V) — A
56 Test2

57 Test1 L: Slave mode, H: Master mode I D
58 DLL_C Analog delay DLL external C pin (100 pF for GND) O A
59 DVDD1 Digital power supply (3 V) CDS, PAG, ADC part — D
60 MON Pulse monitor (SP1, SP2, ADCK, OBP, CPDM, PBLK input) O D 2 mA/10 pF
61 41cont

62 CS Serial data CS at CDS part I D
63 SDATA Input serial data I D
64 SCK Input serial clock I D

H: Normal operation, L: CDS single operation mode
Input 36; PBLK at testing, Input 37; OBP, Input 38; CPDM,
Input 39; ADCK, Input 40; SP2, Input 41; SP1

Input STROB = pin 41, Input SUB_SW = pin 39 at Low
Input Vgate = pin 41, Input ADCK = pin 39 at Hi

Analog(A) or

I/O

Digital(D)

I D

I D

Remarks

Rev.1.0, Feb.12.2004, page 3 of 29

HD49335NP/HNP

A

Input/Output Equivalent Circuit

Pin Name Equivalent Circuit

Digital output

Digital input CLK_in, HD_in, VD_in,

Analog

D0 to D9, HD_in, VD_in,
H1A, H2A, 1/2clk_o,
1/4clk_o, 41cont,
SUB_SW, SUB_PD

ID, RG, MON, XV1 to XV4,
CH1 to CH4, XSUB

ADCLK, OBP, SPBLK,
SPSIG, CS, SCK, SDATA,
PBLK, OEB, Reset, Test1,
Test2, SUB_SW, STROB

CDS_in

DIN

ENABLE

DIN

Digital
input

Note: Only OEB is pulled down to about 70 kΩ.

AV

DD

CDS_in

DV

DV

DD

DD

Digital
output

*1

DV

DD

Digital
output

Internally
connected
to VRT

ADC_in

DC_in

AV

DD

Internally
connected
to VRT

BLKSH, BLKFB, BLKC

AV

DD

VRT, VRM, VRB

BLKFB

+

−

VRT

+

−

+

−

VRB

AV

BLKSH

BLKC

VRM

DD

+

−

BIAS

AV

DD

BIAS

Rev.1.0, Feb.12.2004, page 4 of 29

HD49335NP/HNP

Block Diagram

XSUB

CH4

CH3

CH2

CH1

XV4

XV3

XV2

XV1

1/4clk_o

H2A

1/2clk_o

H1A

RG

VD_in

HD_in

CLK_in

AVDDDV

1 to 4

DD

SUB_SW

SUB_PD

STROB

ADC_in

CDS_in

BLKSH

BLKC

BLKFB

CDS

DC offset

compensation

circuit

ID

MON

DLL_C

PBLK

CPDM

PGA

Serial

interface

SCK

SDATA

OBP

CS

DLL

SP2

ADCLK

Bias

generator

SP1

BIAS

10bit
ADC

VRT

Timing

generator

VRB

VRM

AV

SS

DV

SS

Reset

D9

D8

D7

D6

D5

D4

D3

Output latch circuit

D2

D1

D0

1 to 4

Rev.1.0, Feb.12.2004, page 5 of 29

HD49335NP/HNP

Internal Functions

Functional Description

• CDS input
 CCD low-frequency noise is suppressed by CDS (correlated double sampling).
 The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *
 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *

• ADC input
 The center level of the input signal is clamped at 512 LSB (Typ).
 Gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57

times (–4.86 dB) to 5.14 times (14.22 dB). *

2

• Automatic offset calibration of PGA and ADC

• DC offset compensation feedback for CCD and CDS

• Pre-blanking
 Digital output is fixed at clamp level

• Digital outputs enable function

Note: 1. It is not covered by warranty when 14LSB settings

2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

Operating Description

1

2

Figure 1 shows CDS/PGA + ADC function block.

C3

ADC_in

CDS
AMP

BLKSH

Gain setting

(register)

Current

DAC

BLKC

C4

PG
AMP

DAC

Clamp data

(register)

10bit
ADC

D0 to D9

Offset

calibration

logic

DC offset
feedback

logic

OBP

CDS_in

SP1

SP1

VRT

BLKFB

SP2

C2

C1

SH
AMP

Figure 1 CDS/PGA Functional Block Diagram

1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The

black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SP2 pulse, and then provided to CDSAMP (see figure 1).
The difference between these two signal levels is extracted by the CDSAMP, which also operates as a
programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK
period, the above sampling and bias operation are paused.

2. PGA Circuit
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain

using 8 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 255.

In CDSIN mode: Gain = (–2.36 dB + 0.033 dB) × N (LOG linear).
In ADCIN mode: Gain = (0.57 times + 0.001784 times) × N (linear).
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

Rev.1.0, Feb.12.2004, page 6 of 29

HD49335NP/HNP

3. Automatic Offset Calibration Function and Black-Level Cla mp Data Settings
The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data
(14 LSB to 76 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).

4. DC Offset Co mpe nsation Feedback Function
Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is
the one cycle of the OBP.

∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example: When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039

When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8
times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain
(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.
The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 16 LSB, the high-speed lead-in operation continues,
and when the offset error is 16 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. (Refer to table 2.)

Table 1 Loop Gain Multiplication Factor during

High-Speed Lead-In Operation

HGain-Nsel

(register settings)

[0]

L
H
L
H

[1]

L

L
H
H

Multiplication

Factor N

4

8
16
32

Table 2 High-Speed Lead-In Operation

Cancellation Time

HGstop-Hsel

(register settings)

[0]

L

H

L

H

[1]

L
L
H
H

Cancellation

Time

1 H
2 H
4 H
8 H

5. Pre-Blanking Function
During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (14 to 76 LSB).

Rev.1.0, Feb.12.2004, page 7 of 29

HD49335NP/HNP

6. ADC Digital Outp ut Control Function
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the cod es.

Table 3 ADC Digital Output Functions

ADC Digital Output

STBYD9TEST0

H
L

Note: 1. STBY, TEST, LINV, and MINV are set by register.

TEST1

LINV

X

X

X
L

H

L

L

L
H
H
X
L

H

L
H
H
X
L

X

L
H
H

MINV

X
L
H
L
H
X
L
H
L
H
X
L
H
L
H

PBLK

Hi-Z

X

Same as in table 4.

L

D9 is inverted in table 4.

L

D8 to D0 are inverted in table 4.

L

D9 to D0 are inverted in table 4.

L

Output code is set up to Clamp Level.

H

Same as in table 5.

L

D9 is inverted in table 5.

L

D8 to D0 are inverted in table 5.

L

D9 to D0 are inverted in table 5.

L

Output code is set up to Clamp Level.

H
X
X
X
X

H

L

L

H

L

H

L

H

H

L

H

L

D0D1D2D3D4D5D6D7D8

L

H

L

H

L

L

H

L

H

L

H

L

H

H

L

H

L

H

L

H

H

L

H

H

L

H

Operating Mode

Low-power wait state
Normal operation

Pre-blanking
Normal operation

Pre-blanking

L

Test mode

L

Table 4 ADC Output Code (Binary)

Output Pin

Output
codes

Steps

3
4
5
6

511
512

1020
1021
1022
1023

Table 5 ADC Output Code (Gray)

Output Pin

Output
codes

Steps

3
4
5
6

511
512

1020
1021
1022
1023

D9

D9

D8

L
L
L
L

L
H

H
H
H
H

D8

L
L
L
L

L
H

H
H
H
H

D7

L
L
L
L

H
L

H
H
H
H

D7

L
L
L
L

H
H

L
L
L
L

D6

L
L
L
L

H
L

H
H
H
H

D6

L
L
L
L

L
L

L
L
L
L

D5

L
L
L
L

H
L

H
H
H
H

L
L
L
L

L
L

L
L
L
L

L
L
L
L

H
L

H
H
H
H

D5

L
L
L
L

L
L

L
L
L
L

D4

H

H
H
H
H

D4

D3

L
L
L
L

L

D3

L
L
L
L

L
L

L
L
L
L

D2

L
L
L
L

H
L

H
H
H
H

D2

L
L
L
L

L
L

L
L
L
L

D1

L
H
H
H

H
L

H
H
H
H

L
H
H
H

L
L

L
L
L
L

H
L
L
H

H
L

L
L
H
H

D1

H
H
H
L

L
L

H
H
L
L

D0

D0

H
L
H
L

H
L

L
H
L
H

L
L
H
H

L
L

L
H
H
L

Rev.1.0, Feb.12.2004, page 8 of 29

HD49335NP/HNP

7. Adjustment of Black-Level S/H Response Frequency Characteristics
The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the
register settings, as shown in tabl e 6.

Table 6 SHSW CR Time Constant Setting

SHSW-fsel (Register setting)

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

L

[1]

L

L

[2]

L

L

H

2.30 nsec
(69 MHz)

[3]

[0]

H

H

4.80 nsec
(33 MHz)

L

[1]

L

L

[2]

L

L

L

2.51 nsec
(63 MHz)

[3]

[0]

H

L

5.87 nsec
(27 MHz)

H

L

L

H

H

L

L

L

2.64 nsec
(60 MHz)

SHSW-fsel (Register setting)

[1]

[2]

[3]

[0]

[1]

H

L

H

H

H

6.60 nsec
(24 MHz)

[2]

L

2.93 nsec
(54 MHz)

[3]

[0]

H

L

8.80 nsec
(18 MHz)

L

[1]

L

H

[2]

H

L

H

3.11 nsec
(51 MHz)

[3]

[0]

H

H

10.6 nsec
(15 MHz)

L

[1]

L

H

[2]

H

L

L

3.52 nsec
(45 MHz)

[3]

[0]

H

L

17.6 nsec
(9 MHz)

H

[1]

H

H

[2]

H

L

CR Time Constant (Typ)
(cutoff frequency conversion)

CR Time Constant (Typ)
(cutoff frequency conversion)

2.20 nsec
(72 MHz)

[0]

L

4.40 nsec
(36 MHz)

[3]

[0]

L

H

3.77 nsec
(42 MHz)

[3]

[0]

H

H

26.4 nsec
(6 MHz)

[1]

H

[1]

H

[3]

[2]

H

L

[2]H[3]

H

The SHAMP frequency characteristics can be adjusted by changing the register settings

8.
and the C4 value of the external pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.

Recommendation value of C is 1000 pF

Table 7 SHAMP Frequency Characteristics Setting

SHA-fsel (Register setting)

LoPwr

(Register setting)

"Lo"

"Hi" 24 MHz

Note: Upper line

Middle line
Lower line

[0]

L

230 MHz

6800 pF

(240 pF)

100 MHz

10000 pF

(560 pF)

: SHAMP cutoff frequency (Typ)
: Standard value of C4 (maximum value is not defined)
: Minimum value of C4 (do not set below this value)

[1]

L

[0]

H

116 MHz

10000 pF

(270 pF)

49 MHz

15000 pF

(620 pF)

[1]

L

[0]

L

75 MHz

13000 pF

(300 pF)

32 MHz

22000 pF

(750 pF)

[1]

H

BLKC

31

[0]

C

H

56 MHz

18000 pF

(360 pF)

27000 pF

(820 pF)

[1]

H

Rev.1.0, Feb.12.2004, page 9 of 29