RENESAS HD404818 User Manual

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Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
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Renesas Technology Home Page: http://www.renesas.com

Renesas T echnology Corp.
Customer Support Dept.
April 1, 2003

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble ma y occur with them. Trouble with
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Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap .

Notes regarding these materials

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contained therein.

HD404818 Series

4-Bit Single-Chip Microcomputer

Preliminary

Rev. 2.0

Sept. 1998

Description

T he H D4 04 81 8 Se ri es of 4-bit single-chip HMCS400 series microcomputers provide high program
productivity. It incorporates a large size memory, LCD controller/driver, voltage comparator, and 32-kHz
watch oscillator circuit.

The HD404818 Series has both standard voltage versions and low voltage versions available. The standard
voltage versions operate at 4.0 V to 6.0 V (mask ROM version) and 4.0 V to 5.5 V (PROM version), while
the low voltage versions operate at 2.7 V to 6.0 V (mask ROM) and 3.0 V to 5.5 V (PROM). Low voltage
versions include an L in their product name.

Standard voltage versions: HD404812, HD404814, HD404816, HD404818, HD4074818

Low voltage versions: HD40L4812, HD40L4814, HD40L4816, HD40L4818, HD407L4818
The HD4074818 and HD407L4818, containing PROMs, are ZTAT microcomputers which can

dramatically shorten system development time and smoothly proceed from debugging to mass production.

ZTATTM : Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

• 2048-word × 10-bit ROM (HD404812, HD40L4812)

• 4096-word × 10-bit ROM (HD404814, HD40L4814)

• 6144-word × 10-bit ROM (HD404816, HD40L4816)

• 8192-word × 10-bit ROM (HD404818, HD40L4818, HD4074818, HD407L4818)

• 1184-digit × 4-bit RAM

• 30 I/O pins, including 10 high-current output pins, all CMOS and programmable as I/O pull-up MOS

• LCD controller/driver (32 segments × 4 commons)

• Three timer/counters

• Clock-synchronous 8-bit serial interface

• Six interrupt sources
 Two by external sources
 Four by internal sources

HD404818 Series

2

• Subroutine stack up to 16 levels, including interrupts

• Instruction cycle time:
 1 µs (f

OSC

= 4 MHz for HD404812/HD404814/HD404816/HD404818/HD4074818)

 5 µs (f

OSC

= 800 kHz for HD40L4812/HD40L4814/HD40L4816/HD40L4818/HD407L4818)

• Four low-power dissipation modes
 Standby mode
 Stop mode
 Watch mode
 Subactive mode

• Internal oscillator:
 Main clock: Can be driven by ceramic oscillator, crystal oscillator, or external clock
 Subclock: 32.768-kHz crystal

• Voltage comparator (2 channels)

• Package
 80-pin plastic flat package (FP-80B, FP-80A)
 80-pin plastic thin flat package (TFP-80)

HD404818 Series

3

Ordering Information

Type

Supply
Voltage

Product
Name Model Name ROM (Word)

Clock
Frequency Package

Mask ROM Standard

(4.0 to 6.0 V)

HD404812 HD404812FS 2,048 4 FP-80B

HD404812H FP-80A
HD404812TF TFP-80

HD404814 HD404814FS 4,096 FP-80B

HD404814H FP-80A
HD404814TF TFP-80

HD404816 HD404816FS 6,144 FP-80B

HD404816H FP-80A
HD404816TF TFP-80

HD404818 HD404818FS 8,192 FP-80B

HD404818H FP-80A
HD404818TF TFP-80

Low-voltage
operation

HD40L4812 HD40L4812FS 2,048 0.8 FP-80B

(2.7 to 6.0 V) HD40L4812H FP-80A

HD40L4812TF TFP-80

HD40L4814 HD40L4814FS 4,096 FP-80B

HD40L4814H FP-80A
HD40L4814TF TFP-80

HD40L4816 HD40L4816FS 6,144 FP-80B

HD40L4816H FP-80A
HD40L4816TF TFP-80

HD40L4818 HD40L4818FS 8,192 FP-80B

HD40L4818H FP-80A
HD40L4818TF TFP-80

ZTAT Standard

(4.0 to 5.5 V)

HD4074818 HD4074818FS 8,192 4 FP-80B

HD4074818H FP-80A
HD4074818TF TFP-80

Low-voltage
operation

HD407L4818 HD407L4818FS 0.8 FP-80B

(3.0 to 5.5 V) HD407L4818H FP-80A

HD407L4818TF TFP-80

HD404818 Series

4

Pin Arrangement

D

RESET

OSC

OSC

VVV

COM4

V

NUMG

NUMO

NUMO

COM3

COM2

COM1

D

1

0

2

CC

321

R2R2R2

R3

SEG2

SEG3

SEG4

SEG5

TIMO/R3

INT /R3

INT /R3

SEG1

SEG6

SEG7

SEG8

R2

3

0

2

1

2

1

0

0

3

1

1

1
2
3
4
5
6
7
8
9
10
11
12

14

13

15

17

16

18

20

19

22

21

24

23

64
63
62

61
60

59
58
57
56
55
54
53

51

52

50

48

49

47

45

46

43

44

41

42

262728

29

343536

37

303132

33

383940

25

797877

76

717069

68

757473

72

676665

80

(top view)

SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9

D
D
D

VC /D
COMP0/D
COMP1/D

X1

TEST

X2

SCK/R0

GND

SI/R0

R0

SO/R0

R1

R1

R1
R1

2

4
5
6
7
8
9

10
11

12
13

0

1
2
3
0
1
2

3

ref

D

D

D
D

3

D

D

1
2
3
4
5
6
7
8
9
10
11
12

14

13

15

17

16

18

20

19

80797877767574737271706968676665646362

61

60
59
58
57
56
55
54
53
52
51
50
49

47

48

46

44

45

43

41

42

21222324252627282930313233343536373839

40

(top view)

DDD

RESET

VVV

OSC

V

COM4

COM3

D

3

2

321

2

NUMG

COM2

COM1

SEG32

SEG31

1

0

OSC

1

CC

NUMO

NUMO

R2R2R2

R3

SEG2

SEG3

SEG4

SEG5

TIMO/R3

INT /R3

INT /R3

SEG1

SEG6

SEG7

SEG8

R2

3

0

2

1

2

100

1

SEG9

SEG10

R1

R1

3

3

2

D
D
D
D
D

4
5
6
7
8
9

D

10

D

11

VC /D

ref

COMP0/D
COMP1/D

12
13

TEST

X1
X2

GND

SCK/R0

0

SI/R0

1

SO/R0

2

R0

3

R1

0

R1

1

SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11

FP-80B

TFP-80
FP-80A

HD404818 Series

5

Pin Description

Pin Number Pin Number
FP-80B FP-80A, TFP-80 Pin Name I/O FP-80B FP-80A, TFP-80 Pin Name I/O

179 D

2

I/O 31 29 R32/INT0I/O

280 D

3

I/O 32 30 R33/INT1I/O

31 D

4

I/O 33 31 SEG1 O

42 D

5

I/O 34 32 SEG2 O

53 D

6

I/O 35 33 SEG3 O

64 D

7

I/O 36 34 SEG4 O

75 D

8

I/O 37 35 SEG5 O

86 D

9

I/O 38 36 SEG6 O
97 D10I 39 37 SEG7 O
10 8 D11/VC

ref

I 40 38 SEG8 O
11 9 D12/COMP

0

I 41 39 SEG9 O
12 10 D13/COMP

1

I 42 40 SEG10 O
13 11 TEST I 43 41 SEG11 O
14 12 X1 I 44 42 SEG12 O
15 13 X2 O 45 43 SEG13 O
16 14 GND 46 44 SEG14 O
17 15 R00/SCK I/O 47 45 SEG15 O
18 16 R01/SI I/O 48 46 SEG16 O
19 17 R02/SO I/O 49 47 SEG17 O
20 18 R0

3

I/O 50 48 SEG18 O
21 19 R1

0

I/O 51 49 SEG19 O
22 20 R1

1

I/O 52 50 SEG20 O
23 21 R1

2

I/O 53 51 SEG21 O
24 22 R1

3

I/O 54 52 SEG22 O
25 23 R2

0

I/O 55 53 SEG23 O
26 24 R2

1

I/O 56 54 SEG24 O
27 25 R2

2

I/O 57 55 SEG25 O
28 26 R2

3

I/O 58 56 SEG26 O
29 27 R3

0

I/O 59 57 SEG27 O
30 28 R31/TIMO I/O 60 58 SEG28 O

HD404818 Series

6

Pin Number Pin Number
FP-80B FP-80A, TFP-80 Pin Name I/O FP-80B FP-80A, TFP-80 Pin Name I/O

61 59 SEG29 O 71 69 V

3

62 60 SEG30 O 72 70 NUMO
63 61 SEG31 O 73 71 NUMO
64 62 SEG32 O 74 72 NUMG
65 63 COM1 O 75 73 V

CC

66 64 COM2 O 76 74 OSC

1

I

67 65 COM3 O 77 75 OSC

2

O
68 66 COM4 O 78 76 RESET I
69 67 V

1

79 77 D

0

I/O
70 68 V

2

80 78 D

1

I/O
Note: I/O: Input/output pin, I: Input pin, O: Output pin, NUMO: Open, NUMG: GND

HD404818 Series

7

Pin Functions

Power Supply

VCC: Apply the VCC power supply voltage to this pin.

GND: Connect to ground.

TEST: For test purposes only. Connect it to VCC.

RESET: MCU reset pin. Refer to the Reset section for details.

NUMG: Non-user pin. Connect it to GND.

NUMO: Non-user pin. Do not connect it to any lines.

Oscillators

OSC1, OSC2: Internal oscillator input pins. They both can be connected to a crystal, ceramic resonator, or

external oscillator circuit. Refer to the Internal Oscillator Circuit section for details.

X1, X2: Watch oscillator 32-kHz crystal pins.

Ports

D0–D13 (D Port): Fourteen 1-bit I/O ports. D0 to D9 are I/O ports and D10 to D13 are input ports. D0–D9 are

high current output ports (15 mA max.). D11–D13 are also available as voltage comparators. Refer to the
Input/Output section for details.

R0–R3 (R Ports): 4-bit I/O ports. R00, R01, R02, R31, R32, and R33 are multiplexed with SCK, SI, SO,
TIMO, INT0, and INT1, respectively.

Interrupts

INT0, INT1: External interrupt pins. INT1 can be used as an external event input pin for timer B. INT0 and
INT1 are multiplexed with R32 and R33, respectively. For details, see the Interrupts section.

Serial Interface

SCK, SI, SO: The transmit clock I/O pin (SCK), serial data input pin (SI), and serial data output pin (SO)
are used for serial interface. SCK, SI, and SO are multiplexed with R00, R01, and R02, respectively. For
details, see the Serial Interface section.

Timer

TIMO: Variable duty-cycle pulse waveform output pin. See the Timer C section for details.

HD404818 Series

8

LCD Driver/Controller

V1, V2, V3: Power supply pins for the LCD driver. Since the LCD driving resistors are provided internally,

no lines should be connected to these pins. The voltage on each pin is VCC ≥ V1 ≥ V2 ≥ V3 ≥ GND. See the
Liquid Crystal Display section for details.

COM1 to COM4: Common signal output pins for the LCD display. See the Liquid Crystal Display section
for details.

SEG1 to SEG32: Segment signals output pins for the LCD display. See the Liquid Crystal Display section
for details.

Voltage Comparator

COMP0, COMP1, VC

ref

: Analog input pins for the voltage comparator. VC

ref

is used as a reference voltage

pin to input the threshold voltage of the analog input pin.

HD404818 Series

9

Block Diagram

Internal address bus

System control circuit

RAM

(1,184 4 bits)×

W (2 bits)

X (4 bits)

SPX (4 bits)

Y (4 bits)

SPY (4 bits)

CA

(1 bit)

ST

(1 bit)

A (4 bits)

B (4 bits)

SP (10 bits)

Instruction

decoder

PC (14 bits)

ROM
(2,048 × 10 bits)
(4,096 × 10 bits)
(6,144 × 10 bits)
(8,192 × 10 bits)

D port

ALU

CPU

INT

0

INT

1

Timer B

Timer C

TIMO

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

10

D

11

R0 port

R0

0

R0

1

R0

2

R0

3

R1 port

R1

0

R1

1

R1

2

R1

3

R2 port

R2

0

R2

1

R2

2

R2

3

R3 port

R3

0

R3

1

R3

2

R3

3

RESET

TEST

OSC

OSCX1X2

VCCGND

Timer A

External
interrupt

control
circuit

Internal data bus

Internal data bus

High­current
pins

LCD
driver
circuit

V

1

V

2

V

3

COM1
COM2
COM3
COM4

SEG1
SEG2
SEG3

SEG31
SEG32

VC

ref

Compa-

rator

Serial

interface

SI

SO

SCK

: Data bus
: Signal lines

1

2

COMP

0

COMP

1

D

12

D

13

HD404818 Series

10

Memory Map

ROM Memory Map

The ROM is described in the following paragraphs with the ROM memory map in figure 1.

0

15
16

63
64

4095
4096

8191
8192

16383

0

$000F

$0FFF
$1000

$1FFF
$2000

$3FFF

$0010

$003F
$0040

Vector address

Zero-page subroutine
(64 words)

Pattern
(4096 words)

Program

Not used

1
2

3
4

5
6

7
8
9

10
11
12

13
14
15

$0000

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007
$0008
$0009

$000A
$000B

$000C
$000D

$000E
$000F

JMPL instruction

(jump to reset routine)

JMPL instruction

(jump to INT routine)

0

JMPL instruction

(jump to timer A routine)

1

JMPL instruction

(jump to timer B routine)

JMPL instruction

(jump to timer C routine)

JMPL instruction

(jump to serial routine)

JMPL instruction

(jump to INT routine)

* HD404812, HD40L4812: 2048 words

HD404814, HD40L4814: 4096 words
HD404816, HD40L4816: 6144 words
HD404818, HD40L4818,
HD4074818, HD407L4818: 8192 words

*

Note:

Figure 1 ROM Memory Map

Vector Address Area ($0000 to $000F): Locations $0000 through $000F are reserved for JMPL

instructions to branch to the starting address of the initialization program and of the interrupt programs.
After reset or an interrupt routine, the program is executed from the vector address.

Zero-Page Subroutine Area ($0000 to $003F): Locations $0000 through $003F are reserved for
subroutines. The program sequence branches to subroutines by the CAL instruction.

Pattern Area ($0000 to $0FFF): Locations $0000 through $0FFF are reserved for ROM data. The P
instruction allows the MCU to reference ROM data as a pattern.

Program Area ($0000 to $07FF: HD404812, HD40L4812; $0000 to $0FFF: HD404814, HD40L4814;
$0000 to $17FF: HD404816, HD40L4816; $0000 to $1FFF: HD404818, HD40L4818, HD4074818,
HD407L4818): Used for program coding.

HD404818 Series

11

RAM Memory Map

The MCU also contains a 1,184-digit × 4-bit RAM as the data and stack area. In addition to these areas,
interrupt control bits and special function registers are mapped on the RAM memory space. The RAM
memory map (figure 2) is described in the following paragraphs.

Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt
control. It is accessible only by RAM bit manipulation instructions. However, the interrupt request flag
cannot be set by software. The RSP bit is used only to reset the stack pointer.

Special Function Registers Area ($004 to $01F, $024 to $03F): The special function registers are the
mode or data registers for the serial interface, timer/counters, LCD, and the data control registers for the
I/O ports. These registers are classified into three types: write-only, read-only, and read/write as shown in
figure 2.

The SEM/REM and SEMD/REMD instructions are available for the LCD control register (LCR).

Other registers cannot be accessed by RAM bit manipulation instructions.

Register Flag Area ($020 to $023): Consist of the LSON, WDON, TGSP, and DTON flags which are bit
registers accessible by the RAM bit manip ula tion instruction.

The WDON flag can only be set, and only by the SEM/SEMD instruction.

The DTON flag can be set, reset, and tested by the SEM/SEMD, REM/REMD, and TMD instructions. Note
that the DTON flag is active only in subactive mode, and is normally reset in active mode.

LCD Data Area ($050 to $06F): Locations $050 to $06F store the LCD data which is automatically
transmitted to the segment driver as display data. The LCD is illuminated with 1s and faded with 0s. This
area can be used as a data area.

Data Area ($040 to $2CF, $100 to $2CF; Bank 0/1): The 16 digits of $040 through $04F are called
memory registers (MR) and are accessible by the LAMR and XMRA instructions (figure 4). 464 digits of
$100 through $2CF are selected as bank 0 or 1 depending on the value of the V register.

Stack Area ($3C0 to $3FF): Locations $3C0 through $3FF are reserved for LIFO stacks to save the
contents of the program counter (PC), status flag (ST), and carry flag (CA) when subroutine calls (CAL or
CALL instruction) and interrupts are processed. This area can be used as a 16-level nesting stack in which
one level requires 4 digits.

Figure 4 shows the save condition. The program counter is restored by the RTN and RTNI instructions. The
status and carry flags are restored only by the RTNI instruction. This area, when not used as a stack, is
available as a data area.

HD404818 Series

12

0

$000 $000

63
64
80

112

959
960

1023

$03F
$040
$050
$070

$3FF

4
5
6
7

0
1
2
3

12
13
14

15

8

9
10
11

16
17

32
35

48

18
19
20

49
50
51

63

$001
$002
$003
$004
$005
$006
$007
$008
$009

$00A
$00B
$00C
$00D
$00E
$00F
$010

$011
$012
$013
$014

$020
$023

$030
$031
$032
$033

$03B
$03C
$03D

$03F

$00A

$00B

$00E

$00F

W
W

R/W

W

W
W

W
W
W

W
W
W
W

W
W
W

W

W

W

W

R

R

R

R

W

R/W

R/W
R/W

R/W
R/W

R/W

$100

$2CF

61

59
60

$3BF
$3C0

$2CF

RAM-mapped registers

Memory registers (MR)

LCD display area (32 digits)

Data (144 digits)

Data (464 digits 2)

V = 0 (bank 0)
V = 1 (bank 1)

Not used

Stack (64 digits)

Interrupt control bits area

Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B (TMB)

Timer B (TCBL/TLRL)
(TCBU/TLRU)

Miscellaneous register (MIS)
Timer mode register C (TMC)

Timer C (TCCL/TCRL)
(TCCU/TCRU)

Not used

Not used
Port mode register B (PMRB)
LCD control register (LCR)
LCD mode register (LMR)

Not used

Register flag area

Not used
Port R0 DCR (DCR0)
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
Port R3 DCR (DCR3)

Not used

Port D –D DCR (DCRB)
Port D –D DCR (DCRC)

Port D –D DCR (DCRD)

Not used
V register (V-REG)

03
47
89

Data (464 digits)

V = 1 (bank 1)

Data (464 digits)

V = 0 (bank 0)

Note: Do not use any area labelled "Not used".

10

11

14

15

Timer counter B lower

(TCBL)

Timer counter B upper

(TCBU)

Timer counter C lower

(TCCL)

Timer counter C upper

(TCCU)

Timer load register B lower

(TLRL)

Timer load register B upper

(TLRU)

Timer load register C lower

(TCRL)

Timer load register C upper

(TCRU)

R:
W:
R/W:

×

$100

Read only
Write only
Read/write

The data area has two banks:
bank 0 (V = 0) and bank 1 (V = 1)

Figure 2 RAM Memory Map (1,184-digit × 4-bit)

HD404818 Series

13

0

1

2

3

Bit 3 Bit 2 Bit 1 Bit 0

IM0

(IM of INT )

0

IF0

(IF of INT )

0

RSP

(Reset SP bit)

IE

(Interrupt enable flag)

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of INT )

1

IF1

(IF of INT )

1

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

Not used Not used

IMS

(IM of serial)

IFS

(IF of serial)

$000

$001

$002

$003

32

DTON

Direct transfer on flag

Not used

WDON

(Watchdog on flag)

LSON

(Low speed on flag)

Not used

$020
$021

$023

IF:
IM:
IE:
SP:
Note:

Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD
instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction.
Other instructions have no effect.
However, note the following usage limitations of RAM bit manipulation instructions.

Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer

IF

RSP

WDON

DTON

SEM/SEMD
Not executed
Not executed

Allowed

Not executed in active mode

Used in subactive mode

REM/REMD

Allowed
Allowed

Not executed

Allowed

TM/TMD

Allowed
Inhibited
Inhibited

Allowed

Note: WDON is reset only by MCU reset.

DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in
ST becomes invalid.

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

HD404818 Series

14

PC to PC :
ST:
CA:

13 0

Memory registers Stack area

64 $040 960 $3C0
65 $041
66 $042
67 $043
68 $044

69 $045
70 $046

71 $047
72 $048
73 $049
74 $04A
75 $04B
76 $04C
77 $04D
78 $04E
79 $04F

MR (0)
MR (1)

MR (2)
MR (3)

MR (4)
MR (5)

MR (6)
MR (7)
MR (8)

MR (9)
MR (10)
MR (11)
MR (12)

MR (13)
MR (14)

MR (15)

Level 16
Level 15
Level 14
Level 13

Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1

1023 $3FF

ST

PC

10

PC

13

PC

12

PC

11

CA

PC

3

PC

9

PC

8

PC

7

PC

6

PC

5

PC

4

PC

2

PC

1

PC

0

Bit 3 Bit 2 Bit 1 Bit 0

$3FC

$3FD

$3FE

$3FF

1022

1023

1020

1021

Program counter
Status flag
Carry flag

Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position

HD404818 Series

15

Functional Description

Registers and Flags

The MCU provides ten registers and two flags for CPU operations. They are illustrated in figure 5 and
described in the following paragraphs.

30

30

30

30

30

30

0

0

0

13

95

1

(B)

(A)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

1111

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry

Status

Program counter
Initial value: 0,
no R/W

Stack pointer
Initial value: $3FF, no R/W

0

(V)

0

0

Initial value: Undefined, R/W

Initial value: Undefined, R/W

V register Initial value: 0, R/W

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: 1, no R/W

Figure 5 Registers and Flags

Accumulator (A), B Register (B): The accumulator and B register are 4-bit registers which hold the

results of the arithmetic logic unit (ALU), and exchange data between memory, I/O, and other registers.

HD404818 Series

16

V Register (V): The V register, available for RAM address expansion, selects the bank of locations $100–
$2CF on the RAM address (464 digits) depending on its value. Therefore, when accessing locations $100–
$2CF on the RAM address, specify the value of the V register (V = $0: bank 0; V = $1: bank 1). Locations
$000–$0FF and $300–$3FF can be accessed independently of the V register. The V register is located at
$03F of the RAM address area.

W Register (W), X Register (X), Y Register (Y): The 2-bit W register and 4-bit X and Y registers address
RAM indirectly. The Y register is also available for addressing port D.

SPX Register (SPX), SPY Register (SPY): The 4-bit SPX and SPY registers are available for assisting the
X and Y registers, respectively.

Carry Flag (CA): The carry flag holds the ALU overflow generated by an arithmetic operation. It is also
affected by the SEC, REC, ROTL, and ROTR instructions. During an interrupt, the carry flag is pushed
onto the stack and restored back from the stack by the RTNI instruction. (It is unaffected by the RTN
instruction.)

Status Flag (ST): The status flag holds the ALU overflow, ALU non-zero, and the results of a bit test
instruction for arithmetic or compare instructions. The status flag is a branch condition of the BR, BRL,
CAL, or CALL instruction. The value of the status flag remains unchanged until an instruction which
affects the next status is executed. The status flag becomes 1 after the BR, BRL, CAL, or CALL instruction
is either executed or skipped. During an interrupt, the status flag is pushed onto the stack and restored back
from the stack by the RTNI instruction, not by the RTN instruction.

Program Counter (PC): The program counter is a 14-bit binary counter for holding the ROM address.

Stack Pointer (SP): The stack pointer is a 10-bit register to indicate the next stacking area up to 16 levels.

The stack pointer is initialized to RAM address $3FF at MCU reset. It is decremented by 4 as data is
pushed onto the stack, and incremented by 4 as data is restored back from the stack. The stack pointer is
initialized to $3FF either by MCU reset or by the RSP bit reset from the REM/REMD instruction.

HD404818 Series

17

Reset

Setting the RESET pin high resets the MCU. At power-on or when cancelling the stop mode for the
oscillator, apply the reset input for at least tRC for the oscillator to stabilize. In all other cases, at least two
instruction cycles of reset input are required for the MCU reset.

Table 1 shows the components initialized by MCU reset, and each of its status.

Table 1 Initial Values after MCU Reset

Items Initial Value Contents

Program counter (PC) $0000 Execute program from the top of the ROM

address

Status flag (ST) 1 Enable branching with conditional branch

instructions
Stack pointer (SP) $3FF Stack level is 0
V register (bank register) (V) 0 Bank 0 (memory)
Interrupt

flags/mask

Interrupt enable flag (IE) 0 Inhibit all interrupts

Interrupt request flag (IF) 0 No interrupt request
Interrupt mask (IM) 1 Masks interrupt request

I/O Port data register (PDR) All bits are 1 Enable to transmit high

Data control register (DCR) All bits are 0 Output buffer is off (high impedance)
Port mode register A (PMRA) 0000 See Port Mode Register A section
Port mode register B (PMRB) 0000 See Port Mode Register B section

Timer/counters,
serial interface

Timer mode register A (TMA) 0000 See Timer Mode Register A section

Timer mode register B (TMB) 0000 See Timer Mode Register B section
Timer mode register C (TMC) 0000 See Timer Mode Register C section
Serial mode register (SMR) 0000 See Serial Mode Register section
Prescaler S $000
Prescaler W $00
Timer counter A (TCA) $00
Timer counter B (TCB) $00
Timer counter C (TCC) $00
Timer load register B (TLR) $00
Timer load register C (TCR) $00
Octal counter 000

HD404818 Series

18

Table 1 Initial Values after MCU Reset (cont)

Items Initial Value Contents

LCD LCD control register (LCR) 000 Refer to description of LCD Control

Register

LCD mode register (LMR) 0000 Refer to description of LCD Duty/Clock

Control
Bit register Low speed on flag (LSON) 0 Refer to description of Low-Power

Dissipation Mode

Watchdog timer on flag
(WDON)

0 Refer to description of Timer C

Direct transfer on flag (DTON) 0 Refer to description of Low-Power

Dissipation Mode
Miscellaneous

register

(MIS) 000 —

Item

After MCU Reset to Recover from
Stop Mode

After MCU Reset to Recover from

Other Modes

Carry flag (CA) The contents of the items before

MCU reset are not retained. It is
necessary to initialize them by
software.

The contents of the items before MCU

reset are not retained. It is necessary to

initialize them by software.

Accumulator (A)
B register (B)
W register (W)
X/SPX registers (X/SPX)
Y/SPY registers (Y/SPY)
Serial data register (SR)
RAM The contents of RAM before MCU

reset (just before STOP instruction)
are retained.

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19

Interrupts

Six interrupt sources are available on the MCU: external requests (INT0, INT1), timer/counters (timers A,
B, and C), and the serial interface. For each source, an interrupt request flag (IF), interrupt mask (IM), and
interrupt vector addresses are provided to control and maintain the interrupt request. The interrupt enable
flag (IE) is also used to control interrupt operations.

Interrupt Control Bits and Interrupt Servicing: The interrupt control bits are mapped on $000 through
$003 by the RAM space. They are accessible by RAM bit manipulations instructions, although the interrupt
request flag (IF) cannot be set by software. The interrupt enable flag (IE) and IF are cleared to 0, and the
interrupt mask (IM) is set to 1 after MCU reset.

Figure 6 is a block diagram of the interrupt control circuit. Table 2 shows the interrupt priority and vector
addresses, and table 3 shows the interrupt conditions corresponding to each interrupt source.

The interrupt request is generated when IF is set to 1 and IM is 0. If IE is 1 at this time, the interrupt will be
activated and vector addresses will be generated from the priority PLA corresponding to the interrupt
sources.

HD404818 Series

20

IE

IF0

IM0

IF1

IM1

IFTA

IMTA

IFTB

IMTB

IFTC

IMTC

IFS

IMS

$ 000,0

$ 000,2

$ 000,3

$ 001,0

$ 001,1

$ 001,2

$ 001,3

$ 002,0

$ 002,1

$ 002,2

$ 002,3

$ 003,0

$ 003,1

Sequence control

• Push PC/CA/ST

• Reset IE

• Jump to vector
address

Priority control logic

Vector
address

Note: $m, n is RAM address $m, bit number n.

Figure 6 Interrupt Control Circuit Block Diagram

Table 2 Vector Addresses and Interrupt Priority

Reset/Interrupt Priority Vector Addresses

RESET — $0000

INT

0

1 $0002

INT

1

2 $0004
Timer A 3 $0006
Timer B 4 $0008
Timer C 5 $000A
Serial 6 $000C

HD404818 Series

21

Table 3 Interrupt Conditions

Interrupt Source

Interrupt Control Bit INT

0

INT

1

Timer A Timer B Timer C Serial

IE 111111
IF0 • IM0 100000
IF1 • IM1 * 10000
IFTA • IMTA **1000
IFTB • IMTB ***100
IFTC • IMTC ****10
IFS • IMS *****1

Note: *Don’t care.

Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If
an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the
second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed
onto the stack. In the third cycle, the instruction is executed after jumping to the vector address.

In each vector address, program the JMPL instruction to branch to the starting address of the interrupt
program. The IF, which caused the interrupt, must be reset by software in the interrupt program.

Instruction
cycles

123456

Instruction

execution

Stacking;

reset of IE

Interrupt

acceptance

JMPL instruction execution

on the vector address

Instruction

execution at

starting address

of the interrupt

routine

Stacking;

vector address

generated

Figure 7 Interrupt Processing Sequence

HD404818 Series

22

Power

on

RESET = 1 ?

Reset MCU

Interrupt

request ?

Execute instruction

PC (PC) + 1

←

PC $0002

←

PC $0004

←

PC $0006

←

PC $0008

←

PC $000A

←

PC $000C

←

IE = 1?

Accept interrupt

IE 0
Stack (PC)
Stack (CA)

Stack (ST)

←

INT

interrupt ?

0

INT

interrupt ?

1

Timer A

interrupt ?

Timer B

interrupt ?

Timer C

interrupt ?

No

Yes

No

Yes

No

Yes

Yes

Yes

Yes

Yes

Yes

No

No

No

No

No

←
←
←

(serial interrupt)

Figure 8 Interrupt Processing Flowchart

HD404818 Series

23

Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests
(table 4). It is reset by an interrupt and set by the RTNI instruction.

Table 4 Interrupt Enable Flag

IE Interrupt Enabled/Disabled

0 Disabled
1 Enabled

External Interrupts (INT0, INT1): The external interrupt request inputs (INT0, INT1) can be selected by
port mode register A (PMRA: $004).

The external interrupt request flags (IF0, IF1) are set at the falling edge of I NT 0 and I NT 1 inputs,
respectively (table 5).

The INT1 input can be used as a clock signal input to timer B, in which timer B counts up at each falling
edge of the INT1 input. When using INT1 as the timer B external event input, the external interrupt mask
(IM1) has to be set so that the interrupt request by INT1 will not be accepted (table 6).

More than two instruction cycle times (2t

cyc

/2t

subcyc

) are needed to detect the edge of INT0 or INT1.

External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request
flags (IF0, IF1) are set at the falling edge of the INT0 and INT1 inputs, respectively (table 5).

Table 5 External Interrupt Request Flags

IF0, IF1 Interrupt Request

0No
1 Yes

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt masks mask the
external interrupt requests (table 6).

Table 6 External Interrupt Masks

IM0, IM1 Interrupt Request

0 Enabled
1 Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag is set by the
overflow output of timer A (table 7).

HD404818 Series

24

Table 7 Timer A Interrupt Request Flag

IFTA Interrupt Request

0No
1 Yes

Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask prevents an interrupt request
from being generated by the timer A interrupt request flag (table 8).

Table 8 Timer A Interrupt Mask

IMTA Interrupt Request

0 Enabled
1 Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the
overflow output of timer B (table 9).

Table 9 Timer B Interrupt Request Flag

IFTB Interrupt Request

0No
1 Yes

Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask prevents an interrupt request
from being generated by the timer B interrupt request flag (table 10).

Table 10 Timer B Interrupt Mask

IMTB Interrupt Request

0 Enabled
1 Disabled (masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): The timer C interrupt request flag is set by the
overflow output of timer C (table 11).

Table 11 Timer C Interrupt Request Flag

IFTC Interrupt Request

0No
1 Yes

HD404818 Series

25

Timer C Interrupt Mask (IMTC: $002, Bit 3): The timer C interrupt mask prevents the interrupt from
being generated by the timer C interrupt request flag (table 12).

Table 12 Timer C Interrupt Mask

IMTC Interrupt Request

0 Enabled
1 Disabled (masked)

Serial Interrupt Request Flag (IFS: $003, Bit 0): The serial interrupt request flag is set when the octal
counter counts eight transmit clock signals, or when data transfer is discontinued by resetting the octal
counter (table 13).

Table 13 Serial Interrupt Request Flag

IFS Interrupt Request

0No
1 Yes

Serial Interrupt Mask (IMS: $003, Bit 1): The serial interrupt mask masks the interrupt request (table

14).

Table 14 Serial Interrupt Mask

IMS Interrupt Request

0 Enabled
1 Disabled (masked)

HD404818 Series

26

Operating Modes

The MCU has five operating modes that are specified by how the clock is used. The functions available in
each mode are listed in table 15, and operations are shown in table 16. Transitions between operating
modes are shown in figure 9.

Table 16 provides additional information for table 26.

Table 15 Functions Available in Each Operating Mode

Mode Name
Active Standby Stop Watch Subactive*

4

Activation method RESET

cancellation,
interrupt
request

SBY
instruction

TMA3 = 0,
STOP
instruction

TMA3 = 1,
STOP
instruction

INT

0

or timer A
interrupt
request from
watch mode

Status System oscillator OP OP Stopped Stopped Stopped

Subsystem oscillator OP OP OP *

1

OP OP

Instruction execution
(ø

CPU

)

OP Stopped Stopped Stopped OP

Peripheral function,
interrupt (ø

PER

)

OP OP Stopped Stopped OP

Clock function,
interrupt (ø

CLK

)

OP OP Stopped OP *

2

OP *

2

RAM OP Retained Retained Retained OP
Registers/flags OP Retained Reset Retained OP
I/O OP Retained High

impedance*

3

Retained*

3

OP *

3

Cancellation method RESET input,

STOP/SBY
instruction

RESET input,
interrupt
request

RESET input RESET input,

INT

0

or timer A
interrupt
request

RESET input,
STOP/SBY
instruction

Notes: OP indicates operating.

1. To reduce current dissipation, stop all oscillation in external circuits.

2. Refer to the Interrupt Frame section for details.

3. Refer to interrupt frame.

4. Subactive mode is an optional function to be specified on the function option list.

5. In the watch and subactive modes, the MCU requires a 32.768-kHz crystal oscillator.

HD404818 Series

27

Table 16 Operations in Low-Power Dissipation Modes

Function Stop Mode Watch Mode Standby Mode Subactive Mode*

2

CPU Reset Retained Retained OP
RAM Retained Retained Retained OP
Timer A Reset OP OP OP
Timer B Reset Stopped OP OP
Timer C Reset Stopped OP OP
Serial interface Reset Stopped*

3

OP OP
LCD Reset OP OP OP
I/O Reset*

1

Retained Retained OP

Notes: OP indicates operating.

1. Output pins are at high impedance.

2. Subactive mode is an optional function to be specified on the function option list.

3. Transmission/reception is activated if a clock is input in external clock mode. (However,
interrupts are stopped.)

Table 17 I/O Status in Low-Power Dissipation Modes

Output Input
Standby Mode, Watch Mode Stop Mode Active Mode, Subactive Mode

D0–D

9

Retained High impedance Input enabled

D10–D

13

— — Input enabled

R0–R3 Retained High impedance Input enabled

System Clock (ø

CPU

)

Operating Stopped

Non-time-base peripheral function clock (ø

PER

) Operating Active mode Standby mode

Subactive mode

Stopped — Watch mode (TMA3 = 1)

Stop mode (TMA3 = 0)

HD404818 Series

28

Reset

f :
f :
:
:
:

CPU
CLK
PER

OSC
X

Operating
Operating
Stopped
f
f

cyc
cyc

f :
f :
:
:
:

CPU
CLK
PER

OSC
X

Operating
Operating
Stopped
f
f

SUB
cyc

f :
f :
:
:
:

CPU
CLK
PER

OSC
X

Operating
Operating
f
f
f

cyc
cyc
cyc

f :
f :
:
:
:

CPU
CLK
PER

OSC
X

Operating
Operating
f
f
f

cyc
SUB
cyc

f :
f :
:
:
:

CPU
CLK
PER

OSC
X

Stopped
Operating
f
f
f

SUB
SUB
SUB

f :
f :
:
:
:

CPU
CLK
PER

OSC
X

Stopped
Operating
Stopped
Stopped
Stopped

f :
f :
:
:
:

CPU
CLK
PER

OSC
X

Stopped
Operating
Stopped
f
Stopped

SUB

f :
f :
:
:
:

CPU
CLK
PER

OSC
X

Stopped
Operating
Stopped
f
Stopped

SUB

Standby mode Stop mode

(TMA3 = 0)

Watch mode

Subactive mode

(TMA3 = 1) (TMA3 = 1, LSON = 0)

(TMA3 = 1, LSON = 1)

(TMA3 = 0)

SBY (standby)

Interrupt

Timers A, B, C
Serial,
INT , INT

0 1

SBY (standby)

Interrupt

STOP

STOP

INT ,
Timer A

0

1

INT ,
Timer A

0

1

STOP

STOP/SBY

(LSON = 1)

4

2

3

1. Time-base interrupt

2. STOP/SBY (DTON = 1, LSON = 0)

3. STOP/SBY (DTON = 0, LSON = 0)

4. DTON is not affected

f :
f :

f :
f :
:
:
:

LSON:
DTON:

cyc
SUB

OSC
X

Main oscillation frequency
Suboscillation frequency
for time-base
f /4
f /8
System clock
Clock for time-base
Clock for other
peripheral functions
Low speed on flag
Direct transfer on flag

OSC

X
CPU
CLK
PER

Active mode

Timers A, B, C
Serial,
INT , INT

0 1

ø
ø
ø

ø
ø
ø

ø
ø
ø

ø
ø
ø

ø
ø
ø

ø
ø
ø

ø
ø
ø

ø
ø
ø

Notes:

ø
ø
ø

*

*

*

*

*

Figure 9 MCU Status Transitions

Active Mode: The MCU operates according to the clock generated by the system oscillators OSC1 and

OSC2.

Standby Mode: The MCU enters standby mode when the SBY instruction is executed from active mode.
In this mode, the oscillators, interrupts, timer/counters, and serial interface continue to operate, but all
instruction execution-related clocks stop. The stopping of these clocks stops the CPU, retaining all RAM
and register contents and maintaining the current I/O pin status.

Standby mode is terminated by a RESET input oran interrupt request. If it is terminated by a RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and resumes, executing