Renesas HD151TS207SS User Manual

HD151TS207SS

Mother Board Clock Generator
for Intel P4+ Chipset (Springdale)

REJ03D0006-0100Z

Preliminary

Rev.1.00

Apr.25.2003

Description

The HD151TS207SS is Intel CK409T type high-performance, low-skew, low-jitter, PC motherboard clock
generator. It is specifically designed for Intel Pentium®4+ chipset.

Features

• 3 differential pairs of current mode control CPU clocks

• 1 differential pair of Serial Reference Clock (SRC), selectable 100 MHz/200 MHz

• 6 copies PCI clocks and 3 copies PCIF clocks @3.3V, 33.3 MHz

• 1 copy PCI clock @3.3 V, selectable 33.3 MHz/25 MHz

• 1 copy USB clock @3.3 V, selectable 48 MHz/24 MHz

• 1 copy DOT clock @3.3 V, 48 MHz

• 4 copies of 3V66 clocks @3.3 V, 66.6 MHz

• 1 copy of 3V66/VCH clock @3.3 V, selectable 66. 6 MHz/48 MHz

• 2 copies of REF clocks @3.3 V, 14.318 MHz

• Power save and clock stop function

2CTM

• I

• Programmable Clock Control (Spread Spectrum Percentage, Clock Output Skew, Slew Rate)

• Watchdog timer and reset output

• 56pin SSOP (300 mils)

serial port programming

Note: I

Rev.1.00, Apr.25.2003, page 1 of 38

2

C is a trademark of Philips Corporation.

Pentium is registered trademark of Intel Corporation

HD151TS207SS

Key Specifications

• Supply Voltages: VDD = 3.3 V±5%

• CPU clock cycle to cycle jitter = |125ps| (SSC Disabled)

• CPU clock group Skew = 100ps

• 3V66 clock group Skew = 250psmax

• PCI clock group Skew = 500psmax

Rev.1.00, Apr.25.2003, page 2 of 38

HD151TS207SS

Pin Arrangement

MODE/PCI_0

SEL100_200/PCI_4

SEL33_25/PCI_5

PWRDWN#/SAFE_F#

3V66_0/RESET#

REF0
REF1

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

FS2/PCIF_0
FS4/PCIF_1

PCIF_2

VDD_PCI

VSS_PCI

PCI_1
PCI_2
PCI_3

VDD_PCI

VSS_PCI

PCI_6

3V66_1

VDD_3V66

VSS_3V66

3V66_2
3V66_3

SCLK

10
11
12
13
14
15
16
17
18

19

20
21
22
23
24

25
26
27
28

FS_B

1
2

3
4
5

6
7

8

9

56

VDD_A

55
54

VSS_A

53

VSS_IREF
IREF

52
51

FS_A

50

TEST_CLK#

49

PCI_STOP#
VDD_CPU

48
47

CPU_2

46

CPU_2#

45

VSS_CPU
CPU_1

44
43

CPU_1#

42

VDD_CPU

41

CPU_0

40

CPU_0#

39

VSS_SRC

38

SRC

37

SRC#
VDD_SRC

36
35

VTT_PWRGD#

34

VDD_48

33

VSS_48
FS3/DOT_48

32
31

SEL48_24/USB_48

30

SDATA

29

SEL66_48/3V66_4/VCH

(Top view)

PCI_STOP#, PWRDWN# = 150 kΩ Internal Pull-up

Rev.1.00, Apr.25.2003, page 3 of 38

HD151TS207SS

Pin Descriptions

Pin name No. Type Description

VSS_A 54 Ground for PLL
VSS_CPU 45 Ground for outputs
VSS_IREF 53 Ground for current reference
VSS_SRC 39
VSS_3V66 25
VSS_PCI 11, 17
VSS_REF 6
VSS_48 33
VDD_A 55 3.3 V Power Supply for PLL
VDD_CPU 42, 48
VDD_SRC 36
VDD_3V66 24
VDD_PCI 10, 16
VDD_REF 3
VDD_48 34
REF0 1
REF1 2
XTAL_IN 4 INPUT 14.318 MHz XTAL input.
XTAL_OUT 5 OUTPUT 14.318 MHz XTAL output.

FS2/PCIF_[0:1] 7,8 INPUT/

Ground

Ground for outputs

Power

3.3 V Power Supply for outputs

OUTPUT 3.3 V 14.318 MHz reference clock.

Don’t connect when an external clock is applied at XTAL_IN.
Frequency select latch input pin.

OUTPUT

/Free running PCI clock 3.3 V output.

PCIF_2 9 OUTPUT Free running PCI clock 3.3 V output.
**MODE/PCI_0 12 INPUT/

OUTPUT

PCI_[1:3] 13,14,15OUTPUT PCI clock 3.3 V outputs.

**SEL100_200/
PCI_4

**SEL33_25/PCI_5 19 INPUT/

PCI_6 20 OUTPUT PCI clock 3.3 V outputs.
Note: (*): Those pins are 150 kΩ internal pulled-UP.

(**): Those pins are 150 kΩ internal pulled-DOWN.

Rev.1.00, Apr.25.2003, page 4 of 38

18 INPUT/

OUTPUT

OUTPUT

Function select latch input pin for pin 22,
1 = Reset#, 0 = clock output.
/PCI clock 3.3 V output.

Latched select input for SRC output.
1 = 200 MHz, 0 = 100 MHz
/PCI clock 3.3 V output.

Latched select input for PCI5 output.
1 = 25 MHz, 0 = 33 MHz
/PCI clock 3.3 V output.

HD151TS207SS

Pin Descriptions (cont.)

Pin name No. Type Description

PWRDWN#/
SAFE_F#

3V66_0/RESET# 22 OUTPUT 3V66 / Watchdog RESET# selectable output.

3V66_[1:3] 23,26,27OUTPUT 3V66 clock 3.3V outputs.

21 INPUT

PULL–UP*

PWRDWN# / SAFE_F# selectable input.
Default is PWRDWN# input.
Byte15[5] = “1” : SAFE_F# input.
PWRDWN# is all clocks stop pin.
Asynchronous active “Low” input.
When asserted low, all output clocks are disabled.
SAFE_F# is active “Low” input.
When SAFE_F# is “Low” ,frequency mode is changed to the
predefined frequency mode.

Default is 3V66 output.
This signal is active low and selected by Mode latch input.

SCLK 28 INPUT

PULL-UP*

**SEL66_48/
3V66_4/VCH

SDATA 30 IN/OUTPUT

**SEL48_24/
USB_48

FS3/DOT_48 32 INPUT/

VTT_PWRGD# 35 INPUT

SRC# 37 OUTPUT “Complementary” clock of Differential Serial Reference Clock.
SRC 38 OUTPUT “True” clock of Differential Serial Reference Clock.
CPU_[0:2]# 40,43,46OUTPUT “Complementary” clock of differential CPU clock.

CPU_[0:2] 41,44,47OUTPUT “True” clock of differential CPU clock.

PCI_STOP# 49 INPUT

TEST_CLK# 50 INPUT

FS_[A:B] 51,52 INPUT CPU clocks frequency select latch input.
IREF 52 INPUT A precision resistor is attached to this pin which is connected

Note: (*): Those pins are 150 kΩ internal pulled-UP.

(**): Those pins are 150 kΩ internal pulled-DOWN

29 INPUT/

OUTPUT

PULL-UP*

31 INPUT/

OUTPUT

OUTPUT

PULL-UP*

PULL–UP*

PULL-UP*

Clock input for I2C logic.

Latched select input for 3V66/VCH output 1 = 48 MHz,
0 = 66.66 MHz. /3V66 or VCH clock output.

Data input for I2C logic.

Latched select input for 48_24 MHz output
1 = 24 MHz, 0 = 48 MHz / 24_48 MHz clock 3.3 V output.

Frequency select latch input pin.
/DOT_48 clock 3.3 V output.

Qualifying input that latches FS_A and FS_B.
When asserted low, FS_A and FS_B are latched.

PCI clocks stop pin. Active “Low” input.
When asserted low, PCI[6:0] and SRC clocks are
synchronously disabled in low state.
Usually this pin does not give to effect PCIF[2:0] clock outputs.

Test clock mode pin. Active “Low” input.

to internal current reference.
A resistor is connected between this pin and GNDIREF.

Rev.1.00, Apr.25.2003, page 5 of 38

HD151TS207SS

Block Diagram

XTAL

14.318 MHz

PWRDWN#/SAFE_F#

PCI_STOP#

VTT_PWRGD#

TEST_CLK#

*MODE

*SEL100_200

*SEL66_48
*SEL48_24
*SEL33_25

*FS_4/3/2A/B

SCLK

SDATA

3.3 V VDD_48 3.3 V VDD_AVSS_48 VSS_A

CK2

CK1

CK0

1/M2

SSC2

1/N2

1/M1

SSC1

1/N1

1/M0

1/N0

PLL2

For

CPU

PLL1

For

SRC

3V66

PCI

USB

PLL

OSC

Input

Clock

Select

6× 3.3V VDD 6×VSS

VCO2

Clock

VCO1

Divider

VCO0

VSS_IREF IREF

Clock

Select

Delay

Control

Stop

Control

REF[1:0]
(14.318MHz)

CPU[2:0]
CPU[2:0]#

SRC
SRC#

PCI[6:0]
PCIF[2:0]

3V66_0/RESET#
3V66[3:1]
3V66_4/VCH

USB_48

DOT_48

* : Latched Input pin.

Control Logic

Rev.1.00, Apr.25.2003, page 6 of 38

HD151TS207SS

I2C Controlled Register Bit Map

Byte0 Control Register

Bit Description Contents Type Default Note

7 Reserved R 0
6 Reserved R 0
5 Reserved R 0
4 Reserved R 0
3 PCI_Stop Reflects the current value

of the external PCI_STOP# pin
2 Reserved R X
1 FS_B Reflects the value of the

FS_B pin sampled on power up
0 FS_A Reflects the value of the

FS_A pin sampled on power up

Table1 Clock Frequency Function Table

0 = PCI_STOP# pin is Low
1 = PCI_STOP# pin is High

0 = FS_B Low at power up
1 = FS_B High at power up

0 = FS_A Low at power up
1 = FS_A High at power up

RX

RX

RX

See
Table
1

Byte6
Bit5

0 0 0 100 100/200 66 33 14.318 48
0 0 1 200 100/200 66 33 14.318 48
0 1 0 133 100/200 66 33 14.318 48
0 1 1 166 100/200 66 33 14.318 48
1 0 0 200 100/200 66 33 14.318 48
1 0 1 400 100/200 66 33 14.318 48
1 1 0 266 100/200 66 33 14.318 48
1 1 1 333 100/200 66 33 14.318 48

FS_A FS_B CPU

[MHz]

SRC
[MHz]

3V66
[MHz]

PCIF
PCI
[MHz]

REF0
REF1
[MHz]

Table2 Test Clock select table

TEST_CLK# CPU

[MHz]

1 REF/2 REF/2 REF/4 REF/8 REF REF/2
0 Hi–Z Hi–Z Hi–Z Hi–Z Hi–Z Hi–Z

Note: 1. REF is a clock over driven on the XIN during test mode.

SRC
[MHz]

3V66
[MHz]

PCIF
PCI
[MHz]

REF0
REF1
[MHz]

USB
DOT
[MHz]

USB
DOT
[MHz]

Note

Note

See Note1,
Table3

Rev.1.00, Apr.25.2003, page 7 of 38

HD151TS207SS

I2C Controlled Register Bit Map (cont.)

Table3 FS_A and FS_B pin Input level

Logic Level Min Voltage Max Voltage

0 (Low)  0.35V
1 (High) 0.70V 

Byte1 Control Register

Bit Description Contents Type Default Note

7 Allow control of SCR with assertion

of PCI_STOP#

6 SRC Output enable 0 = Disabled (tristate)

5 Reserved RW 1
4 Reserved RW 1
3 Reserved RW 1
2 CPU2 Output enable 0 = Disabled (tristate)

1 CPU1 Output enable 0 = Disabled (tristate)

0 CPU0 Output enable 0 = Disabled (tristate)

0 = Free running
1 = Stopped with
PCI_STOP#

1 = Enabled

1 = Enabled

1 = Enabled

1 = Enabled

RW 0 See

Table5

RW 1

RW 1

RW 1

RW 1

Byte2 Control Register

Bit Description Contents Type Default Note

7 SRC_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate

6 SRC_Stop drive mode 0 = Driven when stopped,

1 = Tristate

5 CPU2_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate

4 CPU1_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate

3 CPU0_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate
2 Reserved RW 0
1 Reserved RW 0
0 Reserved RW 0

Rev.1.00, Apr.25.2003, page 8 of 38

RW 0

RW 0

RW 0

RW 0

RW 0

See
Table5

See
Table4

HD151TS207SS

I2C Controlled Register Bit Map (cont.)

Table4 CPU Clock Power Management Truth Table

Signal Pin

PWRDWN#

CPU[2:0] 1 X Running
CPU[2:0] 0 0 Driven @ Iref x2 See Note1
CPU[2:0] 0 1 Tristate
Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,

Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω)

PWRDWN#
Tristate Bit
Byte2[5:3]

Non-Stop
Outputs
Byte1[5:3] = 1

Note

Table5 SRC Clock Power Management Truth Table

Signal Pin

PWRDWN#

SRC 1 1 X X Running Running
SRC100XRunningDriven @

SRC101XRunningTristate
SRC 0 X X 0 Driven @

SRC 0 X X 1 Tristate Tristate
Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA

Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 Ω)
Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω)

Pin
PCI_STOP#

PCI_STOP#
Tristate Bit
Byte2[6]

PWRDWN#
Tristate Bit
Byte2[7]

Non-Stop
Outputs
Byte1[7] = 1

Iref x2

Stoppable
Outputs
Byte1[7] = 0

Iref x6

Driven @
Iref x2

Note

See Note1

See Note1

Byte3 Control Register

Bit Description Contents Type Default Note

7 PCI_Stop control 0 = Enabled, all stoppable PCI

and SRC clocks are stopped.

1 = Disabled
6 PCI_6 Output enable 0 = Disabled, 1 = Enabled RW 1
5 PCI_5 Output enable 0 = Disabled, 1 = Enabled RW 1
4 PCI_4 Output enable 0 = Disabled, 1 = Enabled RW 1
3 PCI_3 Output enable 0 = Disabled, 1 = Enabled RW 1
2 PCI_2 Output enable 0 = Disabled, 1 = Enabled RW 1
1 PCI_1 Output enable 0 = Disabled, 1 = Enabled RW 1
0 PCI_0 Output enable 0 = Disabled, 1 = Enabled RW 1

Rev.1.00, Apr.25.2003, page 9 of 38

RW 1

HD151TS207SS

I2C Controlled Register Bit Map (cont.)

Byte4 Control Register

Bit Description Contents Type Default Note

7 USB_48 2x output drive 0 = 2x Drive strength,

1 = Normal

6 USB_48MHz Output Enable 0 = Disabled,

1 = Enabled

5 Allow control of PCIF_2 with

assertion of PCI_STOP#

4 Allow control of PCIF_1 with

assertion of PCI_STOP#

3 Allow control of PCIF_0 with

assertion of PCI_STOP#
2 PCIF_2 Output enable 0 = Disabled, 1 = Enabled RW 1
1 PCIF_1 Output enable 0 = Disabled, 1 = Enabled RW 1

0 PCIF_0 Output enable 0 = Disabled, 1 = Enabled RW 1

0 = Free Running
1 = Stopped with PCI_STOP#
0 = Free Running
1 = Stopped with PCI_STOP#
0 = Free Running
1 = Stopped with PCI_STOP#

Byte5 Control Register

Bit Description Contents Type Default Note

7 DOT_48MHz Output Enable 0 = Disabled, 1 = Enabled RW 1
6 Reserved RW 1
5 VCH Select 66MHz / 48MHz 0 = 3V66 mode

1 = VCH (48 MHz) mode

4 3V66_4/VCH Output Enable 0 = Disabled (tristate),

1 = Enabled
3 3V66_3 Output Enable 0 = Disabled, 1 = Enabled RW 1
2 3V66_2 Output Enable 0 = Disabled, 1 = Enabled RW 1
1 3V66_1 Output Enable 0 = Disabled, 1 = Enabled RW 1
0 3V66_0 Output Enable 0 = Disabled, 1 = Enabled RW 1

RW 0
RW 1
RW 0
RW 0
RW 0

RW 0

RW 1

Byte6 Control Register

Bit Description Contents Type Default Note

7 Test Clock Mode 0 = Disabled, 1 = Enabled RW 0
6 Reserved RW 0
5 FS_A & FS_B Operation 0 = Normal, 1 = Test mode RW 0
4 SRC Frequency Sel ect 0 = 100MHz, 1 = 200 MHz RW 0
3 Reserved RW 0
2 Spread Spectrum Mode 0 = Spread OFF

1 = Spread ON
1 REF1 Output Enable 0 = Disabled, 1 = Enabled RW 1
0 REF0 Output Enable 0 = Disabled, 1 = Enabled RW 1

Rev.1.00, Apr.25.2003, page 10 of 38

RW 0 See

B9[7:6]

HD151TS207SS

I2C Controlled Register Bit Map (cont.)

Byte7 Vendor Identification Register

Bit Description Contents Type Default Note

7 Revision Code Bit3 Vendor Specific R 0
6 Revision Code Bit2 Vendor Specific R 0
5 Revision Code Bit1 Vendor Specific R 0
4 Revision Code Bit0 Vendor Specific R 1
3 Vendor ID Bit3 Vendor Specific R 1
2 Vendor ID Bit2 Vendor Specific R 1
1 Vendor ID Bit1 Vendor Specific R 1
0 Vendor ID Bit0 Vendor Specific R 1

Byte8 Read Back Byte Count Register

Bit Description Contents Type Default Note

7 Read back byte count Bit7 RW 0
6 Read back byte count Bit6 RW 0
5 Read back byte count Bit5 RW 0
4 Read back byte count Bit4 RW 1
3 Read back byte count Bit3 RW 1
2 Read back byte count Bit2 RW 1
1 Read back byte count Bit1 RW 1
0 Read back byte count Bit0

Writing to this register will configure
byte Count and how many bytes will
be read back.
Default is 1Ehex = 30 bytes.

RW 0

Rev.1.00, Apr.25.2003, page 11 of 38

HD151TS207SS

I2C Controlled Register Bit Map (cont.)

Byte9 Control Register

Bit Description Contents Type Default Note

7 SSC2 Enable Bit B6[2] = 0 or B9[7] = 1 : SSC2 =OFF

B6[2] = 1 & B9[7] = 0 : SSC2 = ON

6 SSC1 Enable Bit B6[2] = 0 or B9[6] = 1 : SSC1 = OFF

B6[2] = 1 & B9[6] = 0 : SSC1 = ON

5 Clock Frequency Control

Bit4

4 Clock Frequency Control

Bit3

3 Clock Frequency Control

Bit2

2 Clock Frequency Control

Bit1

1 Clock Frequency Control

Bit0

0 Frequency Select Mode Bit 0 = Fr eq. is selected by latched input

Latched input PCIF_1 at Power ON RW X

Latched input DOT48 at Power ON RW X

Latched input PCIF_0 at Power ON RW X

Latched input FS_A at Power ON RW X

Latched input FS_B at Power ON RW X

FS_A and FS_B
1 = Freq. is selected by I

2

C B9[5:1]

RW 0

RW 0

See
Table
6

RW 0

Rev.1.00, Apr.25.2003, page 12 of 38