Renesas H8SX/1650, R5S61650C, H8SX/1650C Hardware Manual
REJ09B0311-0200
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
H8SX/1650C R5S61650C
H8SX/1650Group
Hardware Manual
Renesas 32-Bit CISC Microcomputer
H8SX Family / H8SX/1600 Series
All information contained in this material, including products and product
specifications at the time of publication of this material, is subject to change by
Renesas Technology Corp. without notice. Please review the latest information
published by Renesas Technology Corp. through various means, including the
Renesas Technology Corp. website (http://www.renesas.com).
Rev.2.00
Revision Date: Jun. 28, 2007
Rev.2.00 Jun. 28, 2007 Page ii of xxii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev.2.00 Jun. 28, 2007 Page iii of xxii
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different type numbers, implement a system-evaluation test for
each of the products.
Rev.2.00 Jun. 28, 2007 Page iv of xxii
How to Use This Manual
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the H8SX/1650 Group. Before using any of
the documents, please visit our web site to verify that you have the most up-to-date available
version of the document.
Document Type Contents Document Title Document No.
Data Sheet Overview of hardware and electrical
characteristics
Hardware Manual Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
Software Manual Detailed descriptions of the CPU
and instruction set
Application Note Examples of applications and
sample programs
Renesas Technical
Update
Preliminary report on the
specifications of a product,
document, etc.
H8SX/1650 Group
Hardware Manual
H8SX Family Software
Manual
The latest versions are available from our
web site.
This manual
REJ09B0102
Rev.2.00 Jun. 28, 2007 Page v of xxii
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary: B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal: 1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
(2)
Rev. 0.50, 10/04, page 416 of 914
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Rev.2.00 Jun. 28, 2007 Page vi of xxii
(3)
3. Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of
bits, describing the meanings of the bit settings. The standard format and notation for bit charts
and tables are described below.
[Bit Chart]
Initial value:
[Table of Bits]
Bit:
1514131211109876543210
ASID1 ASID0 ACMP1 ACMP0
0000001000000000
R/W:
R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W
(1) (2) (3) (4)
Bit
15
14
13 to 11
10
9
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this
Bit Name Initial Value R/W Description
−
−
ASID2 to
ASID0
−
−
−
manual.
0
0
All 0
0
1
0
R
Reserved
R
These bits are always read as 0.
R/W
Address Identifier
These bits enable or disable the pin function.
R
Reserved
This bit is always read as 0.
R
Reserved
This bit is always read as 1.
ASID2
ACMP2Q
(5)
IFE
(1) Bit
Indicates the bit number or numbers.
In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case
of a 16-bit register, the bits are arranged in order from 15 to 0.
(2) Bit name
Indicates the name of the bit or bit field.
When the number of bits has to be clearly indicated in the field, appropriate notation is
included (e.g., ASID[3:0]).
A reserved bit is indicated by "−".
Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such
cases, the entry under Bit Name is blank.
(3) Initial value
Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.
0: The initial value is 0
1: The initial value is 1
−: The initial value is undefined
(4) R/W
For each bit and bit field, this entry indicates whether the bit or field is readable or writable,
or both writing to and reading from the bit or field are impossible.
The notation is as follows:
R/W:
The bit or field is readable and writable.
R/(W):
The bit or field is readable and writable.
However, writing is only performed to flag clearing.
R:
The bit or field is readable.
"R" is indicated for all reserved bits. When writing to the register, write
the value under Initial Value in the bit chart to reserved bits or fields.
W:
The bit or field is writable.
(5) Description
Describes the function of the bit or field and specifies the values for writing.
Rev.2.00 Jun. 28, 2007 Page vii of xxii
4. Description of Abbreviations
The abbreviations used in this manual are listed below.
•
Abbreviations specific to this product
Abbreviation Description
BSC Bus controller
CPG Clock pulse generator
DTC Data transfer controller
INTC Interrupt controller
PPG Programmable pulse generator
SCI Serial communication interface
TMR 8-bit timer
TPU 16-bit timer pulse unit
WDT Watchdog timer
• Abbreviations other than those listed above
Abbreviation Description
ACIA Asynchronous communication interface adapter
bps Bits per second
CRC Cyclic redundancy check
DMA Direct memory access
DMAC Direct memory access controller
GSM Global System for Mobile Communications
Hi-Z High impedance
IEBus Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.)
I/O Input/output
IrDA Infrared Data Association
LSB Least significant bit
MSB Most significant bit
NC No connection
PLL Phase-locked loop
PWM Pulse width modulation
SFR Special function register
SIM Subscriber Identity Module
UART Universal asynchronous receiver/transmitter
VCO Voltage-controlled oscillator
All trademarks and registered trademarks are the property of their respective owners.
Rev.2.00 Jun. 28, 2007 Page viii of xxii
Contents
Section 1 Overview................................................................................................1
1.1 Features................................................................................................................................. 1
1.1.1 Applications ..........................................................................................................1
1.1.2 Overview of Functions.......................................................................................... 2
1.2 List of Products..................................................................................................................... 7
1.3 Block Diagram...................................................................................................................... 8
1.4 Pin Assignments ...................................................................................................................9
1.5 Pin Functions ......................................................................................................................10
Section 2 CPU......................................................................................................15
2.1 Features............................................................................................................................... 15
2.2 CPU Operating Modes........................................................................................................ 17
2.2.1 Normal Mode...................................................................................................... 17
2.2.2 Middle Mode....................................................................................................... 19
2.2.3 Advanced Mode .................................................................................................. 20
2.2.4 Maximum Mode ................................................................................................. 21
2.3 Instruction Fetch ................................................................................................................. 23
2.4 Address Space..................................................................................................................... 23
2.5 Registers .............................................................................................................................24
2.5.1 General Registers ................................................................................................ 25
2.5.2 Program Counter (PC) ........................................................................................26
2.5.3 Condition-Code Register (CCR) ......................................................................... 26
2.5.4 Extended Control Register (EXR) ...................................................................... 28
2.5.5 Vector Base Register (VBR)............................................................................... 28
2.5.6 Short Address Base Register (SBR).................................................................... 28
2.5.7 Multiply-Accumulate Register (MAC) ............................................................... 29
2.5.8 Initial Register Values......................................................................................... 29
2.6 Data Formats....................................................................................................................... 30
2.6.1 General Register Data Formats ........................................................................... 30
2.6.2 Memory Data Formats ........................................................................................ 31
2.7 Instruction Set..................................................................................................................... 32
2.7.1 Instructions and Addressing Modes.................................................................... 34
2.7.2 Table of Instructions Classified by Function ...................................................... 38
2.7.3 Basic Instruction Formats ...................................................................................49
2.8 Addressing Modes and Effective Address Calculation....................................................... 50
2.8.1 Register Direct—Rn ........................................................................................... 51
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2.8.2 Register Indirect—@ERn ................................................................................... 51
2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn), or
@(d:32, ERn)...................................................................................................... 51
2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)................. 51
2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,
or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− ............................ 52
2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32................................... 53
2.8.7 Immediate—#xx:8, #xx:16, or #xx:32................................................................ 54
2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) .................................. 55
2.8.9 Program-Counter Relative with Index Register—
@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC).............................................. 55
2.8.10 Memory Indirect—@@aa:8 ............................................................................... 55
2.8.11 Extended Memory Indirect—@@vec:7 ............................................................. 56
2.8.12 Effective Address Calculation ............................................................................ 56
2.8.13 MOVA Instruction.............................................................................................. 58
2.9 Processing States ................................................................................................................ 59
Section 3 MCU Operating Modes .......................................................................61
3.1 Operating Mode Selection .................................................................................................. 61
3.2 Register Descriptions.......................................................................................................... 62
3.2.1 Mode Control Register (MDCR) ........................................................................ 62
3.2.2 System Control Register (SYSCR) ..................................................................... 64
3.3 Operating Mode Descriptions............................................................................................. 66
3.3.1 Mode 4 ................................................................................................................ 66
3.3.2 Mode 5 ................................................................................................................ 66
3.3.3 Pin Functions ...................................................................................................... 67
3.4 Address Map....................................................................................................................... 68
3.4.1 Address Map (Advanced Mode) ......................................................................... 68
Section 4 Exception Handling............................................................................. 69
4.1 Exception Handling Types and Priority.............................................................................. 69
4.2 Exception Sources and Exception Handling Vector Table................................................. 70
4.3 Reset ................................................................................................................................... 72
4.3.1 Reset Exception Handling .................................................................................. 72
4.3.2 Interrupts after Reset........................................................................................... 73
4.3.3 On-Chip Peripheral Functions after Reset Release............................................. 73
4.4 Traces Exception Handling................................................................................................. 75
4.5 Address Error...................................................................................................................... 76
4.5.1 Address Error Source.......................................................................................... 76
Rev.2.00 Jun. 28, 2007 Page x of xxii
4.5.2 Address Error Exception Handling ..................................................................... 77
4.6 Interrupts............................................................................................................................. 78
4.6.1 Interrupt Sources................................................................................................. 78
4.6.2 Interrupt Exception Handling ............................................................................. 78
4.7 Instruction Exception Handling.......................................................................................... 79
4.7.1 Trap Instruction Exception Handling.................................................................. 79
4.7.2 Sleep Instruction Exception Handling ................................................................ 80
4.7.3 Exception Handling by Illegal Instruction .......................................................... 81
4.8 Stack Status after Exception Handling................................................................................ 82
4.9 Usage Note.......................................................................................................................... 83
Section 5 Interrupt Controller ..............................................................................85
5.1 Features............................................................................................................................... 85
5.2 Input/Output Pins................................................................................................................ 87
5.3 Register Descriptions.......................................................................................................... 87
5.3.1 Interrupt Control Register (INTCR) ................................................................... 88
5.3.2 CPU Priority Control Register (CPUPCR) .........................................................89
5.3.3 Interrupt Priority Registers A to C, E to H, K, and L
(IPRA to IPRC, IPRE to IPRH, IPRK, and IPRL).............................................. 90
5.3.4 IRQ Enable Register (IER) .................................................................................92
5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................... 94
5.3.6 IRQ Status Register (ISR)................................................................................... 98
5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................. 99
5.4 Interrupt Sources...............................................................................................................100
5.4.1 External Interrupts ............................................................................................ 100
5.4.2 Internal Interrupts ............................................................................................. 101
5.5 Interrupt Exception Handling Vector Table...................................................................... 102
5.6 Interrupt Control Modes and Interrupt Operation............................................................. 106
5.6.1 Interrupt Control Mode 0 .................................................................................. 106
5.6.2 Interrupt Control Mode 2 .................................................................................. 108
5.6.3 Interrupt Exception Handling Sequence ........................................................... 110
5.6.4 Interrupt Response Times .................................................................................111
5.6.5 DTC Activation by Interrupt............................................................................. 112
5.7 CPU Priority Control Function Over DTC ....................................................................... 115
5.8 Usage Notes...................................................................................................................... 117
5.8.1 Conflict between Interrupt Generation and Disabling ...................................... 117
5.8.2 Instructions that Disable Interrupts ................................................................... 118
5.8.3 Times when Interrupts are Disabled ................................................................. 118
5.8.4 Interrupts during Execution of EEPMOV Instruction....................................... 118
5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions................ 118
Rev.2.00 Jun. 28, 2007 Page xi of xxii
5.8.6 Interrupts Source Flag of Peripheral Modules .................................................. 119
Section 6 Bus Controller (BSC) ........................................................................121
6.1 Features............................................................................................................................. 121
6.2 Register Descriptions........................................................................................................ 124
6.2.1 Bus Width Control Register (ABWCR)............................................................ 124
6.2.2 Access State Control Register (ASTCR) .......................................................... 126
6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 127
6.2.4 Read Strobe Timing Control Register (RDNCR) ............................................. 132
6.2.5 CS Assertion Period Control Registers (CSACR) ............................................ 133
6.2.6 Idle Control Register (IDLCR) ......................................................................... 135
6.2.7 Bus Control Register 1 (BCR1) ........................................................................ 137
6.2.8 Bus Control Register 2 (BCR2) ........................................................................ 139
6.2.9 Endian Control Register (ENDIANCR) ........................................................... 140
6.2.10 SRAM Mode Control Register (SRAMCR) ..................................................... 141
6.2.11 Burst ROM Interface Control Register (BROMCR) ........................................ 142
6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR)............................. 144
6.3 Bus Configuration............................................................................................................. 145
6.4 Multi-Clock Function and Number of Access Cycles ...................................................... 146
6.5 External Bus ..................................................................................................................... 150
6.5.1 Input/Output Pins.............................................................................................. 150
6.5.2 Area Division.................................................................................................... 153
6.5.3 Chip Select Signals ........................................................................................... 154
6.5.4 External Bus Interface ...................................................................................... 155
6.5.5 Area and External Bus Interface ....................................................................... 159
6.5.6 Endian and Data Alignment.............................................................................. 163
6.6 Basic Bus Interface........................................................................................................... 167
6.6.1 Data Bus ........................................................................................................... 167
6.6.2 I/O Pins Used for Basic Bus Interface .............................................................. 167
6.6.3 Basic Timing..................................................................................................... 168
6.6.4 Wait Control ..................................................................................................... 174
6.6.5 Read Strobe (RD) Timing ................................................................................. 176
6.6.6 Extension of Chip Select (CS) Assertion Period............................................... 177
6.7 Byte Control SRAM Interface .......................................................................................... 179
6.7.1 Byte Control SRAM Space Setting................................................................... 179
6.7.2 Data Bus ........................................................................................................... 179
6.7.3 I/O Pins Used for Byte Control SRAM Interface ............................................. 180
6.7.4 Basic Timing..................................................................................................... 181
6.7.5 Wait Control ..................................................................................................... 183
6.7.6 Read Strobe (RD) ............................................................................................. 185
Rev.2.00 Jun. 28, 2007 Page xii of xxii
6.7.7 Extension of Chip Select (CS) Assertion Period............................................... 185
6.8 Burst ROM Interface ........................................................................................................ 185
6.8.1 Burst ROM Space Setting ................................................................................. 185
6.8.2 Data Bus............................................................................................................ 186
6.8.3 I/O Pins Used for Burst ROM Interface............................................................ 186
6.8.4 Basic Timing..................................................................................................... 187
6.8.5 Wait Control ..................................................................................................... 189
6.8.6 Read Strobe (RD) Timing .................................................................................189
6.8.7 Extension of Chip Select (CS) Assertion Period............................................... 189
6.9 Address/Data Multiplexed I/O Interface........................................................................... 189
6.9.1 Address/Data Multiplexed I/O Space Setting ................................................... 189
6.9.2 Address/Data Multiplex .................................................................................... 190
6.9.3 Data Bus............................................................................................................ 190
6.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface .............................. 191
6.9.5 Basic Timing..................................................................................................... 192
6.9.6 Address Cycle Control...................................................................................... 194
6.9.7 Wait Control ..................................................................................................... 195
6.9.8 Read Strobe (RD) Timing .................................................................................195
6.9.9 Extension of Chip Select (CS) Assertion Period............................................... 196
6.10 Idle Cycle.......................................................................................................................... 198
6.10.1 Operation .......................................................................................................... 198
6.10.2 Pin States in Idle Cycle..................................................................................... 206
6.11 Bus Release....................................................................................................................... 207
6.11.1 Operation .......................................................................................................... 207
6.11.2 Pin States in External Bus Released State......................................................... 208
6.11.3 Transition Timing ............................................................................................. 209
6.12 Internal Bus....................................................................................................................... 210
6.12.1 Access to Internal Address Space ..................................................................... 210
6.13 Write Data Buffer Function .............................................................................................. 211
6.13.1 Write Data Buffer Function for External Data Bus........................................... 211
6.13.2 Write Data Buffer Function for Peripheral Modules ........................................ 212
6.14 Bus Arbitration .................................................................................................................213
6.14.1 Operation .......................................................................................................... 213
6.14.2 Bus Transfer Timing......................................................................................... 214
6.15 Bus Controller Operation in Reset .................................................................................... 215
6.16 Usage Notes ...................................................................................................................... 215
Section 7 Data Transfer Controller (DTC) ........................................................217
7.1 Features............................................................................................................................. 217
7.2 Register Descriptions........................................................................................................ 219
Rev.2.00 Jun. 28, 2007 Page xiii of xxii
7.2.1 DTC Mode Register A (MRA) ......................................................................... 220
7.2.2 DTC Mode Register B (MRB).......................................................................... 221
7.2.3 DTC Source Address Register (SAR)............................................................... 223
7.2.4 DTC Destination Address Register (DAR)....................................................... 223
7.2.5 DTC Transfer Count Register A (CRA) ........................................................... 224
7.2.6 DTC Transfer Count Register B (CRB)............................................................ 224
7.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) .................................. 225
7.2.8 DTC Control Register (DTCCR) ...................................................................... 226
7.2.9 DTC Vector Base Register (DTCVBR)............................................................ 227
7.3 Activation Sources............................................................................................................ 227
7.4 Location of Transfer Information and DTC Vector Table................................................ 228
7.5 Operation .......................................................................................................................... 231
7.5.1 Bus Cycle Division ........................................................................................... 233
7.5.2 Transfer Information Read Skip Function ........................................................ 235
7.5.3 Transfer Information Writeback Skip Function................................................ 236
7.5.4 Normal Transfer Mode ..................................................................................... 236
7.5.5 Repeat Transfer Mode ...................................................................................... 237
7.5.6 Block Transfer Mode ........................................................................................ 239
7.5.7 Chain Transfer .................................................................................................. 240
7.5.8 Operation Timing.............................................................................................. 241
7.5.9 Number of DTC Execution Cycles ................................................................... 243
7.5.10 DTC Bus Release Timing ................................................................................. 244
7.5.11 DTC Priority Level Control to the CPU ........................................................... 244
7.6 DTC Activation by Interrupt............................................................................................. 245
7.7 Examples of Use of the DTC............................................................................................ 246
7.7.1 Normal Transfer Mode ..................................................................................... 246
7.7.2 Chain Transfer .................................................................................................. 247
7.7.3 Chain Transfer when Counter = 0..................................................................... 248
7.8 Interrupt Sources...............................................................................................................249
7.9 Usage Notes...................................................................................................................... 249
7.9.1 Module Stop State Setting ................................................................................ 249
7.9.2 On-Chip RAM .................................................................................................. 250
7.9.3 DTCE Bit Setting.............................................................................................. 250
7.9.4 Chain Transfer .................................................................................................. 250
7.9.5 Transfer Information Start Address, Source Address,
and Destination Address ................................................................................... 250
7.9.6 Endian ............................................................................................................... 250
Section 8 I/O Ports.............................................................................................251
8.1 Register Descriptions........................................................................................................ 257
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8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, B, D to F, H, and I)......... 258
8.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, B, D to F, H, and I)............................ 259
8.1.3 Port Register (PORTn) (n = 1 to 3, 5, 6, A, B, D to F, H, and I) ...................... 259
8.1.4 Input Buffer Control Register (PnICR)
(n = 1 to 3, 5, 6, A, B, D to F, H, and I)............................................................ 260
8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, H, and I)....................... 261
8.1.6 Open-Drain Control Register (PnODR) (n = 2 and F)...................................... 262
8.2 Output Buffer Control....................................................................................................... 262
8.2.1 Port 1................................................................................................................. 262
8.2.2 Port 2................................................................................................................. 265
8.2.3 Port 3................................................................................................................. 269
8.2.4 Port 5................................................................................................................. 273
8.2.5 Port 6................................................................................................................. 274
8.2.6 Port A................................................................................................................ 276
8.2.7 Port B ................................................................................................................ 280
8.2.8 Port D................................................................................................................ 282
8.2.9 Port E ................................................................................................................ 282
8.2.10 Port F ................................................................................................................ 283
8.2.11 Port H................................................................................................................ 286
8.2.12 Port I .................................................................................................................286
8.3 Port Function Controller ................................................................................................... 292
8.3.1 Port Function Control Register 0 (PFCR0)....................................................... 292
8.3.2 Port Function Control Register 1 (PFCR1)....................................................... 293
8.3.3 Port Function Control Register 2 (PFCR2)....................................................... 294
8.3.4 Port Function Control Register 4 (PFCR4)....................................................... 296
8.3.5 Port Function Control Register 6 (PFCR6)....................................................... 297
8.3.6 Port Function Control Register 9 (PFCR9)....................................................... 298
8.3.7 Port Function Control Register B (PFCRB)...................................................... 300
8.3.8 Port Function Control Register C (PFCRC)...................................................... 301
8.4 Usage Notes...................................................................................................................... 303
8.4.1 Notes on Input Buffer Control Register (ICR) Setting ..................................... 303
8.4.2 Notes on Port Function Control Register (PFCR) Settings ............................... 303
Section 9 16-Bit Timer Pulse Unit (TPU) .........................................................305
9.1 Features............................................................................................................................. 305
9.2 Input/Output Pins.............................................................................................................. 309
9.3 Register Descriptions........................................................................................................ 310
9.3.1 Timer Control Register (TCR).......................................................................... 312
9.3.2 Timer Mode Register (TMDR) ......................................................................... 318
9.3.3 Timer I/O Control Register (TIOR) .................................................................. 319
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9.3.4 Timer Interrupt Enable Register (TIER)........................................................... 337
9.3.5 Timer Status Register (TSR)............................................................................. 339
9.3.6 Timer Counter (TCNT)..................................................................................... 343
9.3.7 Timer General Register (TGR) ......................................................................... 343
9.3.8 Timer Start Register (TSTR) ............................................................................ 344
9.3.9 Timer Synchronous Register (TSYR)............................................................... 345
9.4 Operation .......................................................................................................................... 346
9.4.1 Basic Functions................................................................................................. 346
9.4.2 Synchronous Operation..................................................................................... 352
9.4.3 Buffer Operation ............................................................................................... 354
9.4.4 Cascaded Operation .......................................................................................... 357
9.4.5 PWM Modes..................................................................................................... 359
9.4.6 Phase Counting Mode....................................................................................... 364
9.5 Interrupt Sources...............................................................................................................370
9.6 DTC Activation ................................................................................................................ 372
9.7 A/D Converter Activation................................................................................................. 372
9.8 Operation Timing.............................................................................................................. 373
9.8.1 Input/Output Timing ......................................................................................... 373
9.8.2 Interrupt Signal Timing .................................................................................... 377
9.9 Usage Notes...................................................................................................................... 381
9.9.1 Module Stop State Setting ................................................................................ 381
9.9.2 Input Clock Restrictions ................................................................................... 381
9.9.3 Caution on Cycle Setting .................................................................................. 382
9.9.4 Conflict between TCNT Write and Clear Operations....................................... 382
9.9.5 Conflict between TCNT Write and Increment Operations ............................... 383
9.9.6 Conflict between TGR Write and Compare Match........................................... 383
9.9.7 Conflict between Buffer Register Write and Compare Match.......................... 384
9.9.8 Conflict between TGR Read and Input Capture ............................................... 384
9.9.9 Conflict between TGR Write and Input Capture .............................................. 385
9.9.10 Conflict between Buffer Register Write and Input Capture.............................. 386
9.9.11 Conflict between Overflow/Underflow and Counter Clearing ......................... 387
9.9.12 Conflict between TCNT Write and Overflow/Underflow ................................ 387
9.9.13 Multiplexing of I/O Pins................................................................................... 388
9.9.14 Interrupts and Module Stop State ..................................................................... 388
Section 10 Programmable Pulse Generator (PPG)............................................ 389
10.1 Features............................................................................................................................. 389
10.2 Input/Output Pins.............................................................................................................. 391
10.3 Register Descriptions........................................................................................................ 392
10.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ..................................... 392
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10.3.2 Output Data Registers H, L (PODRH, PODRL)............................................... 394
10.3.3 Next Data Registers H, L (NDRH, NDRL) ...................................................... 395
10.3.4 PPG Output Control Register (PCR) ................................................................ 398
10.3.5 PPG Output Mode Register (PMR) .................................................................. 399
10.4 Operation .......................................................................................................................... 401
10.4.1 Output Timing................................................................................................... 401
10.4.2 Sample Setup Procedure for Normal Pulse Output........................................... 402
10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)............ 403
10.4.4 Non-Overlapping Pulse Output......................................................................... 404
10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output........................... 406
10.4.6 Example of Non-Overlapping Pulse Output
(Example of 4-Phase Complementary Non-Overlapping Pulse Output) .......... 407
10.4.7 Inverted Pulse Output ....................................................................................... 409
10.4.8 Pulse Output Triggered by Input Capture ......................................................... 410
10.5 Usage Notes ...................................................................................................................... 410
10.5.1 Module Stop State Setting ................................................................................ 410
10.5.2 Operation of Pulse Output Pins......................................................................... 410
Section 11 8-Bit Timers (TMR).........................................................................411
11.1 Features............................................................................................................................. 411
11.2 Input/Output Pins.............................................................................................................. 414
11.3 Register Descriptions ........................................................................................................ 415
11.3.1 Timer Counter (TCNT)..................................................................................... 416
11.3.2 Time Constant Register A (TCORA)................................................................ 416
11.3.3 Time Constant Register B (TCORB)................................................................ 417
11.3.4 Timer Control Register (TCR).......................................................................... 417
11.3.5 Timer Counter Control Register (TCCR) ......................................................... 419
11.3.6 Timer Control/Status Register (TCSR)............................................................. 421
11.4 Operation .......................................................................................................................... 425
11.4.1 Pulse Output...................................................................................................... 425
11.4.2 Reset Input ........................................................................................................ 426
11.5 Operation Timing.............................................................................................................. 427
11.5.1 TCNT Count Timing ........................................................................................ 427
11.5.2 Timing of CMFA and CMFB Setting at Compare Match................................. 427
11.5.3 Timing of Timer Output at Compare Match..................................................... 428
11.5.4 Timing of Counter Clear by Compare Match ................................................... 428
11.5.5 Timing of TCNT External Reset....................................................................... 429
11.5.6 Timing of Overflow Flag (OVF) Setting ..........................................................429
11.6 Operation with Cascaded Connection............................................................................... 430
11.6.1 16-Bit Counter Mode ........................................................................................430
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11.6.2 Compare Match Count Mode............................................................................ 430
11.7 Interrupt Sources...............................................................................................................431
11.7.1 Interrupt Sources and DTC Activation ............................................................. 431
11.7.2 A/D Converter Activation................................................................................. 431
11.8 Usage Notes ...................................................................................................................... 432
11.8.1 Notes on Setting Cycle ..................................................................................... 432
11.8.2 Conflict between TCNT Write and Clear ......................................................... 432
11.8.3 Conflict between TCNT Write and Increment.................................................. 433
11.8.4 Conflict between TCOR Write and Compare Match........................................ 433
11.8.5 Conflict between Compare Matches A and B................................................... 434
11.8.6 Switching of Internal Clocks and TCNT Operation ......................................... 434
11.8.7 Mode Setting with Cascaded Connection ......................................................... 436
11.8.8 Module Stop State Setting ................................................................................ 436
11.8.9 Interrupts in Module Stop State ........................................................................ 436
Section 12 Watchdog Timer (WDT) .................................................................437
12.1 Features............................................................................................................................. 437
12.2 Input/Output Pin ............................................................................................................... 438
12.3 Register Descriptions........................................................................................................ 438
12.3.1 Timer Counter (TCNT)..................................................................................... 438
12.3.2 Timer Control/Status Register (TCSR)............................................................. 439
12.3.3 Reset Control/Status Register (RSTCSR)......................................................... 441
12.4 Operation .......................................................................................................................... 442
12.4.1 Watchdog Timer Mode..................................................................................... 442
12.4.2 Interval Timer Mode......................................................................................... 444
12.5 Interrupt Source ................................................................................................................444
12.6 Usage Notes ...................................................................................................................... 445
12.6.1 Notes on Register Access ................................................................................. 445
12.6.2 Conflict between Timer Counter (TCNT) Write and Increment....................... 446
12.6.3 Changing Values of Bits CKS2 to CKS0.......................................................... 446
12.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode............. 446
12.6.5 Internal Reset in Watchdog Timer Mode.......................................................... 447
12.6.6 System Reset by WDTOVF Signal................................................................... 447
12.6.7 Transition to Watchdog Timer Mode or Software Standby Mode.................... 447
Section 13 Serial Communication Interface (SCI)............................................ 449
13.1 Features............................................................................................................................. 449
13.2 Input/Output Pins.............................................................................................................. 451
13.3 Register Descriptions........................................................................................................ 452
13.3.1 Receive Shift Register (RSR) ........................................................................... 454
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13.3.2 Receive Data Register (RDR)........................................................................... 454
13.3.3 Transmit Data Register (TDR).......................................................................... 454
13.3.4 Transmit Shift Register (TSR) .......................................................................... 455
13.3.5 Serial Mode Register (SMR) ............................................................................ 455
13.3.6 Serial Control Register (SCR)........................................................................... 458
13.3.7 Serial Status Register (SSR) ............................................................................. 463
13.3.8 Smart Card Mode Register (SCMR)................................................................. 470
13.3.9 Bit Rate Register (BRR) ................................................................................... 471
13.3.10 Serial Extended Mode Register (SEMR) ..........................................................479
13.4 Operation in Asynchronous Mode .................................................................................... 481
13.4.1 Data Transfer Format........................................................................................ 482
13.4.2 Receive Data Sampling Timing
and Reception Margin in Asynchronous Mode................................................. 483
13.4.3 Clock................................................................................................................. 484
13.4.4 SCI Initialization (Asynchronous Mode).......................................................... 485
13.4.5 Serial Data Transmission (Asynchronous Mode) ............................................. 486
13.4.6 Serial Data Reception (Asynchronous Mode)................................................... 488
13.5 Multiprocessor Communication Function......................................................................... 492
13.5.1 Multiprocessor Serial Data Transmission .........................................................494
13.5.2 Multiprocessor Serial Data Reception .............................................................. 495
13.6 Operation in Clocked Synchronous Mode ........................................................................ 498
13.6.1 Clock................................................................................................................. 498
13.6.2 SCI Initialization (Clocked Synchronous Mode).............................................. 499
13.6.3 Serial Data Transmission (Clocked Synchronous Mode) ................................. 500
13.6.4 Serial Data Reception (Clocked Synchronous Mode)....................................... 502
13.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) .......................................................................... 504
13.7 Operation in Smart Card Interface Mode.......................................................................... 506
13.7.1 Sample Connection ........................................................................................... 506
13.7.2 Data Format (Except in Block Transfer Mode) ................................................507
13.7.3 Block Transfer Mode ........................................................................................ 508
13.7.4 Receive Data Sampling Timing and Reception Margin.................................... 509
13.7.5 Initialization ...................................................................................................... 510
13.7.6 Data Transmission (Except in Block Transfer Mode) ...................................... 511
13.7.7 Serial Data Reception (Except in Block Transfer Mode).................................. 514
13.7.8 Clock Output Control........................................................................................ 515
13.8 Interrupt Sources...............................................................................................................517
13.8.1 Interrupts in Normal Serial Communication Interface Mode ........................... 517
13.8.2 Interrupts in Smart Card Interface Mode .......................................................... 518
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13.9 Usage Notes ...................................................................................................................... 519
13.9.1 Module Stop State Setting ................................................................................ 519
13.9.2 Break Detection and Processing ....................................................................... 519
13.9.3 Mark State and Break Detection ....................................................................... 519
13.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ................................................................. 519
13.9.5 Relation between Writing to TDR and TDRE Flag.......................................... 520
13.9.6 Restrictions on Using DTC............................................................................... 520
13.9.7 SCI Operations during Power-Down State ....................................................... 521
Section 14 A/D Converter .................................................................................525
14.1 Features............................................................................................................................. 525
14.2 Input/Output Pins.............................................................................................................. 527
14.3 Register Descriptions........................................................................................................ 527
14.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .......................................... 528
14.3.2 A/D Control/Status Register (ADCSR) ............................................................ 529
14.3.3 A/D Control Register (ADCR) ......................................................................... 531
14.4 Operation .......................................................................................................................... 532
14.4.1 Single Mode...................................................................................................... 532
14.4.2 Scan Mode ........................................................................................................ 533
14.4.3 Input Sampling and A/D Conversion Time ...................................................... 535
14.4.4 External Trigger Input Timing.......................................................................... 537
14.5 Interrupt Source ................................................................................................................537
14.6 A/D Conversion Accuracy Definitions............................................................................. 538
14.7 Usage Notes ...................................................................................................................... 540
14.7.1 Module Stop State Setting ................................................................................ 540
14.7.2 Permissible Signal Source Impedance.............................................................. 540
14.7.3 Influences on Absolute Accuracy ..................................................................... 541
14.7.4 Setting Range of Analog Power Supply and Other Pins................................... 541
14.7.5 Notes on Board Design ..................................................................................... 541
14.7.6 Notes on Noise Countermeasures ..................................................................... 542
14.7.7 A/D Input Hold Function in Software Standby Mode ...................................... 543
Section 15 D/A Converter .................................................................................545
15.1 Features............................................................................................................................. 545
15.2 Input/Output Pins.............................................................................................................. 546
15.3 Register Descriptions........................................................................................................ 546
15.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)......................................... 546
15.3.2 D/A Control Register 01 (DACR01) ................................................................ 547
15.4 Operation .......................................................................................................................... 549
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15.5 Usage Notes ...................................................................................................................... 550
15.5.1 Module Stop State Setting ................................................................................ 550
15.5.2 D/A Output Hold Function in Software Standby Mode.................................... 550
Section 16 RAM ................................................................................................551
Section 17 Clock Pulse Generator .....................................................................553
17.1 Register Description ......................................................................................................... 554
17.1.1 System Clock Control Register (SCKCR) ........................................................554
17.2 Oscillator........................................................................................................................... 557
17.2.1 Connecting Crystal Resonator .......................................................................... 557
17.2.2 External Clock Input......................................................................................... 558
17.3 PLL Circuit ....................................................................................................................... 558
17.4 Frequency Divider ............................................................................................................ 558
17.5 Usage Notes ...................................................................................................................... 559
17.5.1 Notes on Clock Pulse Generator....................................................................... 559
17.5.2 Notes on Resonator........................................................................................... 560
17.5.3 Notes on Board Design .....................................................................................560
Section 18 Power-Down States..........................................................................563
18.1 Features............................................................................................................................. 563
18.2 Register Descriptions ........................................................................................................ 565
18.2.1 Standby Control Register (SBYCR) ................................................................. 566
18.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) .......... 569
18.2.3 Module Stop Control Register C (MSTPCRC)................................................. 572
18.3 Multi-Clock Function ....................................................................................................... 573
18.4 Module Stop Function ...................................................................................................... 573
18.5 Sleep Mode ....................................................................................................................... 574
18.5.1 Transition to Sleep Mode.................................................................................. 574
18.5.2 Clearing Sleep Mode......................................................................................... 574
18.6 All-Module-Clock-Stop Mode.......................................................................................... 575
18.7 Software Standby Mode.................................................................................................... 575
18.7.1 Transition to Software Standby Mode .............................................................. 575
18.7.2 Clearing Software Standby Mode..................................................................... 576
18.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ....... 576
18.7.4 Software Standby Mode Application Example................................................. 579
18.8 Hardware Standby Mode .................................................................................................. 580
18.8.1 Transition to Hardware Standby Mode............................................................. 580
18.8.2 Clearing Hardware Standby Mode.................................................................... 580
18.8.3 Hardware Standby Mode Timing...................................................................... 580
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18.8.4 Timing Sequence at Power-On ......................................................................... 581
18.9 Sleep Instruction Exception Handling .............................................................................. 582
18.10 Bφ Clock Output Control.................................................................................................. 585
18.11 Usage Notes...................................................................................................................... 586
18.11.1 I/O Port Status................................................................................................... 586
18.11.2 Current Consumption during Oscillation Settling Standby Period ................... 586
18.11.3 DTC Module Stop............................................................................................. 586
18.11.4 On-Chip Peripheral Module Interrupts ............................................................. 586
18.11.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC....................................... 586
Section 19 List of Registers............................................................................... 587
19.1 Register Addresses (Address Order)................................................................................. 588
19.2 Register Bits ..................................................................................................................... 597
19.3 Register States in Each Operating Mode .......................................................................... 607
Section 20 Electrical Characteristics .................................................................617
20.1 Absolute Maximum Ratings ............................................................................................. 617
20.2 DC Characteristics ............................................................................................................ 618
20.3 AC Characteristics ............................................................................................................ 621
20.3.1 Clock Timing .................................................................................................... 622
20.3.2 Control Signal Timing ...................................................................................... 624
20.3.3 Bus Timing ....................................................................................................... 625
20.3.4 Timing of On-Chip Peripheral Modules ........................................................... 640
20.4 A/D Conversion Characteristics ....................................................................................... 644
20.5 D/A Conversion Characteristics ....................................................................................... 645
Appendix .............................................................................................................647
A. Port States in Each Pin State............................................................................................. 647
B. Product Lineup..................................................................................................................650
C. Package Dimensions ......................................................................................................... 651
D. Treatment of Unused Pins................................................................................................. 652
Main Revisions and Additions in this Edition..................................................... 655
Index ...................................................................................................................661
Rev.2.00 Jun. 28, 2007 Page xxii of xxii
Section 1 Overview
Section 1 Overview
1.1 Features
The core of each product in the H8SX/1650 Group of CISC (complex instruction set computer)
microcomputers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU
provides upward-compatibility with the CPUs of other Renesas Technology-original
microcomputers; H8/300, H8/300H, and H8S.
As peripheral functions, each LSI of the Group includes a bus-state controller that enables direct
connection to different kinds of memory. The LSI of the Group also includes serial
communication interfaces, A/D and D/A converters, and a multi-function timer that makes motor
control easy. Together, the modules realize low-cost configurations for end systems. The power
consumption of these modules are kept down dynamically by an on-chip power-management
function.
1.1.1 Applications
Examples of the applications of this LSI include PC peripheral equipment, optical storage devices,
office automation equipment, and industrial equipment.
Notes: The following additions and changes have been made in the switch from the H8SX/1650A
to the H8SX/1650C.
• The chip select signal is added to PF7, PF6, and PF5.
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Section 1 Overview
1.1.2 Overview of Functions
Table 1.1 lists the functions of H8SX/1650 Group products in outline.
Table 1.1 Overview of Functions
Module/
Classification
Memory
CPU
Function Description
RAM
CPU
• ROM lineup: ROMless versions only
• RAM capacity: 24 Kbytes
• 32-bit high-speed H8SX CPU (CISC type)
Upward compatibility for H8/300, H8/300H, and H8S CPUs at
object level
• Sixteen 16-bit general registers
• Eleven addressing modes
• 4-Gbyte address space
Program: 4 Gbytes available
Data: 4 Gbytes available
• 87 basic instructions, classifiable as bit arithmetic and logic
instructions, multiply and divide instructions, bit manipulation
instructions, multiply-and-accumulate instructions, and others
• Minimum instruction execution time: 20.0 ns (for an ADD
instruction while system clock Iφ = 50 MHz and
= 3.0 to 3.6 V)
V
CC
• On-chip multiplier (16 × 16 → 32 bits)
• Supports multiply-and-accumulate instructions
(16 × 16 + 32 → 32 bits)
Operating
• Advanced mode
mode
MCU
operating
mode
Mode 4: On-chip ROM disabled external extended mode, 16-bit
bus
(selected by driving the MD0 pin low)
Mode 5: On-chip ROM disabled external extended mode, 8-bit bus
(selected by driving the MD0 pin high)
• Low power consumption state (transition driven by the SLEEP
instruction)
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Module/
Classification
Interrupt
(source)
Function Description
Interrupt
controller
(INTC)
• Thirteen external interrupt pins (NMI, and IRQ11 to IRQ0)
• 56 internal interrupt sources
• Two interrupt control modes (specified by the interrupt control
• Eight priority orders specifiable (by setting the interrupt priority
• Independent vector addresses
DMA Data
• Allows DMA transfer over 45 channels (number of DTC
transfer
controller
(DTC)
• Activated by interrupt sources (chain transfer enabled)
• Three transfer modes (normal transfer, repeat transfer, block
• Short-address mode or full-address mode selectable
External bus
extension
Bus
controller
(BSC)
• 16-Mbyte external address space
• The external address space can be divided into eight areas,
• Bus arbitration function (arbitrates bus mastership among the
Section 1 Overview
register)
register)
activation sources)
transfer)
each of which is independently controllable
Chip-select signals (CS0 to CA7) can be output
Access in two or three states can be selected for each area
Program wait cycles can be inserted
The period of CS assertion can be extended
Idle cycles can be inserted
internal CPU and DTC, and external bus masters)
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Section 1 Overview
Module/
Classification
External bus
extension
Function Description
Bus
controller
(BSC)
Bus formats
• External memory interfaces (for the connection of ROM, burst
ROM, SRAM, and byte control SRAM)
• Address/data bus format: Support for both separate and
multiplexed buses (8-bit access or 16-bit access)
• Endian conversion function for connecting devices in littleendian format
Clock Clock pulse
generator
(CPG)
• One clock generation circuit available
• Separate clock signals are provided for each of functional
modules (detailed below) and each is independently specifiable
(multi-clock function)
System-intended data transfer modules, i.e. the CPU, runs
Internal peripheral functions run in synchronization with the
Modules in the external space are supplied with the external
• Includes a PLL frequency multiplication circuit and frequency
divider, so the operating frequency is selectable
• Five low-power-consumption modes: Sleep mode, module-stop
mode, all-module-clock-stop mode, software standby mode,
and hardware standby mode
A/D converter A/D
converter
(ADC)
• 10-bit resolution × eight input channels
• Sample and hold function included
• Conversion time: 7.4 µs per channel (with peripheral module
clock (Pφ) at 35-MHz operation)
• Two operating modes: single mode and scan mode
• Three ways to start A/D conversion: software, timer (TPU/TMR)
trigger, and external trigger
in synchronization with the system clock (Iφ): 8 to 50 MHz
peripheral module clock (Pφ): 8 to 35 MHz
bus clock (Bφ): 8 to 50 MHz
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Module/
Classification
Function Description
D/A converter D/A
converter
(DAC)
Timer
8-bit timer
(TMR)
16-bit timer
pulse unit
(TPU)
Programmable pulse
generator
(PPG)
Watchdog timer Watchdog
timer
(WDT)
Section 1 Overview
• 8-bit resolution × two output channels
• Output voltage: 0 V to Vref, maximum conversion time: 10 µs
(with 20-pF load)
• 8 bits × four channels (can be used as 16 bits × two channels)
• Select from among seven clock sources (six internal clocks and
one external clock)
• Allows the output of pulse trains with a desired duty cycle or
PWM signals
• 16 bits × six channels (general pulse timer unit)
• Select from among eight counter-input clocks for each channel
• Up to 16 pulse inputs and outputs
• Counter clear operation, simultaneous writing to multiple timer
counters (TCNT), simultaneous clearing by compare match and
input capture possible, simultaneous input/output for registers
possible by counter synchronous operation, and up to 15-phase
PWM output possible by combination with synchronous
operation
• Buffered operation, cascaded operation (32 bits × two
channels), and phase counting mode (two-phase encoder
input) settable for each channel
• Input capture function supported
• Output compare function (by the output of compare match
waveform) supported
• 16-bit pulse output
• Four output groups, non-overlapping mode, and inverted output
can be set
• Selectable output trigger signals; the PPG can operate in
conjunction with the data transfer controller (DTC)
• 8 bits × one channel (selectable from eight counter input clocks)
• Switchable between watchdog timer mode and interval timer
mode
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Section 1 Overview
Module/
Classification
Serial interface
Function Description
Serial
communication
interface
Smart card/
(SCI)
SIM
I/O ports
Package
Operating frequency/
Power supply voltage
Operating peripheral
temperature (°C)
• Four channels (select asynchronous or clocked synchronous
serial communication mode)
• Full-duplex communication capability
• Select the desired bit rate and LSB-first or MSB-first transfer
• The SCI module supports a smart card (SIM) interface.
• Eight CMOS input-only pins
• 50 CMOS input/output pins
• Eight large-current drive pins (port 3)
• 11 pull-up resistors
• 11 open drains
• 120-pin thin QFP package (package code: FP-120B, package
dimensions: 14 × 14 mm, pin pitch: 0.40 mm)
• Lead- (Pb-) free versions available
• Operating frequency: 8 to 50 MHz
• Power supply voltage: Vcc = 3.0 to 3.6 V, Avcc = 3.0 to 3.6 V
• Supply current:
45 mA (typ.) (Vcc = 3.3 V, Avcc = 3.3 V, Iφ = Bφ = 50 MHz,
Pφ = 25 MHz)
• −20 to +75°C (regular specifications)
• −40 to +85°C (wide-range specifications)
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Section 1 Overview
1.2 List of Products
Table 1.2 is the list of products, and figure 1.1 shows how to read the product name code.
Table 1.2 List of Products
Product Type No. ROM Capacity RAM Capacity Package Remarks
R5S61650CFPV 24 Kbytes PLQP0120LA-A
(FP-120BV)
(as of August, 2005)
ROMless versions
only
Product type no. R 5 S 61650C FP
Figure 1.1 How to Read the Product Name Code
V
Indicates the Pb-free version.
Indicates the package.
FP: LQFP
Indicates the product-specific number.
H8SX/1650 Group
Indicates the type of ROM device.
S: External ROM
Indicates the product classification
Microcomputer
R indicates a Renesas semiconductor product.
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Section 1 Overview
1.3 Block Diagram
RAM
H8SX
CPU
DTC
Clock pulse
generator
WDT
Interrupt
controller
BSC
Internal system bus
Internal peripheral bus
TMR (unit 0)
× 2 channels
TMR (unit 1)
× 2 channels
TPU × 6 channels
PPG
SCI × 4 channels
A/D converter
D/A converter
Por t 1
Por t 2
Por t 3
Por t 5
Por t 6
Por t A
Por t B
Por t D
Por t E
Por t F
Por t H
External bus
[Legend]
CPU:
Central processing unit
DTC:
Data transfer controller
BSC:
Bus controller
WDT:
Watchdog timer
TMR:
8-bit timer
TPU:
16-bit timer pulse unit
PPG:
Programmable pulse generator
SCI:
Serial communications interface
Figure 1.2 Block Diagram
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Por t I
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