REJ09B0311-0200
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
H8SX/1650C R5S61650C
H8SX/1650Group
Hardware Manual
Renesas 32-Bit CISC Microcomputer
H8SX Family / H8SX/1600 Series
All information contained in this material, including products and product
specifications at the time of publication of this material, is subject to change by
Renesas Technology Corp. without notice. Please review the latest information
published by Renesas Technology Corp. through various means, including the
Renesas Technology Corp. website (http://www.renesas.com).
Rev.2.00
Revision Date: Jun. 28, 2007
Rev.2.00 Jun. 28, 2007 Page ii of xxii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev.2.00 Jun. 28, 2007 Page iii of xxii
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different type numbers, implement a system-evaluation test for
each of the products.
Rev.2.00 Jun. 28, 2007 Page iv of xxii
How to Use This Manual
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the H8SX/1650 Group. Before using any of
the documents, please visit our web site to verify that you have the most up-to-date available
version of the document.
Document Type Contents Document Title Document No.
Data Sheet Overview of hardware and electrical
characteristics
Hardware Manual Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
Software Manual Detailed descriptions of the CPU
and instruction set
Application Note Examples of applications and
sample programs
Renesas Technical
Update
Preliminary report on the
specifications of a product,
document, etc.
H8SX/1650 Group
Hardware Manual
H8SX Family Software
Manual
The latest versions are available from our
web site.
This manual
REJ09B0102
Rev.2.00 Jun. 28, 2007 Page v of xxii
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary: B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal: 1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
(2)
Rev. 0.50, 10/04, page 416 of 914
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Rev.2.00 Jun. 28, 2007 Page vi of xxii
(3)
3. Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of
bits, describing the meanings of the bit settings. The standard format and notation for bit charts
and tables are described below.
[Bit Chart]
Initial value:
[Table of Bits]
Bit:
1514131211109876543210
ASID1 ASID0 ACMP1 ACMP0
0000001000000000
R/W:
R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W
(1) (2) (3) (4)
Bit
15
14
13 to 11
10
9
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this
Bit Name Initial Value R/W Description
−
−
ASID2 to
ASID0
−
−
−
manual.
0
0
All 0
0
1
0
R
Reserved
R
These bits are always read as 0.
R/W
Address Identifier
These bits enable or disable the pin function.
R
Reserved
This bit is always read as 0.
R
Reserved
This bit is always read as 1.
ASID2
ACMP2Q
(5)
IFE
(1) Bit
Indicates the bit number or numbers.
In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case
of a 16-bit register, the bits are arranged in order from 15 to 0.
(2) Bit name
Indicates the name of the bit or bit field.
When the number of bits has to be clearly indicated in the field, appropriate notation is
included (e.g., ASID[3:0]).
A reserved bit is indicated by "−".
Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such
cases, the entry under Bit Name is blank.
(3) Initial value
Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.
0: The initial value is 0
1: The initial value is 1
−: The initial value is undefined
(4) R/W
For each bit and bit field, this entry indicates whether the bit or field is readable or writable,
or both writing to and reading from the bit or field are impossible.
The notation is as follows:
R/W:
The bit or field is readable and writable.
R/(W):
The bit or field is readable and writable.
However, writing is only performed to flag clearing.
R:
The bit or field is readable.
"R" is indicated for all reserved bits. When writing to the register, write
the value under Initial Value in the bit chart to reserved bits or fields.
W:
The bit or field is writable.
(5) Description
Describes the function of the bit or field and specifies the values for writing.
Rev.2.00 Jun. 28, 2007 Page vii of xxii
4. Description of Abbreviations
The abbreviations used in this manual are listed below.
•
Abbreviations specific to this product
Abbreviation Description
BSC Bus controller
CPG Clock pulse generator
DTC Data transfer controller
INTC Interrupt controller
PPG Programmable pulse generator
SCI Serial communication interface
TMR 8-bit timer
TPU 16-bit timer pulse unit
WDT Watchdog timer
• Abbreviations other than those listed above
Abbreviation Description
ACIA Asynchronous communication interface adapter
bps Bits per second
CRC Cyclic redundancy check
DMA Direct memory access
DMAC Direct memory access controller
GSM Global System for Mobile Communications
Hi-Z High impedance
IEBus Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.)
I/O Input/output
IrDA Infrared Data Association
LSB Least significant bit
MSB Most significant bit
NC No connection
PLL Phase-locked loop
PWM Pulse width modulation
SFR Special function register
SIM Subscriber Identity Module
UART Universal asynchronous receiver/transmitter
VCO Voltage-controlled oscillator
All trademarks and registered trademarks are the property of their respective owners.
Rev.2.00 Jun. 28, 2007 Page viii of xxii
Contents
Section 1 Overview................................................................................................1
1.1 Features................................................................................................................................. 1
1.1.1 Applications ..........................................................................................................1
1.1.2 Overview of Functions.......................................................................................... 2
1.2 List of Products..................................................................................................................... 7
1.3 Block Diagram...................................................................................................................... 8
1.4 Pin Assignments ...................................................................................................................9
1.5 Pin Functions ......................................................................................................................10
Section 2 CPU......................................................................................................15
2.1 Features............................................................................................................................... 15
2.2 CPU Operating Modes........................................................................................................ 17
2.2.1 Normal Mode...................................................................................................... 17
2.2.2 Middle Mode....................................................................................................... 19
2.2.3 Advanced Mode .................................................................................................. 20
2.2.4 Maximum Mode ................................................................................................. 21
2.3 Instruction Fetch ................................................................................................................. 23
2.4 Address Space..................................................................................................................... 23
2.5 Registers .............................................................................................................................24
2.5.1 General Registers ................................................................................................ 25
2.5.2 Program Counter (PC) ........................................................................................26
2.5.3 Condition-Code Register (CCR) ......................................................................... 26
2.5.4 Extended Control Register (EXR) ...................................................................... 28
2.5.5 Vector Base Register (VBR)............................................................................... 28
2.5.6 Short Address Base Register (SBR).................................................................... 28
2.5.7 Multiply-Accumulate Register (MAC) ............................................................... 29
2.5.8 Initial Register Values......................................................................................... 29
2.6 Data Formats....................................................................................................................... 30
2.6.1 General Register Data Formats ........................................................................... 30
2.6.2 Memory Data Formats ........................................................................................ 31
2.7 Instruction Set..................................................................................................................... 32
2.7.1 Instructions and Addressing Modes.................................................................... 34
2.7.2 Table of Instructions Classified by Function ...................................................... 38
2.7.3 Basic Instruction Formats ...................................................................................49
2.8 Addressing Modes and Effective Address Calculation....................................................... 50
2.8.1 Register Direct—Rn ........................................................................................... 51
Rev.2.00 Jun. 28, 2007 Page ix of xxii
2.8.2 Register Indirect—@ERn ................................................................................... 51
2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn), or
@(d:32, ERn)...................................................................................................... 51
2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)................. 51
2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,
or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− ............................ 52
2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32................................... 53
2.8.7 Immediate—#xx:8, #xx:16, or #xx:32................................................................ 54
2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) .................................. 55
2.8.9 Program-Counter Relative with Index Register—
@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC).............................................. 55
2.8.10 Memory Indirect—@@aa:8 ............................................................................... 55
2.8.11 Extended Memory Indirect—@@vec:7 ............................................................. 56
2.8.12 Effective Address Calculation ............................................................................ 56
2.8.13 MOVA Instruction.............................................................................................. 58
2.9 Processing States ................................................................................................................ 59
Section 3 MCU Operating Modes .......................................................................61
3.1 Operating Mode Selection .................................................................................................. 61
3.2 Register Descriptions.......................................................................................................... 62
3.2.1 Mode Control Register (MDCR) ........................................................................ 62
3.2.2 System Control Register (SYSCR) ..................................................................... 64
3.3 Operating Mode Descriptions............................................................................................. 66
3.3.1 Mode 4 ................................................................................................................ 66
3.3.2 Mode 5 ................................................................................................................ 66
3.3.3 Pin Functions ...................................................................................................... 67
3.4 Address Map....................................................................................................................... 68
3.4.1 Address Map (Advanced Mode) ......................................................................... 68
Section 4 Exception Handling............................................................................. 69
4.1 Exception Handling Types and Priority.............................................................................. 69
4.2 Exception Sources and Exception Handling Vector Table................................................. 70
4.3 Reset ................................................................................................................................... 72
4.3.1 Reset Exception Handling .................................................................................. 72
4.3.2 Interrupts after Reset........................................................................................... 73
4.3.3 On-Chip Peripheral Functions after Reset Release............................................. 73
4.4 Traces Exception Handling................................................................................................. 75
4.5 Address Error...................................................................................................................... 76
4.5.1 Address Error Source.......................................................................................... 76
Rev.2.00 Jun. 28, 2007 Page x of xxii
4.5.2 Address Error Exception Handling ..................................................................... 77
4.6 Interrupts............................................................................................................................. 78
4.6.1 Interrupt Sources................................................................................................. 78
4.6.2 Interrupt Exception Handling ............................................................................. 78
4.7 Instruction Exception Handling.......................................................................................... 79
4.7.1 Trap Instruction Exception Handling.................................................................. 79
4.7.2 Sleep Instruction Exception Handling ................................................................ 80
4.7.3 Exception Handling by Illegal Instruction .......................................................... 81
4.8 Stack Status after Exception Handling................................................................................ 82
4.9 Usage Note.......................................................................................................................... 83
Section 5 Interrupt Controller ..............................................................................85
5.1 Features............................................................................................................................... 85
5.2 Input/Output Pins................................................................................................................ 87
5.3 Register Descriptions.......................................................................................................... 87
5.3.1 Interrupt Control Register (INTCR) ................................................................... 88
5.3.2 CPU Priority Control Register (CPUPCR) .........................................................89
5.3.3 Interrupt Priority Registers A to C, E to H, K, and L
(IPRA to IPRC, IPRE to IPRH, IPRK, and IPRL).............................................. 90
5.3.4 IRQ Enable Register (IER) .................................................................................92
5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................... 94
5.3.6 IRQ Status Register (ISR)................................................................................... 98
5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................. 99
5.4 Interrupt Sources...............................................................................................................100
5.4.1 External Interrupts ............................................................................................ 100
5.4.2 Internal Interrupts ............................................................................................. 101
5.5 Interrupt Exception Handling Vector Table...................................................................... 102
5.6 Interrupt Control Modes and Interrupt Operation............................................................. 106
5.6.1 Interrupt Control Mode 0 .................................................................................. 106
5.6.2 Interrupt Control Mode 2 .................................................................................. 108
5.6.3 Interrupt Exception Handling Sequence ........................................................... 110
5.6.4 Interrupt Response Times .................................................................................111
5.6.5 DTC Activation by Interrupt............................................................................. 112
5.7 CPU Priority Control Function Over DTC ....................................................................... 115
5.8 Usage Notes...................................................................................................................... 117
5.8.1 Conflict between Interrupt Generation and Disabling ...................................... 117
5.8.2 Instructions that Disable Interrupts ................................................................... 118
5.8.3 Times when Interrupts are Disabled ................................................................. 118
5.8.4 Interrupts during Execution of EEPMOV Instruction....................................... 118
5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions................ 118
Rev.2.00 Jun. 28, 2007 Page xi of xxii
5.8.6 Interrupts Source Flag of Peripheral Modules .................................................. 119
Section 6 Bus Controller (BSC) ........................................................................121
6.1 Features............................................................................................................................. 121
6.2 Register Descriptions........................................................................................................ 124
6.2.1 Bus Width Control Register (ABWCR)............................................................ 124
6.2.2 Access State Control Register (ASTCR) .......................................................... 126
6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 127
6.2.4 Read Strobe Timing Control Register (RDNCR) ............................................. 132
6.2.5 CS Assertion Period Control Registers (CSACR) ............................................ 133
6.2.6 Idle Control Register (IDLCR) ......................................................................... 135
6.2.7 Bus Control Register 1 (BCR1) ........................................................................ 137
6.2.8 Bus Control Register 2 (BCR2) ........................................................................ 139
6.2.9 Endian Control Register (ENDIANCR) ........................................................... 140
6.2.10 SRAM Mode Control Register (SRAMCR) ..................................................... 141
6.2.11 Burst ROM Interface Control Register (BROMCR) ........................................ 142
6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR)............................. 144
6.3 Bus Configuration............................................................................................................. 145
6.4 Multi-Clock Function and Number of Access Cycles ...................................................... 146
6.5 External Bus ..................................................................................................................... 150
6.5.1 Input/Output Pins.............................................................................................. 150
6.5.2 Area Division.................................................................................................... 153
6.5.3 Chip Select Signals ........................................................................................... 154
6.5.4 External Bus Interface ...................................................................................... 155
6.5.5 Area and External Bus Interface ....................................................................... 159
6.5.6 Endian and Data Alignment.............................................................................. 163
6.6 Basic Bus Interface........................................................................................................... 167
6.6.1 Data Bus ........................................................................................................... 167
6.6.2 I/O Pins Used for Basic Bus Interface .............................................................. 167
6.6.3 Basic Timing..................................................................................................... 168
6.6.4 Wait Control ..................................................................................................... 174
6.6.5 Read Strobe (RD) Timing ................................................................................. 176
6.6.6 Extension of Chip Select (CS) Assertion Period............................................... 177
6.7 Byte Control SRAM Interface .......................................................................................... 179
6.7.1 Byte Control SRAM Space Setting................................................................... 179
6.7.2 Data Bus ........................................................................................................... 179
6.7.3 I/O Pins Used for Byte Control SRAM Interface ............................................. 180
6.7.4 Basic Timing..................................................................................................... 181
6.7.5 Wait Control ..................................................................................................... 183
6.7.6 Read Strobe (RD) ............................................................................................. 185
Rev.2.00 Jun. 28, 2007 Page xii of xxii
6.7.7 Extension of Chip Select (CS) Assertion Period............................................... 185
6.8 Burst ROM Interface ........................................................................................................ 185
6.8.1 Burst ROM Space Setting ................................................................................. 185
6.8.2 Data Bus............................................................................................................ 186
6.8.3 I/O Pins Used for Burst ROM Interface............................................................ 186
6.8.4 Basic Timing..................................................................................................... 187
6.8.5 Wait Control ..................................................................................................... 189
6.8.6 Read Strobe (RD) Timing .................................................................................189
6.8.7 Extension of Chip Select (CS) Assertion Period............................................... 189
6.9 Address/Data Multiplexed I/O Interface........................................................................... 189
6.9.1 Address/Data Multiplexed I/O Space Setting ................................................... 189
6.9.2 Address/Data Multiplex .................................................................................... 190
6.9.3 Data Bus............................................................................................................ 190
6.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface .............................. 191
6.9.5 Basic Timing..................................................................................................... 192
6.9.6 Address Cycle Control...................................................................................... 194
6.9.7 Wait Control ..................................................................................................... 195
6.9.8 Read Strobe (RD) Timing .................................................................................195
6.9.9 Extension of Chip Select (CS) Assertion Period............................................... 196
6.10 Idle Cycle.......................................................................................................................... 198
6.10.1 Operation .......................................................................................................... 198
6.10.2 Pin States in Idle Cycle..................................................................................... 206
6.11 Bus Release....................................................................................................................... 207
6.11.1 Operation .......................................................................................................... 207
6.11.2 Pin States in External Bus Released State......................................................... 208
6.11.3 Transition Timing ............................................................................................. 209
6.12 Internal Bus....................................................................................................................... 210
6.12.1 Access to Internal Address Space ..................................................................... 210
6.13 Write Data Buffer Function .............................................................................................. 211
6.13.1 Write Data Buffer Function for External Data Bus........................................... 211
6.13.2 Write Data Buffer Function for Peripheral Modules ........................................ 212
6.14 Bus Arbitration .................................................................................................................213
6.14.1 Operation .......................................................................................................... 213
6.14.2 Bus Transfer Timing......................................................................................... 214
6.15 Bus Controller Operation in Reset .................................................................................... 215
6.16 Usage Notes ...................................................................................................................... 215
Section 7 Data Transfer Controller (DTC) ........................................................217
7.1 Features............................................................................................................................. 217
7.2 Register Descriptions........................................................................................................ 219
Rev.2.00 Jun. 28, 2007 Page xiii of xxii
7.2.1 DTC Mode Register A (MRA) ......................................................................... 220
7.2.2 DTC Mode Register B (MRB).......................................................................... 221
7.2.3 DTC Source Address Register (SAR)............................................................... 223
7.2.4 DTC Destination Address Register (DAR)....................................................... 223
7.2.5 DTC Transfer Count Register A (CRA) ........................................................... 224
7.2.6 DTC Transfer Count Register B (CRB)............................................................ 224
7.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) .................................. 225
7.2.8 DTC Control Register (DTCCR) ...................................................................... 226
7.2.9 DTC Vector Base Register (DTCVBR)............................................................ 227
7.3 Activation Sources............................................................................................................ 227
7.4 Location of Transfer Information and DTC Vector Table................................................ 228
7.5 Operation .......................................................................................................................... 231
7.5.1 Bus Cycle Division ........................................................................................... 233
7.5.2 Transfer Information Read Skip Function ........................................................ 235
7.5.3 Transfer Information Writeback Skip Function................................................ 236
7.5.4 Normal Transfer Mode ..................................................................................... 236
7.5.5 Repeat Transfer Mode ...................................................................................... 237
7.5.6 Block Transfer Mode ........................................................................................ 239
7.5.7 Chain Transfer .................................................................................................. 240
7.5.8 Operation Timing.............................................................................................. 241
7.5.9 Number of DTC Execution Cycles ................................................................... 243
7.5.10 DTC Bus Release Timing ................................................................................. 244
7.5.11 DTC Priority Level Control to the CPU ........................................................... 244
7.6 DTC Activation by Interrupt............................................................................................. 245
7.7 Examples of Use of the DTC............................................................................................ 246
7.7.1 Normal Transfer Mode ..................................................................................... 246
7.7.2 Chain Transfer .................................................................................................. 247
7.7.3 Chain Transfer when Counter = 0..................................................................... 248
7.8 Interrupt Sources...............................................................................................................249
7.9 Usage Notes...................................................................................................................... 249
7.9.1 Module Stop State Setting ................................................................................ 249
7.9.2 On-Chip RAM .................................................................................................. 250
7.9.3 DTCE Bit Setting.............................................................................................. 250
7.9.4 Chain Transfer .................................................................................................. 250
7.9.5 Transfer Information Start Address, Source Address,
and Destination Address ................................................................................... 250
7.9.6 Endian ............................................................................................................... 250
Section 8 I/O Ports.............................................................................................251
8.1 Register Descriptions........................................................................................................ 257
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8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, B, D to F, H, and I)......... 258
8.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, B, D to F, H, and I)............................ 259
8.1.3 Port Register (PORTn) (n = 1 to 3, 5, 6, A, B, D to F, H, and I) ...................... 259
8.1.4 Input Buffer Control Register (PnICR)
(n = 1 to 3, 5, 6, A, B, D to F, H, and I)............................................................ 260
8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, H, and I)....................... 261
8.1.6 Open-Drain Control Register (PnODR) (n = 2 and F)...................................... 262
8.2 Output Buffer Control....................................................................................................... 262
8.2.1 Port 1................................................................................................................. 262
8.2.2 Port 2................................................................................................................. 265
8.2.3 Port 3................................................................................................................. 269
8.2.4 Port 5................................................................................................................. 273
8.2.5 Port 6................................................................................................................. 274
8.2.6 Port A................................................................................................................ 276
8.2.7 Port B ................................................................................................................ 280
8.2.8 Port D................................................................................................................ 282
8.2.9 Port E ................................................................................................................ 282
8.2.10 Port F ................................................................................................................ 283
8.2.11 Port H................................................................................................................ 286
8.2.12 Port I .................................................................................................................286
8.3 Port Function Controller ................................................................................................... 292
8.3.1 Port Function Control Register 0 (PFCR0)....................................................... 292
8.3.2 Port Function Control Register 1 (PFCR1)....................................................... 293
8.3.3 Port Function Control Register 2 (PFCR2)....................................................... 294
8.3.4 Port Function Control Register 4 (PFCR4)....................................................... 296
8.3.5 Port Function Control Register 6 (PFCR6)....................................................... 297
8.3.6 Port Function Control Register 9 (PFCR9)....................................................... 298
8.3.7 Port Function Control Register B (PFCRB)...................................................... 300
8.3.8 Port Function Control Register C (PFCRC)...................................................... 301
8.4 Usage Notes...................................................................................................................... 303
8.4.1 Notes on Input Buffer Control Register (ICR) Setting ..................................... 303
8.4.2 Notes on Port Function Control Register (PFCR) Settings ............................... 303
Section 9 16-Bit Timer Pulse Unit (TPU) .........................................................305
9.1 Features............................................................................................................................. 305
9.2 Input/Output Pins.............................................................................................................. 309
9.3 Register Descriptions........................................................................................................ 310
9.3.1 Timer Control Register (TCR).......................................................................... 312
9.3.2 Timer Mode Register (TMDR) ......................................................................... 318
9.3.3 Timer I/O Control Register (TIOR) .................................................................. 319
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9.3.4 Timer Interrupt Enable Register (TIER)........................................................... 337
9.3.5 Timer Status Register (TSR)............................................................................. 339
9.3.6 Timer Counter (TCNT)..................................................................................... 343
9.3.7 Timer General Register (TGR) ......................................................................... 343
9.3.8 Timer Start Register (TSTR) ............................................................................ 344
9.3.9 Timer Synchronous Register (TSYR)............................................................... 345
9.4 Operation .......................................................................................................................... 346
9.4.1 Basic Functions................................................................................................. 346
9.4.2 Synchronous Operation..................................................................................... 352
9.4.3 Buffer Operation ............................................................................................... 354
9.4.4 Cascaded Operation .......................................................................................... 357
9.4.5 PWM Modes..................................................................................................... 359
9.4.6 Phase Counting Mode....................................................................................... 364
9.5 Interrupt Sources...............................................................................................................370
9.6 DTC Activation ................................................................................................................ 372
9.7 A/D Converter Activation................................................................................................. 372
9.8 Operation Timing.............................................................................................................. 373
9.8.1 Input/Output Timing ......................................................................................... 373
9.8.2 Interrupt Signal Timing .................................................................................... 377
9.9 Usage Notes...................................................................................................................... 381
9.9.1 Module Stop State Setting ................................................................................ 381
9.9.2 Input Clock Restrictions ................................................................................... 381
9.9.3 Caution on Cycle Setting .................................................................................. 382
9.9.4 Conflict between TCNT Write and Clear Operations....................................... 382
9.9.5 Conflict between TCNT Write and Increment Operations ............................... 383
9.9.6 Conflict between TGR Write and Compare Match........................................... 383
9.9.7 Conflict between Buffer Register Write and Compare Match.......................... 384
9.9.8 Conflict between TGR Read and Input Capture ............................................... 384
9.9.9 Conflict between TGR Write and Input Capture .............................................. 385
9.9.10 Conflict between Buffer Register Write and Input Capture.............................. 386
9.9.11 Conflict between Overflow/Underflow and Counter Clearing ......................... 387
9.9.12 Conflict between TCNT Write and Overflow/Underflow ................................ 387
9.9.13 Multiplexing of I/O Pins................................................................................... 388
9.9.14 Interrupts and Module Stop State ..................................................................... 388
Section 10 Programmable Pulse Generator (PPG)............................................ 389
10.1 Features............................................................................................................................. 389
10.2 Input/Output Pins.............................................................................................................. 391
10.3 Register Descriptions........................................................................................................ 392
10.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ..................................... 392
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10.3.2 Output Data Registers H, L (PODRH, PODRL)............................................... 394
10.3.3 Next Data Registers H, L (NDRH, NDRL) ...................................................... 395
10.3.4 PPG Output Control Register (PCR) ................................................................ 398
10.3.5 PPG Output Mode Register (PMR) .................................................................. 399
10.4 Operation .......................................................................................................................... 401
10.4.1 Output Timing................................................................................................... 401
10.4.2 Sample Setup Procedure for Normal Pulse Output........................................... 402
10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)............ 403
10.4.4 Non-Overlapping Pulse Output......................................................................... 404
10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output........................... 406
10.4.6 Example of Non-Overlapping Pulse Output
(Example of 4-Phase Complementary Non-Overlapping Pulse Output) .......... 407
10.4.7 Inverted Pulse Output ....................................................................................... 409
10.4.8 Pulse Output Triggered by Input Capture ......................................................... 410
10.5 Usage Notes ...................................................................................................................... 410
10.5.1 Module Stop State Setting ................................................................................ 410
10.5.2 Operation of Pulse Output Pins......................................................................... 410
Section 11 8-Bit Timers (TMR).........................................................................411
11.1 Features............................................................................................................................. 411
11.2 Input/Output Pins.............................................................................................................. 414
11.3 Register Descriptions ........................................................................................................ 415
11.3.1 Timer Counter (TCNT)..................................................................................... 416
11.3.2 Time Constant Register A (TCORA)................................................................ 416
11.3.3 Time Constant Register B (TCORB)................................................................ 417
11.3.4 Timer Control Register (TCR).......................................................................... 417
11.3.5 Timer Counter Control Register (TCCR) ......................................................... 419
11.3.6 Timer Control/Status Register (TCSR)............................................................. 421
11.4 Operation .......................................................................................................................... 425
11.4.1 Pulse Output...................................................................................................... 425
11.4.2 Reset Input ........................................................................................................ 426
11.5 Operation Timing.............................................................................................................. 427
11.5.1 TCNT Count Timing ........................................................................................ 427
11.5.2 Timing of CMFA and CMFB Setting at Compare Match................................. 427
11.5.3 Timing of Timer Output at Compare Match..................................................... 428
11.5.4 Timing of Counter Clear by Compare Match ................................................... 428
11.5.5 Timing of TCNT External Reset....................................................................... 429
11.5.6 Timing of Overflow Flag (OVF) Setting ..........................................................429
11.6 Operation with Cascaded Connection............................................................................... 430
11.6.1 16-Bit Counter Mode ........................................................................................430
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11.6.2 Compare Match Count Mode............................................................................ 430
11.7 Interrupt Sources...............................................................................................................431
11.7.1 Interrupt Sources and DTC Activation ............................................................. 431
11.7.2 A/D Converter Activation................................................................................. 431
11.8 Usage Notes ...................................................................................................................... 432
11.8.1 Notes on Setting Cycle ..................................................................................... 432
11.8.2 Conflict between TCNT Write and Clear ......................................................... 432
11.8.3 Conflict between TCNT Write and Increment.................................................. 433
11.8.4 Conflict between TCOR Write and Compare Match........................................ 433
11.8.5 Conflict between Compare Matches A and B................................................... 434
11.8.6 Switching of Internal Clocks and TCNT Operation ......................................... 434
11.8.7 Mode Setting with Cascaded Connection ......................................................... 436
11.8.8 Module Stop State Setting ................................................................................ 436
11.8.9 Interrupts in Module Stop State ........................................................................ 436
Section 12 Watchdog Timer (WDT) .................................................................437
12.1 Features............................................................................................................................. 437
12.2 Input/Output Pin ............................................................................................................... 438
12.3 Register Descriptions........................................................................................................ 438
12.3.1 Timer Counter (TCNT)..................................................................................... 438
12.3.2 Timer Control/Status Register (TCSR)............................................................. 439
12.3.3 Reset Control/Status Register (RSTCSR)......................................................... 441
12.4 Operation .......................................................................................................................... 442
12.4.1 Watchdog Timer Mode..................................................................................... 442
12.4.2 Interval Timer Mode......................................................................................... 444
12.5 Interrupt Source ................................................................................................................444
12.6 Usage Notes ...................................................................................................................... 445
12.6.1 Notes on Register Access ................................................................................. 445
12.6.2 Conflict between Timer Counter (TCNT) Write and Increment....................... 446
12.6.3 Changing Values of Bits CKS2 to CKS0.......................................................... 446
12.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode............. 446
12.6.5 Internal Reset in Watchdog Timer Mode.......................................................... 447
12.6.6 System Reset by WDTOVF Signal................................................................... 447
12.6.7 Transition to Watchdog Timer Mode or Software Standby Mode.................... 447
Section 13 Serial Communication Interface (SCI)............................................ 449
13.1 Features............................................................................................................................. 449
13.2 Input/Output Pins.............................................................................................................. 451
13.3 Register Descriptions........................................................................................................ 452
13.3.1 Receive Shift Register (RSR) ........................................................................... 454
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13.3.2 Receive Data Register (RDR)........................................................................... 454
13.3.3 Transmit Data Register (TDR).......................................................................... 454
13.3.4 Transmit Shift Register (TSR) .......................................................................... 455
13.3.5 Serial Mode Register (SMR) ............................................................................ 455
13.3.6 Serial Control Register (SCR)........................................................................... 458
13.3.7 Serial Status Register (SSR) ............................................................................. 463
13.3.8 Smart Card Mode Register (SCMR)................................................................. 470
13.3.9 Bit Rate Register (BRR) ................................................................................... 471
13.3.10 Serial Extended Mode Register (SEMR) ..........................................................479
13.4 Operation in Asynchronous Mode .................................................................................... 481
13.4.1 Data Transfer Format........................................................................................ 482
13.4.2 Receive Data Sampling Timing
and Reception Margin in Asynchronous Mode................................................. 483
13.4.3 Clock................................................................................................................. 484
13.4.4 SCI Initialization (Asynchronous Mode).......................................................... 485
13.4.5 Serial Data Transmission (Asynchronous Mode) ............................................. 486
13.4.6 Serial Data Reception (Asynchronous Mode)................................................... 488
13.5 Multiprocessor Communication Function......................................................................... 492
13.5.1 Multiprocessor Serial Data Transmission .........................................................494
13.5.2 Multiprocessor Serial Data Reception .............................................................. 495
13.6 Operation in Clocked Synchronous Mode ........................................................................ 498
13.6.1 Clock................................................................................................................. 498
13.6.2 SCI Initialization (Clocked Synchronous Mode).............................................. 499
13.6.3 Serial Data Transmission (Clocked Synchronous Mode) ................................. 500
13.6.4 Serial Data Reception (Clocked Synchronous Mode)....................................... 502
13.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) .......................................................................... 504
13.7 Operation in Smart Card Interface Mode.......................................................................... 506
13.7.1 Sample Connection ........................................................................................... 506
13.7.2 Data Format (Except in Block Transfer Mode) ................................................507
13.7.3 Block Transfer Mode ........................................................................................ 508
13.7.4 Receive Data Sampling Timing and Reception Margin.................................... 509
13.7.5 Initialization ...................................................................................................... 510
13.7.6 Data Transmission (Except in Block Transfer Mode) ...................................... 511
13.7.7 Serial Data Reception (Except in Block Transfer Mode).................................. 514
13.7.8 Clock Output Control........................................................................................ 515
13.8 Interrupt Sources...............................................................................................................517
13.8.1 Interrupts in Normal Serial Communication Interface Mode ........................... 517
13.8.2 Interrupts in Smart Card Interface Mode .......................................................... 518
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13.9 Usage Notes ...................................................................................................................... 519
13.9.1 Module Stop State Setting ................................................................................ 519
13.9.2 Break Detection and Processing ....................................................................... 519
13.9.3 Mark State and Break Detection ....................................................................... 519
13.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ................................................................. 519
13.9.5 Relation between Writing to TDR and TDRE Flag.......................................... 520
13.9.6 Restrictions on Using DTC............................................................................... 520
13.9.7 SCI Operations during Power-Down State ....................................................... 521
Section 14 A/D Converter .................................................................................525
14.1 Features............................................................................................................................. 525
14.2 Input/Output Pins.............................................................................................................. 527
14.3 Register Descriptions........................................................................................................ 527
14.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .......................................... 528
14.3.2 A/D Control/Status Register (ADCSR) ............................................................ 529
14.3.3 A/D Control Register (ADCR) ......................................................................... 531
14.4 Operation .......................................................................................................................... 532
14.4.1 Single Mode...................................................................................................... 532
14.4.2 Scan Mode ........................................................................................................ 533
14.4.3 Input Sampling and A/D Conversion Time ...................................................... 535
14.4.4 External Trigger Input Timing.......................................................................... 537
14.5 Interrupt Source ................................................................................................................537
14.6 A/D Conversion Accuracy Definitions............................................................................. 538
14.7 Usage Notes ...................................................................................................................... 540
14.7.1 Module Stop State Setting ................................................................................ 540
14.7.2 Permissible Signal Source Impedance.............................................................. 540
14.7.3 Influences on Absolute Accuracy ..................................................................... 541
14.7.4 Setting Range of Analog Power Supply and Other Pins................................... 541
14.7.5 Notes on Board Design ..................................................................................... 541
14.7.6 Notes on Noise Countermeasures ..................................................................... 542
14.7.7 A/D Input Hold Function in Software Standby Mode ...................................... 543
Section 15 D/A Converter .................................................................................545
15.1 Features............................................................................................................................. 545
15.2 Input/Output Pins.............................................................................................................. 546
15.3 Register Descriptions........................................................................................................ 546
15.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)......................................... 546
15.3.2 D/A Control Register 01 (DACR01) ................................................................ 547
15.4 Operation .......................................................................................................................... 549
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15.5 Usage Notes ...................................................................................................................... 550
15.5.1 Module Stop State Setting ................................................................................ 550
15.5.2 D/A Output Hold Function in Software Standby Mode.................................... 550
Section 16 RAM ................................................................................................551
Section 17 Clock Pulse Generator .....................................................................553
17.1 Register Description ......................................................................................................... 554
17.1.1 System Clock Control Register (SCKCR) ........................................................554
17.2 Oscillator........................................................................................................................... 557
17.2.1 Connecting Crystal Resonator .......................................................................... 557
17.2.2 External Clock Input......................................................................................... 558
17.3 PLL Circuit ....................................................................................................................... 558
17.4 Frequency Divider ............................................................................................................ 558
17.5 Usage Notes ...................................................................................................................... 559
17.5.1 Notes on Clock Pulse Generator....................................................................... 559
17.5.2 Notes on Resonator........................................................................................... 560
17.5.3 Notes on Board Design .....................................................................................560
Section 18 Power-Down States..........................................................................563
18.1 Features............................................................................................................................. 563
18.2 Register Descriptions ........................................................................................................ 565
18.2.1 Standby Control Register (SBYCR) ................................................................. 566
18.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) .......... 569
18.2.3 Module Stop Control Register C (MSTPCRC)................................................. 572
18.3 Multi-Clock Function ....................................................................................................... 573
18.4 Module Stop Function ...................................................................................................... 573
18.5 Sleep Mode ....................................................................................................................... 574
18.5.1 Transition to Sleep Mode.................................................................................. 574
18.5.2 Clearing Sleep Mode......................................................................................... 574
18.6 All-Module-Clock-Stop Mode.......................................................................................... 575
18.7 Software Standby Mode.................................................................................................... 575
18.7.1 Transition to Software Standby Mode .............................................................. 575
18.7.2 Clearing Software Standby Mode..................................................................... 576
18.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ....... 576
18.7.4 Software Standby Mode Application Example................................................. 579
18.8 Hardware Standby Mode .................................................................................................. 580
18.8.1 Transition to Hardware Standby Mode............................................................. 580
18.8.2 Clearing Hardware Standby Mode.................................................................... 580
18.8.3 Hardware Standby Mode Timing...................................................................... 580
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18.8.4 Timing Sequence at Power-On ......................................................................... 581
18.9 Sleep Instruction Exception Handling .............................................................................. 582
18.10 Bφ Clock Output Control.................................................................................................. 585
18.11 Usage Notes...................................................................................................................... 586
18.11.1 I/O Port Status................................................................................................... 586
18.11.2 Current Consumption during Oscillation Settling Standby Period ................... 586
18.11.3 DTC Module Stop............................................................................................. 586
18.11.4 On-Chip Peripheral Module Interrupts ............................................................. 586
18.11.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC....................................... 586
Section 19 List of Registers............................................................................... 587
19.1 Register Addresses (Address Order)................................................................................. 588
19.2 Register Bits ..................................................................................................................... 597
19.3 Register States in Each Operating Mode .......................................................................... 607
Section 20 Electrical Characteristics .................................................................617
20.1 Absolute Maximum Ratings ............................................................................................. 617
20.2 DC Characteristics ............................................................................................................ 618
20.3 AC Characteristics ............................................................................................................ 621
20.3.1 Clock Timing .................................................................................................... 622
20.3.2 Control Signal Timing ...................................................................................... 624
20.3.3 Bus Timing ....................................................................................................... 625
20.3.4 Timing of On-Chip Peripheral Modules ........................................................... 640
20.4 A/D Conversion Characteristics ....................................................................................... 644
20.5 D/A Conversion Characteristics ....................................................................................... 645
Appendix .............................................................................................................647
A. Port States in Each Pin State............................................................................................. 647
B. Product Lineup..................................................................................................................650
C. Package Dimensions ......................................................................................................... 651
D. Treatment of Unused Pins................................................................................................. 652
Main Revisions and Additions in this Edition..................................................... 655
Index ...................................................................................................................661
Rev.2.00 Jun. 28, 2007 Page xxii of xxii
Section 1 Overview
Section 1 Overview
1.1 Features
The core of each product in the H8SX/1650 Group of CISC (complex instruction set computer)
microcomputers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU
provides upward-compatibility with the CPUs of other Renesas Technology-original
microcomputers; H8/300, H8/300H, and H8S.
As peripheral functions, each LSI of the Group includes a bus-state controller that enables direct
connection to different kinds of memory. The LSI of the Group also includes serial
communication interfaces, A/D and D/A converters, and a multi-function timer that makes motor
control easy. Together, the modules realize low-cost configurations for end systems. The power
consumption of these modules are kept down dynamically by an on-chip power-management
function.
1.1.1 Applications
Examples of the applications of this LSI include PC peripheral equipment, optical storage devices,
office automation equipment, and industrial equipment.
Notes: The following additions and changes have been made in the switch from the H8SX/1650A
to the H8SX/1650C.
• The chip select signal is added to PF7, PF6, and PF5.
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Section 1 Overview
1.1.2 Overview of Functions
Table 1.1 lists the functions of H8SX/1650 Group products in outline.
Table 1.1 Overview of Functions
Module/
Classification
Memory
CPU
Function Description
RAM
CPU
• ROM lineup: ROMless versions only
• RAM capacity: 24 Kbytes
• 32-bit high-speed H8SX CPU (CISC type)
Upward compatibility for H8/300, H8/300H, and H8S CPUs at
object level
• Sixteen 16-bit general registers
• Eleven addressing modes
• 4-Gbyte address space
Program: 4 Gbytes available
Data: 4 Gbytes available
• 87 basic instructions, classifiable as bit arithmetic and logic
instructions, multiply and divide instructions, bit manipulation
instructions, multiply-and-accumulate instructions, and others
• Minimum instruction execution time: 20.0 ns (for an ADD
instruction while system clock Iφ = 50 MHz and
= 3.0 to 3.6 V)
V
CC
• On-chip multiplier (16 × 16 → 32 bits)
• Supports multiply-and-accumulate instructions
(16 × 16 + 32 → 32 bits)
Operating
• Advanced mode
mode
MCU
operating
mode
Mode 4: On-chip ROM disabled external extended mode, 16-bit
bus
(selected by driving the MD0 pin low)
Mode 5: On-chip ROM disabled external extended mode, 8-bit bus
(selected by driving the MD0 pin high)
• Low power consumption state (transition driven by the SLEEP
instruction)
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Module/
Classification
Interrupt
(source)
Function Description
Interrupt
controller
(INTC)
• Thirteen external interrupt pins (NMI, and IRQ11 to IRQ0)
• 56 internal interrupt sources
• Two interrupt control modes (specified by the interrupt control
• Eight priority orders specifiable (by setting the interrupt priority
• Independent vector addresses
DMA Data
• Allows DMA transfer over 45 channels (number of DTC
transfer
controller
(DTC)
• Activated by interrupt sources (chain transfer enabled)
• Three transfer modes (normal transfer, repeat transfer, block
• Short-address mode or full-address mode selectable
External bus
extension
Bus
controller
(BSC)
• 16-Mbyte external address space
• The external address space can be divided into eight areas,
• Bus arbitration function (arbitrates bus mastership among the
Section 1 Overview
register)
register)
activation sources)
transfer)
each of which is independently controllable
Chip-select signals (CS0 to CA7) can be output
Access in two or three states can be selected for each area
Program wait cycles can be inserted
The period of CS assertion can be extended
Idle cycles can be inserted
internal CPU and DTC, and external bus masters)
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Section 1 Overview
Module/
Classification
External bus
extension
Function Description
Bus
controller
(BSC)
Bus formats
• External memory interfaces (for the connection of ROM, burst
ROM, SRAM, and byte control SRAM)
• Address/data bus format: Support for both separate and
multiplexed buses (8-bit access or 16-bit access)
• Endian conversion function for connecting devices in littleendian format
Clock Clock pulse
generator
(CPG)
• One clock generation circuit available
• Separate clock signals are provided for each of functional
modules (detailed below) and each is independently specifiable
(multi-clock function)
System-intended data transfer modules, i.e. the CPU, runs
Internal peripheral functions run in synchronization with the
Modules in the external space are supplied with the external
• Includes a PLL frequency multiplication circuit and frequency
divider, so the operating frequency is selectable
• Five low-power-consumption modes: Sleep mode, module-stop
mode, all-module-clock-stop mode, software standby mode,
and hardware standby mode
A/D converter A/D
converter
(ADC)
• 10-bit resolution × eight input channels
• Sample and hold function included
• Conversion time: 7.4 µs per channel (with peripheral module
clock (Pφ) at 35-MHz operation)
• Two operating modes: single mode and scan mode
• Three ways to start A/D conversion: software, timer (TPU/TMR)
trigger, and external trigger
in synchronization with the system clock (Iφ): 8 to 50 MHz
peripheral module clock (Pφ): 8 to 35 MHz
bus clock (Bφ): 8 to 50 MHz
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Module/
Classification
Function Description
D/A converter D/A
converter
(DAC)
Timer
8-bit timer
(TMR)
16-bit timer
pulse unit
(TPU)
Programmable pulse
generator
(PPG)
Watchdog timer Watchdog
timer
(WDT)
Section 1 Overview
• 8-bit resolution × two output channels
• Output voltage: 0 V to Vref, maximum conversion time: 10 µs
(with 20-pF load)
• 8 bits × four channels (can be used as 16 bits × two channels)
• Select from among seven clock sources (six internal clocks and
one external clock)
• Allows the output of pulse trains with a desired duty cycle or
PWM signals
• 16 bits × six channels (general pulse timer unit)
• Select from among eight counter-input clocks for each channel
• Up to 16 pulse inputs and outputs
• Counter clear operation, simultaneous writing to multiple timer
counters (TCNT), simultaneous clearing by compare match and
input capture possible, simultaneous input/output for registers
possible by counter synchronous operation, and up to 15-phase
PWM output possible by combination with synchronous
operation
• Buffered operation, cascaded operation (32 bits × two
channels), and phase counting mode (two-phase encoder
input) settable for each channel
• Input capture function supported
• Output compare function (by the output of compare match
waveform) supported
• 16-bit pulse output
• Four output groups, non-overlapping mode, and inverted output
can be set
• Selectable output trigger signals; the PPG can operate in
conjunction with the data transfer controller (DTC)
• 8 bits × one channel (selectable from eight counter input clocks)
• Switchable between watchdog timer mode and interval timer
mode
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Section 1 Overview
Module/
Classification
Serial interface
Function Description
Serial
communication
interface
Smart card/
(SCI)
SIM
I/O ports
Package
Operating frequency/
Power supply voltage
Operating peripheral
temperature (°C)
• Four channels (select asynchronous or clocked synchronous
serial communication mode)
• Full-duplex communication capability
• Select the desired bit rate and LSB-first or MSB-first transfer
• The SCI module supports a smart card (SIM) interface.
• Eight CMOS input-only pins
• 50 CMOS input/output pins
• Eight large-current drive pins (port 3)
• 11 pull-up resistors
• 11 open drains
• 120-pin thin QFP package (package code: FP-120B, package
dimensions: 14 × 14 mm, pin pitch: 0.40 mm)
• Lead- (Pb-) free versions available
• Operating frequency: 8 to 50 MHz
• Power supply voltage: Vcc = 3.0 to 3.6 V, Avcc = 3.0 to 3.6 V
• Supply current:
45 mA (typ.) (Vcc = 3.3 V, Avcc = 3.3 V, Iφ = Bφ = 50 MHz,
Pφ = 25 MHz)
• −20 to +75°C (regular specifications)
• −40 to +85°C (wide-range specifications)
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Section 1 Overview
1.2 List of Products
Table 1.2 is the list of products, and figure 1.1 shows how to read the product name code.
Table 1.2 List of Products
Product Type No. ROM Capacity RAM Capacity Package Remarks
R5S61650CFPV 24 Kbytes PLQP0120LA-A
(FP-120BV)
(as of August, 2005)
ROMless versions
only
Product type no. R 5 S 61650C FP
Figure 1.1 How to Read the Product Name Code
V
Indicates the Pb-free version.
Indicates the package.
FP: LQFP
Indicates the product-specific number.
H8SX/1650 Group
Indicates the type of ROM device.
S: External ROM
Indicates the product classification
Microcomputer
R indicates a Renesas semiconductor product.
Rev.2.00 Jun. 28, 2007 Page 7 of 666
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Section 1 Overview
1.3 Block Diagram
RAM
H8SX
CPU
DTC
Clock pulse
generator
WDT
Interrupt
controller
BSC
Internal system bus
Internal peripheral bus
TMR (unit 0)
× 2 channels
TMR (unit 1)
× 2 channels
TPU × 6 channels
PPG
SCI × 4 channels
A/D converter
D/A converter
Por t 1
Por t 2
Por t 3
Por t 5
Por t 6
Por t A
Por t B
Por t D
Por t E
Por t F
Por t H
External bus
[Legend]
CPU:
Central processing unit
DTC:
Data transfer controller
BSC:
Bus controller
WDT:
Watchdog timer
TMR:
8-bit timer
TPU:
16-bit timer pulse unit
PPG:
Programmable pulse generator
SCI:
Serial communications interface
Figure 1.2 Block Diagram
Rev.2.00 Jun. 28, 2007 Page 8 of 666
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Por t I
1.4 Pin Assignments
Section 1 Overview
P62/TMO2/SCK4/IRQ10-B
P56/AN6/DA0/IRQ6-B
P57/AN7/DA1/IRQ7-B
PB0/CS0/CS4-A/CS5-B
PLLVcc
P63/TMRI3/IRQ11-B
PLLVss
P64/TMCI3
P65/TMO3
MD0
P50/AN0/IRQ0-B
P51/AN1/IRQ1-B
P52/AN2/IRQ2-B
AVcc
P53/AN3/IRQ3-B
AVss
P54/AN4/IRQ4-B
Vref
P55/AN5/IRQ5-B
PA0/BREQO/BS-A
PA1/BACK/(RD/WR)
MD1
PA2/BREQ/WAIT
PA3/LLWR/LLB
PA4/LHWR/LUB
PA5/RD
PA6/AS/AH/BS-B
PA7/Bφ
Vss
Vcc
P60/TMRI2/TxD4/IRQ8-B
STBY
P17/IRQ7-A/TCLKD-B
P16/IRQ6-A/TCLKC-B
Vcc
P61/TMCI2/RxD4/IRQ9-B
9089888786858483828180797877767574737271706968676665646362
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
1234567891011121314151617181920212223242526272829
EXTAL
MD2
PF6/A22/CS6-D
PF5/A21/CS5-D
PB3/CS3/CS7-A
PB2/CS2-A/CS6-A
CL
XTAL
Vss
WDTOVF
P15/IRQ5-A/TCLKB-B
P14/IRQ4-A/TCLKA-B
V
P12/SCK2/IRQ2-A
P11/RxD2/IRQ1-A
P10/TxD2/IRQ0-A
PI7/D15
P13/ADTRG0/IRQ3-A
Vss
PE5/A13
PE4/A12
Vcc
PE3/A11
PI6/D14
PE2/A10
RES
Vss
H8SX/1650 Group
PLQP0120LA-A (FP-120BV)
(top view)
Vss
PF4/A20
PF3/A19
PF2/A18
PF1/A17
PF0/A16
PE7/A15
PE6/A14
PI5/D13
PI4/D12
PE1/A9
PE0/A8
Vss
PI3/D11
PD7/A7
PD6/A6
PI2/D10
PI1/D9
Vss
PD5/A5
cc
PI0/D8
V
PD4/A4
PD3/A3
PH7/D7
61
60
PH6/D6
59
PH5/D5
58
PH4/D4
57
Vss
56
PH3/D3
55
PH2/D2
54
PH1/D1
53
PH0/D0
52
NMI
51
P37/PO15/TIOCA2/TIOCB2/TCLKD-A
50
P36/PO14/TIOCA2
49
P35/PO13/TIOCA1/TIOCB1/TCLKC-A
48
P34/PO12/TIOCA1
47
P33/PO11/TIOCC0/TIOCD0/TCLKB-A
46
P32/PO10/TIOCC0/TCLKA-A
45
P31/PO9/TIOCA0/TIOCB0
44
Vcc
43
P30/PO8/TIOCA0
42
Vss
41
P27/PO7/TIOCA5/TIOCB5
40
P26/PO6/TIOCA5/TMO1/TxD1
39
P25/PO5/TIOCA4/TMCI1/RxD1
38
P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1
37
P23/PO3/TIOCC3/TIOCD3/IRQ11-A
36
P22/PO2/TIOCC3/TMO0/TxD0/IRQ10-A
P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A
35
P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A
34
EMLE
33
PD0/A0
32
PD1/A1
31
30
PD2/A2
PF7/A23/CS4-C/CS5-C/CS6-C/CS7-C
PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B
Figure 1.3 Pin Assignments
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Section 1 Overview
1.5 Pin Functions
Table 1.3 Pin Functions
Classification Pin Name I/O Description
Power supply V
V
V
PLLVCC Power supply pin for the PLL circuit.
PLLVSS Ground pin for the PLL circuit.
Clock XTAL Input
EXTAL Input
Bφ Output Outputs the system clock for external devices.
Operating mode
control
System control RES Input Reset signal input pin. This LSI enters the reset state when
STBY Input This LSI enters hardware standby mode when this signal
EMLE Input Input pin for the on-chip emulator enable signal. The signal
Address bus A23 to A0 Output Output pins for the address bits.
Data bus D15 to D0 Input/
Bus control BREQ Input External bus-master modules assert this signal to request
BREQO Output Internal bus-master modules assert this signal to request
Power supply pins. Connect them to the system power
CC
supply.
Connect this pin to VSS via a 0.1-uF capacitor (The capacitor
CL
should be placed close to the pin).
Ground pins. Connect them to the system power supply
SS
(0 V).
Pins for a crystal resonator. An external clock signal can be
input through the EXTAL pin. For an example of this
connection, see section 17, Clock Pulse Generator.
MD2 to MD0 Input Pins for setting the operating mode. The signal levels on
these pins must not be changed during operation.
this signal goes low.
goes low.
level should normally be fixed low.
Input and output for the bidirectional data bus. These pins
output
also output addresses when accessing an address–data
multiplexed I/O interface space.
the bus.
access to the external space via the bus in the external bus
released state.
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Section 1 Overview
Classification Pin Name I/O Description
Bus control BACK Output Bus acknowledge signal, which indicates that the bus has
been released.
BS-A/BS-B Output Indicates the start of a bus cycle.
AS Output Strobe signal which indicates that the output address on the
address bus is valid in access to the basic bus interface or
byte control SRAM interface space.
AH Output This signal is used to hold the address when accessing the
address-data multiplexed I/O interface space.
RD Output Strobe signal which indicates that reading from the basic
bus interface space is in progress.
RD/WR Output Indicates the direction (input or output) of the data bus.
LHWR Output Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the basic bus interface
space.
LLWR Output Strobe signal which indicates that the lower-order byte (D7
to D0) is valid in access to the basic bus interface space.
LUB Output Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the byte control SRAM
interface space.
LLB Output Strobe signal which indicates that the lower-order byte (D7
to D0) is valid in access to the byte control SRAM interface
space.
CS0
CS1
CS2-A/CS2-B
CS3
CS4-A/CS4-C
CS5-A/CS5-B/
CS5-C/CS5-D
CS6-A/CS6-B/
CS6-C/CS6-D
CS7-A/CS7-B/
CS7-C
WAIT Input Requests wait cycles in access to the external space.
Output Select signals for areas 0 to 7.
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Section 1 Overview
Classification Pin Name I/O Description
Interrupt NMI Input Non-maskable interrupt request signal. When this pin is not
in use, this signal must be fixed high.
IRQ11-A/IRQ11-B
IRQ10-A/IRQ10-B
IRQ9-A/IRQ9-B
IRQ8-A/IRQ8-B
IRQ7-A/IRQ7-B
IRQ6-A/IRQ6-B
IRQ5-A/IRQ5-B
IRQ4-A/IRQ4-B
IRQ3-A/IRQ3-B
IRQ2-A/IRQ2-B
IRQ1-A/IRQ1-B
IRQ0-A/IRQ0-B
16-bit timer
pulse unit (TPU)
TIOCA0
TIOCA1
TCLKA-A/TCLKA-B
TCLKB-A/TCLKB-B
TCLKC-A/TCLKC-B
TCLKD-A/TCLKD-B
TIOCB0
TIOCC0
TIOCD0
TIOCB1
Input Maskable interrupt request signal.
Input Input pins for the external clock signals.
Input/
output
Input/
output
Signals for TGRA_0 to TGRD_0. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
Signals for TGRA_1 and TGRB_1. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
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Classification Pin Name I/O Description
16-bit timer
pulse unit (TPU)
TIOCA3
TIOCA4
TIOCA5
Programmable
pulse generator
(PPG)
8-bit timer
(TMR)
Watchdog timer
(WDT)
Serial
communication
interface (SCI)
RxD0 to RxD4 Input Input pins for data reception.
SCK0 to SCK4 Input/
TIOCA2
TIOCB2
TIOCB3
TIOCC3
TIOCD3
TIOCB4
TIOCB5
PO15 to PO0 Output Output pins for the pulse signals.
TMO0 to TMO3 Output Output pins for the compare match signals.
TMCI0 to TMCI3 Input Input pins for the external clock signals that drive for the
TMRI0 to TMRI3 Input Input pins for the counter-reset signals.
WDTOVF Output Output pin for the counter-overflow signal in watchdog-timer
TxD0 to TxD4 Output Output pins for data transmission.
Input/
output
Input/
output
Input/
output
Input/
output
output
Signals for TGRA_2 and TGRB_2. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
Signals for TGRA_3 to TGRD_3. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
Signals for TGRA_4 and TGRB_4. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
Signals for TGRA_5 and TGRB_5. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
counters.
mode.
Input/output pins for clock signals.
Section 1 Overview
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Section 1 Overview
Classification Pin Name I/O Description
A/D converter AN7 to AN0 Input Input pins for the analog signals to be processed by the A/D
converter.
ADTRG0 Input Input pin for the external trigger signal that starts A/D
conversion.
D/A converter DA1
DA0
A/D converter,
D/A converter
AVSS Ground pin for the A/D and D/A converters. Connect this pin
Vref Reference power supply pin for the A/D and D/A converters.
I/O ports P17 to P10 Input/
P27 to P20 Input/
P37 to P30 Input/
P57 to P50 Input 8 input/output pins.
P65 to P60 Input/
PA6, PA4
PB3 to PB0 Input/
PF7 to PF5 Input/
PI7 to PI0 Input/
AVCC Analog power supply pin for the A/D and D/A converters.
PA2 to PA0
Output Output pins for the analog signals from the D/A converter.
When the A/D and D/A converters are not in use, connect
this pin to the system power supply.
to the system power supply (0 V).
When the A/D and D/A converters are not in use, connect
this pin to the system power supply.
8 input/output pins.
output
8 input/output pins.
output
8 input/output pins.
output
6 input/output pins.
output
Input/
output
output
output
output
5 input/output pins.
4 input/output pins.
3 input/output pins.
8 input/output pins.
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Section 2 CPU
Section 2 CPU
The H8SX CPU is a high-speed central processing unit with an internal 32-bit architecture that is
upward-compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control
system.
2.1 Features
• High-speed CPU that is upward-compatible with H8/300, H8/300H, and H8S CPUs
Can execute these CPU's object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• 87 basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Bit field transfer instructions
Powerful bit-manipulation instructions
Bit condition branch instructions
Multiply-and-accumulate instruction
• Eleven addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)]
Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W),
@(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)]
Register indirect with post-/pre-increment or post-/pre-decrement
[@+ERn/@−ERn/@ERn+/@ERn−]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or @(ERn.L,PC)]
Memory indirect [@@aa:8]
Extended memory indirect [@@vec:7]
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Section 2 CPU
• Two base registers
Vector base register
Short address base register
• 4-Gbyte address space
Program: 4 Gbytes
Data: 4 Gbytes
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 1 state
16 ÷ 8-bit register-register divide: 10 states
16 × 16-bit register-register multiply: 1 state
32 ÷ 16-bit register-register divide: 18 states
32 × 32-bit register-register multiply: 5 states
32 ÷ 32-bit register-register divide: 18 states
• Four CPU operating modes
Normal mode
Middle mode
Advanced mode
Maximum mode
• Power-down modes
Transition is made by execution of SLEEP instruction
Choice of CPU operating clocks
Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1650
Group. Normal, middle, and maximum modes are not supported.
2. The multiplier and divider are supported by the H8SX/1650 Group.
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Section 2 CPU
2.2 CPU Operating Modes
The H8SX CPU has four operating modes: normal, middle, advanced, and maximum modes. As
for selecting the mode, see section 3.1, Operating Mode Selection.
Normal mode
Middle mode
CPU operating modes
Advanced mode
Maximum mode
Maximum 64 Kbytes for program
and data areas combined
Maximum 16-Mbyte program
area and 64-Kbyte data area,
maximum 16 Mbytes for program
and data areas combined
Maximum 16-Mbyte program
area and 4-Gbyte data area,
maximum 4 Gbytes for program
and data areas combined
Maximum 4 Gbytes for program
and data areas combined
Figure 2.1 CPU Operating Modes
2.2.1 Normal Mode
In normal mode, the exception handling vector table and stack have the same structure as in the
H8/300 CPU.
Note This LSI does not support this mode.
• Address Space
A maximum address space of 64 kbytes can be accessed.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even
when the corresponding general register (Rn) is used as an address register. If the general
register Rn is referenced in the register indirect addressing mode with pre-/post-increment or
decrement and a carry or borrow occurs, however, the value in the corresponding extended
register will be affected.
• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
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Section 2 CPU
• Exception Handling Vector Table and Memory Indirect Branch Addresses
In normal mode, the top area starting at H'0000 is allocated to the exception handling vector
table. One branch address is stored per 16 bits. The structure of the exception handling vector
table is shown in figure 2.2.
H'0000
H'0001
H'0002
H'0003
Reset exception vector
Reset exception vector
Exception
vector table
Figure 2.2 Exception Handling Vector Table (Normal Mode)
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are
used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code
specifies a memory location. Execution branches to the address contained in the memory location.
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling branch are shown in figure 2.3. The PC contents are saved or restored in 16-bit units.
SP SP
PC
(16 bits)
(SP )
2
*
1
EXR*
Reserved*1,*
CCR
3
CCR*
PC
(16 bits)
3
(a) Subroutine Branch (b) Exception Handling
Notes: 1.
When EXR is not used it is not stored on the stack.
SP when EXR is not used.
2.
Ignored on return.
3.
Figure 2.3 Stack Structure in Normal Mode
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Section 2 CPU
2.2.2 Middle Mode
The program area in middle mode is extended to 16 Mbytes as compared with that in normal
mode.
• Address Space
A maximum address space of 16 Mbytes can be accessed in a total of the program and data
areas. For individual areas, up to 16 Mbytes of the program area and up to 64 Kbytes of the
data area can be allocated.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. When En is used as a 16-bit register (in other than the JMP and
JSR instructions), it can contain any value even when the corresponding general register (Rn)
is used as an address register. If the general register Rn is referenced in the register indirect
addressing mode with pre-/post-increment or decrement and a carry or borrow occurs,
however, the value in the corresponding extended register will be affected.
• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid and the upper eight bits are sign-extended.
• Exception Handling Vector Table and Memory Indirect Branch Addresses
In middle mode, the top area starting at H'000000 is allocated to the exception handling vector
table in 32-bit units. In each 32 bits, the upper eight bits are ignored and one branch address is
stored in the lower 24 bits. The structure of the exception handling vector table is shown in
figure 2.4.
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address.
The upper eight bits are reserved and assumed to be H'00.
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling branch are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.
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Section 2 CPU
2.2.3 Advanced Mode
The data area in advanced mode is extended to 4 Gbytes as compared with that in middle mode.
• Address Space
A maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16
Mbytes of the program area and up to 4 Gbytes of the data area can be allocated.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.
• Instruction Set
All instructions and addressing modes can be used.
• Exception Handling Vector Table and Memory Indirect Branch Addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception handling
vector table in 32-bit units. In each 32 bits, the upper eight bits are ignored and one branch
address is stored in the lower 24 bits. The structure of the exception handling vector table is
shown in figure 2.4.
H'00000000
H'00000001
H'00000002
H'00000003
H'00000004
H'00000005
H'00000006
H'00000007
Reserved
Reset exception vector
Reserved
Exception vector table
Figure 2.4 Exception Handling Vector Table (Middle and Advanced Modes)
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are
used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code
specifies a memory location. Execution branches to the contents of the memory location.
In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address.
The upper eight bits are eserved and assumed to be H'00.
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Section 2 CPU
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling branch are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.
1
SP
SP
Reserved
PC
(24 bits)
(a) Subroutine Branch (b) Exception Handling
2
*
(SP )
EXR*
Reserved*1,*
CCR
PC
(24 bits)
3
Notes: 1.
When EXR is not used it is not stored on the stack.
SP when EXR is not used.
2.
Ignored on return.
3.
Figure 2.5 Stack Structure in Middle and Advanced Modes
2.2.4 Maximum Mode
The program area in maximum mode is extended to 4 Gbytes as compared with that in advanced
mode.
• Address Space
A maximum address space of 4 Gbytes can be linearly accessed.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit
segments of 32-bit registers or address registers.
• Instruction Set
All instructions and addressing modes can be used.
• Exception Handling Vector Table and Memory Indirect Branch Addresses
In maximum mode, the top area starting at H'00000000 is allocated to the exception handling
vector table in 32-bit units. One branch address is stored in 32 bits. The structure of the
exception handling vector table is shown in figure 2.6.
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Section 2 CPU
H'00000000
H'00000001
H'00000002
H'00000003
H'00000004
H'00000005
H'00000006
H'00000007
Reset exception vector
Exception vector table
Figure 2.6 Exception Handling Vector Table (Maximum Modes)
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are
used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code
specifies a memory location. Execution branches to the contents of the memory location.
In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address.
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling branch are shown in figure 2.7. The PC contents are saved or restored in 32-bit units.
The EXR contents are saved or restored regardless of whether or not EXR is in use.
SP
PC
(32 bits)
(a) Subroutine Branch (b) Exception Handling
SP
Figure 2.7 Stack Structure in Maximum Mode
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EXR
CCR
PC
(32 bits)
Section 2 CPU
2.3 Instruction Fetch
The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended
that the mode should be set according to the bus width of the memory in which the program is
stored.
The instruction-fetch mode setting does not affect operation other than instruction fetch such as
data accesses. The FETCHMD bit in SYSCR selects one of the two modes. For details, see section
3.2.2, System Control Register (SYSCR).
2.4 Address Space
Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the
operating mode.
Normal mode
H'0000 H'000000
H'007FFF
Program area
Data area
H'FFFF
(64 Kbytes)
H'FF8000
H'FFFFFF
Middle mode Advanced mode
H'00000000
Program area
(16 Mbytes)
Data area
(64 Kbytes)
H'00FFFFFF
H'FFFFFFFF
Figure 2.8 Memory Map
H'00000000
Program area
(16 Mbytes)
Data area
(4 Gbytes)
H'FFFFFFFF
Maximum mode
Program area
Data area
(4 Gbytes)
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Section 2 CPU
2.5 Registers
The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers:
general registers and control registers. The control registers are the 32-bit program counter (PC),
8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base
register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register
(MAC).
General Registers and Extended Registers
15 07 07 0
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
Control Registers
[Legend]
SP:
PC:
CCR:
I:
UI:
H:
U:
N:
31 0
PC
31 012
VBR
31 08
SBR
63
MAC
Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag
Sign extension
MACL
Zero flag
Z:
Overflow flag
V:
Carry flag
C:
Extended control register
EXR:
Trace bit
T:
Interrupt mask bits
I2 to I0:
Vector base register
VBR:
Short address base register
SBR:
Multiply-accumulate register
MAC:
Figure 2.9 CPU Registers
76543210
CCR
7654321
EXR
(Reserved)
IUIHUNZVC
0
T————I2I1I0
(Reserved)
3241
MACH
031
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Section 2 CPU
2.5.1 General Registers
The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike
and can be used as both address registers and data registers. When a general register is used as a
data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the
usage of the general registers.
When the general registers are used as 32-bit registers or address registers, they are designated by
the letters ER (ER0 to ER7).
The ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7)
and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16bit registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H)
and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of
sixteen 8-bit registers.
The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index
registers. The size in the operand field determines which register is selected.
The usage of each register can be selected independently.
16-bit registers
Address registers
•
32-bit registers
•
32-bit index registers
•
General registers ER
(ER0 to ER7)
•
General registers E
(E0 to E7)
16-bit registers
•
16-bit index registers
•
General registers R
(R0 to R7)
8-bit registers
•
General registers RH
(R0H to R7H)
8-bit registers
•
8-bit index registers
•
General registers RL
(R0L to R7L)
Figure 2.10 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.11 shows the
stack.
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Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.11 Stack
2.5.2 Program Counter (PC)
PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The
length of all CPU instructions is two bytes (one word) or a multiple of two bytes, so the least
significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.
2.5.3 Condition-Code Register (CCR)
CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask
(I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C)
flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Initial
Bit Bit Name
7 I 1 R/W Interrupt Mask Bit
6 UI Undefined R/W User Bit or Interrupt Mask Bit
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Value R/W Description
Masks interrupts when set to 1. This bit is set to 1 at the
start of an exception-handling sequence.
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions. This bit can
also be used as an interrupt mask bit.
Initial
Bit Bit Name
Value R/W Description
5 H Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4 U Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3 N Undefined R/W Negative Flag
Stores the value of the most significant bit (regarded as
sign bit) of data.
2 Z Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1 V Undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.
0 C Undefined R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. A carry flag indicates the following:
• A carry by an add instruction
• A borrow by a subtract instruction
• A carry by a shift or rotate instruction
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
Section 2 CPU
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Section 2 CPU
2.5.4 Extended Control Register (EXR)
EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0).
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instructions.
For details, see section 4, Exception Handling.
Initial
Bit Bit Name
7 T 0 R/W Trace Bit
6 to 3 All 1 R/W Reserved
2
1
0
I2
I1
I0
Value R/W Description
Selects trace mode. When this bit is cleared to 0,
instructions are executed in sequence. When this bit is
set to 1, a trace exception is generated each time an
instruction is executed.
These bits are always read as 1. The write value should
always be 1.
1
1
1
R/W
R/W
R/W
Interrupt Mask Bits
These bits designate the interrupt mask level (0 to 7).
2.5.5 Vector Base Register (VBR)
VBR is a 32-bit register that has the valid upper 20 bits. The lower 12 bits of this register are read
as 0s. This register value is a base address of the vector area for exception handling other than a
reset and a CPU address error (extended memory indirect is also out of the target). The initial
value is H'00000000.
2.5.6 Short Address Base Register (SBR)
SBR is a 32-bit register that has the valid upper 24 bits. The lower eight bits are read as 0s. In 8-bit
absolute addressing mode (@aa:8), this register is used as the upper address. The initial value is
H'FFFFFF00.
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Section 2 CPU
2.5.7 Multiply-Accumulate Register (MAC)
MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists
of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the
upper bits are sign-extended.
2.5.8 Initial Register Values
Reset exception handling loads the start address from the vector table into the PC contents, clears
the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR
bits, MAC and the general registers are not initialized. In particular, the stack pointer (ER7) is not
initialized. The stack pointer should therefore be initialized using an MOV.L instruction executed
immediately after a reset.
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Section 2 CPU
2.6 Data Formats
The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword)
data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of
byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of
4-bit BCD data.
2.6.1 General Register Data Formats
Figure 2.12 shows the data formats in general registers.
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
Word data
Word data
Longword data
RnH
RnL
RnH
RnL
RnH
RnL
Rn
En
ERn
15
MSB LSB
31
MSB
[Legend]
ERn:
General register ER
En:
General register E
Rn:
General register R
RnH:
General register RH
En
16
43
0
70
Don't careUpper Lower
43
7
Upper
0
Don't care
LSB
70
MSB
Rn
7
76543210 Don't care
Don't care 7 654321
70
Don't care
7
MSB
Don't care
15
MSB
0
15
General register RL
RnL:
Most significant bit
MSB:
Least significant bit
LSB:
0
0
Lower
LSB
0
LSB
0
LSB
Figure 2.12 General Register Data Formats
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Section 2 CPU
2.6.2 Memory Data Formats
Figure 2.13 shows the data formats in memory.
The H8SX CPU can access word data and longword data that are stored at any addresses in
memory. When word data begin at an odd address or longword data begin at an address other than
a multiple of 4, a bus cycle is divided into two or more accesses. For example, when longword
data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. In this
case, these accesses are assumed to be individual bus cycles.
However, instructions to be fetched, word and longword data to be accessed during execution of
the stack manipulation, block transfer instructions, and MAC instruction should be located to even
addresses.
When the stack pointer (ER7) is used as an address register to access the stack, the operand size
should be word size or longword size.
Data Type Data Format
Address
70
1-bit data
Address L
76543210
Byte data
Word data
Longword data
Address L
Address 2M
Address 2M + 1
Address 2N
Address 2N + 1
Address 2N + 2
Address 2N + 3
MSB LSB
MSB
LSB
MSB
LSB
Figure 2.13 Memory Data Formats
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Section 2 CPU
2.7 Instruction Set
The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown
in table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
Data transfer MOV B/W/L 6
MOVFPE*6, MOVTPE*6 B
POP, PUSH*1 W/L
LDM, STM L
MOVA B/W*2
Block transfer EEPMOV B 3
MOVMD B/W/L
MOVSD B
ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC B/W/L 27 Arithmetic
operations
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
MULU, DIVU, MULS, DIVS W/L
MULU/U, MULS/U L
EXTU, EXTS W/L
TAS B
MAC
LDMAC, STMAC
CLRMAC
Logic operations AND, OR, XOR, NOT B/W/L 4
Shift SHLL, SHLR, SHAL, SHAR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,
BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ B
BFLD, BFST B
DAA, DAS B
B 20
BXOR, BIXOR, BLD, BILD, BST, BIST
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Section 2 CPU
Function Instructions Size Types
Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC B*3 9
Bcc*4, JMP, BSR, JSR, RTS
RTS/L L*5
BRA/S
System control TRAPA, RTE, SLEEP, NOP 10
RTE/L L*5
LDC, STC, ANDC, ORC, XORC B/W/L
Total 87
[Legend]
B: Byte size
W: Word size
L: Longword size
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and
MOV.W Rn, @−SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn
and MOV.L ERn, @−SP.
2. Size of data to be added with a displacement
3. Size of data to specify a branch condition
4. Bcc is the generic designation of a conditional branch instruction.
5. Size of a general register to be restored
6. Not supported in this LSI
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Section 2 CPU
2.7.1 Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can
use.
Table 2.2 Combinations of Instructions and Addressing Modes (1)
Addressing Mode
@(d,
@−ERn/
RnL.B/
@ERn+/
Rn.W/
Classification
Data
transfer
Block
transfer
Arithmetic
operations
@ERn−/
ERn.L)
Instruction Size #xx Rn @ERn @(d,ERn)
B/W/L S SD SD SD SD SD SD MOV
B S/D S/D
MOVFPE,
MOVTPE*
POP, PUSH W/L S/D S/D*2
LDM, STM L S/D S/D*2
4
MOVA*
B/W S S S S S S
EEPMOV B SD*3
MOVMD B/W/L SD*3
MOVSD B SD*
ADD, CMP B/W/L S SD SD SD SD SD SD
SUB B S D D D D D
B SD SD SD SD SD SD
W/L S SD SD SD SD SD SD
ADDX, SUBX B/W/L S SD
B/W/L S SD
B/W/L S SD*5
INC, DEC B/W/L D
ADDS, SUBS L D
DAA, DAS B D
MULXU, DIVXU B/W S:4 SD
MULU, DIVU W/L S:4 SD
MULXS, DIVXS B/W S:4 SD
B S/D S/D*
12
@+ERn
@aa:8
@aa:16/
@aa:32
1
3
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Classification
Arithmetic
operations
operations
Shift
Bit manipu-
lation
Branch
Section 2 CPU
Addressing Mode
@(d,
@−ERn/
RnL.B/
@ERn+/
Rn.W/
@ERn−/
Instruction Size #xx Rn @ERn @(d,ERn)
ERn.L)
@+ERn @aa:8
MULS, DIVS W/L S:4 SD
NEG B/W/L D D D D D D
EXTU, EXTS W/L D D D D D D
TAS B D
MAC
CLRMAC O
LDMAC S
STMAC D
AND, OR, XOR B/W/L S SD SD SD SD SD SD Logic
NOT B/W/L D D D D D D
SHLL, SHLR B/W/L*6 D D D D D D
B/W/L*7 D
SHAL, SHAR B/W/L D D D D D D
ROTL, ROTR B/W/L D D D D D D
ROTXL, ROTXR B/W/L D D D D D D
BSET, BCLR,
B D D D D
BNOT, BTST,
BSET/cc,
BCLR/cc
BAND, BIAND,
B D D D D
BOR, BIOR,
BXOR, BIXOR,
BLD, BILD,
BST, BIST,
BSTZ, BISTZ
BFLD B D S S S
BFST B S D D D
BRA/BS,
BRA/BC*
BSR/BS,
BSR/BC*
B S S S
8
B S S S
8
@aa:16/
@aa:32
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Section 2 CPU
Addressing Mode
@(d,
@−ERn/
RnL.B/
@ERn+/
Classification
System
control
Instruction Size #xx Rn @ERn @(d,ERn)
LDC
(CCR, EXR)
LDC
(VBR, SBR)
STC
(CCR, EXR)
STC
(VBR, SBR)
ANDC, ORC,
XORC
SLEEP O
NOP O
B/W*9 S S S S S*10 S
L S
B/W*9 D D D D*11 D
L D
B S
Rn.W/
@ERn−/
ERn.L)
@+ERn @aa:8
@aa:16/
@aa:32
[Legend]
d: d:16 or d:32
S: Can be specified as a source operand.
D: Can be specified as a destination operand.
SD: Can be specified as either source or destination operand or both.
S/D: Can be specified as either source or destination operand.
S:4: 4-bit immediate data can be specified as a source operand.
Notes: 1. @aa:16 is only available.
2. @ERn+ as a source operand and @−ERn as a destination operand
3. Specified by ER5 as a source address and ER6 as a destination address for data
transfer
4. Size of data to be added with a displacement
5. @ERn− is only available.
6. When the number of bits to be shifted is 1, 2, 4, 8, or 16
7. When the number of bits to be shifted is specified by 5-bit immediate data or a general
register
8. Size of data to specify a branch condition
9. Byte for immediate or register direct; otherwise, word
10. @ERn+ is only available.
11. @−ERn is only available.
12. Not supported in this LSI
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Table 2.2 Combinations of Instructions and Addressing Modes (2)
Addressing Mode
@(RnL.B/
Rn.W/
Classification
Branch
control
Instruction Size @ERn @(d,PC)
BRA/BS,
BRA/BC
BSR/BS,
BSR/BC
Bcc O
BRA O O
BRA/S O*
JMP O O O O O
BSR O
JSR O O O O O
RTS, RTS/L O
TRAPA O System
RTE, RTE/L O
O
O
[Legend]
d: d:8 or d:16
Note: * @(d:8, PC) is only available.
ERn.L,
PC) @aa:24 @aa:32 @@aa:8 @@vec:7
Section 2 CPU
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Section 2 CPU
2.7.2 Table of Instructions Classified by Function
Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in the
tables is defined in table 2.3.
Table 2.3 Operation Notation
Operation Notation Description
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
VBR Vector base register
SBR Short address base register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
− Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical exclusive OR
→ Move
∼ Logical not (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Table 2.4 Data Transfer Instructions
Instruction Size Function
MOV B/W/L #IMM → (EAd), (EAs) → (EAd)
Transfers data between immediate data, general registers, and memory.
MOVFPE* B (EAs) → Rd
MOVTPE* B Rs → (EAs)
POP W/L @SP+ → Rn
Restores the data from the stack to a general register.
PUSH W/L Rn → @−SP
Saves general register contents on the stack.
LDM L @SP+ → Rn (register list)
Restores the data from the stack to general registers. Two, three, or four
general registers which have serial register numbers can be specified.
STM L Rn (register list) → @−SP
Saves the contents of general registers on the stack. Two, three, or four
general registers which have serial register numbers can be specified.
MOVA B/W EA → Rd
Zero-extends the contents of a specified general register or memory data
and adds them with a displacement. The result is stored in a general
register.
Note * Not supported in this LSI
Section 2 CPU
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Section 2 CPU
Table 2.5 Block Transfer Instructions
Instruction Size Function
EEPMOV.B
EEPMOV.W
MOVMD.B B Transfers a data block.
MOVMD.W W Transfers a data block.
MOVMD.L L Transfers a data block.
MOVSD.B B Transfers a data block with zero data detection.
B Transfers a data block.
Transfers byte data from a memory location specified by ER5 to a
memory location specified by ER6. The number of byte data to be
transferred is specified by R4 or R4L.
Transfers byte data from a memory location specified by ER5 to a
memory location specified by ER6. The number of byte data to be
transferred is specified by R4.
Transfers word data from a memory location specified by ER5 to a
memory location specified by ER6. The number of word data to be
transferred is specified by R4.
Transfers longword data from a memory location specified by ER5 to a
memory location specified by ER6. The number of longword data to be
transferred is specified by R4.
Transfers byte data from a memory location specified by ER5 to a
memory location specified by ER6. The number of byte data to be
transferred is specified by R4. When zero data is detected during transfer,
the transfer stops and execution branches to a specified address.
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Table 2.6 Arithmetic Operation Instructions
Instruction Size Function
ADD
SUB
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
MULXU B/W Rd × Rs → Rd
MULU W/L Rd × Rs → Rd
MULU/U L Rd × Rs → Rd
MULXS B/W Rd × Rs → Rd
MULS W/L Rd × Rs → Rd
MULS/U L Rd × Rs → Rd
B/W/L (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd)
Performs addition or subtraction on data between immediate data,
general registers, and memory. Immediate byte data cannot be
subtracted from byte data in a general register.
B/W/L (EAd) ± #IMM ± C → (EAd), (EAd) ± (EAs) ± C → (EAd)
Performs addition or subtraction with carry on data between immediate
data, general registers, and memory. A memory location can be specified
in the register indirect addressing mode with post-decrement or the
register indirect addressing mode.
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a general register.
B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 2-digit 4-bit BCD data.
Performs unsigned multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Performs unsigned multiplication on data in two general registers: either
16 bits × 16 bits → 16 bits or 32 bits × 32 bits → 32 bits.
Performs unsigned multiplication on data in two general registers (32 bits
× 32 bits → upper 32 bits).
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Performs signed multiplication on data in two general registers: either 16
bits × 16 bits → 16 bits or 32 bits × 32 bits → 32 bits.
Performs signed multiplication on data in two general registers (32 bits ×
32 bits → upper 32 bits).
Section 2 CPU
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Instruction Size Function
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
DIVU W/L Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits
÷ 16 bits → 16-bit quotient or 32 bits ÷ 32 bits → 32-bit quotient.
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
DIVS W/L Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
16 bits → 16-bit quotient or 32 bits ÷ 32 bits → 32-bit quotient.
CMP B/W/L (EAd) − #IMM, (EAd) − (EAs)
Compares data between immediate data, general registers, and memory
and stores CCR bits according to the result.
NEG B/W/L 0 − (EAd) → (EAd)
Takes the two's complement (arithmetic complement) of the contents of a
general register or a memory location.
EXTU W/L (EAd) (zero extension) → (EAd)
Extends the lower 8 or 16 bits of data in a general register or a memory
location to word or longword size by padding with 0s.
The lower eight bits can be extended to word or longword, or lower 16 bits
to longword.
EXTS W/L (EAd) (sign extension) → (EAd)
Extends the lower 8 or 16 bits of data in a general register or a memory
location to word size by padding with signs.
The lower eight bits can be extended to word or longword, or lower 16 bits
to longword.
TAS B @ERd − 0, 1 → (<bit 7> of @EAd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
MAC (EAd) × (EAs) + MAC → MAC
Performs signed multiplication on memory contents and adds the result to
the MAC.
CLRMAC 0 → MAC
Clears the MAC to zero.
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Instruction Size Function
LDMAC Rs → MAC
Loads data from a general register to the MAC.
STMAC MAC → Rd
Stores data from the MAC to a general register.
Table 2.7 Logic Operation Instructions
Instruction Size Function
AND B/W/L (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd)
Performs a logical AND operation on data between immediate data,
general registers, and memory.
OR B/W/L (EAd) ∨ #IMM → (EAd), (EAd) ∨ (EAs) → (EAd)
Performs a logical OR operation on data between immediate data,
general registers, and memory.
XOR B/W/L (EAd) ⊕ #IMM → (EAd), (EAd) ⊕ (EAs) → (EAd)
Performs a logical exclusive OR operation on data between immediate
data, general registers, and memory.
NOT B/W/L ∼ (EAd) → (EAd)
Takes the one's complement (logical complement) of the contents of a
general register or a memory location.
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Table 2.8 Shift Operation Instructions
Instruction Size Function
SHLL
SHLR
B/W/L (EAd) (shift) → (EAd)
Performs a logical shift on the contents of a general register or a memory
location.
The contents of a general register or a memory location can be shifted by
1, 2, 4, 8, or 16 bits. The contents of a general register can also be shifted
by any bits. In this case, the number of bits is specified by 5-bit immediate
data or the lower 5 bits of general register contents.
SHAL
SHAR
B/W/L (EAd) (shift) → (EAd)
Performs an arithmetic shift on the contents of a general register or a
memory location.
1-bit or 2-bit shift is possible.
ROTL
ROTR
B/W/L (EAd) (rotate) → (EAd)
Rotates the contents of a general register or a memory location.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR
B/W/L (EAd) (rotate) → (EAd)
Rotates the contents of a general register or a memory location with the
carry flag.
1-bit or 2-bit rotation is possible.
Table 2.9 Bit Manipulation Instructions
Instruction Size Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in the contents of a general register or a memory
location to 1. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
BSET/cc B if cc, 1 → (<bit-No.> of <EAd>)
If the specified condition is satisfied, this instruction sets a specified bit in
a memory location to 1. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in the contents of a general register or a memory
location to 0. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
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Instruction Size Function
BCLR/cc B if cc, 0 → (<bit-No.> of <EAd>)
If the specified condition is satisfied, this instruction clears a specified bit
in a memory location to 0. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.
BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in the contents of a general register or a memory
location. The bit number is specified by 3-bit immediate data or the lower
three bits of a general register.
BTST B ∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in the contents of a general register or a memory
location and sets or clears the Z flag accordingly. The bit number is
specified by 3-bit immediate data or the lower three bits of a general
register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
BIAND B C ∧ [∼ (<bit-No.> of <EAd>)] → C
Logically ANDs the carry flag with the inverse of a specified bit in the
contents of a general register or a memory location and stores the result
in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR B C ∨ (<bit-No.> of <EAd>) → C
Logically ORs the carry flag with a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
BIOR B C ∨ [∼ (<bit-No.> of <EAd>)] → C
Logically ORs the carry flag with the inverse of a specified bit in the
contents of a general register or a memory location and stores the result
in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with a specified bit in the contents
of a general register or a memory location and stores the result in the
carry flag.
The bit number is specified by 3-bit immediate data.
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Instruction Size Function
BIXOR B C ⊕ [∼ (<bit-No.> of <EAd>)] → C
Logically exclusive-ORs the carry flag with the inverse of a specified bit in
the contents of a general register or a memory location and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in the contents of a general register or a memory
location to the carry flag.
The bit number is specified by 3-bit immediate data.
BILD B ∼ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in the contents of a general
register or a memory location to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in the contents of a
general register or a memory location.
The bit number is specified by 3-bit immediate data.
BSTZ B Z → (<bit-No.> of <EAd>)
Transfers the zero flag value to a specified bit in the contents of a
memory location.
The bit number is specified by 3-bit immediate data.
BIST B ∼ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in the
contents of a general register or a memory location.
The bit number is specified by 3-bit immediate data.
BISTZ B ∼ Z → (<bit-No.> of <EAd>)
Transfers the inverse of the zero flag value to a specified bit in the
contents of a memory location.
The bit number is specified by 3-bit immediate data.
BFLD B (EAs) (bit field) → Rd
Transfers a specified bit field in memory location contents to the lower bits
of a specified general register.
BFST B Rd → (EAd) (bit field)
Transfers the lower bits of a specified general register to a specified bit
field in memory location contents.
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Table 2.10 Branch Instructions
Instruction Size Function
BRA/BS
BRA/BC
BSR/BS
BSR/BC
Bcc Branches to a specified address if the specified condition is satisfied.
BRA/S Branches unconditionally to a specified address after executing the next
JMP Branches unconditionally to a specified address.
BSR Branches to a subroutine at a specified address.
JSR Branches to a subroutine at a specified address.
RTS Returns from a subroutine
RTS/L Returns from a subroutine, restoring data from the stack to general
B Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a specified address.
B Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a subroutine at a specified
address.
instruction. The next instruction should be a 1-word instruction except for
the block transfer and branch instructions.
registers.
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Table 2.11 System Control Instructions
Instruction Size Function
TRAPA Starts trap-instruction exception handling.
RTE Returns from an exception-handling routine.
RTE/L Returns from an exception-handling routine, restoring data from the stack
to general registers.
SLEEP Causes a transition to a power-down state.
LDC
STC
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
NOP PC + 2 → PC
B/W #IMM → CCR, (EAs) → CCR, #IMM → EXR, (EAs) → EXR
Loads immediate data or the contents of a general register or a memory
location to CCR or EXR. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and memory. The upper
eight bits are valid.
L Rs → VBR, Rs → SBR
Transfers the general register contents to VBR or SBR.
B/W CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper eight bits are valid.
L VBR → Rd, SBR → Rd
Transfers the contents of VBR or SBR to a general register.
Logically ANDs the CCR or EXR contents with immediate data.
Logically ORs the CCR or EXR contents with immediate data.
Logically exclusive-ORs the CCR or EXR contents with immediate data.
Only increments the program counter.
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2.7.3 Basic Instruction Formats
The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
Figure 2.14 shows examples of instruction formats.
(1) Operation field only
op
(2) Operation field and register fields
op
(3) Operation field, register fields, and effective address extension
op
EA (disp)
(4) Operation field, effective address extension, and condition field
op cc EA (disp) BRA d:16, etc
rn
rn rm
rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm, etc.
Figure 2.14 Instruction Formats
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field
Specifies the branching condition of Bcc instructions.
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2.8 Addressing Modes and Effective Address Calculation
The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a
subset of these addressing modes.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.12 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)
4 Index register indirect with displacement @(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L)
@(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)
Register indirect with post-increment @ERn+
5
Register indirect with pre-decrement @−ERn
Register indirect with pre-increment @+ERn
Register indirect with post-decrement @ERn−
6 Absolute address @aa:8/@aa:16/@aa:24/@aa:32
7 Immediate #xx:3/#xx:4/#xx:8/#xx:16/#xx:32
8 Program-counter relative @(d:8,PC)/@(d:16,PC)
9 Program-counter relative with index register @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)
10 Memory indirect @@aa:8
11 Extended memory indirect @@vec:7
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2.8.1 Register Direct—Rn
The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the
register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit
registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified
as 32-bit registers.
2.8.2 Register Indirect—@ERn
The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field in the instruction code.
In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are
valid and the upper eight bits are all assumed to be 0 (H'00).
2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn)
The operand value is the contents of a memory location which is pointed to by the sum of the
contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the
register field of the instruction code. The displacement is included in the instruction code and the
16-bit displacement is sign-extended when added to ERn.
This addressing mode has a short format (@(d:2, ERn)). The short format can be used: when a
displacement is 1, 2, or 3 and the operand is byte data, when a displacement is 2, 4, or 6 and the
operand is word data, or when a displacement is 4, 8, or 12 and the operand is longword data.
2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)
The operand value is the contents of a memory location which is pointed to by the sum of the
following operation result and a 16- or 32-bit displacement: specified bits of the contents of an
address register (RnL, Rn, ERn) specified by the register field in the instruction code are zeroextended to 32-bit data and multiplied by 1, 2, or 4.
The displacement is included in the instruction code and the 16-bit displacement is sign-extended
when added to ERn. If the operand is byte data, ERn is multiplied by 1. If the operand is word or
longword data, ERn is multiplied by 2 or 4, respectively.
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2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,
or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn−
(1) Register indirect with post-increment—@ERn+
The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field in the instruction code. After the
memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is
stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for
longword access.
(2) Register indirect with pre-decrement—@−ERn
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn)
which is specified by the register field in the instruction code. After that, the subtraction result is
stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for
longword access.
(3) Register indirect with pre-increment—@+ERn
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn) which is
specified by the register field in the instruction code. After that, the sum is stored in the address
register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.
(4) Register indirect with post-decrement—@ERn−
The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field in the instruction code. After the
memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the
subtraction result is stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access.
If the contents of a general register which is also used as an address register is written to memory
using this addressing mode, data to be written is the contents of the general register after
calculating an effective address. If the same general register is specified in an instruction and two
effective addresses are calculated, the contents of the general register after the first calculation of
an effective address is used in the second calculation of an effective address.
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Example 1:
MOV.W R0, @ER0+
When ER0 before execution is H'12345678, H'567A is written at H'12345678.
Example 2:
MOV.B @ER0+, @ER0+
When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at
H'00001001.
After execution, ER0 is H'00001002.
2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The operand value is the contents of a memory location which is pointed to by an absolute address
included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and
32-bit (@aa:32) absolute addresses.
To access the data area, the absolute address of eight bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specified by SBR. For a 16bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the
entire address space.
To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used.
For a 24-bit absolute address, the upper eight bits are all assumed to be 0 (H'00).
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Table 2.13 shows the accessible absolute address ranges.
Table 2.13 Absolute Address Access Ranges
Absolute Address
Data area
8 bits
(@aa:8)
16 bits
(@aa:16)
32 bits
(@aa:32)
24 bits
(@aa:24)
32 bits
(@aa:32)
Normal
Mode
A consecutive 256-byte area (the upper address bits are set in SBR)
H'0000 to H'FFFF
Middle
Mode
H'000000 to
H'007FFF,
H'FF8000 to
H'FFFFFF
H'000000 to
H'FFFFFF
Advanced
Mode
H'00000000 to H'00007FFF,
H'FFFF8000 to H'FFFFFFFF
H'00000000 to H'FFFFFFFF
H'00000000 to H'00FFFFFF Program area
H'00000000 to
H'00FFFFFF
Maximum
Mode
H'00000000 to
H'FFFFFFFF
2.8.7 Immediate—#xx:8, #xx:16, or #xx:32
The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the
instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can
be used.
When the size of immediate data is less than that of the operand size (byte, word, or longword),
the immediate data is zero-extended.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The BFLD and BFST instructions contain 8-bit immediate data in its instruction code,
specifying bit numbers. The TRAPA instruction contains 2-bit immediate data in its instruction
code, specifying a vector address.
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2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, P C)
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,
which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of
the PC contents. The 8-bit or 16-bit displacement is sign-extended when added to the PC contents.
The PC contents to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is −126 to +128 bytes (−63 to +64 words) or −32766
to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting value
should be an even number. In advanced mode, only the lower 24 bits of this branch address are
valid; the upper eight bits are all assumed to be 0 (H'00).
2.8.9 Program-Counter Relative with Index Register—@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC)
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,
which is the sum of the following operation result and the 32-bit address of the PC contents:
specified bits of the contents of an address register (RnL, Rn, or ERn) specified by the register
field in the instruction code is zero-extended to 32-bit data and multiplied by 2.
The PC content to which the displacement is added is the address of the first byte of the next
instruction. In advanced mode, only the lower 24 bits of this branch address are valid; the upper
eight bits are all assumed to be 0 (H'00).
2.8.10 Memory Indirect—@@aa:8
This mode is used in the JMP and JSR instructions. The operand value is a branch address, which
is the content of a memory location pointed to by an 8-bit absolute address in the instruction code.
The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range to store a
branch address is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other
modes). In normal mode, the memory location is pointed to by word-size data and the branch
address is 16 bits long. In other modes, the memory location is pointed to by longword-size data.
In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).
Note that the top part of the address range is also used as the exception handling vector area. A
vector address of an exception handling other than a reset or a CPU address error can be changed
by VBR.
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Figure 2.15 shows an example of specification of a branch address using this addressing mode.
Specified
by @aa:8
Branch address
(a) Normal Mode (b) Advanced Mode
Specified
by @aa:8
Reserved
Branch address
Figure 2.15 Branch Address Specification in Memory Indirect Mode
2.8.11 Extended Memory Indirect—@@vec:7
This mode is used in the JMP and JSR instructions. The operand value is a branch address, which
is the contents of a memory location pointed to by the following operation result: the sum of 7-bit
data in the instruction code and the value of H'80 is multiplied by 2 or 4.
The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to
H'0003FF in other modes. In assembler notation, an address to store a branch address is specified.
In normal mode, the memory location is pointed to by word-size data and the branch address is 16
bits long. In other modes, the memory location is pointed to by longword-size data. In middle or
advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).
2.8.12 Effective Address Calculation
Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. In
normal mode, the upper eight bits of the effective address are ignored in order to generate a 16-bit
address.
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Table 2.14 Effective Address Calculation for Transfer and Operation Instructions
No.
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
1
Immediate
IMM
Register direct
2
opoprm rn
Register indirect
3
op
r
4
Register indirect with 16-bit displacement
r
op
disp
Register indirect with 32-bit displacement
op
r
disp
31 0 31 0
General register contents
31 0
General register contents
31 15
Sign extension
31 0
General register contents
disp
disp
31 0
+
0
31 0
+
5
Index register indirect with 16-bit displacement
r
op
disp
Index register indirect with 32-bit displacement
r
op
Register indirect with post-increment or post-decrement
6
op
Register indirect with pre-increment or pre-decrement
op
8-bit absolute address
7
op
16-bit absolute address
op
32-bit absolute address
op
disp
r
r
aa
aa
aa
31 0
Zero extension
Contents of general register
(RL, R, or ER)
31 15
Sign extension
31 0
Zero extension
Contents of general register
(RL, R, or ER)
31
31
31
31 07
31 15
Sign extension
31
disp
General register contents
General register contents
SBR
aa
1, 2, or 4
disp
1, 2, or 4
1, 2, or 4
1, 2, or 4
aa
aa
×
31 0
+
0
×
31 0
0
+
0
31 0
±
0
31 0
±
31 0
31 0
0
0
31 0
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Section 2 CPU
Table 2.15 Effective Address Calculation for Branch Instructions
No.
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Register indirect
1
op
r
Program-counter relative with 8-bit displacement
2
op
disp
Program-counter relative with 16-bit displacement
op
disp
31 0 31
General register contents
31 0
31 7 0
31 0
31 15 0
Sign extension
Sign extension
PC contents
PC contents
disp
disp
+
+
31 0
31 0
0
Program-counter relative with index register
3
r
op
24-bit absolute address
4
op
32-bit absolute address
op
aa
Memory indirect
5
op aa
6
Extended memory indirect
op
vec
aa aa
31 0
Zero extension
Contents of general register (RL, R, or ER)
31
Zero
31 23 0
extension
31
31 0
31
31
31
31
PC contents
Zero extension
Memory contents
Zero extension
Memory contents
aa
7
aa
17vec
2 or 4
×
2
31 0
+
0
31 0
31 0
0
31 0
0
0
×
0
0
31 0
2.8.13 MOVA Instruction
The MOVA Instruction stores the effective address into the general register.
1. Obtains data in the addressing mode of No.2 in table 2.14.
2. By using this data as the index instead of the general register in row No.5 in table 14.2, the
effective address calculation is executed, and the outcome is stored in the general register. For
details, see the H8SX Family Software Manual.
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Section 2 CPU
2.9 Processing States
The H8SX CPU has five main processing states: the reset state, exception-handling state, program
execution state, bus-released state, and program stop state. Figure 2.16 indicates the state
transitions.
• Reset state
In this state the CPU and internal peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, see section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow when available.
• Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or
trap instruction. The CPU fetches a start address (vector) from the exception handling vector
table and branches to that address. For further details, see section 4, Exception Handling.
• Program execution state
In this state the CPU executes program instructions in sequence.
• Bus-released state
The bus-released state occurs when the bus has been released in response to a bus request from
a bus master other than the CPU. While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
see section 18, Power-Down States.
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Section 2 CPU
Reset state*
Exception-handling
Request for exception
handling
Program execution
Note: *
A transition to the reset state occurs whenever the RES signal goes low.
A transition can also be made to the reset state when the watchdog timer
overflows.
RES = high
state
End of exception
handling
state
Interrupt
request
Bus
request
End of
bus request
SLEEP instruction
Figure 2.16 State Transitions
RES = low
Bus-released state
Bus request
Program stop state
End of bus request
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1 Operating Mode Selection
This LSI has two operating modes (modes 4 and 5). The operating mode is selected by the setting
of mode pins (MD2 to MD0). Table 3.1 lists MCU operating mode settings.
Table 3.1 MCU Operating Mode Settings
MCU
Operating
Mode MD2 MD1 MD0
4 1 0 0 Advanced 16 Mbytes Disabled 16 bits 16 bits
5 1 0 1
CPU
Operating
Mode
Address
Space Description
On-chip ROM
disabled extended
mode
On-Chip
ROM
Disabled 8 bits 16 bits
External Data
Bus Width
Default Max.
In this LSI, advanced mode for the CPU operating mode, 16 Mbytes for the address space, and
eight or 16 bits for the default external bus width are available.
In modes 4 and 5, which are external extended modes, it is possible to access the external memory
and devices. In external extended mode, the external address space can be designated as 8-bit or
16-bit address space for each area by the bus controller after starting program execution. If 16-bit
address space is designated for any one area, the bus mode switches to 16 bits. If 8-bit address
space is designated for all areas, the bus mode switches to 8 bits.
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Section 3 MCU Operating Modes
3.2 Register Descriptions
The following registers are related to the operating mode setting.
• Mode control register (MDCR)
• System control register (SYSCR)
3.2.1 Mode Control Register (MDCR)
MDCR indicates the current operating mode.
When MDCR is read, the input levels in pins MD2 to MD0 are latched. These latches are released
by a reset.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: * Determined by pins MD2 to MD0.
15
0
R
7
0
R
14
1
R
6
1
R
13
0
R
5
0
R
12
1
R
4
1
R
Bit Bit Name Initial Value R/W Descriptions
15
14
13
12
11
10
9
8
MDS2
MDS1
MDS0
0
1
0
1
0
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
R
R
Reserved
These are read-only bits and cannot be modified.
Mode Select 2 to 0
These bits indicate the operating mode selected by the
mode pins (MD2 to MD0) (see table 3.2).
When MDCR is read, the signal levels input on pins
MD2 to MD0 are latched into these bits. These latches
are released by a reset.
11
0
R
3
0
R
10
MDS2
Undefined*
R
2
Undefined*
R
9
MDS1
Undefined*
R
1
Undefined*
R
8
MDS0
Undefined*
R
0
Undefined*
R
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Bit Bit Name Initial Value R/W Descriptions
7
6
5
4
3
2
1
0
0
1
0
1
0
Undefined*
Undefined*
Undefined*
R
Reserved
R
These are read-only bits and cannot be modified.
R
R
R
R
R
R
Note: * Determined by pins MD2 to MD0.
Table 3.2 Settings of Bits MSD2 to MSD0
Section 3 MCU Operating Modes
MCU Operating
Mode
MDCR
MD2 MD1 MD0 MDS2 MDS1 MDS0
4 1 0 0 0 1 0
5 1 0 1 0 0 1
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Section 3 MCU Operating Modes
3.2.2 System Control Register (SYSCR)
SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets
external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: * The initial value depends on the startup mode.
15
1
R/W
7
0
R/W
14
1
R/W
6
0
R/W
13
MACS
0
R/W
5
0
R/W
12
1
R/W
4
0
R/W
11
FETCHMD
0
R/W
3
0
R/W
10
0
R/W
2
0
R/W
Initial
Bit Bit Name
Value R/W Descriptions
15, 14 All 1 R/W Reserved
These bits are always read as 1. The write value should
always be 1.
13 MACS 0 R/W MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction is non-saturation operation
1: MAC instruction is saturation operation
12 1 R/W Reserved
This bit is always read as 1. The write value should
always be 1.
11 FETCHMD 0 R/W Instruction Fetch Mode Select
The H8SX CPU has two modes for instruction fetch: 16bit and 32-bit modes. It is recommended that the mode
should be set according to the bus width of the memory in
which the program is stored*
1
.
0: 32-bit width
1: 16-bit width
9
EXPE
Undefined*
R/W
1
DTCMD
1
R/W
8
RAME
1
R/W
0
1
R/W
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Initial
Bit Bit Name
Value R/W Descriptions
10 0 R/W Reserved
This bit is always read as 0. The write value should
always
be 0.
9 EXPE Undefined*
2
R/W External Bus Mode Enable
Selects external bus mode. In external extended mode,
this bit is fixed at 1 and cannot be changed. In singlechip mode, the initial value of this bit is 0, and can be
read from or written to.
When writing 0 to this bit after reading EXPE = 1, an
external bus cycle should not be executed.
The external bus cycle may be carried out in parallel
with the internal bus cycle depending on the setting of
the write data buffer function.
0: External bus disabled
1: External bus enabled
8 RAME 1 R/W RAM Enable
Enables or disables the on-chip RAM. This bit is
initialized when the reset state is released. Do not write
0 during access to the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
7 to 2 All 0 R/W Reserved
These bits are always read as 0. The write value should
always be 0.
1 DTCMD 1 R/W DTC Mode Select
Selects DTC operation mode.
0: DTC is in full-address mode
1: DTC is in short address mode
0 1 R/W Reserved
This bit is always read as 1. The write value should
always
be 1.
Notes: 1. For details, see section 2.3, Instruction Fetch.
2. The initial value depends on the startup mode.
In operating modes 4 and 5, which are external extended modes, EXPE = 1.
Section 3 MCU Operating Modes
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Section 3 MCU Operating Modes
3.3 Operating Mode Descriptions
3.3.1 Mode 4
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled.
The initial bus mode immediately after a reset is 16 bits, with 16-bit access to all areas. Ports D, E,
and F function as an address bus, ports H and I function as a data bus, and parts of ports A and B
function as bus control signals. However, if all areas are designated as an 8-bit access space by the
bus controller, the bus mode switches to 8 bits, and only port H functions as a data bus.
3.3.2 Mode 5
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled.
The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. Ports D, E,
and F function as an address bus, port H functions as a data bus, and parts of ports A and B
function as bus control signals. However, if all areas are designated as a 16-bit access space by the
bus controller, the bus mode switches to 16 bits, and ports H and I function as a data bus.
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Section 3 MCU Operating Modes
3.3.3 Pin Functions
Table 3.3 lists the pin functions in each operating mode.
Table 3.3 Pin Functions in Each Operating Mode (Advanced Mode)
Port Mode 4 Mode 5
Port A
Port D A A
Port E A A
Port F PF7 to PF5 P*/A P*/A
PF4 to PF0 A A
Port H D D
Port I P/D* P*/D
[Legend]
P: I/O port
A: Address bus output
D: Data bus input/output
C: Control signals, clock input/output
*: Immediately after a reset
PA7 P/C* P/C*
PA6, PA4 P/C* P/C*
PA2 to PA0 P*/C P*/C
PB3 to 1 P*/C P*/C Port B
PB0 P/C* P/C*
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Section 3 MCU Operating Modes
3.4 Address Map
3.4.1 Address Map (Advanced Mode)
Figure 3.1 shows the address map.
On-chip ROM disabled
extended mode
(Advanced mode)
H'000000
External address
Modes 4, 5
space
H'FD9000
H'FDC000
H'FF0000
H'FF6000
H'FFC000
H'FFEA00
H'FFFF00
H'FFFF20
H'FFFFFF
Note: * This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
(Access prohibited
space)
External address
space
(Access prohibited
space)
On-chip RAM/
external address
space*
External address
space
On-chip I/O registers
External address
space
On-chip I/O registers
Figure 3.1 Address Map (Advanced Mode)
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Section 4 Exception Handling
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an
interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal
instruction or slot illegal instruction). Exception handling is prioritized as shown in table 4.1. If
two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode. For details on the interrupt control mode, see section 5, Interrupt Controller.
Table 4.1 Exception Types and Priority
Priority Exception Type Exception Handling Start Timing
High Reset Exception handling starts at the timing of level change from
low to high on the RES pin, or when the watchdog timer
overflows. The CPU enters the reset state when the RES
pin is low.
Illegal instruction Exception handling starts when an undefined code is
executed.
Trace*1 Exception handling starts after execution of the current
instruction or exception handling, if the trace (T) bit in EXR
is set to 1.
Address error After an address error has occurred, exception handling
starts on completion of instruction execution.
Interrupt Exception handling starts after execution of the current
instruction or exception handling, if an interrupt request has
occurred.*2
Sleep instruction Exception handling starts by execution of a sleep instruction
(SLEEP), if the SSBY bit in SBYCR is set to 0 and the
SLPIE bit in SBYCR is set to 1.
Trap instruction*
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests and sleep instruction exception handling
requests are accepted at all times in program execution state.
3
Exception handling starts by execution of a trap instruction
(TRAPA).
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Section 4 Exception Handling
4.2 Exception Sources and Exception Handling Vector Table
Different vector table address offsets are assigned to different exception sources. The vector table
addresses are calculated from the contents of the vector base register (VBR) and vector table
address offset of the vector number. The start address of the exception service routine is fetched
from the exception handling vector table indicated by this vector table address.
Table 4.2 shows the correspondence between the exception sources and vector table address
offsets. Table 4.3 shows the calculation method of exception handling vector table addresses.
Since the usable modes differ depending on the product, for details on the available modes, see
section 3, MCU Operating Modes.
Table 4.2 Exception Handling Vector Table
Vector Table Address Offset*1
Exception Source Vector Number Normal Mode*
Reset 0 H'0000 to H'0001 H'0000 to H'0003
Reserved for system use 1 H'0002 to H'0003 H'0004 to H'0007
2 H'0004 to H'0005 H'0008 to H'000B
3 H'0006 to H'0007 H'000C to H'000F
Illegal instruction 4 H'0008 to H'0009 H'0010 to H'0013
Trace 5 H'000A to H'000B H'0014 to H'0017
Reserved for system use 6 H'000C to H'000D H'0018 to H'001B
Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F
Trap instruction (#0) 8 H'0010 to H'0011 H'0020 to H'0023
(#1) 9 H'0012 to H'0013 H'0024 to H'0027
(#2) 10 H'0014 to H'0015 H'0028 to H'002B
(#3) 11 H'0016 to H'0017 H'002C to H'002F
CPU address error 12 H'0018 to H'0019 H'0030 to H'0033
DMA address error*3 13 H'001A to H'001B H'0034 to H'0037
Reserved for system use 14
17
Sleep instruction 18 H'0024 to H'0025 H'0048 to H'004B
H'001C to H'001D
H'0022 to H'0023
2
Advanced, Middle*2,
Maximum*2 Modes
H'0038 to H'003B
H'0044 to H'0047
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Section 4 Exception Handling
Vector Table Address Offset*1
Advanced, Middle*2,
Exception Source Vector Number Normal Mode*2
Reserved for system use 19
23
User area (open space) 24
63
H'0026 to H'0027
H'002E to H'002F
H'0030 to H'0031
H'007E to H'007F
Maximum*2 Modes
H'004C to H'004F
H'005C to H'005F
H'0060 to H'0063
H'00FC to H'00FF
External interrupt IRQ0 64 H'0080 to H'0081 H'0100 to H'0103
IRQ1 65 H'0082 to H'0083 H'0104 to H'0107
IRQ2 66 H'0084 to H'0085 H'0108 to H'010B
IRQ3 67 H'0086 to H'0087 H'010C to H'010F
IRQ4 68 H'0088 to H'0089 H'0110 to H'0113
IRQ5 69 H'008A to H'008B H'0114 to H'0117
IRQ6 70 H'008C to H'008D H'0118 to H'011B
IRQ7 71 H'008E to H'008F H'011C to H'011F
IRQ8 72 H'0090 to H'0091 H'0120 to H'0123
IRQ9 73 H'0092 to H'0093 H'0124 to H'0127
IRQ10 74 H'0094 to H'0095 H'0128 to H'012B
IRQ11 75 H'0096 to H'0097 H'012C to H'012F
Reserved for system use 76
79
Internal interrupt*4 80
255
H'0098 to H'0099
H'009E to H'009F
H'00A0 to H'00A1
H'01FE to H'01FF
H'0130 to H'0133
H'013C to H'013F
H'0140 to H'0143
H'03FC to H'03FF
Notes: 1. Lower 16 bits of the address.
2. Not available in this LSI.
3. A DMA address error is generated by the DTC.
4. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
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Section 4 Exception Handling
Table 4.3 Calculation Method of Exception Handling Vector Table Address
Exception Source Calculation Method of Vector Table Address
Reset, CPU address error Vector table address = (vector table address offset)
Other than above Vector table address = VBR + (vector table address offset)
[Legend]
VBR: Vector base register
Vector table address offset: See table 4.2.
4.3 Reset
A reset has priority over any other exception. When the RES pin goes low, all processing halts and
this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20
ms with the STBY pin driven high when the power is turned on. When operation is in progress,
hold the RES pin low for at least 20 cycles.
The chip can also be reset by overflow of the watchdog timer. For details, see section 12,
Watchdog Timer (WDT).
A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules.
The interrupt control mode is 0 immediately after a reset.
4.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are
set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset sequence.
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Section 4 Exception Handling
4.3.2 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3 On-Chip Peripheral Functions after Reset Release
After the reset state is released, MSTPCRA and MSTPCRB are initialized to H'0FFF and H'FFFF,
respectively, and all modules except the DTC enter module stop state.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when module stop state is canceled.
Vector
fetch
Iφ
RES
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1) Reset exception handling vector address (when reset, (1) = H'000000)
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First instruction in the exception handling routine
Internal
operation
(1)
High
(2) (4)
First
instruction
prefetch
(3)
Figure 4.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)
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Section 4 Exception Handling
Vector fetch
Bφ
RES
Address bus
RD
HWR, LWR
D15 to D0
(1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5) = (2)(4))
(6) First instruction in the exception handling routine
Note: * Seven program wait cycles are inserted.
* * *
(1)
(2) (4) (6)
Internal
operation
(3) (5)
High
First instruction
prefetch
Figure 4.2 Reset Sequence
(16-Bit External Access in On-chip ROM Disabled Advanced Mode)
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Section 4 Exception Handling
4.4 Traces Exception Handling
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit
must be cleared. For details on interrupt control modes, see section 5, Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table
4.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is
canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit
saved on the stack retains its value of 1, and when control is returned from the trace exception
handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not
carried out after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 4.4 Status of CCR and EXR after Trace Exception Handling
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
0 Trace exception handling cannot be used.
2 1 0
[Legend]
1: Set to 1
0: Cleared to 0
: Retains the previous value.
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Section 4 Exception Handling
4.5 Address Error
4.5.1 Address Error Source
Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address
error.
Table 4.5 Bus Cycle and Address Error
Bus Cycle
Type Bus Master Description Address Error
Instruction
fetch
operation
Data
read/write
Data
read/write
Notes: 1. For on-chip peripheral module space, see section 6, Bus Controller (BSC).
2. For the access-prohibited area, see figure 3.1, Address Map (Advanced Mode) in
CPU Fetches instructions from even addresses No (normal)
Fetches instructions from odd addresses Occurs
Fetches instructions from areas other than on-chip
No (normal)
peripheral module space*1
Fetches instructions from on-chip peripheral module
Occurs
space*1
Fetches instructions from external memory space in
Occurs
single-chip mode
Fetches instructions from access prohibited area.*
CPU Accesses stack when the stack pointer value is even
2
Occurs
No (normal) Stack
address
Accesses stack when the stack pointer value is odd Occurs
CPU Accesses word data from even addresses No (normal)
Accesses word data from odd addresses No (normal)
Accesses external memory space in single-chip
Occurs
mode
Accesses to access prohibited area*
2
Occurs
DTC Accesses word data from even addresses No (normal)
Accesses word data from odd addresses No (normal)
Accesses external memory space in single-chip
Occurs
mode
2
Accesses to access prohibited area*
Occurs
section 3.4, Address Map.
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Section 4 Exception Handling
4.5.2 Address Error Exception Handling
When an address error occurs, address error exception handling starts after the bus cycle causing
the address error ends and current instruction execution completes. The address error exception
handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the address error is generated, the
start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
Even though an address error occurs during a transition to an address error exception handling, the
address error is not accepted. This prevents an address error from occurring due to stacking for
exception handling, thereby preventing infinitive stacking.
If the SP contents are not a multiple of 2 when an address error exception handling occurs, the
stacked values (PC, CCR, and EXR) are undefined.
When an address error occurs, the following is performed to halt the DTC.
• The ERR bit in DTCCR is set to 1.
Table 4.6 shows the state of CCR and EXR after execution of the address error exception
handling.
Table 4.6 Status of CCR and EXR after Address Error Exception Handling
CCR EXR
Interrupt Control Mode I UI T I2 to I0
0 1
2 1 0 7
[Legend]
1: Set to 1
0: Cleared to 0
: Retains the previous value.
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Section 4 Exception Handling
4.6 Interrupts
4.6.1 Interrupt Sources
Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 4.7.
Table 4.7 Interrupt Sources
Type Source Number of Sources
NMI NMI pin (external input) 1
IRQ0 to IRQ11 Pins IRQ0 to IRQ11 (external input) 12
On-chip
peripheral
module
8-bit timer (TMR) 12
Serial communications interface (SCI) 16
Different vector numbers and vector table offsets are assigned to different interrupt sources. For
vector number and vector table offset, see table 5.2, Interrupt Sources, Vector Address Offsets,
and Interrupt Priority in section 5, Interrupt Controller.
Watchdog timer (WDT) 1
A/D converter 1
16-bit timer pulse unit (TPU) 26
4.6.2 Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiple-interrupt control. The source to start interrupt exception handling and the vector address
differ depending on the product. For details, see section 5, Interrupt Controller.
The interrupt exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the interrupt source is generated,
the start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
Rev.2.00 Jun. 28, 2007 Page 78 of 666
REJ09B0311-0200
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