Renesas H8SX/1500 Series, H8SX/1520 Series, H8SX/1525, H8SX Series, R5F61525 Hardware Manual

REJ09B0104-0300

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32

H8SX/1527 R5F61527
H8SX/1525 R5F61525

H8SX/1520Group

Hardware Manual

Renesas 32-Bit CISC Microcomputer

H8SX Family H8SX/1500 Series

Rev.3.00
Revision Date: Mar. 14, 2006

Rev. 3.00 Mar. 14, 2006 Page ii of xxxviii

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 3.00 Mar. 14, 2006 Page iii of xxxviii

General Precautions on Handling of Product

1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are hi g h-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Rese r ved Ad dresses
Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 3.00 Mar. 14, 2006 Page iv of xxxviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 3.00 Mar. 14, 2006 Page v of xxxviii

Preface

The H8SX/1520 Group is a single-chip microcomputer made up of the high-speed internal 32-bit
H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX
CPU is upward compatible with the H8/300, H8/300H, and H8S CPUs.

Target Users: This manual was written for users who will be using the H8SX/1520 Group in the

design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8SX/1520 Group to the target users.
Refer to the H8SX Family Software Manual for a detailed description of the
instruction set.

Notes on reading this manual:

In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughl y categorized into parts
on the CPU, system control functions, and peripheral functions.

In order to understand the details of the CPU's functions

Read the H8SX Family Software Manual.

In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 20,
List of Registers.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial
communication interface, is implemented on more than one
channel:
XXX_N (XXX is the register name and N is the channel

number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our w eb site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/

Rev. 3.00 Mar. 14, 2006 Page vi of xxxviii

H8SX/1520 Group manuals:

Document Title Document No.

H8SX/1520 Group Hardware Manual This manual

H8/SX Family Software Manual REJ09B0102

Rev. 3.00 Mar. 14, 2006 Page vii of xxxviii

Rev. 3.00 Mar. 14, 2006 Page viii of xxxviii

Contents

Section 1 Overview................................................................................................1

1.1 Features.................................................................................................................................. 1

1.2 Block Diagram....................................................................................................................... 2

1.3 Pin Assignments.....................................................................................................................4

1.3.1 Pin Assignments.......................................................................................................4

1.3.2 Pin Configuration in Each Operating Mode..............................................................6

1.3.3 Pin Functions ..........................................................................................................10

Section 2 CPU......................................................................................................19

2.1 Features................................................................................................................................ 19

2.2 CPU Operating Modes......................................................................................................... 21

2.2.1 Normal Mode..........................................................................................................21

2.2.2 Middle Mode..........................................................................................................23

2.2.3 Advanced Mode......................................................................................................24

2.2.4 Maximum Mode.....................................................................................................25

2.3 Instruction Fetch..................................................................................................................27

2.4 Address Space...................................................................................................................... 27

2.5 Registers...............................................................................................................................28

2.5.1 General Registers....................................................................................................29

2.5.2 Program Counter (PC)............................................................................................30

2.5.3 Condition-Code Register (CCR).............................................................................30

2.5.4 Extended Control Register (EXR)..........................................................................32

2.5.5 Vector Base Register (VBR)................................................................................... 32

2.5.6 Short Address Base Register (SBR)........................................................................32

2.5.7 Multiply-Accumulate Register (MAC)...................................................................33

2.5.8 Initial Values of CPU Registers.............................................................................. 33

2.6 2Data Formats...................................................................................................................... 33

2.6.1 General Register Data Formats...............................................................................33

2.6.2 Memory Data Formats............................................................................................ 35

2.7 Instruction Set......................................................................................................................36

2.7.1 Instructions and Addressing Modes........................................................................ 38

2.7.2 Table of Instru ctions Classified by Function.......................................................... 42

2.7.3 Basic Instruction Formats.......................................................................................53

2.8 Addressing Modes and Effective Address Calculation........................................................54

2.8.1 Register Direct—Rn...............................................................................................55

2.8.2 Register Indirect—@ERn....................................................................................... 55

Rev. 3.00 Mar. 14, 2006 Page ix of xxxviii

2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn),

or @(d:32, ERn) ..................................................................................................... 55

2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),

@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 56

2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,

or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− ................................56

2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.......................................58

2.8.7 Immediate—#xx.....................................................................................................59

2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC):.....................................59

2.8.9 Program-Counter Relative with Index Register— @(RnL.B, PC),

@(Rn.W, PC), or @(ERn.L, PC)............................................................................ 59

2.8.10 Memory Indirect—@@aa:8 ................................................................................... 60

2.8.11 Extended Memory Indirect—@@vec:7 .................................................................61

2.8.12 Effective Address Calculation ................................................................................ 61

2.8.13 MOVA Instruction.................................................................................................. 63

2.9 Processing States..................................................................................................................64

Section 3 MCU Operating Modes.......................................................................67

3.1 Operating Mode Selection...................................................................................................67

3.2 Register Descriptions...........................................................................................................68

3.2.1 Mode Control Register (MDCR)............................................................................68

3.2.2 System Control Register (SYSCR)......................................................................... 69

3.3 Operating Mode Descriptions.............................................................................................. 71

3.3.1 Mode 1.................................................................................................................... 71

3.3.2 Mode 2.................................................................................................................... 71

3.3.3 Mode 3.................................................................................................................... 71

3.4 Address Map........................................................................................................................ 72

3.4.1 Address Map (Advanced Mode)............................................................................. 72

Section 4 Exception Handling.............................................................................73

4.1 Exception Handling Types and Priority............................................................................... 73

4.2 Exception Sources and Exception Handling Vector Table.................................................. 74

4.3 Reset....................................................................................................................................76

4.3.1 Reset Exception Handling ...................................................................................... 76

4.3.2 Interrupts after Reset............................................................................................... 77

4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 77

4.4 Traces...................................................................................................................................78

4.5 Address Error....................................................................................................................... 79

4.5.1 Address Error Source.............................................................................................. 79

4.5.2 Address Error Exception Handling ......................................................................... 80

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4.6 Interrupts..............................................................................................................................81

4.6.1 Interrupt Sources..................................................................................................... 81

4.6.2 Interrupt Exception Handling .................................................................................82

4.7 Instruction Exception Handling...........................................................................................83

4.7.1 Trap Instruction.......................................................................................................83

4.7.2 Exception Handling by Illegal Instruction.............................................................. 84

4.8 Stack Status after Exception Handling.................................................................................85

4.9 Usage Note...........................................................................................................................86

Section 5 Interrupt Controller..............................................................................87

5.1 Features................................................................................................................................ 87

5.2 Input/Output Pi ns................................................................................................................. 88

5.3 Register Descriptions...........................................................................................................89

5.3.1 Interrupt Control Register (INTCR) .......................................................................89

5.3.2 CPU Priority Control Register (CPUPCR).............................................................90

5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R

(IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR).......................................92

5.3.4 IRQ Ena ble Register (IER).....................................................................................94

5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL)..................................96

5.3.6 IRQ Status Regi ster (ISR)..................................................................................... 101

5.3.7 Software Standby Release IRQ Enable Register (SSIER).................................... 102

5.4 Interrupt Source s................................................................................................................ 103

5.4.1 External Interrupts ................................................................................................103

5.4.2 Internal Inter r u pts.................................................................................................104

5.5 Interrupt Exception Handling Vector Table....................................................................... 105

5.6 Interrupt Control Modes and Interrupt Operation.............................................................. 112

5.6.1 Interrupt Control Mode 0...................................................................................... 112

5.6.2 Interrupt Control Mode 2...................................................................................... 114

5.6.3 Interrupt Exception Handling Sequence...............................................................116

5.6.4 Interrupt Response Times.....................................................................................117

5.6.5 DMAC Activa tion by Interrupt............................................................................. 118

5.7 CPU Priority Control Function Over DMAC....................................................................120

5.8 Usage Notes....................................................................................................................... 122

5.8.1 Conflict between Inter r upt Generation and Disabling ..........................................122

5.8.2 Instructions that Disable Interrupts.......................................................................123

5.8.3 Times when Interrupts are Disabled .....................................................................123

5.8.4 Interr upts during Execution of EEPMOV Instruction...........................................123

5.8.5 Interr upts during Execution of MOVMD and MOVSD Instructions....................123

5.8.6 Interrupt Flags of Peripheral Modules..................................................................124

Rev. 3.00 Mar. 14, 2006 Page xi of xxxviii

Section 6 Bus Controller (BSC)........................................................................125

6.1 Features.............................................................................................................................. 125

6.2 Register Descriptions......................................................................................................... 126

6.2.1 Bus Control Register 2 (BCR2)............................................................................ 126

6.3 Bus Configuration.............................................................................................................. 127

6.4 Multi-Clock Function ........................................................................................................ 128

6.5 Internal Bus........................................................................................................................129

6.5.1 Access to Internal Address Space......................................................................... 129

6.6 Write Data Buffer Function............................................................................................... 130

6.6.1 Write Data Buffer Function for Peripheral Module............................................... 130

6.7 Bus Arbitration..................................................................................................................131

6.7.1 Operation ..............................................................................................................131

6.7.2 Bus Transfer Timing............................................................................................. 131

6.8 Bus Controller Operation in Reset..................................................................................... 132

6.9 Usage Notes....................................................................................................................... 132

Section 7 DMA Controller (DMAC).................................................................133

7.1 Features.............................................................................................................................. 133

7.2 Register Descriptions......................................................................................................... 136

7.2.1 DMA Source Address Register (DSAR) .............................................................. 137

7.2.2 DMA Destination Address Register (DDAR) ...................................................... 138

7.2.3 DMA Offset Register (DOFR)..............................................................................139

7.2.4 DMA Transfer Count Register (DTCR)...............................................................140

7.2.5 DMA Block Size Register (DBSR) ...................................................................... 141

7.2.6 DMA Mode Control Register (DMDR)................................................................ 142

7.2.7 DMA Address Control Register (DACR)............................................................. 151

7.2.8 DMA Module Request Select Register (DMRSR)............................................... 157

7.3 Transfer Modes..................................................................................................................157

7.4 Operations.......................................................................................................................... 158

7.4.1 Address Modes ..................................................................................................... 158

7.4.2 Transfer Modes..................................................................................................... 162

7.4.3 Activation Sources................................................................................................ 166

7.4.4 Bus Access Modes................................................................................................ 168

7.4.5 Extended Repeat Area Function...........................................................................170

7.4.6 Address Updat e Function using Offset................................................................. 172

7.4.7 Register during DMA Transfer............................................................................. 176

7.4.8 Priority of Cha nnels.............................................................................................. 181

7.4.9 DMA Basic Bus Cycle.......................................................................................... 182

7.4.10 Bus Cycles in Dual Address Mode.......................................................................183

Rev. 3.00 Mar. 14, 2006 Page xii of xxxviii

7.4.11 Bus Cycles in Single Address Mode.....................................................................191

7.5 DMA Transfer End............................................................................................................ 196

7.6 Relationship among DMAC and Other Bus Masters......................................................... 198

7.6.1 CPU Priority Control Function Over DMAC .......................................................198

7.6.2 Bus Arbitration among DMAC and Other Bus Masters.......................................199

7.7 Interrupt Source s................................................................................................................ 200

7.8 Notes on Usage..................................................................................................................203

Section 8 I/O Ports.............................................................................................205

8.1 Register Descriptions......................................................................................................... 210

8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D, H, J, and K).................... 212

8.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, D, H, J, and K).......................................212

8.1.3 Port Register (PORTn) (n = 1 to 6, A, D, H, J, and K).........................................213

8.1.4 Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, H, J, and K)................213

8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D, H, J, and K).............................214

8.1.6 Open-Drain Control Register (PnODR) (n = 2).................................................... 215

8.1.7 Port H Realtime Input Data Register (PHRTIDR)................................................ 215

8.2 Output Buffer Control........................................................................................................ 216

8.2.1 Port 1.....................................................................................................................216

8.2.2 Port 2.....................................................................................................................219

8.2.3 Port 3.....................................................................................................................221

8.2.4 Port 6.....................................................................................................................225

8.2.5 Port A....................................................................................................................227

8.2.6 Port D....................................................................................................................230

8.2.7 Port H....................................................................................................................233

8.2.8 Port J.....................................................................................................................233

8.2.9 Port K....................................................................................................................236

8.3 Port Function Controller ....................................................................................................243

8.3.1 Port Function Control Register 9 (PFCR9)...........................................................243

8.3.2 Port Function Control Register A (PFCRA)......................................................... 245

8.3.3 Port Function Control Register B (PFCRB)..........................................................247

8.4 Usage Notes....................................................................................................................... 249

8.4.1 Notes on Input Buffer Control Register (ICR) Setting ......................................... 249

8.4.2 Notes on Port Function Control Register (PFCR) Settings................................... 249

Section 9 16-Bit Timer Pulse Unit (TPU) .........................................................251

9.1 Features.............................................................................................................................. 251

9.2 Input/Output Pi ns...............................................................................................................258

9.3 Register Descriptions......................................................................................................... 260

9.3.1 Timer Control Register (TCR).............................................................................. 265

Rev. 3.00 Mar. 14, 2006 Page xiii of xxxviii

9.3.2 Timer Mode Register (TMDR)............................................................................. 270

9.3.3 Timer I/O Control Register (TIOR)...................................................................... 272

9.3.4 Timer Interr upt Enable Register (TIER)............................................................... 290

9.3.5 Timer Status Register (TSR)................................................................................. 292

9.3.6 Timer Counter (TCNT)......................................................................................... 296

9.3.7 Timer Gene ral Regi ster (TGR)............................................................................. 296

9.3.8 Timer Start Register (TSTR) ................................................................................ 297

9.3.9 Timer Synchronous Register (TSYR)................................................................... 298

9.4 Operation...........................................................................................................................299

9.4.1 Basic Functions.....................................................................................................299

9.4.2 Synchronous Operation......................................................................................... 305

9.4.3 Buffer Operation................................................................................................... 307

9.4.4 Cascaded Operation.............................................................................................. 311

9.4.5 PWM Modes ......................................................................................................... 313

9.4.6 Phase Counting Mode........................................................................................... 318

9.5 Interrupt Source s................................................................................................................ 326

9.6 DMAC Activation..............................................................................................................329

9.7 A/D Converter Activation.................................................................................................. 329

9.8 Operation Timing...............................................................................................................330

9.8.1 Input/Output Timing............................................................................................. 330

9.8.2 Interr upt Signal Timing ........................................................................................ 334

9.9 Usage Notes....................................................................................................................... 337

9.9.1 Module Stop Mode Setting................................................................................... 337

9.9.2 Input Clock Restrictions ....................................................................................... 337

9.9.3 Caution on Cycle Setting......................................................................................338

9.9.4 Conflict between TCNT Write and Clear Operations........................................... 338

9.9.5 Conflict between TCNT Write and Increment Operations...................................339

9.9.6 Conflict between TGR Write and Compare Match...............................................339

9.9.7 Conflict between Buffer Register Write and Compare Match.............................. 340

9.9.8 Conflict between TGR Read and Input Capture................................................... 340

9.9.9 Conflict between TGR Write and Input Capture..................................................341

9.9.10 Conflict between Buffer Register Write and Input Capture.................................. 341

9.9.11 Conflict between Overflow/Underflow and Counter Clearing............................. 342

9.9.12 Conflict between TCNT Write and Overflow/Underflow....................................342

9.9.13 Multiplexing of I/O Pins.......................................................................................343

9.9.14 Interrupts and Module Stop Mode........................................................................343

Section 10 Programmable Pulse Generator (PPG)............................................345

10.1 Features.............................................................................................................................. 345

10.2 Input/Output Pins...............................................................................................................346

Rev. 3.00 Mar. 14, 2006 Page xiv of xxxviii

10.3 Register Descriptions......................................................................................................... 347

10.3.1 Next Data Enable Registers H, L (NDERH, NDERL) .........................................347

10.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 349

10.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 350

10.3.4 PPG Output Control Register (PCR) .................................................................... 353

10.3.5 PPG Output Mode Register (PMR) ...................................................................... 354

10.4 Operation ........................................................................................................................... 356

10.4.1 Output Timing....................................................................................................... 356

10.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 357

10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)................ 358

10.4.4 Non-Overlapping Pulse Output............................................................................. 359

10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................... 361

10.4.6 Example of Non-Overlapping Pulse Output

(Example of 4-Phase Complementary Non-Overlapping Pulse Output) ..............362

10.4.7 Inverted Pulse Output ........................................................................................... 364

10.4.8 Pulse Output Triggered by Input Capture.............................................................365

10.5 Usage Notes.......................................................................................................................365

10.5.1 Module Stop Mode Setting...................................................................................365

10.5.2 Operation of Pulse Output Pins............................................................................. 365

Section 11 Watchdog Timer (WDT)..................................................................367

11.1 Features..............................................................................................................................367

11.2 Register Descriptions......................................................................................................... 368

11.2.1 Timer Counter (TCNT).........................................................................................368

11.2.2 Timer Control/Status Register (TCSR)................................................................. 369

11.2.3 Reset Control/Status Register (RSTCSR)............................................................. 370

11.3 Operation ........................................................................................................................... 372

11.3.1 Watchdog Timer Mode.........................................................................................372

11.3.2 Interval Timer Mode............................................................................................. 373

11.4 Interrupt Source .................................................................................................................373

11.5 Usage Notes.......................................................................................................................374

11.5.1 Notes on Register Access...................................................................................... 374

11.5.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 375

11.5.3 Changing Values of Bits CKS2 to CKS0.............................................................. 375

11.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode.................375

11.5.5 Transition to Watchdog Timer Mode or Software Standby Mode........................376

Section 12 Serial Communication Interface (SCI)............................................377

12.1 Features..............................................................................................................................377

12.2 Input/Output Pins...............................................................................................................379

Rev. 3.00 Mar. 14, 2006 Page xv of xxxviii

12.3 Register Descriptions......................................................................................................... 380

12.3.1 Receive Shift Register (RSR) ............................................................................... 381

12.3.2 Receive Data Register (RDR)............................................................................... 381

12.3.3 Transmit Data Register (TDR).............................................................................. 381

12.3.4 Transmit Shift Register (TSR)..............................................................................382

12.3.5 Serial Mode Register (SMR) ................................................................................ 382

12.3.6 Serial Control Register (SCR) ..............................................................................385

12.3.7 Serial Status Register (SSR) ................................................................................. 389

12.3.8 Smart Card Mode Register (SCMR)..................................................................... 397

12.3.9 Bit Rate Register (BRR) ....................................................................................... 398

12.4 Operation in Asynchronous Mode..................................................................................... 405

12.4.1 Data Transfer Format............................................................................................ 406

12.4.2 Receive Data Sampling Timing and Reception Margin

in Asynchronous Mode......................................................................................... 407

12.4.3 Clock..................................................................................................................... 408

12.4.4 SCI Initialization (Asynchronous Mode).............................................................. 409

12.4.5 Serial Data Transmission (Asynchronous Mode).................................................410

12.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 412

12.5 Multiprocessor Communication Function..........................................................................416

12.5.1 Multiprocessor Serial Data Transmission.............................................................418

12.5.2 Multiprocessor Serial Data Reception .................................................................. 419

12.6 Operation in Clocked Synchronous Mode......................................................................... 422

12.6.1 Clock..................................................................................................................... 422

12.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 423

12.6.3 Serial Data Transmission (Clocked Synchronous Mode).....................................424

12.6.4 Serial Data Reception (Clocked Synchronous Mode) ..........................................426

12.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode)..............................................................................427

12.7 Operation in Smart Card Interface Mode........................................................................... 429

12.7.1 Sample Connection............................................................................................... 429

12.7.2 Data Format (Except in Block Transfer Mode) .................................................... 430

12.7.3 Block Transfer Mode............................................................................................ 431

12.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 432

12.7.5 Initialization..........................................................................................................433

12.7.6 Data Transmission (Except in Block Transfer Mode) .......................................... 434

12.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 437

12.7.8 Clock Output Control............................................................................................ 438

12.8 Interrupt Sources................................................................................................................ 440

12.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 440

12.8.2 Interrupts in Smart Card Interface Mode..............................................................441

Rev. 3.00 Mar. 14, 2006 Page xvi of xxxviii

12.9 Usage Notes.......................................................................................................................442

12.9.1 Module Stop Mode Setting...................................................................................442

12.9.2 Break Detection and Processing ........................................................................... 442

12.9.3 Mark State and Break Detection...........................................................................442

12.9.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) .....................................................................442

12.9.5 Relation between Writing to TDR and TDRE Flag..............................................443

12.9.6 Restrictions on Using DMAC............................................................................... 443

12.9.7 SCI Operations during Mode Transitions .............................................................444

Section 13 Controller Area Network (HCAN) ..................................................449

13.1 Features..............................................................................................................................449

13.2 Input/Output Pins...............................................................................................................451

13.3 Register Descriptions......................................................................................................... 452

13.3.1 Master Control Register (MCR) ...........................................................................453

13.3.2 General Status Register (GSR) ............................................................................. 454

13.3.3 Bit Configuration Register (BCR) ........................................................................ 456

13.3.4 Mailbox Configuration Register (MBCR) ............................................................458

13.3.5 Transmit Wait Register (TXPR) ........................................................................... 459

13.3.6 Transmit Wait Cancel Register (TXCR)............................................................... 460

13.3.7 Transmit Acknowledge Register (TXACK) ......................................................... 461

13.3.8 Abort Acknowledge Register (ABACK) ..............................................................462

13.3.9 Receive Complete Register (RXPR)..................................................................... 463

13.3.10 Remote Request Register (RFPR).........................................................................464

13.3.11 Interrupt Register (IRR)........................................................................................ 465

13.3.12 Mailbox Interrupt Mask Register (MBIMR).........................................................470

13.3.13 Interrupt Mask Register (IMR)............................................................................. 471

13.3.14 Receive Error Counter (REC)............................................................................... 473

13.3.15 Transmit Error Counter (TEC)..............................................................................473

13.3.16 Unread Message Status Register (UMSR)............................................................ 474

13.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)............................................ 475

13.3.18 Message Control (MC0 to MC15)........................................................................ 478

13.3.19 Message Data (MD0 to MD15) ............................................................................ 481

13.3.20 HCAN Monitor Register (HCANMON)...............................................................483

13.4 Operation ........................................................................................................................... 484

13.4.1 Hardware and Software Resets.............................................................................484

13.4.2 Initialization after Hardware Reset ....................................................................... 484

13.4.3 Message Transmission..........................................................................................490

13.4.4 Message Reception ............................................................................................... 494

13.4.5 HCAN Sleep Mode...............................................................................................498

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13.4.6 HCAN Halt Mode................................................................................................. 500

13.5 Interrupt Sources................................................................................................................ 501

13.6 DMAC Interface................................................................................................................502

13.7 CAN Bus Interface............................................................................................................. 503

13.8 Usage Notes....................................................................................................................... 504

13.8.1 Module Stop Mode Setting...................................................................................504

13.8.2 Reset ..................................................................................................................... 504

13.8.3 HCAN Sleep Mode............................................................................................... 504

13.8.4 Interrupts............................................................................................................... 505

13.8.5 Error Counters ......................................................................................................505

13.8.6 Register Access..................................................................................................... 505

13.8.7 Register Hold in Standby Modes..........................................................................505

13.8.8 Use on Bit Manipulation Instructions...................................................................505

13.8.9 HCAN TXCR Operation ......................................................................................506

13.8.10 HCAN Transmission Setting................................................................................507

13.8.11 Canceling HCAN Reset and HCAN Sleep Mode................................................. 507

13.8.12 Accessing Mailbox in HCAN Sleep Mode........................................................... 507

Section 14 Synchronous Serial Communication Unit (SSU)............................509

14.1 Features.............................................................................................................................. 509

14.2 Input/Output Pins...............................................................................................................511

14.3 Register Descriptions......................................................................................................... 512

14.3.1 SS Control Register H (SSCRH) .......................................................................... 514

14.3.2 SS Control Register L (SSCRL) ........................................................................... 516

14.3.3 SS Mode Register (SSMR)...................................................................................517

14.3.4 SS Enable Register (SSER) .................................................................................. 518

14.3.5 SS Status Register (SSSR).................................................................................... 519

14.3.6 SS Control Register 2 (SSCR2)............................................................................521

14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 523

14.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 524

14.3.9 SS Shift Register (SSTRSR)................................................................................. 525

14.4 Operation ........................................................................................................................... 526

14.4.1 Transfer Clock ...................................................................................................... 526

14.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 526

14.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 527

14.4.4 Communication Modes and Pin Functions...........................................................528

14.4.5 SSU Mode............................................................................................................. 530

14.4.6 SCS Pin Control and Conflict Error...................................................................... 538

14.4.7 Clock Synchronous Communication Mode..........................................................539

14.5 Interrupt Requests..............................................................................................................545

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14.6 Usage Note......................................................................................................................... 546

14.6.1 Setting of Module Stop Mode............................................................................... 546

14.6.2 Notes on Clearing Module Stop Mode .................................................................546

Section 15 A/D Converter..................................................................................547

15.1 Features..............................................................................................................................547

15.2 Input/Output Pins...............................................................................................................550

15.3 Register Descriptions......................................................................................................... 551

15.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 552

15.3.2 A/D Control/Status Register (ADCSR) ................................................................ 553

15.3.3 A/D Control Register (ADCR) ............................................................................. 555

15.4 Operation ........................................................................................................................... 556

15.4.1 Single Mode.......................................................................................................... 556

15.4.2 Scan Mode ............................................................................................................ 557

15.4.3 Input Sampling and A/D Conversion Time .......................................................... 559

15.4.4 External Trigger Input Timing.............................................................................. 560

15.5 Interrupt Source .................................................................................................................561

15.6 A/D Conversion Accuracy Definitions.............................................................................. 561

15.7 Usage Notes.......................................................................................................................563

15.7.1 Module Stop Mode Setting...................................................................................563

15.7.2 Permissible Signal Source Impedance..................................................................563

15.7.3 Influences on Absolute Accuracy .........................................................................564

15.7.4 Setting Range of Analog Power Supply and Other Pins.......................................564

15.7.5 Notes on Board Design.........................................................................................564

15.7.6 Notes on Noise Countermeasures .........................................................................565

15.7.7 A/D Input Hold Function in Software Standby Mode .......................................... 566

Section 16 RAM ................................................................................................567

Section 17 Flash Memory (0.18-µm F-ZTAT Version)....................................569

17.1 Features..............................................................................................................................569

17.2 Mode Transition Diagram.................................................................................................. 571

17.3 Memory MAT Configuration.............................................................................................573

17.4 Block Structure..................................................................................................................574

17.5 Programming/Erasing Interface......................................................................................... 575

17.6 Input/Output Pins...............................................................................................................577

17.7 Register Descriptions......................................................................................................... 578

17.7.1 Programming/Erasing Interface Registers ............................................................579

17.7.2 Programming/Erasing Interface Parameters ......................................................... 586

17.7.3 RAM Emulation Register (RAMER)....................................................................598

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17.8 On-Board Programming Mode..........................................................................................599

17.8.1 Boot Mode ............................................................................................................ 599

17.8.2 User Program Mode.............................................................................................. 603

17.8.3 User Boot Mode.................................................................................................... 613

17.8.4 On-Chip Program and Storable Area for Program Data.......................................617

17.9 Protection........................................................................................................................... 623

17.9.1 Hardware Protection ............................................................................................. 623

17.9.2 Software Protection ..............................................................................................624

17.9.3 Error Protection ....................................................................................................624

17.10 Flash Memory Emulation Using RAM..............................................................................626

17.11 Switching between User MAT and User Boot MAT......................................................... 629

17.12 Programmer Mode.............................................................................................................630

17.13 Standard Serial Communication Interface Specifications for Boot Mode ......................... 630

17.14 Usage Notes....................................................................................................................... 658

Section 18 Clock Pulse Generator.....................................................................661

18.1 Register Description .......................................................................................................... 662

18.1.1 System Clock Control Register (SCKCR)............................................................662

18.2 Oscillator............................................................................................................................ 665

18.2.1 Connecting Crystal Resonator .............................................................................. 665

18.2.2 External Clock Input............................................................................................. 666

18.3 PLL Circuit........................................................................................................................666

18.4 Frequency Divider.............................................................................................................666

18.5 Usage Notes....................................................................................................................... 667

18.5.1 Notes on Clock Pulse Generator........................................................................... 667

18.5.2 Notes on Resonator............................................................................................... 668

18.5.3 Notes on Board Design.........................................................................................668

18.5.4 Notes on Input Clock Frequency .......................................................................... 669

Section 19 Power-Down Modes........................................................................671

19.1 Features.............................................................................................................................. 671

19.2 Register Descriptions......................................................................................................... 672

19.2.1 Standby Control Register (SBYCR).....................................................................673

19.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB)..............675

19.2.3 Module Stop Control Register C (MSTPCRC)..................................................... 678

19.3 Multi-Clock Function ........................................................................................................ 679

19.4 Module Stop Mode ............................................................................................................ 679

19.5 Sleep Mode........................................................................................................................680

19.5.1 Transition to Sleep Mode...................................................................................... 680

19.5.2 Clearing Sleep Mode ............................................................................................680

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19.6 All-Module-Clock-Stop Mode........................................................................................... 680

19.7 Software Standby Mode..................................................................................................... 681

19.7.1 Transition to Software Standby Mode ..................................................................681

19.7.2 Clearing Software Standby Mode.........................................................................681

19.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ........... 682

19.7.4 Software Standby Mode Application Example.....................................................684

19.8 Bφ Clock Output Control................................................................................................... 685

19.9 Usage Notes.......................................................................................................................686

19.9.1 I/O Port Status.......................................................................................................686

19.9.2 Current Consumption during Oscillation Settling Standby Period ....................... 686

19.9.3 DMAC Module Stop.............................................................................................686

19.9.4 On-Chip Peripheral Module Interrupts .................................................................686

19.9.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC...........................................686

Section 20 List of Registers...............................................................................687

20.1 Register Addresses (Address Order).................................................................................. 688

20.2 Register Bits....................................................................................................................... 711

20.3 Register States in Each Operating Mode ...........................................................................738

Section 21 Electrical Characteristics .................................................................761

21.1 Absolute Maximum Ratings..............................................................................................761

21.2 DC Characteristics.............................................................................................................762

21.3 AC Characteristics.............................................................................................................764

21.3.1 Clock Timing........................................................................................................765

21.3.2 Control Signal Timing .......................................................................................... 767

21.3.3 Timing of On-Chip Peripheral Modules ...............................................................768

21.4 A/D Conversion Characteristics.........................................................................................776

21.5 Flash Memory Characteristics ........................................................................................... 777

Appendix .........................................................................................................779

A. Port States in Each Pin State.............................................................................................. 779

B. Product Lineup................................................................................................................... 780

C. Package Dimensions ..........................................................................................................781

Main Revisions and Additions in this Edition.....................................................783

Index .........................................................................................................799

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Figures

Section 1 Overview

Figure 1.1 Block Diagram of H8SX/1527...................................................................................... 2

Figure 1.2 Block Diagram of H8SX/1525...................................................................................... 3

Figure 1.3 Pin Assignments of H8SX/1527.................................................................................... 4

Figure 1.4 Pin Assignments of H8SX/1525.................................................................................... 5

Section 2 CPU

Figure 2.1 CPU Operating Modes ................................................................................................21

Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 22

Figure 2.3 Stack Structure (Normal Mode) ..................................................................................22

Figure 2.4 Exception Vector Table (Middle and Advanced Modes)............................................ 24

Figure 2.5 Stack Structure (Middle and Advanced Modes).......................................................... 25

Figure 2.6 Exception Vector Table (Maximum Modes)............................................................... 26

Figure 2.7 Stack Structure (Maximum Mode).............................................................................. 26

Figure 2.8 Memory Map............................................................................................................... 27

Figure 2.9 CPU Registers .............................................................................................................28

Figure 2.10 Usage of General Registers....................................................................................... 29

Figure 2.11 Stack.......................................................................................................................... 30

Figure 2.12 General Register Data Formats .................................................................................34

Figure 2.13 Memory Data Formats...............................................................................................35

Figure 2.14 Instruction Formats.................................................................................................... 53

Figure 2.15 Branch Address Specification in Memory Indirect Mode......................................... 60

Figure 2.16 State Transitions........................................................................................................ 65

Section 3 MCU Operating Modes

Figure 3.1 Address Map (Advanced Mode) .................................................................................72

Section 4 Exception Handling

Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode)....................................... 77

Figure 4.2 Stack Status after Exception Handling........................................................................ 85

Figure 4.3 Operation when SP Value Is Odd................................................................................ 86

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 88

Figure 5.2 Block Diagram of Interrupts IRQn............................................................................ 104

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0... 113
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 115

Figure 5.5 Interrupt Exception Handling.................................................................................... 116

Figure 5.6 Block Diagram of DMAC and Interrupt Controller .................................................. 118

Figure 5.7 Conflict between Interrupt Generation and Disabling............................................... 122

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Section 6 Bus Controller (BSC)

Figure 6.1 Block Diagram of Bus Controller..............................................................................125

Figure 6.2 Internal Bus Configuration........................................................................................ 127

Figure 6.3 Example of Timing when Write Data Buffer Function is Used ................................ 130

Section 7 DMA Controller (DMAC)

Figure 7.1 Block Diagram of DMAC......................................................................................... 135

Figure 7.2 Example of Signal Timing in Dual Address Mode ................................................... 159

Figure 7.3 Operations in Dual Address Mode ............................................................................159

Figure 7.4 Data Flow in Single Address Mode........................................................................... 160

Figure 7.5 Example of Signal Timing in Single Address Mode................................................. 161

Figure 7.6 Operations in Single Address Mode.......................................................................... 161

Figure 7.7 Example of Signal Timing in Normal Transfer Mode...............................................162

Figure 7.8 Operations in Normal Transfer Mode ....................................................................... 162

Figure 7.9 Operations in Repeat Transfer Mode ........................................................................163

Figure 7.10 Operations in Block Transfer Mode........................................................................ 164

Figure 7.11 Operation in Single Address Mode in Block Transfer Mode

(Block Area Specified) ...........................................................................................165

Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode

(Block Area Not Specified) ..................................................................................... 165

Figure 7.13 Example of Timing in Cycle Stealing Mode........................................................... 169

Figure 7.14 Example of Timing in Burst Mode.......................................................................... 169

Figure 7.15 Example of Extended Repeat Area Operation......................................................... 171

Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode ...................171

Figure 7.17 Address Update Method.......................................................................................... 172

Figure 7.18 Operation of Offset Addition .................................................................................. 173

Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode..........174

Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode .........175

Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred.............. 179

Figure 7.22 Example of Timing for Channel Priority................................................................. 181

Figure 7.23 Example of Bus Timing of DMA Transfer ............................................................. 182

Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 183

Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing

(Transfer Source DSAR = Odd Address and Source Address Increment).............. 184

Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing

(Transfer Destination DDAR = Odd Address and Destination

Address Decrement) .............................................................................................. 184

Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access........................... 185

Figure 7.28 Example of Transfer in Block Transfer Mode......................................................... 186

Figure 7.29 Example of Transfer in Normal Transfer Mode Activated

by DREQ Falling Edge........................................................................................... 187

Figure 7.30 Example of Transfer in Normal Transfer Mode Activated

by DREQ Low Level.............................................................................................. 188

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Figure 7.31 Example of Transfer in Block Transfer Mode Activated

by DREQ Low Level.............................................................................................. 189

Figure 7.32 Example of Transfer in Normal Transfer Mode Activated

by DREQ Low Level with NRD = 1.......................................................................190

Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) ....................................191

Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) ....................................192

Figure 7.35 Example of Transfer in Single Address Mode Activated

by DREQ Falling Edge........................................................................................... 193

Figure 7.36 Example of Transfer in Single Address Mode Activated

by DREQ Low Level.............................................................................................. 194

Figure 7.37 Example of Transfer in Single Address Mode Activated

by DREQ Low Level with NRD = 1.......................................................................195

Figure 7.38 Interrupt and Interrupt Sources................................................................................ 202

Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source ...............202

Section 8 I/O Ports

Figure 8.1 Port Block Diagram................................................................................................... 211

Section 9 16-Bit Timer Pulse Unit (TPU)

Figure 9.1 Block Diagram of TPU (Unit 0)................................................................................ 256

Figure 9.2 Block Diagram of TPU (Unit 1)................................................................................ 257

Figure 9.3 Example of Counter Operation Setting Procedure ....................................................299

Figure 9.4 Free-Running Counter Operation.............................................................................. 300

Figure 9.5 Periodic Counter Operation....................................................................................... 301

Figure 9.6 Example of Setting Procedure for Waveform Output by Compare Match................ 301

Figure 9.7 Example of 0-Output/1-Output Operation................................................................. 302

Figure 9.8 Example of Toggle Output Operation .......................................................................302

Figure 9.9 Example of Setting Procedure for Input Capture Operation...................................... 303

Figure 9.10 Example of Input Capture Operation.......................................................................304

Figure 9.11 Example of Synchronous Operation Setting Procedure ..........................................305

Figure 9.12 Example of Synchronous Operation........................................................................ 306

Figure 9.13 Compare Match Buffer Operation........................................................................... 307

Figure 9.14 Input Capture Buffer Operation...............................................................................308

Figure 9.15 Example of Buffer Operation Setting Procedure..................................................... 308

Figure 9.16 Example of Buffer Operation (1)............................................................................. 309

Figure 9.17 Example of Buffer Operation (2)............................................................................. 310

Figure 9.18 Example of Cascaded Operation Setting Procedure................................................ 311

Figure 9.19 Example of Cascaded Operation (1)........................................................................ 312

Figure 9.20 Example of Cascaded Operation (2)........................................................................ 312

Figure 9.21 Example of PWM Mode Setting Procedure ............................................................315

Figure 9.22 Example of PWM Mode Operation (1) ...................................................................316

Figure 9.23 Example of PWM Mode Operation (2) ...................................................................316

Figure 9.24 Example of PWM Mode Operation (3) ...................................................................317

Figure 9.25 Example of Phase Counting Mode Setting Procedure............................................. 319

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Figure 9.26 Example of Phase Counting Mode 1 Operation ......................................................320

Figure 9.27 Example of Phase Counting Mode 2 Operation ......................................................321

Figure 9.28 Example of Phase Counting Mode 3 Operation ......................................................322

Figure 9.29 Example of Phase Counting Mode 4 Operation ......................................................323

Figure 9.30 Phase Counting Mode Application Example........................................................... 325

Figure 9.31 Count Timing in Internal Clock Operation..............................................................330

Figure 9.32 Count Timing in External Clock Operation ............................................................ 330

Figure 9.33 Output Compare Output Timing ............................................................................. 331

Figure 9.34 Input Capture Input Signal Timing.......................................................................... 331

Figure 9.35 Counter Clear Timing (Compare Match) ................................................................332

Figure 9.36 Counter Clear Timing (Input Capture).................................................................... 332

Figure 9.37 Buffer Operation Timing (Compare Match) ........................................................... 333

Figure 9.38 Buffer Operation Timing (Input Capture) ............................................................... 333

Figure 9.39 TGI Interrupt Timing (Compare Match)................................................................. 334

Figure 9.40 TGI Interrupt Timing (Input Capture)..................................................................... 334

Figure 9.41 TCIV Interrupt Setting Timing................................................................................ 335

Figure 9.42 TCIU Interrupt Setting Timing................................................................................ 335

Figure 9.43 Timing for Status Flag Clearing by CPU ................................................................ 336

Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (1)..................................... 336

Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2)..................................... 337

Figure 9.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode.................. 337

Figure 9.47 Conflict between TCNT Write and Clear Operations .............................................338

Figure 9.48 Conflict between TCNT Write and Increment Operations...................................... 339

Figure 9.49 Conflict between TGR Write and Compare Match................................................. 339

Figure 9.50 Conflict between Buffer Register Write and Compare Match ................................ 340

Figure 9.51 Conflict between TGR Read and Input Capture...................................................... 340

Figure 9.52 Conflict between TGR Write and Input Capture..................................................... 341

Figure 9.53 Conflict between Buffer Register Write and Input Capture.................................... 341

Figure 9.54 Conflict between Overflow and Counter Clearing .................................................. 342

Figure 9.55 Conflict between TCNT Write and Overflow......................................................... 342

Section 10 Programmable Pulse Generator (PPG)

Figure 10.1 Block Diagram of PPG............................................................................................ 345

Figure 10.2 Schematic Diagram of PPG..................................................................................... 356

Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)................................. 356

Figure 10.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 357

Figure 10.5 Normal Pulse Output Example (5-Phase Pulse Output) .......................................... 358

Figure 10.6 Non-Overlapping Pulse Output ............................................................................... 359

Figure 10.7 Non-Overlapping Operation and NDR Write Timing............................................. 360

Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example).............................361

Figure 10.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) .....................362

Figure 10.10 Inverted Pulse Output (Example).......................................................................... 364

Figure 10.11 Pulse Output Triggered by Input Capture (Example)............................................ 365

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Section 11 Watchdog Timer (WDT)

Figure 11.1 Block Diagram of WDT.......................................................................................... 367

Figure 11.2 Operation in Watchdog Timer Mode.......................................................................372

Figure 11.3 Operation in Interval Timer Mode...........................................................................373

Figure 11.4 Writing to TCNT, TCSR, and RSTCSR.................................................................. 374

Figure 11.5 Conflict between TCNT Write and Increment ........................................................375

Section 12 Serial Communication Interface (SCI)

Figure 12.1 Block Diagram of SCI............................................................................................. 378

Figure 12.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................405

Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................407

Figure 12.4 Phase Relation between Output Clock and Transmit Data

(Asynchronous Mode) ............................................................................................408

Figure 12.5 Sample SCI Initialization Flowchart .......................................................................409

Figure 12.6 Example of Operation for Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 410

Figure 12.7 Sample Serial Transmission Flowchart ...................................................................411

Figure 12.8 Example of SCI Operation for Reception

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 412

Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 414

Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 415

Figure 12.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A).......................................... 417

Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart........................................ 418

Figure 12.12 Example of SCI Operation for Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................419

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 420

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 421

Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 422

Figure 12.15 Sample SCI Initialization Flowchart .....................................................................423

Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode .............425

Figure 12.17 Sample Serial Transmission Flowchart................................................................. 425

Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode...................426

Figure 12.19 Sample Serial Reception Flowchart ......................................................................427

Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ..............428

Figure 12.21 Pin Connection for Smart Card Interface .............................................................. 429

Figure 12.22 Data Formats in Normal Smart Card Interface Mode............................................ 430

Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0) ......................................................430

Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 431

Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode

(When Clock Frequency is 372 Times the Bit Rate) ............................................432

Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode ......................................435

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Figure 12.27 TEND Flag Set Timing during Transmission........................................................ 435

Figure 12.28 Sample Transmission Flowchart ...........................................................................436

Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode............................................ 437

Figure 12.30 Sample Reception Flowchart................................................................................. 438

Figure 12.31 Clock Output Fixing Timing .................................................................................438

Figure 12.32 Clock Stop and Restart Procedure......................................................................... 439

Figure 12.33 Sample Transmission using DMAC in Clocked Synchronous Mode....................443

Figure 12.34 Sample Flowchart for Mode Transition during Transmission............................... 445

Figure 12.35 Port Pin States during Mode Transition

(Internal Clock, Asynchronous Transmission) .....................................................446

Figure 12.36 Port Pin States during Mode Transition

(Internal Clock, Clocked Synchronous Transmission) .........................................446

Figure 12.37 Sample Flowchart for Mode Transition during Reception.................................... 447

Section 13 Controller Area Network (HCAN)

Figure 13.1 HCAN Block Diagram............................................................................................ 450

Figure 13.2 Message Control Register Configuration ................................................................ 478

Figure 13.3 Standard Format...................................................................................................... 478

Figure 13.4 Extended Format ..................................................................................................... 478

Figure 13.5 Message Data Configuration ................................................................................... 481

Figure 13.6 Hardware Reset Flowchart ...................................................................................... 485

Figure 13.7 Software Reset Flowchart .......................................................................................486

Figure 13.8 Detailed Description of One Bit.............................................................................. 487

Figure 13.9 Transmission Flowchart.......................................................................................... 490

Figure 13.10 Transmit Message Cancellation Flowchart ...........................................................493

Figure 13.11 Reception Flowchart ............................................................................................. 494

Figure 13.12 Unread Message Overwrite Flowchart.................................................................. 497

Figure 13.13 HCAN Sleep Mode Flowchart ..............................................................................498

Figure 13.14 HCAN Halt Mode Flowchart ................................................................................ 500

Figure 13.15 DMAC Transfer Flowchart ................................................................................... 502

Figure 13.16 High-Speed Interface Using PCA82C250............................................................. 503

Section 14 Synchronous Serial Communication Unit (SSU)

Figure 14.1 Block Diagram of SSU............................................................................................ 510

Figure 14.2 Relationship of Clock Phase, Polarity, and Data..................................................... 526

Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register ..................... 527

Figure 14.4 Example of Initial Settings in SSU Mode ...............................................................530

Figure 14.5 Example of Transmission Operation (SSU Mode).................................................. 532

Figure 14.6 Flowchart Example of Data Transmission (SSU Mode) .........................................533

Figure 14.7 Example of Reception Operation (SSU Mode)....................................................... 535

Figure 14.8 Flowchart Example of Data Reception (SSU Mode) ..............................................536

Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode).......... 537

Figure 14.10 Conflict Error Detection Timing (Before Transfer) ..............................................538

Figure 14.11 Conflict Error Detection Timing (After Transfer End) .........................................538

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Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode........... 539

Figure 14.13 Example of Transmission Operation

(Clock Synchronous Communication Mode)........................................................540

Figure 14.14 Flowchart Example of Transmission Operation

(Clock Synchronous Communication Mode)........................................................541

Figure 14.15 Example of Reception Operation

(Clock Synchronous Communication Mode)........................................................542

Figure 14.16 Flowchart Example of Data Reception

(Clock Synchronous Communication Mode)........................................................543

Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception

(Clock Synchronous Communication Mode)........................................................544

Section 15 A/D Converter

Figure 15.1 Block Diagram of A/D Converter (Unit 0/AD_0)................................................... 548

Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1)................................................... 549

Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 557

Figure 15.4 Example of A/D Conversion

(Scan Mode, Three Channels (AN0 to AN2) Selected).......................................... 558

Figure 15.5 A/D Conversion Timing.......................................................................................... 559

Figure 15.6 External Trigger Input Timing ................................................................................560

Figure 15.7 A/D Conversion Accuracy Definitions....................................................................562

Figure 15.8 A/D Conversion Accuracy Definitions....................................................................562

Figure 15.9 Example of Analog Input Circuit ............................................................................563

Figure 15.10 Example of Analog Input Protection Circuit ......................................................... 565

Figure 15.11 Analog Input Pin Equivalent Circuit .....................................................................566

Section 17 Flash Memory (0.18-mm F-ZTAT Version)

Figure 17.1 Block Diagram of Flash Memory............................................................................ 570

Figure 17.2 Mode Transition of Flash Memory.......................................................................... 571

Figure 17.3 Memory MAT Configuration .................................................................................. 573

Figure 17.4 Block Structure of User MAT ................................................................................. 574

Figure 17.5 Procedure for Creating Procedure Program.............................................................575

Figure 17.6 System Configuration in Boot Mode....................................................................... 599

Figure 17.7 Automatic-Bit-Rate Adjustment Operation............................................................. 600

Figure 17.8 Boot Mode State Transition Diagram...................................................................... 601

Figure 17.9 Programming/Erasing Flow.....................................................................................603

Figure 17.10 RAM Map when Programming/Erasing is Executed ............................................604

Figure 17.11 Programming Procedure in User Program Mode ..................................................605

Figure 17.12 Erasing Procedure in User Program Mode............................................................ 610

Figure 17.13 Repeating Procedure of Erasing, Programming,

and RAM Emulation in User Program Mode .......................................................612

Figure 17.14 Procedure for Programming User MAT in User Boot Mode ................................614

Figure 17.15 Procedure for Erasing User MAT in User Boot Mode.......................................... 616

Figure 17.16 Transitions to Error Protection State .....................................................................625

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Figure 17.17 RAM Emulation Flow........................................................................................... 626

Figure 17.18 Address Map of Overlaid RAM Area ................................................................... 627

Figure 17.19 Programming Tuned Data .....................................................................................628

Figure 17.20 Switching between User MAT and User Boot MAT ............................................ 629

Figure 17.21 Boot Program States..............................................................................................631

Figure 17.22 Bit-Rate-Adjustment Sequence ............................................................................. 632

Figure 17.23 Communication Protocol Format.......................................................................... 633

Figure 17.24 New Bit-Rate Selection Sequence......................................................................... 644

Figure 17.25 Programming Sequence......................................................................................... 648

Figure 17.26 Erasure Sequence .................................................................................................. 649

Section 18 Clock Pulse Generator

Figure 18.1 Block Diagram of Clock Pulse Generator ............................................................... 661

Figure 18.2 Connection of Crystal Resonator (Example)........................................................... 665

Figure 18.3 Crystal Resonator Equivalent Circuit...................................................................... 665

Figure 18.4 External Clock Input (Examples) ............................................................................ 666

Figure 18.5 Clock Modification Timing..................................................................................... 667

Figure 18.6 Note on Board Design for Oscillation Circuit......................................................... 668

Figure 18.7 Connection Example of Bypass Capacitor.............................................................. 669

Section 19 Power-Down Modes

Figure 19.1 Mode Transitions..................................................................................................... 672

Figure 19.2 Software Standby Mode Application Example .......................................................684

Section 21 Electrical Characteristics

Figure 21.1 Output Load Circuit ................................................................................................ 764

Figure 21.2 System Bus Clock Timing....................................................................................... 765

Figure 21.3 Oscillation Settling Timing after Software Standby Mode .....................................766

Figure 21.4 Oscillation Settling Timing ..................................................................................... 766

Figure 21.5 External Input Clock Timing................................................................................... 766

Figure 21.6 Reset Input Timing.................................................................................................. 767

Figure 21.7 Interrupt Input Timing............................................................................................. 768

Figure 21.8 I/O Port Input/Output Timing.................................................................................. 771

Figure 21.9 Data Input Timing for Realtime Input Port............................................................. 771

Figure 21.10 TPU Input/Output Timing..................................................................................... 772

Figure 21.11 TPU Clock Input Timing....................................................................................... 772

Figure 21.12 PPG Output Timing............................................................................................... 772

Figure 21.13 SCK Clock Input/Output Timing ..........................................................................772

Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode....................................... 773

Figure 21.15 A/D Converter External Trigger Input Timing...................................................... 773

Figure 21.16 HCAN Input/Output Timing .................................................................................773

Figure 21.17 SSU Timing (Master, CPHS = 1).......................................................................... 774

Figure 21.18 SSU Timing (Master, CPHS = 0).......................................................................... 774

Figure 21.19 SSU Timing (Slave, CPHS = 1)............................................................................ 775

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