Renesas H8SX/1500 Series, H8SX/1520 Series, H8SX/1525, H8SX Series, R5F61525 Hardware Manual

REJ09B0104-0300

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32

H8SX/1527 R5F61527
H8SX/1525 R5F61525

H8SX/1520Group

Hardware Manual

Renesas 32-Bit CISC Microcomputer

H8SX Family H8SX/1500 Series

Rev.3.00
Revision Date: Mar. 14, 2006

Rev. 3.00 Mar. 14, 2006 Page ii of xxxviii

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 3.00 Mar. 14, 2006 Page iii of xxxviii

General Precautions on Handling of Product

1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are hi g h-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Rese r ved Ad dresses
Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 3.00 Mar. 14, 2006 Page iv of xxxviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 3.00 Mar. 14, 2006 Page v of xxxviii

Preface

The H8SX/1520 Group is a single-chip microcomputer made up of the high-speed internal 32-bit
H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX
CPU is upward compatible with the H8/300, H8/300H, and H8S CPUs.

Target Users: This manual was written for users who will be using the H8SX/1520 Group in the

design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8SX/1520 Group to the target users.
Refer to the H8SX Family Software Manual for a detailed description of the
instruction set.

Notes on reading this manual:

In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughl y categorized into parts
on the CPU, system control functions, and peripheral functions.

In order to understand the details of the CPU's functions

Read the H8SX Family Software Manual.

In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 20,
List of Registers.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial
communication interface, is implemented on more than one
channel:
XXX_N (XXX is the register name and N is the channel

number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our w eb site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/

Rev. 3.00 Mar. 14, 2006 Page vi of xxxviii

H8SX/1520 Group manuals:

Document Title Document No.

H8SX/1520 Group Hardware Manual This manual

H8/SX Family Software Manual REJ09B0102

Rev. 3.00 Mar. 14, 2006 Page vii of xxxviii

Rev. 3.00 Mar. 14, 2006 Page viii of xxxviii

Contents

Section 1 Overview................................................................................................1

1.1 Features.................................................................................................................................. 1

1.2 Block Diagram....................................................................................................................... 2

1.3 Pin Assignments.....................................................................................................................4

1.3.1 Pin Assignments.......................................................................................................4

1.3.2 Pin Configuration in Each Operating Mode..............................................................6

1.3.3 Pin Functions ..........................................................................................................10

Section 2 CPU......................................................................................................19

2.1 Features................................................................................................................................ 19

2.2 CPU Operating Modes......................................................................................................... 21

2.2.1 Normal Mode..........................................................................................................21

2.2.2 Middle Mode..........................................................................................................23

2.2.3 Advanced Mode......................................................................................................24

2.2.4 Maximum Mode.....................................................................................................25

2.3 Instruction Fetch..................................................................................................................27

2.4 Address Space...................................................................................................................... 27

2.5 Registers...............................................................................................................................28

2.5.1 General Registers....................................................................................................29

2.5.2 Program Counter (PC)............................................................................................30

2.5.3 Condition-Code Register (CCR).............................................................................30

2.5.4 Extended Control Register (EXR)..........................................................................32

2.5.5 Vector Base Register (VBR)................................................................................... 32

2.5.6 Short Address Base Register (SBR)........................................................................32

2.5.7 Multiply-Accumulate Register (MAC)...................................................................33

2.5.8 Initial Values of CPU Registers.............................................................................. 33

2.6 2Data Formats...................................................................................................................... 33

2.6.1 General Register Data Formats...............................................................................33

2.6.2 Memory Data Formats............................................................................................ 35

2.7 Instruction Set......................................................................................................................36

2.7.1 Instructions and Addressing Modes........................................................................ 38

2.7.2 Table of Instru ctions Classified by Function.......................................................... 42

2.7.3 Basic Instruction Formats.......................................................................................53

2.8 Addressing Modes and Effective Address Calculation........................................................54

2.8.1 Register Direct—Rn...............................................................................................55

2.8.2 Register Indirect—@ERn....................................................................................... 55

Rev. 3.00 Mar. 14, 2006 Page ix of xxxviii

2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn),

or @(d:32, ERn) ..................................................................................................... 55

2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),

@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 56

2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,

or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− ................................56

2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.......................................58

2.8.7 Immediate—#xx.....................................................................................................59

2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC):.....................................59

2.8.9 Program-Counter Relative with Index Register— @(RnL.B, PC),

@(Rn.W, PC), or @(ERn.L, PC)............................................................................ 59

2.8.10 Memory Indirect—@@aa:8 ................................................................................... 60

2.8.11 Extended Memory Indirect—@@vec:7 .................................................................61

2.8.12 Effective Address Calculation ................................................................................ 61

2.8.13 MOVA Instruction.................................................................................................. 63

2.9 Processing States..................................................................................................................64

Section 3 MCU Operating Modes.......................................................................67

3.1 Operating Mode Selection...................................................................................................67

3.2 Register Descriptions...........................................................................................................68

3.2.1 Mode Control Register (MDCR)............................................................................68

3.2.2 System Control Register (SYSCR)......................................................................... 69

3.3 Operating Mode Descriptions.............................................................................................. 71

3.3.1 Mode 1.................................................................................................................... 71

3.3.2 Mode 2.................................................................................................................... 71

3.3.3 Mode 3.................................................................................................................... 71

3.4 Address Map........................................................................................................................ 72

3.4.1 Address Map (Advanced Mode)............................................................................. 72

Section 4 Exception Handling.............................................................................73

4.1 Exception Handling Types and Priority............................................................................... 73

4.2 Exception Sources and Exception Handling Vector Table.................................................. 74

4.3 Reset....................................................................................................................................76

4.3.1 Reset Exception Handling ...................................................................................... 76

4.3.2 Interrupts after Reset............................................................................................... 77

4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 77

4.4 Traces...................................................................................................................................78

4.5 Address Error....................................................................................................................... 79

4.5.1 Address Error Source.............................................................................................. 79

4.5.2 Address Error Exception Handling ......................................................................... 80

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4.6 Interrupts..............................................................................................................................81

4.6.1 Interrupt Sources..................................................................................................... 81

4.6.2 Interrupt Exception Handling .................................................................................82

4.7 Instruction Exception Handling...........................................................................................83

4.7.1 Trap Instruction.......................................................................................................83

4.7.2 Exception Handling by Illegal Instruction.............................................................. 84

4.8 Stack Status after Exception Handling.................................................................................85

4.9 Usage Note...........................................................................................................................86

Section 5 Interrupt Controller..............................................................................87

5.1 Features................................................................................................................................ 87

5.2 Input/Output Pi ns................................................................................................................. 88

5.3 Register Descriptions...........................................................................................................89

5.3.1 Interrupt Control Register (INTCR) .......................................................................89

5.3.2 CPU Priority Control Register (CPUPCR).............................................................90

5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R

(IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR).......................................92

5.3.4 IRQ Ena ble Register (IER).....................................................................................94

5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL)..................................96

5.3.6 IRQ Status Regi ster (ISR)..................................................................................... 101

5.3.7 Software Standby Release IRQ Enable Register (SSIER).................................... 102

5.4 Interrupt Source s................................................................................................................ 103

5.4.1 External Interrupts ................................................................................................103

5.4.2 Internal Inter r u pts.................................................................................................104

5.5 Interrupt Exception Handling Vector Table....................................................................... 105

5.6 Interrupt Control Modes and Interrupt Operation.............................................................. 112

5.6.1 Interrupt Control Mode 0...................................................................................... 112

5.6.2 Interrupt Control Mode 2...................................................................................... 114

5.6.3 Interrupt Exception Handling Sequence...............................................................116

5.6.4 Interrupt Response Times.....................................................................................117

5.6.5 DMAC Activa tion by Interrupt............................................................................. 118

5.7 CPU Priority Control Function Over DMAC....................................................................120

5.8 Usage Notes....................................................................................................................... 122

5.8.1 Conflict between Inter r upt Generation and Disabling ..........................................122

5.8.2 Instructions that Disable Interrupts.......................................................................123

5.8.3 Times when Interrupts are Disabled .....................................................................123

5.8.4 Interr upts during Execution of EEPMOV Instruction...........................................123

5.8.5 Interr upts during Execution of MOVMD and MOVSD Instructions....................123

5.8.6 Interrupt Flags of Peripheral Modules..................................................................124

Rev. 3.00 Mar. 14, 2006 Page xi of xxxviii

Section 6 Bus Controller (BSC)........................................................................125

6.1 Features.............................................................................................................................. 125

6.2 Register Descriptions......................................................................................................... 126

6.2.1 Bus Control Register 2 (BCR2)............................................................................ 126

6.3 Bus Configuration.............................................................................................................. 127

6.4 Multi-Clock Function ........................................................................................................ 128

6.5 Internal Bus........................................................................................................................129

6.5.1 Access to Internal Address Space......................................................................... 129

6.6 Write Data Buffer Function............................................................................................... 130

6.6.1 Write Data Buffer Function for Peripheral Module............................................... 130

6.7 Bus Arbitration..................................................................................................................131

6.7.1 Operation ..............................................................................................................131

6.7.2 Bus Transfer Timing............................................................................................. 131

6.8 Bus Controller Operation in Reset..................................................................................... 132

6.9 Usage Notes....................................................................................................................... 132

Section 7 DMA Controller (DMAC).................................................................133

7.1 Features.............................................................................................................................. 133

7.2 Register Descriptions......................................................................................................... 136

7.2.1 DMA Source Address Register (DSAR) .............................................................. 137

7.2.2 DMA Destination Address Register (DDAR) ...................................................... 138

7.2.3 DMA Offset Register (DOFR)..............................................................................139

7.2.4 DMA Transfer Count Register (DTCR)...............................................................140

7.2.5 DMA Block Size Register (DBSR) ...................................................................... 141

7.2.6 DMA Mode Control Register (DMDR)................................................................ 142

7.2.7 DMA Address Control Register (DACR)............................................................. 151

7.2.8 DMA Module Request Select Register (DMRSR)............................................... 157

7.3 Transfer Modes..................................................................................................................157

7.4 Operations.......................................................................................................................... 158

7.4.1 Address Modes ..................................................................................................... 158

7.4.2 Transfer Modes..................................................................................................... 162

7.4.3 Activation Sources................................................................................................ 166

7.4.4 Bus Access Modes................................................................................................ 168

7.4.5 Extended Repeat Area Function...........................................................................170

7.4.6 Address Updat e Function using Offset................................................................. 172

7.4.7 Register during DMA Transfer............................................................................. 176

7.4.8 Priority of Cha nnels.............................................................................................. 181

7.4.9 DMA Basic Bus Cycle.......................................................................................... 182

7.4.10 Bus Cycles in Dual Address Mode.......................................................................183

Rev. 3.00 Mar. 14, 2006 Page xii of xxxviii

7.4.11 Bus Cycles in Single Address Mode.....................................................................191

7.5 DMA Transfer End............................................................................................................ 196

7.6 Relationship among DMAC and Other Bus Masters......................................................... 198

7.6.1 CPU Priority Control Function Over DMAC .......................................................198

7.6.2 Bus Arbitration among DMAC and Other Bus Masters.......................................199

7.7 Interrupt Source s................................................................................................................ 200

7.8 Notes on Usage..................................................................................................................203

Section 8 I/O Ports.............................................................................................205

8.1 Register Descriptions......................................................................................................... 210

8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D, H, J, and K).................... 212

8.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, D, H, J, and K).......................................212

8.1.3 Port Register (PORTn) (n = 1 to 6, A, D, H, J, and K).........................................213

8.1.4 Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, H, J, and K)................213

8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D, H, J, and K).............................214

8.1.6 Open-Drain Control Register (PnODR) (n = 2).................................................... 215

8.1.7 Port H Realtime Input Data Register (PHRTIDR)................................................ 215

8.2 Output Buffer Control........................................................................................................ 216

8.2.1 Port 1.....................................................................................................................216

8.2.2 Port 2.....................................................................................................................219

8.2.3 Port 3.....................................................................................................................221

8.2.4 Port 6.....................................................................................................................225

8.2.5 Port A....................................................................................................................227

8.2.6 Port D....................................................................................................................230

8.2.7 Port H....................................................................................................................233

8.2.8 Port J.....................................................................................................................233

8.2.9 Port K....................................................................................................................236

8.3 Port Function Controller ....................................................................................................243

8.3.1 Port Function Control Register 9 (PFCR9)...........................................................243

8.3.2 Port Function Control Register A (PFCRA)......................................................... 245

8.3.3 Port Function Control Register B (PFCRB)..........................................................247

8.4 Usage Notes....................................................................................................................... 249

8.4.1 Notes on Input Buffer Control Register (ICR) Setting ......................................... 249

8.4.2 Notes on Port Function Control Register (PFCR) Settings................................... 249

Section 9 16-Bit Timer Pulse Unit (TPU) .........................................................251

9.1 Features.............................................................................................................................. 251

9.2 Input/Output Pi ns...............................................................................................................258

9.3 Register Descriptions......................................................................................................... 260

9.3.1 Timer Control Register (TCR).............................................................................. 265

Rev. 3.00 Mar. 14, 2006 Page xiii of xxxviii

9.3.2 Timer Mode Register (TMDR)............................................................................. 270

9.3.3 Timer I/O Control Register (TIOR)...................................................................... 272

9.3.4 Timer Interr upt Enable Register (TIER)............................................................... 290

9.3.5 Timer Status Register (TSR)................................................................................. 292

9.3.6 Timer Counter (TCNT)......................................................................................... 296

9.3.7 Timer Gene ral Regi ster (TGR)............................................................................. 296

9.3.8 Timer Start Register (TSTR) ................................................................................ 297

9.3.9 Timer Synchronous Register (TSYR)................................................................... 298

9.4 Operation...........................................................................................................................299

9.4.1 Basic Functions.....................................................................................................299

9.4.2 Synchronous Operation......................................................................................... 305

9.4.3 Buffer Operation................................................................................................... 307

9.4.4 Cascaded Operation.............................................................................................. 311

9.4.5 PWM Modes ......................................................................................................... 313

9.4.6 Phase Counting Mode........................................................................................... 318

9.5 Interrupt Source s................................................................................................................ 326

9.6 DMAC Activation..............................................................................................................329

9.7 A/D Converter Activation.................................................................................................. 329

9.8 Operation Timing...............................................................................................................330

9.8.1 Input/Output Timing............................................................................................. 330

9.8.2 Interr upt Signal Timing ........................................................................................ 334

9.9 Usage Notes....................................................................................................................... 337

9.9.1 Module Stop Mode Setting................................................................................... 337

9.9.2 Input Clock Restrictions ....................................................................................... 337

9.9.3 Caution on Cycle Setting......................................................................................338

9.9.4 Conflict between TCNT Write and Clear Operations........................................... 338

9.9.5 Conflict between TCNT Write and Increment Operations...................................339

9.9.6 Conflict between TGR Write and Compare Match...............................................339

9.9.7 Conflict between Buffer Register Write and Compare Match.............................. 340

9.9.8 Conflict between TGR Read and Input Capture................................................... 340

9.9.9 Conflict between TGR Write and Input Capture..................................................341

9.9.10 Conflict between Buffer Register Write and Input Capture.................................. 341

9.9.11 Conflict between Overflow/Underflow and Counter Clearing............................. 342

9.9.12 Conflict between TCNT Write and Overflow/Underflow....................................342

9.9.13 Multiplexing of I/O Pins.......................................................................................343

9.9.14 Interrupts and Module Stop Mode........................................................................343

Section 10 Programmable Pulse Generator (PPG)............................................345

10.1 Features.............................................................................................................................. 345

10.2 Input/Output Pins...............................................................................................................346

Rev. 3.00 Mar. 14, 2006 Page xiv of xxxviii

10.3 Register Descriptions......................................................................................................... 347

10.3.1 Next Data Enable Registers H, L (NDERH, NDERL) .........................................347

10.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 349

10.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 350

10.3.4 PPG Output Control Register (PCR) .................................................................... 353

10.3.5 PPG Output Mode Register (PMR) ...................................................................... 354

10.4 Operation ........................................................................................................................... 356

10.4.1 Output Timing....................................................................................................... 356

10.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 357

10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)................ 358

10.4.4 Non-Overlapping Pulse Output............................................................................. 359

10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................... 361

10.4.6 Example of Non-Overlapping Pulse Output

(Example of 4-Phase Complementary Non-Overlapping Pulse Output) ..............362

10.4.7 Inverted Pulse Output ........................................................................................... 364

10.4.8 Pulse Output Triggered by Input Capture.............................................................365

10.5 Usage Notes.......................................................................................................................365

10.5.1 Module Stop Mode Setting...................................................................................365

10.5.2 Operation of Pulse Output Pins............................................................................. 365

Section 11 Watchdog Timer (WDT)..................................................................367

11.1 Features..............................................................................................................................367

11.2 Register Descriptions......................................................................................................... 368

11.2.1 Timer Counter (TCNT).........................................................................................368

11.2.2 Timer Control/Status Register (TCSR)................................................................. 369

11.2.3 Reset Control/Status Register (RSTCSR)............................................................. 370

11.3 Operation ........................................................................................................................... 372

11.3.1 Watchdog Timer Mode.........................................................................................372

11.3.2 Interval Timer Mode............................................................................................. 373

11.4 Interrupt Source .................................................................................................................373

11.5 Usage Notes.......................................................................................................................374

11.5.1 Notes on Register Access...................................................................................... 374

11.5.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 375

11.5.3 Changing Values of Bits CKS2 to CKS0.............................................................. 375

11.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode.................375

11.5.5 Transition to Watchdog Timer Mode or Software Standby Mode........................376

Section 12 Serial Communication Interface (SCI)............................................377

12.1 Features..............................................................................................................................377

12.2 Input/Output Pins...............................................................................................................379

Rev. 3.00 Mar. 14, 2006 Page xv of xxxviii

12.3 Register Descriptions......................................................................................................... 380

12.3.1 Receive Shift Register (RSR) ............................................................................... 381

12.3.2 Receive Data Register (RDR)............................................................................... 381

12.3.3 Transmit Data Register (TDR).............................................................................. 381

12.3.4 Transmit Shift Register (TSR)..............................................................................382

12.3.5 Serial Mode Register (SMR) ................................................................................ 382

12.3.6 Serial Control Register (SCR) ..............................................................................385

12.3.7 Serial Status Register (SSR) ................................................................................. 389

12.3.8 Smart Card Mode Register (SCMR)..................................................................... 397

12.3.9 Bit Rate Register (BRR) ....................................................................................... 398

12.4 Operation in Asynchronous Mode..................................................................................... 405

12.4.1 Data Transfer Format............................................................................................ 406

12.4.2 Receive Data Sampling Timing and Reception Margin

in Asynchronous Mode......................................................................................... 407

12.4.3 Clock..................................................................................................................... 408

12.4.4 SCI Initialization (Asynchronous Mode).............................................................. 409

12.4.5 Serial Data Transmission (Asynchronous Mode).................................................410

12.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 412

12.5 Multiprocessor Communication Function..........................................................................416

12.5.1 Multiprocessor Serial Data Transmission.............................................................418

12.5.2 Multiprocessor Serial Data Reception .................................................................. 419

12.6 Operation in Clocked Synchronous Mode......................................................................... 422

12.6.1 Clock..................................................................................................................... 422

12.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 423

12.6.3 Serial Data Transmission (Clocked Synchronous Mode).....................................424

12.6.4 Serial Data Reception (Clocked Synchronous Mode) ..........................................426

12.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode)..............................................................................427

12.7 Operation in Smart Card Interface Mode........................................................................... 429

12.7.1 Sample Connection............................................................................................... 429

12.7.2 Data Format (Except in Block Transfer Mode) .................................................... 430

12.7.3 Block Transfer Mode............................................................................................ 431

12.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 432

12.7.5 Initialization..........................................................................................................433

12.7.6 Data Transmission (Except in Block Transfer Mode) .......................................... 434

12.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 437

12.7.8 Clock Output Control............................................................................................ 438

12.8 Interrupt Sources................................................................................................................ 440

12.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 440

12.8.2 Interrupts in Smart Card Interface Mode..............................................................441

Rev. 3.00 Mar. 14, 2006 Page xvi of xxxviii

12.9 Usage Notes.......................................................................................................................442

12.9.1 Module Stop Mode Setting...................................................................................442

12.9.2 Break Detection and Processing ........................................................................... 442

12.9.3 Mark State and Break Detection...........................................................................442

12.9.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) .....................................................................442

12.9.5 Relation between Writing to TDR and TDRE Flag..............................................443

12.9.6 Restrictions on Using DMAC............................................................................... 443

12.9.7 SCI Operations during Mode Transitions .............................................................444

Section 13 Controller Area Network (HCAN) ..................................................449

13.1 Features..............................................................................................................................449

13.2 Input/Output Pins...............................................................................................................451

13.3 Register Descriptions......................................................................................................... 452

13.3.1 Master Control Register (MCR) ...........................................................................453

13.3.2 General Status Register (GSR) ............................................................................. 454

13.3.3 Bit Configuration Register (BCR) ........................................................................ 456

13.3.4 Mailbox Configuration Register (MBCR) ............................................................458

13.3.5 Transmit Wait Register (TXPR) ........................................................................... 459

13.3.6 Transmit Wait Cancel Register (TXCR)............................................................... 460

13.3.7 Transmit Acknowledge Register (TXACK) ......................................................... 461

13.3.8 Abort Acknowledge Register (ABACK) ..............................................................462

13.3.9 Receive Complete Register (RXPR)..................................................................... 463

13.3.10 Remote Request Register (RFPR).........................................................................464

13.3.11 Interrupt Register (IRR)........................................................................................ 465

13.3.12 Mailbox Interrupt Mask Register (MBIMR).........................................................470

13.3.13 Interrupt Mask Register (IMR)............................................................................. 471

13.3.14 Receive Error Counter (REC)............................................................................... 473

13.3.15 Transmit Error Counter (TEC)..............................................................................473

13.3.16 Unread Message Status Register (UMSR)............................................................ 474

13.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)............................................ 475

13.3.18 Message Control (MC0 to MC15)........................................................................ 478

13.3.19 Message Data (MD0 to MD15) ............................................................................ 481

13.3.20 HCAN Monitor Register (HCANMON)...............................................................483

13.4 Operation ........................................................................................................................... 484

13.4.1 Hardware and Software Resets.............................................................................484

13.4.2 Initialization after Hardware Reset ....................................................................... 484

13.4.3 Message Transmission..........................................................................................490

13.4.4 Message Reception ............................................................................................... 494

13.4.5 HCAN Sleep Mode...............................................................................................498

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13.4.6 HCAN Halt Mode................................................................................................. 500

13.5 Interrupt Sources................................................................................................................ 501

13.6 DMAC Interface................................................................................................................502

13.7 CAN Bus Interface............................................................................................................. 503

13.8 Usage Notes....................................................................................................................... 504

13.8.1 Module Stop Mode Setting...................................................................................504

13.8.2 Reset ..................................................................................................................... 504

13.8.3 HCAN Sleep Mode............................................................................................... 504

13.8.4 Interrupts............................................................................................................... 505

13.8.5 Error Counters ......................................................................................................505

13.8.6 Register Access..................................................................................................... 505

13.8.7 Register Hold in Standby Modes..........................................................................505

13.8.8 Use on Bit Manipulation Instructions...................................................................505

13.8.9 HCAN TXCR Operation ......................................................................................506

13.8.10 HCAN Transmission Setting................................................................................507

13.8.11 Canceling HCAN Reset and HCAN Sleep Mode................................................. 507

13.8.12 Accessing Mailbox in HCAN Sleep Mode........................................................... 507

Section 14 Synchronous Serial Communication Unit (SSU)............................509

14.1 Features.............................................................................................................................. 509

14.2 Input/Output Pins...............................................................................................................511

14.3 Register Descriptions......................................................................................................... 512

14.3.1 SS Control Register H (SSCRH) .......................................................................... 514

14.3.2 SS Control Register L (SSCRL) ........................................................................... 516

14.3.3 SS Mode Register (SSMR)...................................................................................517

14.3.4 SS Enable Register (SSER) .................................................................................. 518

14.3.5 SS Status Register (SSSR).................................................................................... 519

14.3.6 SS Control Register 2 (SSCR2)............................................................................521

14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 523

14.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 524

14.3.9 SS Shift Register (SSTRSR)................................................................................. 525

14.4 Operation ........................................................................................................................... 526

14.4.1 Transfer Clock ...................................................................................................... 526

14.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 526

14.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 527

14.4.4 Communication Modes and Pin Functions...........................................................528

14.4.5 SSU Mode............................................................................................................. 530

14.4.6 SCS Pin Control and Conflict Error...................................................................... 538

14.4.7 Clock Synchronous Communication Mode..........................................................539

14.5 Interrupt Requests..............................................................................................................545

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14.6 Usage Note......................................................................................................................... 546

14.6.1 Setting of Module Stop Mode............................................................................... 546

14.6.2 Notes on Clearing Module Stop Mode .................................................................546

Section 15 A/D Converter..................................................................................547

15.1 Features..............................................................................................................................547

15.2 Input/Output Pins...............................................................................................................550

15.3 Register Descriptions......................................................................................................... 551

15.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 552

15.3.2 A/D Control/Status Register (ADCSR) ................................................................ 553

15.3.3 A/D Control Register (ADCR) ............................................................................. 555

15.4 Operation ........................................................................................................................... 556

15.4.1 Single Mode.......................................................................................................... 556

15.4.2 Scan Mode ............................................................................................................ 557

15.4.3 Input Sampling and A/D Conversion Time .......................................................... 559

15.4.4 External Trigger Input Timing.............................................................................. 560

15.5 Interrupt Source .................................................................................................................561

15.6 A/D Conversion Accuracy Definitions.............................................................................. 561

15.7 Usage Notes.......................................................................................................................563

15.7.1 Module Stop Mode Setting...................................................................................563

15.7.2 Permissible Signal Source Impedance..................................................................563

15.7.3 Influences on Absolute Accuracy .........................................................................564

15.7.4 Setting Range of Analog Power Supply and Other Pins.......................................564

15.7.5 Notes on Board Design.........................................................................................564

15.7.6 Notes on Noise Countermeasures .........................................................................565

15.7.7 A/D Input Hold Function in Software Standby Mode .......................................... 566

Section 16 RAM ................................................................................................567

Section 17 Flash Memory (0.18-µm F-ZTAT Version)....................................569

17.1 Features..............................................................................................................................569

17.2 Mode Transition Diagram.................................................................................................. 571

17.3 Memory MAT Configuration.............................................................................................573

17.4 Block Structure..................................................................................................................574

17.5 Programming/Erasing Interface......................................................................................... 575

17.6 Input/Output Pins...............................................................................................................577

17.7 Register Descriptions......................................................................................................... 578

17.7.1 Programming/Erasing Interface Registers ............................................................579

17.7.2 Programming/Erasing Interface Parameters ......................................................... 586

17.7.3 RAM Emulation Register (RAMER)....................................................................598

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17.8 On-Board Programming Mode..........................................................................................599

17.8.1 Boot Mode ............................................................................................................ 599

17.8.2 User Program Mode.............................................................................................. 603

17.8.3 User Boot Mode.................................................................................................... 613

17.8.4 On-Chip Program and Storable Area for Program Data.......................................617

17.9 Protection........................................................................................................................... 623

17.9.1 Hardware Protection ............................................................................................. 623

17.9.2 Software Protection ..............................................................................................624

17.9.3 Error Protection ....................................................................................................624

17.10 Flash Memory Emulation Using RAM..............................................................................626

17.11 Switching between User MAT and User Boot MAT......................................................... 629

17.12 Programmer Mode.............................................................................................................630

17.13 Standard Serial Communication Interface Specifications for Boot Mode ......................... 630

17.14 Usage Notes....................................................................................................................... 658

Section 18 Clock Pulse Generator.....................................................................661

18.1 Register Description .......................................................................................................... 662

18.1.1 System Clock Control Register (SCKCR)............................................................662

18.2 Oscillator............................................................................................................................ 665

18.2.1 Connecting Crystal Resonator .............................................................................. 665

18.2.2 External Clock Input............................................................................................. 666

18.3 PLL Circuit........................................................................................................................666

18.4 Frequency Divider.............................................................................................................666

18.5 Usage Notes....................................................................................................................... 667

18.5.1 Notes on Clock Pulse Generator........................................................................... 667

18.5.2 Notes on Resonator............................................................................................... 668

18.5.3 Notes on Board Design.........................................................................................668

18.5.4 Notes on Input Clock Frequency .......................................................................... 669

Section 19 Power-Down Modes........................................................................671

19.1 Features.............................................................................................................................. 671

19.2 Register Descriptions......................................................................................................... 672

19.2.1 Standby Control Register (SBYCR).....................................................................673

19.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB)..............675

19.2.3 Module Stop Control Register C (MSTPCRC)..................................................... 678

19.3 Multi-Clock Function ........................................................................................................ 679

19.4 Module Stop Mode ............................................................................................................ 679

19.5 Sleep Mode........................................................................................................................680

19.5.1 Transition to Sleep Mode...................................................................................... 680

19.5.2 Clearing Sleep Mode ............................................................................................680

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19.6 All-Module-Clock-Stop Mode........................................................................................... 680

19.7 Software Standby Mode..................................................................................................... 681

19.7.1 Transition to Software Standby Mode ..................................................................681

19.7.2 Clearing Software Standby Mode.........................................................................681

19.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ........... 682

19.7.4 Software Standby Mode Application Example.....................................................684

19.8 Bφ Clock Output Control................................................................................................... 685

19.9 Usage Notes.......................................................................................................................686

19.9.1 I/O Port Status.......................................................................................................686

19.9.2 Current Consumption during Oscillation Settling Standby Period ....................... 686

19.9.3 DMAC Module Stop.............................................................................................686

19.9.4 On-Chip Peripheral Module Interrupts .................................................................686

19.9.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC...........................................686

Section 20 List of Registers...............................................................................687

20.1 Register Addresses (Address Order).................................................................................. 688

20.2 Register Bits....................................................................................................................... 711

20.3 Register States in Each Operating Mode ...........................................................................738

Section 21 Electrical Characteristics .................................................................761

21.1 Absolute Maximum Ratings..............................................................................................761

21.2 DC Characteristics.............................................................................................................762

21.3 AC Characteristics.............................................................................................................764

21.3.1 Clock Timing........................................................................................................765

21.3.2 Control Signal Timing .......................................................................................... 767

21.3.3 Timing of On-Chip Peripheral Modules ...............................................................768

21.4 A/D Conversion Characteristics.........................................................................................776

21.5 Flash Memory Characteristics ........................................................................................... 777

Appendix .........................................................................................................779

A. Port States in Each Pin State.............................................................................................. 779

B. Product Lineup................................................................................................................... 780

C. Package Dimensions ..........................................................................................................781

Main Revisions and Additions in this Edition.....................................................783

Index .........................................................................................................799

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Figures

Section 1 Overview

Figure 1.1 Block Diagram of H8SX/1527...................................................................................... 2

Figure 1.2 Block Diagram of H8SX/1525...................................................................................... 3

Figure 1.3 Pin Assignments of H8SX/1527.................................................................................... 4

Figure 1.4 Pin Assignments of H8SX/1525.................................................................................... 5

Section 2 CPU

Figure 2.1 CPU Operating Modes ................................................................................................21

Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 22

Figure 2.3 Stack Structure (Normal Mode) ..................................................................................22

Figure 2.4 Exception Vector Table (Middle and Advanced Modes)............................................ 24

Figure 2.5 Stack Structure (Middle and Advanced Modes).......................................................... 25

Figure 2.6 Exception Vector Table (Maximum Modes)............................................................... 26

Figure 2.7 Stack Structure (Maximum Mode).............................................................................. 26

Figure 2.8 Memory Map............................................................................................................... 27

Figure 2.9 CPU Registers .............................................................................................................28

Figure 2.10 Usage of General Registers....................................................................................... 29

Figure 2.11 Stack.......................................................................................................................... 30

Figure 2.12 General Register Data Formats .................................................................................34

Figure 2.13 Memory Data Formats...............................................................................................35

Figure 2.14 Instruction Formats.................................................................................................... 53

Figure 2.15 Branch Address Specification in Memory Indirect Mode......................................... 60

Figure 2.16 State Transitions........................................................................................................ 65

Section 3 MCU Operating Modes

Figure 3.1 Address Map (Advanced Mode) .................................................................................72

Section 4 Exception Handling

Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode)....................................... 77

Figure 4.2 Stack Status after Exception Handling........................................................................ 85

Figure 4.3 Operation when SP Value Is Odd................................................................................ 86

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 88

Figure 5.2 Block Diagram of Interrupts IRQn............................................................................ 104

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0... 113
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 115

Figure 5.5 Interrupt Exception Handling.................................................................................... 116

Figure 5.6 Block Diagram of DMAC and Interrupt Controller .................................................. 118

Figure 5.7 Conflict between Interrupt Generation and Disabling............................................... 122

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Section 6 Bus Controller (BSC)

Figure 6.1 Block Diagram of Bus Controller..............................................................................125

Figure 6.2 Internal Bus Configuration........................................................................................ 127

Figure 6.3 Example of Timing when Write Data Buffer Function is Used ................................ 130

Section 7 DMA Controller (DMAC)

Figure 7.1 Block Diagram of DMAC......................................................................................... 135

Figure 7.2 Example of Signal Timing in Dual Address Mode ................................................... 159

Figure 7.3 Operations in Dual Address Mode ............................................................................159

Figure 7.4 Data Flow in Single Address Mode........................................................................... 160

Figure 7.5 Example of Signal Timing in Single Address Mode................................................. 161

Figure 7.6 Operations in Single Address Mode.......................................................................... 161

Figure 7.7 Example of Signal Timing in Normal Transfer Mode...............................................162

Figure 7.8 Operations in Normal Transfer Mode ....................................................................... 162

Figure 7.9 Operations in Repeat Transfer Mode ........................................................................163

Figure 7.10 Operations in Block Transfer Mode........................................................................ 164

Figure 7.11 Operation in Single Address Mode in Block Transfer Mode

(Block Area Specified) ...........................................................................................165

Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode

(Block Area Not Specified) ..................................................................................... 165

Figure 7.13 Example of Timing in Cycle Stealing Mode........................................................... 169

Figure 7.14 Example of Timing in Burst Mode.......................................................................... 169

Figure 7.15 Example of Extended Repeat Area Operation......................................................... 171

Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode ...................171

Figure 7.17 Address Update Method.......................................................................................... 172

Figure 7.18 Operation of Offset Addition .................................................................................. 173

Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode..........174

Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode .........175

Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred.............. 179

Figure 7.22 Example of Timing for Channel Priority................................................................. 181

Figure 7.23 Example of Bus Timing of DMA Transfer ............................................................. 182

Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 183

Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing

(Transfer Source DSAR = Odd Address and Source Address Increment).............. 184

Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing

(Transfer Destination DDAR = Odd Address and Destination

Address Decrement) .............................................................................................. 184

Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access........................... 185

Figure 7.28 Example of Transfer in Block Transfer Mode......................................................... 186

Figure 7.29 Example of Transfer in Normal Transfer Mode Activated

by DREQ Falling Edge........................................................................................... 187

Figure 7.30 Example of Transfer in Normal Transfer Mode Activated

by DREQ Low Level.............................................................................................. 188

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Figure 7.31 Example of Transfer in Block Transfer Mode Activated

by DREQ Low Level.............................................................................................. 189

Figure 7.32 Example of Transfer in Normal Transfer Mode Activated

by DREQ Low Level with NRD = 1.......................................................................190

Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) ....................................191

Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) ....................................192

Figure 7.35 Example of Transfer in Single Address Mode Activated

by DREQ Falling Edge........................................................................................... 193

Figure 7.36 Example of Transfer in Single Address Mode Activated

by DREQ Low Level.............................................................................................. 194

Figure 7.37 Example of Transfer in Single Address Mode Activated

by DREQ Low Level with NRD = 1.......................................................................195

Figure 7.38 Interrupt and Interrupt Sources................................................................................ 202

Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source ...............202

Section 8 I/O Ports

Figure 8.1 Port Block Diagram................................................................................................... 211

Section 9 16-Bit Timer Pulse Unit (TPU)

Figure 9.1 Block Diagram of TPU (Unit 0)................................................................................ 256

Figure 9.2 Block Diagram of TPU (Unit 1)................................................................................ 257

Figure 9.3 Example of Counter Operation Setting Procedure ....................................................299

Figure 9.4 Free-Running Counter Operation.............................................................................. 300

Figure 9.5 Periodic Counter Operation....................................................................................... 301

Figure 9.6 Example of Setting Procedure for Waveform Output by Compare Match................ 301

Figure 9.7 Example of 0-Output/1-Output Operation................................................................. 302

Figure 9.8 Example of Toggle Output Operation .......................................................................302

Figure 9.9 Example of Setting Procedure for Input Capture Operation...................................... 303

Figure 9.10 Example of Input Capture Operation.......................................................................304

Figure 9.11 Example of Synchronous Operation Setting Procedure ..........................................305

Figure 9.12 Example of Synchronous Operation........................................................................ 306

Figure 9.13 Compare Match Buffer Operation........................................................................... 307

Figure 9.14 Input Capture Buffer Operation...............................................................................308

Figure 9.15 Example of Buffer Operation Setting Procedure..................................................... 308

Figure 9.16 Example of Buffer Operation (1)............................................................................. 309

Figure 9.17 Example of Buffer Operation (2)............................................................................. 310

Figure 9.18 Example of Cascaded Operation Setting Procedure................................................ 311

Figure 9.19 Example of Cascaded Operation (1)........................................................................ 312

Figure 9.20 Example of Cascaded Operation (2)........................................................................ 312

Figure 9.21 Example of PWM Mode Setting Procedure ............................................................315

Figure 9.22 Example of PWM Mode Operation (1) ...................................................................316

Figure 9.23 Example of PWM Mode Operation (2) ...................................................................316

Figure 9.24 Example of PWM Mode Operation (3) ...................................................................317

Figure 9.25 Example of Phase Counting Mode Setting Procedure............................................. 319

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Figure 9.26 Example of Phase Counting Mode 1 Operation ......................................................320

Figure 9.27 Example of Phase Counting Mode 2 Operation ......................................................321

Figure 9.28 Example of Phase Counting Mode 3 Operation ......................................................322

Figure 9.29 Example of Phase Counting Mode 4 Operation ......................................................323

Figure 9.30 Phase Counting Mode Application Example........................................................... 325

Figure 9.31 Count Timing in Internal Clock Operation..............................................................330

Figure 9.32 Count Timing in External Clock Operation ............................................................ 330

Figure 9.33 Output Compare Output Timing ............................................................................. 331

Figure 9.34 Input Capture Input Signal Timing.......................................................................... 331

Figure 9.35 Counter Clear Timing (Compare Match) ................................................................332

Figure 9.36 Counter Clear Timing (Input Capture).................................................................... 332

Figure 9.37 Buffer Operation Timing (Compare Match) ........................................................... 333

Figure 9.38 Buffer Operation Timing (Input Capture) ............................................................... 333

Figure 9.39 TGI Interrupt Timing (Compare Match)................................................................. 334

Figure 9.40 TGI Interrupt Timing (Input Capture)..................................................................... 334

Figure 9.41 TCIV Interrupt Setting Timing................................................................................ 335

Figure 9.42 TCIU Interrupt Setting Timing................................................................................ 335

Figure 9.43 Timing for Status Flag Clearing by CPU ................................................................ 336

Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (1)..................................... 336

Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2)..................................... 337

Figure 9.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode.................. 337

Figure 9.47 Conflict between TCNT Write and Clear Operations .............................................338

Figure 9.48 Conflict between TCNT Write and Increment Operations...................................... 339

Figure 9.49 Conflict between TGR Write and Compare Match................................................. 339

Figure 9.50 Conflict between Buffer Register Write and Compare Match ................................ 340

Figure 9.51 Conflict between TGR Read and Input Capture...................................................... 340

Figure 9.52 Conflict between TGR Write and Input Capture..................................................... 341

Figure 9.53 Conflict between Buffer Register Write and Input Capture.................................... 341

Figure 9.54 Conflict between Overflow and Counter Clearing .................................................. 342

Figure 9.55 Conflict between TCNT Write and Overflow......................................................... 342

Section 10 Programmable Pulse Generator (PPG)

Figure 10.1 Block Diagram of PPG............................................................................................ 345

Figure 10.2 Schematic Diagram of PPG..................................................................................... 356

Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)................................. 356

Figure 10.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 357

Figure 10.5 Normal Pulse Output Example (5-Phase Pulse Output) .......................................... 358

Figure 10.6 Non-Overlapping Pulse Output ............................................................................... 359

Figure 10.7 Non-Overlapping Operation and NDR Write Timing............................................. 360

Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example).............................361

Figure 10.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) .....................362

Figure 10.10 Inverted Pulse Output (Example).......................................................................... 364

Figure 10.11 Pulse Output Triggered by Input Capture (Example)............................................ 365

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Section 11 Watchdog Timer (WDT)

Figure 11.1 Block Diagram of WDT.......................................................................................... 367

Figure 11.2 Operation in Watchdog Timer Mode.......................................................................372

Figure 11.3 Operation in Interval Timer Mode...........................................................................373

Figure 11.4 Writing to TCNT, TCSR, and RSTCSR.................................................................. 374

Figure 11.5 Conflict between TCNT Write and Increment ........................................................375

Section 12 Serial Communication Interface (SCI)

Figure 12.1 Block Diagram of SCI............................................................................................. 378

Figure 12.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................405

Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................407

Figure 12.4 Phase Relation between Output Clock and Transmit Data

(Asynchronous Mode) ............................................................................................408

Figure 12.5 Sample SCI Initialization Flowchart .......................................................................409

Figure 12.6 Example of Operation for Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 410

Figure 12.7 Sample Serial Transmission Flowchart ...................................................................411

Figure 12.8 Example of SCI Operation for Reception

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 412

Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 414

Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 415

Figure 12.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A).......................................... 417

Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart........................................ 418

Figure 12.12 Example of SCI Operation for Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................419

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 420

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 421

Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 422

Figure 12.15 Sample SCI Initialization Flowchart .....................................................................423

Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode .............425

Figure 12.17 Sample Serial Transmission Flowchart................................................................. 425

Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode...................426

Figure 12.19 Sample Serial Reception Flowchart ......................................................................427

Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ..............428

Figure 12.21 Pin Connection for Smart Card Interface .............................................................. 429

Figure 12.22 Data Formats in Normal Smart Card Interface Mode............................................ 430

Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0) ......................................................430

Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 431

Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode

(When Clock Frequency is 372 Times the Bit Rate) ............................................432

Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode ......................................435

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Figure 12.27 TEND Flag Set Timing during Transmission........................................................ 435

Figure 12.28 Sample Transmission Flowchart ...........................................................................436

Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode............................................ 437

Figure 12.30 Sample Reception Flowchart................................................................................. 438

Figure 12.31 Clock Output Fixing Timing .................................................................................438

Figure 12.32 Clock Stop and Restart Procedure......................................................................... 439

Figure 12.33 Sample Transmission using DMAC in Clocked Synchronous Mode....................443

Figure 12.34 Sample Flowchart for Mode Transition during Transmission............................... 445

Figure 12.35 Port Pin States during Mode Transition

(Internal Clock, Asynchronous Transmission) .....................................................446

Figure 12.36 Port Pin States during Mode Transition

(Internal Clock, Clocked Synchronous Transmission) .........................................446

Figure 12.37 Sample Flowchart for Mode Transition during Reception.................................... 447

Section 13 Controller Area Network (HCAN)

Figure 13.1 HCAN Block Diagram............................................................................................ 450

Figure 13.2 Message Control Register Configuration ................................................................ 478

Figure 13.3 Standard Format...................................................................................................... 478

Figure 13.4 Extended Format ..................................................................................................... 478

Figure 13.5 Message Data Configuration ................................................................................... 481

Figure 13.6 Hardware Reset Flowchart ...................................................................................... 485

Figure 13.7 Software Reset Flowchart .......................................................................................486

Figure 13.8 Detailed Description of One Bit.............................................................................. 487

Figure 13.9 Transmission Flowchart.......................................................................................... 490

Figure 13.10 Transmit Message Cancellation Flowchart ...........................................................493

Figure 13.11 Reception Flowchart ............................................................................................. 494

Figure 13.12 Unread Message Overwrite Flowchart.................................................................. 497

Figure 13.13 HCAN Sleep Mode Flowchart ..............................................................................498

Figure 13.14 HCAN Halt Mode Flowchart ................................................................................ 500

Figure 13.15 DMAC Transfer Flowchart ................................................................................... 502

Figure 13.16 High-Speed Interface Using PCA82C250............................................................. 503

Section 14 Synchronous Serial Communication Unit (SSU)

Figure 14.1 Block Diagram of SSU............................................................................................ 510

Figure 14.2 Relationship of Clock Phase, Polarity, and Data..................................................... 526

Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register ..................... 527

Figure 14.4 Example of Initial Settings in SSU Mode ...............................................................530

Figure 14.5 Example of Transmission Operation (SSU Mode).................................................. 532

Figure 14.6 Flowchart Example of Data Transmission (SSU Mode) .........................................533

Figure 14.7 Example of Reception Operation (SSU Mode)....................................................... 535

Figure 14.8 Flowchart Example of Data Reception (SSU Mode) ..............................................536

Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode).......... 537

Figure 14.10 Conflict Error Detection Timing (Before Transfer) ..............................................538

Figure 14.11 Conflict Error Detection Timing (After Transfer End) .........................................538

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Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode........... 539

Figure 14.13 Example of Transmission Operation

(Clock Synchronous Communication Mode)........................................................540

Figure 14.14 Flowchart Example of Transmission Operation

(Clock Synchronous Communication Mode)........................................................541

Figure 14.15 Example of Reception Operation

(Clock Synchronous Communication Mode)........................................................542

Figure 14.16 Flowchart Example of Data Reception

(Clock Synchronous Communication Mode)........................................................543

Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception

(Clock Synchronous Communication Mode)........................................................544

Section 15 A/D Converter

Figure 15.1 Block Diagram of A/D Converter (Unit 0/AD_0)................................................... 548

Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1)................................................... 549

Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 557

Figure 15.4 Example of A/D Conversion

(Scan Mode, Three Channels (AN0 to AN2) Selected).......................................... 558

Figure 15.5 A/D Conversion Timing.......................................................................................... 559

Figure 15.6 External Trigger Input Timing ................................................................................560

Figure 15.7 A/D Conversion Accuracy Definitions....................................................................562

Figure 15.8 A/D Conversion Accuracy Definitions....................................................................562

Figure 15.9 Example of Analog Input Circuit ............................................................................563

Figure 15.10 Example of Analog Input Protection Circuit ......................................................... 565

Figure 15.11 Analog Input Pin Equivalent Circuit .....................................................................566

Section 17 Flash Memory (0.18-mm F-ZTAT Version)

Figure 17.1 Block Diagram of Flash Memory............................................................................ 570

Figure 17.2 Mode Transition of Flash Memory.......................................................................... 571

Figure 17.3 Memory MAT Configuration .................................................................................. 573

Figure 17.4 Block Structure of User MAT ................................................................................. 574

Figure 17.5 Procedure for Creating Procedure Program.............................................................575

Figure 17.6 System Configuration in Boot Mode....................................................................... 599

Figure 17.7 Automatic-Bit-Rate Adjustment Operation............................................................. 600

Figure 17.8 Boot Mode State Transition Diagram...................................................................... 601

Figure 17.9 Programming/Erasing Flow.....................................................................................603

Figure 17.10 RAM Map when Programming/Erasing is Executed ............................................604

Figure 17.11 Programming Procedure in User Program Mode ..................................................605

Figure 17.12 Erasing Procedure in User Program Mode............................................................ 610

Figure 17.13 Repeating Procedure of Erasing, Programming,

and RAM Emulation in User Program Mode .......................................................612

Figure 17.14 Procedure for Programming User MAT in User Boot Mode ................................614

Figure 17.15 Procedure for Erasing User MAT in User Boot Mode.......................................... 616

Figure 17.16 Transitions to Error Protection State .....................................................................625

Rev. 3.00 Mar. 14, 2006 Page xxix of xxxviii

Figure 17.17 RAM Emulation Flow........................................................................................... 626

Figure 17.18 Address Map of Overlaid RAM Area ................................................................... 627

Figure 17.19 Programming Tuned Data .....................................................................................628

Figure 17.20 Switching between User MAT and User Boot MAT ............................................ 629

Figure 17.21 Boot Program States..............................................................................................631

Figure 17.22 Bit-Rate-Adjustment Sequence ............................................................................. 632

Figure 17.23 Communication Protocol Format.......................................................................... 633

Figure 17.24 New Bit-Rate Selection Sequence......................................................................... 644

Figure 17.25 Programming Sequence......................................................................................... 648

Figure 17.26 Erasure Sequence .................................................................................................. 649

Section 18 Clock Pulse Generator

Figure 18.1 Block Diagram of Clock Pulse Generator ............................................................... 661

Figure 18.2 Connection of Crystal Resonator (Example)........................................................... 665

Figure 18.3 Crystal Resonator Equivalent Circuit...................................................................... 665

Figure 18.4 External Clock Input (Examples) ............................................................................ 666

Figure 18.5 Clock Modification Timing..................................................................................... 667

Figure 18.6 Note on Board Design for Oscillation Circuit......................................................... 668

Figure 18.7 Connection Example of Bypass Capacitor.............................................................. 669

Section 19 Power-Down Modes

Figure 19.1 Mode Transitions..................................................................................................... 672

Figure 19.2 Software Standby Mode Application Example .......................................................684

Section 21 Electrical Characteristics

Figure 21.1 Output Load Circuit ................................................................................................ 764

Figure 21.2 System Bus Clock Timing....................................................................................... 765

Figure 21.3 Oscillation Settling Timing after Software Standby Mode .....................................766

Figure 21.4 Oscillation Settling Timing ..................................................................................... 766

Figure 21.5 External Input Clock Timing................................................................................... 766

Figure 21.6 Reset Input Timing.................................................................................................. 767

Figure 21.7 Interrupt Input Timing............................................................................................. 768

Figure 21.8 I/O Port Input/Output Timing.................................................................................. 771

Figure 21.9 Data Input Timing for Realtime Input Port............................................................. 771

Figure 21.10 TPU Input/Output Timing..................................................................................... 772

Figure 21.11 TPU Clock Input Timing....................................................................................... 772

Figure 21.12 PPG Output Timing............................................................................................... 772

Figure 21.13 SCK Clock Input/Output Timing ..........................................................................772

Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode....................................... 773

Figure 21.15 A/D Converter External Trigger Input Timing...................................................... 773

Figure 21.16 HCAN Input/Output Timing .................................................................................773

Figure 21.17 SSU Timing (Master, CPHS = 1).......................................................................... 774

Figure 21.18 SSU Timing (Master, CPHS = 0).......................................................................... 774

Figure 21.19 SSU Timing (Slave, CPHS = 1)............................................................................ 775

Rev. 3.00 Mar. 14, 2006 Page xxx of xxxviii

Figure 21.20 SSU Timing (Slave, CPHS = 0) ............................................................................ 775

Appendix

Figure C.1 Package Dimensions (PRQP0100KB-A)..................................................................781

Rev. 3.00 Mar. 14, 2006 Page xxxi of xxxviii

Rev. 3.00 Mar. 14, 2006 Page xxxii of xxxviii

Tables

Section 1 Overview

Table 1.1

Table 1.2 Pin Functions ..........................................................................................................10

Section 2 CPU

Table 2.1

Table 2.2 Combinations of Instructions and Addressing Modes (1)....................................... 38

Table 2.2 Combinations of Instructions and Addressing Modes (2)....................................... 41

Table 2.3 Operation Notation .................................................................................................42

Table 2.4 Data Transfer Instructions.......................................................................................43

Table 2.5 Block Transfer Instructions.....................................................................................44

Table 2.6 Arithmetic Operation Instructions ..........................................................................45

Table 2.7 Logic Operation Instructions ..................................................................................47

Table 2.8 Shift Operation Instructions.................................................................................... 48

Table 2.9 Bit Manipulation Instructions ................................................................................. 49

Table 2.10 Branch Instructions................................................................................................. 51

Table 2.11 System Control Instructions....................................................................................52

Table 2.12 Addressing Modes ..................................................................................................54

Table 2.13 Absolute Address Access Ranges ........................................................................... 58

Table 2.14 Effective Address Calculation for Transfer and Operation Instructions.................62

Table 2.15 Effective Address Calculation for Branch Instructions........................................... 63

Pin Configuration in Each Operating Mode..............................................................6

Instruction Classification........................................................................................ 36

Section 3 MCU Operating Modes

Table 3.1

Table 3.2 Settings of Bits MSD3 to MSD0 ............................................................................69

Section 4 Exception Handling

Table 4.1

Table 4.2 Exception Handling Vector Table...........................................................................74

Table 4.3 Calculation Method of Exception Handling Vector Table Address........................76

Table 4.4 Status of CCR and EXR after Trace Exception Handling.......................................78

Table 4.5 Bus Cycle and Address Error.................................................................................. 79

Table 4.6 States of CCR and EXR after Address Error Exception Handling .........................81

Table 4.7 Interrupt Sources..................................................................................................... 81

Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling...................... 83

Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling ...................84

Section 5 Interrupt Controller

Table 5.1

MCU Operating Mode Settings .............................................................................. 67

Exception Types and Priority..................................................................................73

Pin Configuration....................................................................................................88

Rev. 3.00 Mar. 14, 2006 Page xxxiii of xxxviii

Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority........................ 105

Table 5.3 Interrupt Control Modes ....................................................................................... 112

Table 5.4 Interrupt Response Times ..................................................................................... 117

Table 5.5 Number of Execution States in Interrupt Handling Routine................................. 118

Table 5.6 Interrupt Source Selection and Clear Control ....................................................... 119

Table 5.7 CPU Priority Control ............................................................................................121

Table 5.8 Example of Priority Control Function Setting and Control State ......................... 121

Section 6 Bus Controller (BSC)

Table 6.1

Table 6.2 Number of Access Cycles for On-Chip Memory Spaces...................................... 129

Table 6.3 Number of Access Cycles for Registers of On-Chip Peripheral Modules............ 129

Section 7 DMA Controller (DMAC)

Table 7.1

Table 7.2 Settings and Areas of Extended Repeat Area .......................................................156

Table 7.3 Transfer Modes..................................................................................................... 157

Table 7.4 List of On-chip module interrupts to DMAC........................................................167

Table 7.5 Priority among DMAC Channels.......................................................................... 181

Table 7.6 Interrupt Sources and Priority............................................................................... 200

Section 8 I/O Ports

Table 8.1

Table 8.2 Register Configuration in Each Port..................................................................... 210

Table 8.3 Input Pull-Up MOS State...................................................................................... 214

Table 8.4 Available Output Signals and Settings in Each Port............................................. 239

Synchronization Clocks and Their Corresponding Functions...............................128

Data Access Size, Valid Bits, and Settable Size ................................................... 142

Port Functions....................................................................................................... 205

Section 9 16-Bit Timer Pulse Unit (TPU)

Table 9.1

Table 9.2 TPU Functions (Unit 0) ........................................................................................252

Table 9.3 TPU Functions (Unit 1) ........................................................................................254

Table 9.4 Pin Configuration.................................................................................................. 258

Table 9.5 CCLR2 to CCLR0 (Channels 0 and 3) .................................................................266

Table 9.6 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) ........................................................266

Table 9.7 Input Clock Edge Selection ..................................................................................267

Table 9.8 TPSC2 to TPSC0 (Channel 0) .............................................................................. 267

Table 9.9 TPSC2 to TPSC0 (Channel 1) .............................................................................. 267

Table 9.10 TPSC2 to TPSC0 (Channel 2) ..............................................................................268

Table 9.11 TPSC2 to TPSC0 (Channel 3) ..............................................................................268

Table 9.12 TPSC2 to TPSC0 (Channel 4) ..............................................................................269

Table 9.13 TPSC2 to TPSC0 (Channel 5) ..............................................................................269

Table 9.14 MD3 to MD0 ........................................................................................................271

Rev. 3.00 Mar. 14, 2006 Page xxxiv of xxxviii

Unit Configuration for Each Product.................................................................... 252

Table 9.15 TIORH_0 .............................................................................................................. 274

Table 9.16 TIORL_0...............................................................................................................275

Table 9.17 TIOR_1................................................................................................................. 276

Table 9.18 TIOR_2................................................................................................................. 277

Table 9.19 TIORH_3 .............................................................................................................. 278

Table 9.20 TIORL_3...............................................................................................................279

Table 9.21 TIOR_4................................................................................................................. 280

Table 9.22 TIOR_5................................................................................................................. 281

Table 9.23 TIORH_0 .............................................................................................................. 282

Table 9.24 TIORL_0...............................................................................................................283

Table 9.25 TIOR_1................................................................................................................. 284

Table 9.26 TIOR_2................................................................................................................. 285

Table 9.27 TIORH_3 .............................................................................................................. 286

Table 9.28 TIORL_3...............................................................................................................287

Table 9.29 TIOR_4................................................................................................................. 288

Table 9.30 TIOR_5................................................................................................................. 289

Table 9.31 Register Combinations in Buffer Operation .........................................................307

Table 9.32 Cascaded Combinations........................................................................................ 311

Table 9.33 PWM Output Registers and Output Pins ..............................................................314

Table 9.34 Clock Input Pins in Phase Counting Mode ...........................................................318

Table 9.35 Up/Down-Count Conditions in Phase Counting Mode 1...................................... 320

Table 9.36 Up/Down-Count Conditions in Phase Counting Mode 2...................................... 321

Table 9.37 Up/Down-Count Conditions in Phase Counting Mode 3..................................... 322

Table 9.38 Up/Down-Count Conditions in Phase Counting Mode 4...................................... 323

Table 9.39 TPU Interrupts ......................................................................................................326

Section 10 Programmable Pulse Generator (PPG)

Table 10.1

Section 11 Watchdog Timer (WDT)

Table 11.1

Section 12 Serial Communication Interface (SCI)

Table 12.1

Table 12.2 Relationships between N Setting in BRR and Bit Rate B..................................... 398

Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ......399

Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ......400

Table 12.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode)..........401

Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................401

Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 402

Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ....403

Pin Configuration.................................................................................................. 346

WDT Interrupt Source ..........................................................................................373

Pin Configuration.................................................................................................. 379

Rev. 3.00 Mar. 14, 2006 Page xxxv of xxxviii

Table 12.8 BRR Settings for Various Bit Rates

(Smart Card Interface Mode, n = 0, S = 372) .......................................................404

Table 12.9 Maximum Bit Rate for Each Operating Frequency

(Smart Card Interface Mode, S = 372).................................................................. 404

Table 12.10 Serial Transfer Formats (Asynchronous Mode)................................................ 406

Table 12.11 SSR Status Flags and Receive Data Handling.................................................. 413

Table 12.12 SCI Interrupt Sources........................................................................................ 440

Table 12.13 SCI Interrupt Sources........................................................................................ 441

Section 13 Controller Area Network (HCAN)

Table 13.1

Table 13.2 Limits for the Settable Value................................................................................ 487

Table 13.3 Setting Range for TSEG1 and TSEG2 in BCR..................................................... 488

Table 13.4 HCAN Interrupt Sources ......................................................................................501

Table 13.5 Duration between Transmission Setting ............................................................... 507

Section 14 Synchronous Serial Communication Unit (SSU)

Table 14.1

Table 14.2 Correspondence Between DATS Bit Setting and SSTDR.................................... 524

Table 14.3 Correspondence Between DATS Bit Setting and SSRDR.................................... 525

Table 14.4 Communication Modes and Pin States of SSI and SSO Pins ............................... 528

Table 14.5 Communication Modes and Pin States of SSCK Pin............................................ 529

Table 14.6 Communication Modes and Pin States of SCS Pin............................................... 529

Table 14.7 Interrupt Sources................................................................................................... 545

Pin Configuration.................................................................................................. 451

Pin Configuration.................................................................................................. 511

Section 15 A/D Converter

Table 15.1

Table 15.2 Analog Input Channels and Corresponding ADDR Registers.............................. 552

Table 15.3 A/D Conversion Characteristics (Single Mode) ................................................... 560

Table 15.4 A/D Conversion Characteristics (Scan Mode)...................................................... 560

Table 15.5 A/D Converter Interrupt Source............................................................................561

Table 15.6 Analog Pin Specifications..................................................................................... 565

Section 17 Flash Memory (0.18-mm F-ZTAT Version)

Table 17.1

Table 17.2 Pin Configuration.................................................................................................. 577

Table 17.3 Registers/Parameters and Target Modes............................................................... 579

Table 17.4 Parameters and Target Modes............................................................................... 586

Table 17.5 On-Board Programming Mode Setting................................................................. 599

Table 17.6 System Clock Frequency for Automatic-Bit-Rate Adjustment............................. 600

Table 17.7 Executable Memory MAT.................................................................................... 618

Rev. 3.00 Mar. 14, 2006 Page xxxvi of xxxviii

Pin Configuration.................................................................................................. 550

Differences between Boot Mode, User Program Mode, User Boot Mode,

and Programmer Mode ......................................................................................... 572

Table 17.8 Usable Area for Programming in User Program Mode.........................................619

Table 17.9 Usable Area for Erasure in User Program Mode ..................................................620

Table 17.10 Usable Area for Programming in User Boot Mode...........................................621

Table 17.11 Usable Area for Erasure in User Boot Mode ....................................................622

Table 17.12 Hardware Protection .........................................................................................623

Table 17.13 Software Protection...........................................................................................624

Table 17.14 Device Types Supported in Programmer Mode................................................ 630

Table 17.15 Inquiry and Selection Commands..................................................................... 634

Table 17.16 Programming/Erasing Commands .................................................................... 647

Table 17.17 Status Code....................................................................................................... 657

Table 17.18 Error Code ........................................................................................................657

Section 18 Clock Pulse Generator

Table 18.1

Table 18.2 Crystal Resonator Characteristics......................................................................... 666

Section 19 Power-Down Modes

Table 19.1

Table 19.2 Oscillation Settling Time Settings ........................................................................682

Table 19.3 Bφ Pin (PA7) State in Each Processing State .......................................................685

Section 21 Electrical Characteristics

Table 21.1

Table 21.2 DC Characteristics (1)...........................................................................................762

Table 21.2 DC Characteristics (2)...........................................................................................763

Table 21.3 Permissible Output Currents................................................................................. 764

Table 21.4 Clock Timing........................................................................................................ 765

Table 21.5 Control Signal Timing ..........................................................................................767

Table 21.6 Timing of On-Chip Peripheral Modules (1)..........................................................768

Table 21.6 Timing of On-Chip Peripheral Modules (2)..........................................................770

Table 21.7 A/D Conversion Characteristics............................................................................776

Table 21.8 Flash Memory Characteristics ..............................................................................777

Damping Resistance Value................................................................................... 665

Operating States.................................................................................................... 671

Absolute Maximum Ratings .................................................................................761

Appendix

Table A.1

Port States in Each Pin State................................................................................. 779

Rev. 3.00 Mar. 14, 2006 Page xxxvii of xxxviii

Rev. 3.00 Mar. 14, 2006 Page xxxviii of xxxviii

Section 1 Overview

Section 1 Overview

1.1 Features

• 32-bit high-speed H8SX CPU
Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU
Sixteen 16-bit general registers
87 basic instructions

• Extensive peripheral functions
DMA controller (DMAC)
16-bit timer pulse unit (TPU)
Programmable pulse generator (PPG)*
Watch dog timer (WDT)
Serial communication interface (SCI) can be used in asynchronous and clocked synchronous

mode
Controller area network (HCAN)
Synchronous serial communication unit (SSU)
10-bit A/D converter
Clock pulse generator

Note: * Supported only by the H8SX/1527.

• On-chip memory

Product Classification Product Model ROM RAM

Flash memory version H8SX/1527 R5F61527 256 kbytes 12 kbytes

H8SX/1525 R5F61525 256 kbytes 12 kbytes

• General I/O port
65 input/output ports
17 input ports

• Supports power-down modes

• Small package

Package Code Body Size Pin Pitch

QFP-100 PRQP0100KB-A

(FP-100M)

14.0 × 14.0 mm 0.50 mm

Rev. 3.00 Mar. 14, 2006 Page 1 of 804

REJ09B0104-0300

Section 1 Overview

1.2 Block Diagram

RAM

ROM

H8SX

CPU

Clock pulse

generator

Internal bus

Interrupt

controller

BSC

DMAC

× 4 channels

WDT

TPU (unit 0)
× 6 channels

TPU (unit 1)
× 6 channels

PPG

SCI × 2 channels

HCAN

Peripheral bus

SSU × 3 channels

A/D (unit 0)

× 8 channels

A/D (unit 1)

× 8 channels

On-chip debugging

function for E10A

Por t 1

Por t 2

Por t 3

Por t 4

Por t 5

Por t 6

Por t A

Por t D

Por t H

Por t J

[Legend]
CPU: Central processing unit
DMAC: DMA controller
BSC: Bus controller
WDT: Watchdog timer
TPU: 16-bit timer pulse unit

PPG: Programmable pulse generator
SCI: Serial communication interface
HCAN: Controller area network
SSU: Synchronous communication unit

Figure 1.1 Block Diagram of H8SX/1527

Rev. 3.00 Mar. 14, 2006 Page 2 of 804

REJ09B0104-0300

Por t K

Section 1 Overview

RAM

ROM

H8SX

CPU

Clock pulse

generator

Internal bus

Interrupt
controller

BSC

DMAC

x 4 channels

Peripheral bus

A/D (unit 0) x 8 channels

A/D (unit 1) x 8 channels

WDT

TPU (unit 1)

x 6 channels

SCI x 2 channels

HCAN

SSU x 3 channels

On-chip debugging

function for E10A

Por t 1

Por t 2

Por t 3

Por t 4

Por t 5

Por t 6

Por t A

Por t D

Por t H

Por t J

Por t K

[Legend]
CPU: Central processing unit
DMAC: DMA controller
BSC: Bus controller
WDT: Watchdog timer
TPU: 16-bit timer pulse unit

SCI: Serial communication interface
HCAN: Controller area network
SSU: Synchronous communication unit

Figure 1.2 Block Diagram of H8SX/1525

Rev. 3.00 Mar. 14, 2006 Page 3 of 804

REJ09B0104-0300

Section 1 Overview

1.3 Pin Assignments

1.3.1 Pin Assignments

PA1/SSCK2

PA2/SSI2

PA3/SSO2

EMLE*

Vss

EXTAL

757473727170 6968 6766 6564 6362 6160 5958 5756 5554 5352 51

MD1

AVcc1

AVss

AVcc0

MD0

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

123456789101112131415161718192021222324

P40/AN12
P41/AN13
P42/AN14
P43/AN15

P44/AN8
P45/AN9

P46/AN10

P47/AN11

P50/AN0

P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7

PD0/SSO0

PD1/SSI0

PD2/SSCK0

PD3/SCS0

XTAL

Vcc

NMI

RES

P37/PO15/TIOCA2/TIOCB2/TCLKD/TCK*

P36/PO14/TIOCA2/TDI*

P35/PO13/TIOCA1/TIOCB1/TCLKC/TMS*

P34/PO12/TIOCA1/TRST*

P33/PO11/TIOCC0/TIOCD0/TCLKB

P32/PO10/TIOCC0/TCLKA

PRQP0100KB-A (FP-100M)

(top view)

P31/PO9/TIOCA0/TIOCB0

P30/PO8/TIOCA0

PA 4

PA 5

PA 6

Vcc

PA7/Bφ

Vss

P23/TIOCC3/TIOCD3/IRQ11-A

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

25

P22/TIOCC3/IRQ10-A
P21/TIOCA3/IRQ9-A/SCS2
P20/TIOCA3/TIOCB3/IRQ8-A
P17/ADTRG1/IRQ7
P16/SCK3/IRQ6
P15/RxD3/IRQ5
P14/TxD3/IRQ4
P13/ADTRG0/IRQ3
P12/IRQ2
V

CL

P11/IRQ1
Vss
P10/IRQ0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PK7/TIOCA11/TIOCB11
PK6/TIOCA11
PK5/TIOCA10/TIOCB10
PK4/TIOCA10

Vss

Vcc

PD5/SSI1

PD7/SCS1

PD4/SSO1

PD6/SSCK1

P60/TxD4/IRQ8-B

P61/RxD4/IRQ9-B

Note: * The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE
pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A. In this
case, other pin functions are disabled.

P66/IRQ14

PJ0/TIOCA6

PJ4/TIOCA7

PJ6/TIOCA8

PK0/TIOCA9

P64/IRQ12/HTxD

P65/IRQ13/HRxD

P63/IRQ11-B/TDO*

P62/SCK4/IRQ10-B

PJ2/TIOCC6/TCLKE

PJ1/TIOCA6/TIOCB6

PJ3/TIOCC6/TIOCD6/TCLKF

PJ7/TIOCA8/TIOCB8/TCLKH

PJ5/TIOCA7/TIOCB7/TCLKG

Figure 1.3 Pin Assignments of H8SX/1527

Rev. 3.00 Mar. 14, 2006 Page 4 of 804

REJ09B0104-0300

PK2/TIOCC9

PK1/TIOCA9/TIOCB9

PK3/TIOCC9/TIOCD9

MD1
P40/AN12
P41/AN13
P42/AN14
P43/AN15

P44/AN8
P45/AN9

P46/AN10

AVcc1

P47/AN11

AVss

P50/AN0

AVcc0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7

MD0

PD0/SSO0

PD1/SSI0

PD2/SSCK0

PD3/SCS0

PA1/SSCK2

PA2/SSI2

PA3/SSO2

EMLE*

Vss

EXTAL

XTAL

Vcc

NMI

RES

P37/TCK*

P36/TDI*

P35/TMS*

P34/TRST*

P33

P32

P31

P30

PA 4

PA 5

PA 6

Vcc

7574737271 7069 6867 6665 6463 6261 6059 5857 565554535251

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

1 2 3 4 5 6 7 8 9 10111213 14 1516 171819 20 21222324

PD5/SSI1

PD4/SSO1

PRQP0100KB-A (FP-100M)

PD7/SCS1

PD6/SSCK1

P60/TxD4/IRQ8-B

P61/RxD4/IRQ9-B

P63/IRQ11-B/TDO*

P62/SCK4/IRQ10-B

P64/IRQ12/HTxD

P65/IRQ13/HRxD

(top view)

P66/IRQ14

PJ0/TIOCA6

PJ4/TIOCA7

PJ2/TIOCC6/TCLKE

PJ1/TIOCA6/TIOCB6

Vss

PJ6/TIOCA8

PK0/TIOCA9

Vcc

PA 7/ B φ

Vss

P23/IRQ11-A

P22/IRQ10-A

50

P21/IRQ9-A/SCS2

49

P20/IRQ8-A

48

P17/ADTRG1/IRQ7

47

P16/SCK3/IRQ6

46

P15/RxD3/IRQ5

45

P14/TxD3/IRQ4

44

P13/ADTRG0/IRQ3

43

P12/IRQ2

42

V

CL

41

P11/IRQ1

40

Vss

39

P10/IRQ0

38

PH7

37

PH6

36

PH5

35

PH4

34

PH3

33

PH2

32

PH1

31

PH0

30

PK7/TIOCA11/TIOCB11

29

PK6/TIOCA11

28

PK5/TIOCA10/TIOCB10

27

PK4/TIOCA10

26

25

PK2/TIOCC9

PK1/TIOCA9/TIOCB9

PK3/TIOCC9/TIOCD9

Section 1 Overview

PJ3/TIOCC6/TIOCD6/TCLKF

PJ7/TIOCA8/TIOCB8/TCLKH

PJ5/TIOCA7/TIOCB7/TCLKG

Note: * The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE
pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A. In this
case, other pin functions are disabled.

Figure 1.4 Pin Assignments of H8SX/1525

Rev. 3.00 Mar. 14, 2006 Page 5 of 804

REJ09B0104-0300

Section 1 Overview

1.3.2 Pin Configuration in Each Operating Mode

Table 1.1 Pin Configuration in Each Operating Mode

Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3

1 PD4/SSO1

2 PD5/SSI1

3 PD6/SSCK1
4 PD7/SCS1
5 P60/TxD4/IRQ8-B
6 P61/RxD4/IRQ9-B
7 P62/SCK4/IRQ10-B
8 P63/IRQ11-B/TDO*
9 P64/IRQ12/HTxD
10 P65/IRQ13/HRxD
11 P66/IRQ14

12 PJ0/TIOCA6

13 PJ1/TIOCA6/TIOCB6

14 PJ2/TIOCC6/TCLKE

15 PJ3/TIOCC6/TIOCD6/TCLKF

16 PJ4/TIOCA7

17 PJ5/TIOCA7/TIOCB7/TCLKG

18 PJ6/TIOCA8

19 PJ7/TIOCA8/TIOCB8/TCLKH

20 Vss

21 PK0/TIOCA9

22 Vcc

23 PK1/TIOCA9/TIOCB9

24 PK2/TIOCC9

25 PK3/TIOCC9/TIOCD9

26 PK4/TIOCA10

27 PK5/TIOCA10/TIOCB10

28 PK6/TIOCA11

29 PK7/TIOCA11/TIOCB11

30 PH0

2

Rev. 3.00 Mar. 14, 2006 Page 6 of 804

REJ09B0104-0300

Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3

31 PH1

32 PH2

33 PH3

34 PH4

35 PH5

36 PH6

37 PH7
38 P10/IRQ0

39 Vss
40 P11/IRQ1

41 VCL
42 P12/IRQ2
43 P13/ADTRG0/IRQ3
44 P14/TxD3/IRQ4
45 P15/RxD3/IRQ5
46 P16/SCK3/IRQ6
47 P17/ADTRG1/IRQ7
48 P20/(TIOCA3/TIOCB3)*1/IRQ8-A
49 P21/(TIOCA3)*1/IRQ9-A/SCS2
50 P22/(TIOCC3)*1/IRQ10-A
51 P23/(TIOCC3/TIOCD3)*1/IRQ11-A

52 Vss

53 PA7/Bφ

54 Vcc

55 PA6

56 PA5

57 PA4
58 P30/(PO8/TIOCA0)*
59 P31/(PO9/TIOCA0/TIOCB0)*
60 P32/(PO10/TIOCC0/TCLKA)*

1

1

1

Section 1 Overview

Rev. 3.00 Mar. 14, 2006 Page 7 of 804

REJ09B0104-0300

Section 1 Overview

Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3

1

61 P33/(PO11/TIOCC0/TIOCD0/TCLKB)*
62 P34/(PO12/TIOCA1)*1/TRST*

2

63 P35/(PO13/TIOCA1/TIOCB1/TCLKC)*1/TMS*
64 P36/(PO14/TIOCA2)*1/TDI*

2

65 P37/(PO15/TIOCA2/TIOCB2/TCLKD)*1/TCK*
66 RES

67 NMI

68 Vcc

69 XTAL

70 EXTAL

71 Vss
72 EMLE*

2

73 PA3/SSO2

74 PA2/SSI2

75 PA1/SSCK2

76 MD1

77 P40/AN12

78 P41/AN13

79 P42/AN14

80 P43/AN15

81 P44/AN8

82 P45/AN9

83 P46/AN10

84 AVcc1

85 P47/AN11

86 AVss

87 P50/AN0

88 AVcc0

89 P51/AN1

90 P52/AN2

2

2

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REJ09B0104-0300

Section 1 Overview

Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3

91 P53/AN3

92 P54/AN4

93 P55/AN5

94 P56/AN6

95 P57/AN7

96 MD0

97 PD0/SSO0

98 PD1/SSI0

99 PD2/SSCK0
100 PD3/SCS0

Notes: 1. Not supported by the H8SX/1525.

2. The EMLE (emulator enable) pin enables/disables the on-chip debugging functions.
When the EMLE pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used
specific for the E10A. In this case, other pin functions are disabled.

Rev. 3.00 Mar. 14, 2006 Page 9 of 804

REJ09B0104-0300

Section 1 Overview

1.3.3 Pin Functions

Table 1.2 Pin Functions

Pin Number
Classifi-

cation Abbreviation H8SX/1527 H8SX/1525 I/O Description

Power
supply

V

V

Clock XTAL 69 69 Input

EXTAL 70 70 Input

Bφ 53 53 Output Supplies the system clock to external

Operating
mode
control

System
control

EMLE 72 72 Input Input pin for on-chip emulator enable

VCC 22, 54, 68 22, 54, 68 Input Power supply pins. Connect to the system

power supply.

41 41 Input Connect to VSS via a 0.1-uF capacitor

CL

(place it close to this pin).

20, 39, 52,

SS

71

20, 39, 52,
71

Input Ground pins. Connect to the system power

supply (0 V).

Pins for a crystal resonator. External clock
can be input to the EXTAL pin. For a
connection example, see section 18, Clock
Pulse Generator.

devices.

MD1

MD0

76

96

76

96

Input Pins for setting the operating mode. The

signal levels of these pins must not be
changed during operation.

RES 66 66 Input Reset signal input pin. This LSI enters the

reset state when this signal goes low.

signal. Normally the signal level should be
fixed low.

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REJ09B0104-0300

Section 1 Overview

Pin Number
Classifi-

cation Abbreviation H8SX/1527 H8SX/1525 I/O Description

Interrupts NMI 67 67 Input Non-maskable interrupt request signal.

When this pin is not in use, this signal
must be fixed high.

interface

TDO 8 8 Output

TDI 64 64 Input

TCK 65 65 Input

16-bit
timer
pulse unit
(TPU)
(unit 0)*

IRQ14
IRQ13
IRQ12
IRQ11-A/IRQ11-B
IRQ10-A/IRQ10-B
IRQ9-A/IRQ9-B
IRQ8-A/IRQ8-B
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
TRST 62 62 Input Debugging

TMS 63 63 Input

TCLKA

TCLKB

TCLKC

TCLKD

TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1

11

10

9

51/8

50/7

49/6

48/5

47

46

45

44

43

42

40

38

60

61

63

65

58, 59

59

60, 61

61

62, 63

63

11

10

9

51/8

50/7

49/6

48/5

47

46

45

44

43

42

40

38





















Input Maskable interrupt request signal.

Interface pins for debugging by the on-chip
emulator.

Input Input pins for the external clocks.

I/O Signals for TGRA_0 to TGRD_0. These

are used for the input capture
inputs/output compare outputs/PWM
outputs.

I/O Signals for TGRA_1 and TGRB_1. These

are used for the input capture
inputs/output compare outputs/PWM
outputs.

Rev. 3.00 Mar. 14, 2006 Page 11 of 804

REJ09B0104-0300

Section 1 Overview

Pin Number
Classifi-

cation Abbreviation H8SX/1527 H8SX/1525 I/O Description

16-bit
timer
pulse unit
(TPU)
(unit 0)*

timer
pulse unit
(TPU)
(unit 1)

TIOCA7

TIOCA8

TIOCA9

TIOCA10

TIOCA11

TIOCA2

TIOCB2

TIOCA3

TIOCB3

TIOCC3

TIOCD3

TCLKE

TCLKF

TCLKG

TCLKH

TIOCA6

TIOCB6

TIOCC6

TIOCD6

TIOCB7

TIOCB8

TIOCB9

TIOCC9

TIOCD9

TIOCB10

TIOCB11

64, 65

65

48, 49

48

50, 51

51

14

15

17

19

12, 13

13

14, 15

15

16, 17

17

18, 19

19

21, 23

23

24, 25

25

26, 27

27

28, 29

29













14

15

17

18

12, 13

13

14, 15

14

16, 17

17

18, 19

19

21, 23

23

24, 25

25

26, 27

27

28, 29

29

I/O Signals for TGRA_2 and TGRB_2. These

are used for the input capture
inputs/output compare outputs/PWM
outputs.

I/O Signals for TGRA_3 toTGRD_3. These are

used for the input capture inputs/output
compare outputs/PWM outputs.

Input Input pins for the external clocks. 16-bit

I/O Signals for TGRA_6 toTGRD_6. These are

used for the input capture inputs/output
compare outputs/PWM outputs.

I/O Signals for TGRA_7 toTGRB_7. These are

used for the input capture inputs/output
compare outputs/PWM outputs.

I/O Signals for TGRA_8 toTGRB_8. These are

used for the input capture inputs/output
compare outputs/PWM outputs.

I/O Signals for TGRA_9 toTGRD_9. These are

used for the input capture inputs/output
compare outputs/PWM outputs.

I/O Signals for TGRA_10 toTGRB_10. These

are used for the input capture
inputs/output compare outputs/PWM
outputs.

I/O Signals for TGRA_11 toTGRB_11. These

are used for the input capture
inputs/output compare outputs/PWM
outputs.

Rev. 3.00 Mar. 14, 2006 Page 12 of 804

REJ09B0104-0300

Pin Number
Classifi-

cation Abbreviation H8SX/1527 H8SX/1525 I/O Description

Program­mable
pulse
generator
(PPG)*

Serial
communi­cation
interface
(SCI)

area
network
(HCAN)

nous serial
communi­cation unit
(SSU)

SSCK2

SCS2

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

TxD3

TxD4

RxD3

RxD4

SCK3

SCK4

HTxD 9 9 Output Output pin for CAN bus transmission. Controller

HRxD 10 10 Input Input pin for CAN bus reception.

SSO2
SSO1
SSO0

SSI2

SSI1

SSI0

SSCK1

SSCK0

SCS1

SCS0

65

64

63

62

61

60

59

58

44

5

45

6

46

7

73

1

97

74

2

98

75

3

99

49

4

100

















44

5

45

6

46

7

73

1

97

74

2

98

75

3

99

49

4

100

Output Output pins for the pulse signals.

Output Output pins for transmit data.

Input Input pins for receive data.

I/O Input/output pins for clock signals.

I/O Input/output pins for data. Synchro-

I/O Input/output pins for data.

I/O Input/output pins for clock.

I/O Input/output pins for chip select.

Section 1 Overview

Rev. 3.00 Mar. 14, 2006 Page 13 of 804

REJ09B0104-0300

Section 1 Overview

Pin Number
Classifi-

cation Abbreviation H8SX/1527 H8SX/1525 I/O Description

A/D
converter

ADTRG0

AVCC0

AN15

AN14

AN13

AN12

AN11

AN10

AN9

AN8

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

ADTRG1

1

AV

CC

80

79

78

77

85

83

82

81

95

94

93

92

91

90

89

87

43

47

88

84

80

79

78

77

85

83

82

81

95

94

93

92

91

90

89

87

43

47

88

84

Input Input pins for the analog signals for the

A/D converter.

Input Input pins for the external trigger signal to

start A/D conversion.

Input Analog power supply and reference power

supply pins for the A/D converter. When
the A/D converter is not in use, connect to
the system power supply.

AVSS 86 86 Input Ground pin for the A/D and D/A

converters. Connect to the system power
supply (0 V).

Rev. 3.00 Mar. 14, 2006 Page 14 of 804

REJ09B0104-0300

Pin Number
Classifi-

cation Abbreviation H8SX/1527 H8SX/1525 I/O Description

I/O port P17

P16

P15

P14

P13

P12

P11

P10

P23

P22

P21

P20

P37

P36

P35

P34

P33

P32

P31

P30

P47

P46

P45

P44

P43

P42

P41

P40

47

46

45

44

43

42

40

38

51

50

49

48

65

64

63

62

61

60

59

58

85

83

82

81

80

79

78

77

47

46

45

44

43

42

40

38

51

50

49

48

65

64

63

62

61

60

59

58

85

83

82

81

80

79

78

77

I/O 8-bit input/output pins.

I/O 4-bit input/output pins.

I/O 8-bit input/output pins.

Input 8-bit input pins.

Section 1 Overview

Rev. 3.00 Mar. 14, 2006 Page 15 of 804

REJ09B0104-0300

Section 1 Overview

Pin Number
Classifi-

cation Abbreviation H8SX/1527 H8SX/1525 I/O Description

I/O port P57

P56

P55

P54

P53

P52

P51

P50

P66

P65

P64

P63

P62

P61

P60

PA7 53 53 Input 1-bit input pin.

PA6

PA5

PA4

PA3

PA2

PA1

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

95

94

93

92

91

90

89

87

11

10

9

8

7

6

5

55

56

57

73

74

75

4

3

2

1

100

99

98

97

95

94

93

92

91

90

89

87

11

10

9

8

7

6

5

55

56

57

73

74

75

4

3

2

1

100

99

98

97

Input 8-bit input pins.

I/O 7-bit input/output pins.

I/O 6-bit input/output pins.

I/O 8-bit input/output pins.

Rev. 3.00 Mar. 14, 2006 Page 16 of 804

REJ09B0104-0300

Pin Number
Classifi-

cation Abbreviation H8SX/1527 H8SX/1525 I/O Description

I/O port PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

PK7

PK6

PK5

PK4

PK3

PK2

PK1

PK0

37

36

35

34

33

32

31

30

19

18

17

16

15

14

13

12

29

28

27

26

25

24

23

21

37

36

35

34

33

32

31

30

19

18

17

16

15

14

13

12

29

28

27

26

25

24

23

21

I/O 8-bit input/output pins.

I/O 8-bit input/output pins.

I/O 8-bit input/output pins.

Note: * Supported only by the H8SX/1527.

Section 1 Overview

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REJ09B0104-0300

Section 1 Overview

Rev. 3.00 Mar. 14, 2006 Page 18 of 804

REJ09B0104-0300

Section 2 CPU

Section 2 CPU

The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward­compatible with the H8/300, H8/300H, and H8S CPUs.

The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space,
and is ideal for a realtime control system.

2.1 Features

• Upward-compatible with H8/300, H8/300 H, and H8S CPUs

 Can execute H8/300, H8/300H, and H8S/2000 object programs

• Sixteen 16-bit general registers

 Also usable as sixteen 8-bit registers or eight 32-bit registers

• 87 basic instructions

 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Bit field transfer instructions
 Powerful bit-manipulation instructions
 Bit condition branch instructions
 Multiply-and-accumulate instruction

• Eleven addressing modes

 Register direct [Rn]
 Register indirect [@ERn]
 R egi st er in di rect with displacement [@(d:2,ERn) , @ ( d: 1 6, E R n) , or @( d:32,ERn)]
 Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B),

@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)]

 Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @ER n+, @−

ERn, or @ERn−]

 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32]
 Pr ogram-counter relative [@(d:8,PC) or @(d:16,PC)]
 Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or

@(ERn.L,PC)]

 Memory indirect [@@aa:8]
 Extended memory indirect [@@vec:7]

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REJ09B0104-0300

Section 2 CPU

• Two base registers
 Vector base re gister
 Sh ort a d dress base regi st er

• 4-Gbyte address space
 Program: 4 Gbytes
 Data: 4 Gbytes

• High-speed operation
 All frequently-used instructions executed in one or two states
 8/16/32-bit register-register add/subtract: 1 state
 8 × 8-bit register-register multiply: 1 state
 16 ÷ 8-bit register-register divide: 10 states
 16 × 16-bit register-register multiply: 1 state
 32 ÷ 16-bit register-register divide: 18 states
 32 × 32-bit register-register multiply: 5 states
 32 ÷ 32-bit register-register divide: 18 states

• Four CPU operating modes
 No rmal mo de
 Middle mode
 Advanced mode
 Maximum mode

• Power-down modes
 Transition is made by execution of SLEEP instruction
 Choice of CPU operating clocks

Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1520

Group. Normal, middle, and maximum modes are not supported.

2. The multiplier and divider are supported by the H8SX/1520 Group.

3. In the H8SX/1520 Group, an instruction is fetched in 32-bit mode.

Rev. 3.00 Mar. 14, 2006 Page 20 of 804

REJ09B0104-0300

Section 2 CPU

2.2 CPU Operating Modes

The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. For
details on mode settings, see section 3.1, Operating Mode Selection.

Normal mode

Middle mode

CPU operating modes

Advanced mode

Maximum mode

Maximum 64 kbytes for program

and data areas combined

Maximum 16-Mbyte program

area and 64-kbyte data area,

maximum 16 Mbytes for program

and data areas combined

Maximum 16-Mbyte program

area and 4-Gbyte data area,

maximum 4 Gbytes for program

and data areas combined

Maximum 4 Gbytes for program

and data areas combined

Figure 2.1 CPU Operating Modes

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

Note: Normal mode is not supported in this LSI.

• Address Space
The maximum address space of 64 kbytes can be accessed.

• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers. When the extended register En is used as a 16-bit register it can
contain any value, even when the corresponding general register Rn is used as an address
register. (If the general register Rn is referenced in the register indirect addressing mode with
pre-/post-increment or pre-/post - decrement and a carry or borrow occurs, however, the value in
the corresponding extended register En will be affected.)

• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective

addresses (EA) are valid.

Rev. 3.00 Mar. 14, 2006 Page 21 of 804

REJ09B0104-0300

Section 2 CPU

• Exception Vector Table and Memory Indirect Branch Addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vect o r tabl e. One

branch address is stored per 16 bits. The structure of the exception vector table is shown in
figure 2.2.

H'0000
H'0001
H'0002
H'0003

Reset exception vector

Reset exception vector

Exception
vector table

Figure 2.2 Exception Vector Table (Normal Mode)

The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.

• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception

handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units.

SP SP

PC

(16 bits)

(SP )

2

*

1

EXR*

Reserved*1,*

CCR

3

CCR*

PC

(16 bits)

3

(a) Subroutine Branch (b) Exception Handling

Notes: 1.

When EXR is not used it is not stored on the stack.
SP when EXR is not used.

2.
Ignored on return.

3.

Figure 2.3 Stack Structure (Normal Mode)

Rev. 3.00 Mar. 14, 2006 Page 22 of 804

REJ09B0104-0300

Section 2 CPU

2.2.2 Middle Mode

The program area in middle mode is extended to 16 Mbytes as compared with that in normal
mode.

• Address Space
The maximum address space of 16 Mbytes can be accessed as a total of the program and data

areas. For individual areas, up to 16 Mbytes of the program area or up to 64 kbytes of the data
area can be allocated.

• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers. When the extended register En is used as a 16-bit register (in
other than the JMP and JSR instructions), it can contain any value even when the
corresponding general register Rn is used as an address register. (If the general register Rn is
referenced in the register indirect addressing mode with pre-/post-increment or pre-/post­decrement and a carry or borrow occurs, however, the value in the corresponding extended
register En will be affected.)

• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective

addresses (EA) are valid and the upper eight bits are sign-extended.

• Exception Vector Table and Memory Indirect Branch Addresses
In middle mode, the top area starting at H'000000 is allocated to the exception vector table.

One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits
are stored. The structure of the exception vector table is shown in figure 2.4.

The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.

In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address.
The upper eight bits are reserved and assumed to be H'00.

• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception

handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.

Rev. 3.00 Mar. 14, 2006 Page 23 of 804

REJ09B0104-0300

Section 2 CPU

2.2.3 Advanced Mode

The data area is extended to 4 Gbytes as compared with that in middle mode.

• Address Space
The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to

16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated.

• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers or address registers.

• Instruction Set
All instructions and addressing modes can be used.

• Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector

table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower
24 bits are stored. The structure of the exception vector table is shown in figure 2.4.

H'00000000

H'00000001

H'00000002

H'00000003

H'00000004

H'00000005

H'00000006

H'00000007

Reserved

Reset exception vector

Reserved

Exception vector table

Figure 2.4 Exception Vector Table (Middle and Advanced Modes)

The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.

In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch
address. The upper eight bits are reserved and assumed to be H'00.

Rev. 3.00 Mar. 14, 2006 Page 24 of 804

REJ09B0104-0300

• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception

handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.

1

SP

SP

Reserved

PC

(24 bits)

(a) Subroutine Branch (b) Exception Handling

2

*

(SP )

EXR*

Reserved*1,*

CCR

PC

(24 bits)

3

Section 2 CPU

Notes: 1.

When EXR is not used it is not stored on the stack.
SP when EXR is not used.

2.
Ignored on return.

3.

Figure 2.5 Stack Structure (Middle and Advanced Modes)

2.2.4 Maximum Mode

The program area is extended to 4 Gbytes as compared with that in advanced mode.

• Address Space
The maximum address space of 4 Gbytes can be linearly accessed.

• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit

segments of 32-bit registers or address registers.

• Instruction Set
All instructions and addressing modes can be used.

• Exception Vector Table and Memory Indirect Branch Addresses
In maximum mode, the top area starting at H'00000000 is allocated to the exception vector

table. One branch address is stored per 32 bits. The structure of the exception vector table is
shown in figure 2.6.

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Section 2 CPU

H'00000000

H'00000001

H'00000002

H'00000003

H'00000004

H'00000005

H'00000006

H'00000007

Reset exception vector

Exception vector table

Figure 2.6 Exception Vector Table (Maximum Modes)

The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.

In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch
address.

• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception

handling are shown in figure 2.7. The PC contents are saved or restored in 32-bit units. The
EXR contents are saved or restored regardless of whether or not EXR is in use.

SP

PC

(32 bits)

(a) Subroutine Branch (b) Exception Handling

SP

Figure 2.7 Stack Structure (Maximum Mode)

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EXR

CCR

PC

(32 bits)

Section 2 CPU

2.3 Instruction Fetch

The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended
that the mode be set according to the bus width of the memory in which a program is stored. The
instruction-fetch mode setting does not affect operation other than instruction fetch such as data
accesses.

Note: In the H8SX/1520 Group, an instruction is fetched in 32-bit mode .

2.4 Address Space

Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the
CPU operating mode.

Normal mode

H'0000 H'000000

H'007FFF
Program area
Data area

H'FFFF

(64 kbytes)

H'FF8000

H'FFFFFF

Middle mode Advanced mode

H'00000000

Program area
(16 Mbytes)

Data area
(64 kbytes)

H'00FFFFFF

H'FFFFFFFF

Figure 2.8 Memory Map

H'00000000

Program area
(16 Mbytes)

Data area
(4 Gbytes)

H'FFFFFFFF

Maximum mode

Program area
Data area
(4 Gbytes)

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2.5 Registers

The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers:
general registers and control registers. The control registers are the 32-bit program counter (PC),
8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base
register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register
(MAC).

General Registers and Extended Registers

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

Control Registers

[Legend]

SP:
PC:
CCR:
I:
UI:
H:
U:
N:

15 0 7 0 7 0

E0

E1

E2

E3

E4

E5

E6

E7

31 0

PC

31 012

VBR

31 08

SBR

63

MAC

Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag

Sign extension

Z:
V:
C:
EXR:
T:
I2 to I0:
VBR:
SBR:
MAC:

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

MACL

Zero flag
Overflow flag
Carry flag
Extended control register
Trace bit
Interrupt mask bits
Vector base register
Short address base register
Multiply-accumulate register

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

76543210

UI

HUNZ VCCCR

I

7654321
T

————

(Reserved)

I2 I1 I0EXR

(Reserved)

MACH

0

3241

031

Figure 2.9 CPU Registers

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Section 2 CPU

2.5.1 General Registers

The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike
and can be used as both address registers and data registers. When a general register is used as a
data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the
usage of the general registers.

When the general registers are used as 32-bit registers or address registers, they are designated by
the letters ER (ER0 to ER7).

When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7)
are also referred to as extended registers.

When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing a maximum sixteen 8-bit registers.

The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index
registers. The size in the operand field determines which register is selected.

The usage of each register can be selected independently.

16-bit registers

Address registers

•

32-bit registers

•

32-bit index registers

•

General registers ER
(ER0 to ER7)

•

General registers E
(E0 to E7)

16-bit registers

•

16-bit index registers

•

General registers R
(R0 to R7)

8-bit registers

•

General registers RH
(R0H to R7H)

8-bit registers

•

8-bit index registers

•

General registers RL
(R0L to R7L)

Figure 2.10 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows
the stack.

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Section 2 CPU

Free area

SP (ER7)

Stack area

Figure 2.11 Stack

2.5.2 Program Counter (PC)

PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The
length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant
bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0.

2.5.3 Condition-Code Register (CCR)

CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask
(I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C)
flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc)
instructions.

Initial

Bit Bit Name

7 I 1 R/W Interrupt Mask Bit

6 UI Undefined R/W User Bit or Interrupt Mask Bit

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Value R/W Description

Masks interrupts when set to 1. This bit is set to 1 at the
start of an exception handling.

Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This
bit can also be used as an interrupt mask bit.

Initial

Bit Bit Name

Value R/W Description

5 H Undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or
NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, this flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.

4 U Undefined R/W User Bit

Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit (regarded as
sign bit) of data.

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0
otherwise. A carry has the following types:

• Carry from the result of addition

• Borrow from the result of subtraction

• Carry from the result of shift or rotation

The carry flag is also used as a bit accumulator by bit
manipulation instructions.

Section 2 CPU

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Section 2 CPU

2.5.4 Extended Control Register (EXR)

EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0).

Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instructions.

For details, see the hardware manual for the corresponding product.

Initial

Bit Bit Name

7 T 0 R/W Trace Bit

6 to 3  All 1 R/W Reserved

2

1

0

I2

I1

I0

Value R/W Description

When this bit is set to 1, a trace exception is generated
each time an instruction is executed. When this bit is
cleared to 0, instructions are executed in sequence.

These bits are always read as 1.

1

1

1

R/W

Interrupt Mask Bits

R/W

These bits designate the interrupt mask level (0 to 7).

R/W

2.5.5 Vector Base Register (VBR)

VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are
read as 0s. This register is a base address of the vector area for exception handlings ot her t han a
reset and a CPU address error (extended memory indirect is also out of the target). The initial
value is H'00000000. The VBR contents are changed with the LDC and STC instructions.

2.5.6 Short Address Base Register (SBR)

SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In
8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The
initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions.

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Section 2 CPU

2.5.7 Multiply-Accumulate Register (MAC)

MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists
of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the
upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC,
and STMAC instructions.

2.5.8 Initial Values of CPU Registers

Reset exception handling loads the start address from the vector table into the PC, clears the T bit
in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other
bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is
undefined. The SP should therefore be initialized using an MOV.L instruction executed
immediately after a reset.

2.6 2Data Formats

The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword)
data.

Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte
operand data. The DAA and DAS decimal-adjust instr ucti on s treat byt e d at a as two digi t s of 4-bi t
BCD data.

2.6.1 General Register Data Formats

Figure 2.12 shows the data formats in general registers.

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Section 2 CPU

1-bit data

1-bit data

4-bit BCD data

4-bit BCD data

Byte data

Byte data

Word data

Word data

Longword data

RnH

RnL

RnH

RnL

RnH

RnL

Rn

En

ERn

15

MSB LSB

31

MSB

[Legend]
ERn:

General register ER

En:

General register E

Rn:

General register R

RnH:

General register RH

En

16

43

0

70

Don’t careUpper Lower

43

7

Upper

0

Don’t care

LSB

70

MSB

Rn

7

76543210 Don’t care

Don’t care 7 654321

70

Don’t care

7

MSB

Don’t care

15

MSB

0

15

General register RL

RnL:

Most significant bit

MSB:

Least significant bit

LSB:

0

0

Lower

LSB

0

LSB

0

LSB

Figure 2.12 General Register Data Formats

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Section 2 CPU

2.6.2 Memory Data Formats

Figure 2.13 shows the data formats in memory.

The H8SX CPU can access word data and longword data which are stored at any addresses in
memory. When word data begins at an odd address or longword data begins at an address other
than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when
longword data begins at an odd address, the bus cycle is divided into byte, word, and byte
accesses. In this case, these accesses are assumed to be individual bus cycles.

However, instructions to be fetched, word and longword data to be accessed during execution of
the stack manipulation, branch table manipulation, block transfer instructions, and MAC
instruction should be located to even addresses.

When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.

Data Type Data Format

Address

70

1-bit data

Address L

76543210

Byte data

Word data

Longword data

Address L

Address 2M

Address 2M + 1

Address 2N

Address 2N + 1

Address 2N + 2

Address 2N + 3

MSB LSB

MSB

LSB

MSB

LSB

Figure 2.13 Memory Data Formats

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Section 2 CPU

2.7 Instruction Set

The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown
in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are
called operation instruction in this manual.

Table 2.1 Instruction Classification

Function Instructions Size Types

Data transfer MOV B/W/L 6
MOVFPE*6, MOVTPE*
POP, PUSH*

1

W/L

LDM, STM L
MOVA B/W*

Block transfer EEPMOV B 3

MOVMD B/W/L

MOVSD B

Arithmetic

ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC B/W/L 27

operations

DAA, DAS B

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS B/W

MULU, DIVU, MULS, DIVS W/L

MULU/U, MULS/U L

EXTU, EXTS W/L

TAS B

MAC 

LDMAC, STMAC 

CLRMAC 

Logic operations AND, OR, XOR, NOT B/W/L 4

Shift SHLL, SHLR, SHAL, SHAR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8

Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,

BXOR, BIXOR, BLD, BILD, BST, BIST

BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ B

BFLD, BFST B

6

B

2

B 20

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Section 2 CPU

Function Instructions Size Types

Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC B*
Bcc*

5

, JMP, BSR, JSR, RTS 

RTS/L L*

3

9

5

BRA/S 

System control TRAPA, RTE, SLEEP, NOP  10
RTE/L L*

5

LDC, STC, ANDC, ORC, XORC B/W/L

Total 87

[Legend]
B: Byte size
W: Word size
L: Longword size
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@−SP.

POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,

@−SP.

2. Size of data to be added with a displacement

3. Size of data to specify a branch condition

4. Bcc is the generic designation of a conditional branch instruction.

5. Size of general register to be restored

6. Not available in this LSI.

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Section 2 CPU

2.7.1 Instructions and Addressing Modes

Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can
use.

Table 2.2 Combinations of Instructions and Addressing Modes (1)

Addressing Mode

@(d,

@−ERn/

RnL.B/

@ERn+/
Classifi­cation Instruction Size #xx Rn @ERn @(d,ERn)

Data transfer

MOV B/W/L S SD SD SD SD SD SD

B S/D S/D

MOVFPE,
MOVTPE*

B S/D S/D*

12

POP, PUSH W/L S/D S/D*2
LDM, STM L S/D S/D*2

4

B/W S S S S S S

MOVA*

Block
transfer

EEPMOV B SD*3
MOVMD B/W/L SD*3
MOVSD B SD*

Arithmetic
operations

ADD, CMP B S D D D D D D D

B S D D D D D D

B D S S S S S S

B SD SD SD SD SD

W/L S SD SD SD SD SD SD

SUB B S D D D D D D

B S D D D D D D

B D S S S S S S

B SD SD SD SD SD

W/L S SD SD SD SD SD SD

ADDX, SUBX

B/W/L S SD

B/W/L S SD
B/W/L S SD*

INC, DEC B/W/L D

ADDS, SUBS L D

DAA, DAS B D

Rn.W/

@ERn−/

ERn.L)

@+ERn @aa:8

@aa:16/
@aa:32 

1

5

3

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Section 2 CPU

Addressing Mode

@−ERn/

@(d,

@ERn+/

RnL.B/
Classifi­cation Instruction Size #xx Rn @ERn @(d,ERn)

MULXU, DIVXU B/W S:4 SD Arithmetic

operations

MULXS, DIVXS B/W S:4 SD

W/L D D D D D D

EXTU, EXTS W/L D D D D D D

TAS B D

MAC 

CLRMAC  O

LDMAC  S

STMAC  D

Logic
operations

Shift SHLL, SHLR B D D D D D D D
B/W/L*6 D D D D D D
B/W/L*7 D

Bit
manipu­lation

BAND, BIAND,

MULU, DIVU W/L S:4 SD

MULS, DIVS W/L S:4 SD

NEG B D D D D D D D

AND, OR, XOR

NOT B D D D D D D D

W/L D D D D D D

ROTL, ROTR
ROTXL, ROTXR

BSET, BCLR,
BNOT, BTST,
BSET/cc,
BCLR/cc

BOR, BIOR,
BXOR, BIXOR,
BLD, BILD, BST,
BIST, BSTZ,
BISTZ

B S D D D D D D

B D S S S S S S

B SD SD SD SD SD

W/L S SD SD SD SD SD SD

B D D D D D D D SHAL, SHAR

W/L D D D D D D

B D D D D

B D D D D

@ERn−/

Rn.W/

ERn.L)

@+ERn @aa:8

@aa:16/
@aa:32 

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Section 2 CPU

Addressing Mode

@−ERn/

@(d,

@ERn+/

RnL.B/
Classifi­cation Instruction Size #xx Rn @ERn @(d,ERn)

manipu­lation

Branch BRA/BS,

BSR/BS,

System
control

ANDC, ORC,

SLEEP  O

NOP  O

BFLD B D S S S Bit

BFST B S D D D

8

BRA/BC*

BSR/BC*
LDC (CCR, EXR) B/W*9 S S S S S*10 S

LDC (VBR, SBR) L S
STC (CCR, EXR) B/W*9 D D D D*11 D

STC (VBR, SBR) L D

XORC

8

B S S S

B S S S

B S

@ERn−/

Rn.W/

ERn.L)

@+ERn @aa:8

@aa:16/
@aa:32 

[Legend]
d: d:16 or d:32
S: Can be specified as a source operand.
D: Can be specified as a destination operand.
SD: Can be specified as either a source or destination operand or both.
S/D: Can be specified as either a source or destination operand.
S:4: 4-bit immediate data can be specified as a source operand.
Notes: 1. Only @aa:16 is available.

2. @ERn+ as a source operand and @−ERn as a destination operand

3. Specified by ER5 as a source address and ER6 as a destination address for data
transfer.

4. Size of data to be added with a displacement

5. Only @ERn− is available

6. When the number of bits to be shifted is 1, 2, 4, 8, or 16

7. When the number of bits to be shifted is specified by 5-bit immediate data or a general
register

8. Size of data to specify a branch condition

9. Byte when immediate or register direct, otherwise, word

10. Only @ERn+ is available

11. Only @−ERn is available

12. Not available in this LSI.

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Section 2 CPU

Table 2.2 Combinations of Instructions and Addressing Modes (2)

Addressing Mode

@(RnL.

B/Rn.W/
Classifi­cation

Branch BRA/BS,

Instruction Size @ERn @(d,PC)

 O

BRA/BC

BSR/BS,

 O

BSR/BC

Bcc  O

BRA  O O
BRA/S  O*

JMP  O O O O O

BSR  O

JSR  O O O O O

RTS, RTS/L  O

TRAPA  O System

control

RTE, RTE/L  O

[Legend]
d: d:8 or d:16
Note: * Only @(d:8, PC) is available.

ERn.L,

PC) @aa:24 @ aa:32 @@ aa:8 @@vec:7 

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Section 2 CPU

2.7.2 Table of Instructions Classified by Function

Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in
these tables is defined in table 2.3.

Table 2.3 Operation Notation

Operation Notation Description

Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
VBR Vector base register
SBR Short address base register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement

+ Addition

− Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical exclusive OR
→ Move
∼ Logical not (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

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Table 2.4 Data Transfer Instructions

Instruction Size Function

MOV B/W/L #IMM → (EAd), (EAs) → (EAd)

Transfers data between immediate data, general registers, and memory.

MOVFPE* B (EAs) → Rd
MOVTPE* B Rs → (EAs)

POP W/L @SP+ → Rn

Restores the data from the stack to a general register.

PUSH W/L Rn → @−SP

Saves general register contents on the stack.

LDM L @SP+ → Rn (register list)

Restores the data from the stack to multiple general registers. Two, three,
or four general registers which have serial register numbers can be
specified.

STM L Rn (register list) → @−SP

Saves the contents of multiple general registers on the stack. Two, three,
or four general registers which have serial register numbers can be
specified.

MOVA B/W EA → Rd

Zero-extends and shifts the contents of a specified general register or
memory data and adds them with a displacement. The result is stored in a
general register.

Note: * Not available in this LSI.

Section 2 CPU

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Section 2 CPU

Table 2.5 Block Transfer Instructions

Instruction Size Function

EEPMOV.B
EEPMOV.W

MOVMD.B B Transfers a data block.

MOVMD.W W Transfers a data block.

MOVMD.L L Transfers a data block.

MOVSD.B B Transfers a data block with zero data detection.

B Transfers a data block.

Transfers byte data which begins at a memory location specified by ER5
to a memory location specified by ER6. The number of byte data to be
transferred is specified by R4 or R4L.

Transfers byte data which begins at a memory location specified by ER5
to a memory location specified by ER6. The number of byte data to be
transferred is specified by R4.

Transfers word data which begins at a memory location specified by ER5
to a memory location specified by ER6. The number of word data to be
transferred is specified by R4.

Transfers longword data which begins at a memory location specified by
ER5 to a memory location specified by ER6. The number of longword
data to be transferred is specified by R4.

Transfers byte data which begins at a memory location specified by ER5
to a memory location specified by ER6. The number of byte data to be
transferred is specified by R4. When zero data is detected during transfer,
the transfer stops and execution branches to a specified address.

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Table 2.6 Arithmetic Operation Instructions

Instruction Size Function

ADD
SUB

ADDX
SUBX

INC
DEC

ADDS
SUBS

DAA
DAS

MULXU B/W Rd × Rs → Rd

MULU W/L Rd × Rs → Rd

MULU/U L Rd × Rs → Rd

MULXS B/W Rd × Rs → Rd

MULS W/L Rd × Rs → Rd

MULS/U L Rd × Rs → Rd

B/W/L (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd)

Performs addition or subtraction on data between immediate data,
general registers, and memory. Immediate byte data cannot be
subtracted from byte data in a general register.

B/W/L (EAd) ± #IMM ± C → (EAd), (EAd) ± (EAs) ± C → (EAd)

Performs addition or subtraction with carry on data between immediate
data, general registers, and memory. The addressing mode which
specifies a memory location can be specified as register indirect with
post-decrement or register indirect.

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a general register.

B Rd (decimal adjust) → Rd

Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 2-digit 4-bit BCD data.

Performs unsigned multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.

Performs unsigned multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.

Performs unsigned multiplication on data in two general registers (32 bits
× 32 bits → upper 32 bits).

Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.

Performs signed multiplication on data in two general registers: either 16
bits × 16 bits → 16 bits, or 32 bits × 32 bits → 32 bits.

Performs signed multiplication on data in two general registers (32 bits ×
32 bits → upper 32 bits).

Section 2 CPU

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Section 2 CPU

Instruction Size Function

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.

DIVU W/L Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16 bits
÷ 16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient.

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.

DIVS W/L Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷
16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient.

CMP B/W/L (EAd) − #IMM, (EAd) − (EAs)

Compares data between immediate data, general registers, and memory
and stores the result in CCR.

NEG B/W/L 0 − (EAd) → (EAd)

Takes the two's complement (arithmetic complement) of data in a general
register or the contents of a memory location.

EXTU W/L (EAd) (zero extension) → (EAd)

Performs zero-extension on the lower 8 or 16 bits of data in a general
register or memory to word or longword size.

The lower 8 bits to word or longword, or the lower 16 bits to longword can
be zero-extended.

EXTS W/L (EAd) (sign extension) → (EAd)

Performs sign-extension on the lower 8 or 16 bits of data in a general
register or memory to word or longword size.

The lower 8 bits to word or longword, or the lower 16 bits to longword can
be sign-extended.

TAS B @ERd − 0, 1 → (<bit 7> of @EAd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

MAC  (EAs) × (EAd) + MAC → MAC

Performs signed multiplication on memory contents and adds the result to
MAC.

CLRMAC  0 → MAC

Clears MAC to zero.

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Instruction Size Function

LDMAC  Rs → MAC

Loads data from a general register to MAC.

STMAC  MAC → Rd

Stores data from MAC to a general register.

Table 2.7 Logic Operation Instructions

Instruction Size Function

AND B/W/L (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd)

Performs a logical AND operation on data between immediate data,
general registers, and memory.

OR B/W/L (EAd) ∨ #IMM → (EAd), (EAd) ∨ (EAs) → (EAd)

Performs a logical OR operation on data between immediate data,
general registers, and memory.

XOR B/W/L (EAd) ⊕ #IMM → (EAd), (EAd) ⊕ (EAs) → (EAd)

Performs a logical exclusive OR operation on data between immediate
data, general registers, and memory.

NOT B/W/L ∼ (EAd) → (EAd)

Takes the one's complement of the contents of a general register or a
memory location.

Section 2 CPU

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Section 2 CPU

Table 2.8 Shift Operation Instructions

Instruction Size Function

SHLL

SHLR

SHAL

SHAR

ROTL

ROTR

ROTXL

ROTXR

B/W/L (EAd) (shift) → (EAd)

Performs a logical shift on the contents of a general register or a memory
location.

The contents of a general register or a memory location can be shifted by
1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by
any bits. In this case, the number of bits is specified by 5-bit immediate
data or the lower 5 bits of the contents of a general register.

B/W/L (EAd) (shift) → (EAd)

Performs an arithmetic shift on the contents of a general register or a
memory location.

1-bit or 2-bit shift is possible.

B/W/L (EAd) (rotate) → (EAd)

Rotates the contents of a general register or a memory location.

1-bit or 2-bit rotation is possible.

B/W/L (EAd) (rotate) → (EAd)

Rotates the contents of a general register or a memory location with the
carry bit.

1-bit or 2-bit rotation is possible.

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Table 2.9 Bit Manipulation Instructions

Instruction Size Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in the contents of a general register or a memory
location to 1. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.

BSET/cc B if cc, 1 → (<bit-No.> of <EAd>)

If the specified condition is satisfied, this instruction sets a specified bit in
a memory location to 1. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in the contents of a general register or a memory
location to 0. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.

BCLR/cc B if cc, 0 → (<bit-No.> of <EAd>)

If the specified condition is satisfied, this instruction clears a specified bit
in a memory location to 0. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.

BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in the contents of a general register or a memory
location. The bit number is specified by 3-bit immediate data or the lower
three bits of a general register.

BTST B ∼ (<bit-No.> of <EAd>) → Z

Tests a specified bit in the contents of a general register or a memory
location and sets or clears the Z flag accordingly. The bit number is
specified by 3-bit immediate data or the lower three bits of a general
register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in the contents of a general
register or a memory location and stores the result in the carry flag. The
bit number is specified by 3-bit immediate data.

BIAND B C ∧ [∼ (<bit-No.> of <EAd>)] → C

ANDs the carry flag with the inverse of a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in the contents of a general register
or a memory location and stores the result in the carry flag. The bit
number is specified by 3-bit immediate data.

Section 2 CPU

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Section 2 CPU

Instruction Size Function

BIOR B C ∨ [~ (<bit-No.> of <EAd>)] → C

ORs the carry flag with the inverse of a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.

BIXOR B C ⊕ [~ (<bit-No.> of <EAd>)] → C

Exclusive-ORs the carry flag with the inverse of a specified bit in the
contents of a general register or a memory location and stores the result
in the carry flag. The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in the contents of a general register or a memory
location to the carry flag. The bit number is specified by 3-bit immediate
data.

BILD B ~ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in the contents of a general
register or a memory location to the carry flag. The bit number is specified
by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in the contents of a
general register or a memory location. The bit number is specified by 3-bit
immediate data.

BSTZ B Z → (<bit-No.> of <EAd>)

Transfers the zero flag value to a specified bit in the contents of a
memory location. The bit number is specified by 3-bit immediate data.

BIST B ∼ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in the
contents of a general register or a memory location. The bit number is
specified by 3-bit immediate data.

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Section 2 CPU

Instruction Size Function

BISTZ B ∼ Z → (<bit-No.> of <EAd>)

Transfers the inverse of the zero flag value to a specified bit in the
contents of a memory location. The bit number is specified by 3-bit
immediate data.

BFLD B (EAs) (bit field) → Rd

Transfers a specified bit field in memory location contents to the lower bits
of a specified general register.

BFST B Rs → (EAd) (bit field)

Transfers the lower bits of a specified general register to a specified bit
field in memory location contents.

Table 2.10 Branch Instructions

Instruction Size Function

BRA/BS

BRA/BC

BSR/BS

BSR/BC

Bcc  Branches to a specified address if the specified condition is satisfied.

BRA/S  Branches unconditionally to a specified address after executing the next

JMP  Branches unconditionally to a specified address.

BSR  Branches to a subroutine at a specified address.

JSR  Branches to a subroutine at a specified address.

RTS  Returns from a subroutine.

RTS/L  Returns from a subroutine, restoring data from the stack to multiple

B Tests a specified bit in memory location contents. If the specified

condition is satisfied, execution branches to a specified address.

B Tests a specified bit in memory location contents. If the specified

condition is satisfied, execution branches to a subroutine at a specified
address.

instruction. The next instruction should be a 1-word instruction except for
the block transfer and branch instructions.

general registers.

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Section 2 CPU

Table 2.11 System Control Instructions

Instruction Size Function

TRAPA  Starts trap-instruction exception handling.

RTE  Returns from an exception-handling routine.

RTE/L  Returns from an exception-handling routine, restoring data from the stack

to multiple general registers.

SLEEP  Causes a transition to a power-down state.

LDC

STC

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

NOP  PC + 2 → PC

B/W #IMM → CCR, (EAs) → CCR, #IMM → EXR, (EAs) → EXR

Loads immediate data or the contents of a general register or a memory
location to CCR or EXR.

Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.

L Rs → VBR, Rs → SBR

Transfers the general register contents to VBR or SBR.

B/W CCR → (EAd), EXR → (EAd)

Transfers the contents of CCR or EXR to a general register or memory.

Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.

L VBR → Rd, SBR → Rd

Transfers the contents of VBR or SBR to a general register.

Logically ANDs the CCR or EXR contents with immediate data.

Logically ORs the CCR or EXR contents with immediate data.

Logically exclusive-ORs the CCR or EXR contents with immediate data.

Only increments the program counter.

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Section 2 CPU

2.7.3 Basic Instruction Formats

The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r fi el d), an effective address extension (EA field), and a
condition field (cc).

Figure 2.14 shows examples of instruction formats.

(1) Operation field only

op

(2) Operation field and register fields

op

(3) Operation field, register fields, and effective address extension

op

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16, etc

rn

rn rm

rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

Figure 2.14 Instruction Formats

• Operation Field
Indicates the function of the instruction, and specifies the addressing mode and operation to be

carried out on the operand. The operation field always includes the first four bits of the
instruction. Some instructions have two operation fields.

• Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or

4 bits. Some instructions have two register fi el ds. Some hav e no regist er fi el d.

• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition Field
Specifies the branch condition of Bcc instructions.

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Section 2 CPU

2.8 Addressing Modes and Effective Address Calculation

The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a
subset of these addressing modes.

Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.12 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)

4 Index register indirect with displacement @(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L)

@(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)

5 Register indirect with post-increment @ERn+

Register indirect with pre-decrement @−ERn

Register indirect with pre-increment @+ERn

Register indirect with post-decrement @ERn−

6 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

7 Immediate #xx:3/#xx:4/#xx:8/#xx:16/#xx:32

8 Program-counter relative @(d:8,PC)/@(d:16,PC)

9 Program-counter relative with index register @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)

10 Memory indirect @@aa:8

11 Extended memory indirect @@vec:7

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Section 2 CPU

2.8.1 Register Direct—Rn

The operand value is the contents of an 8-, 16-, or 32-bit general register whi ch is specified by the
register field in the instruction code.

R0H to R7H and R0L to R7L can be specified as 8-bit registers.

R0 to R7 and E0 to E7 can be specified as 16-bit registers.

ER0 to ER7 can be specified as 32-bit registers.

2.8.2 Register Indirect—@ERn

The operand value is the contents of the memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field of the instruction code.

In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).

2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn), or

@(d:32, ERn)

The operand value is the contents of a memory location which is pointed to by the sum of the
contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the
register field of the instruction code. The displacement is included in the instruction code and the
16-bit displacement is sign-extended when added to ERn.

This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the
displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the
operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data.

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Section 2 CPU

2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)

The operand value is the contents of a memory location which is pointed to by the sum of the
following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an
address register (RnL, Rn, ERn) specified by the register field in the instruction code are zero­extended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction
code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data,
ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4,
respectively.

2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,
or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn−

(1) Register indirect with post-increment—@ERn+

The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field of the instruction code. After the
memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is
stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for
longword access.

(2) Register indirect with pre-decrement—@−ERn

The operand value is the contents of a memory location which is pointed to by the fo llowing
operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn).
ERn is specified by the register field of the instruction code. After that, the operand value is stored
in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for
longword access.

(3) Register indirect with pre-increment—@+ERn

The operand value is the contents of a memory location which is pointed to by the fo llowing
operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn is
specified by the register field of the instruction code. After that, the operand value is stored in the
address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.

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Section 2 CPU

(4) Register indirect with post-decrement—@ERn−

The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field of the instruction code. After the
memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the
remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for word
access, or 4 for longword access.

If the contents of a general register which is also used as an address register is written to memory
using this addressing mode, data to be written is the contents of the general register after
calculating an effective address. If the same general register is specified in an instruction and two
effective addresses are calculated, the contents of the general register after the first calculation of
an effective address is used in the second calculation of an effective address.

Example 1:

MOV.W R0, @ER0+

When ER0 before execution is H'12345678, H'567A is written at H'12345678.

Example 2:

MOV.B @ER0+, @ER0+

When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at
H'00001001.

After execution, ER0 is H'00001002.

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2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32

The operand value is the contents of a memory location which is pointed to by an ab solute address
included in the instruction code.

There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute
addresses.

To access the data area, the absolute address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specif ied by SBR. For a 16­bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the
entire address space.

To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used.
For a 24-bit absolute address, the upper 8 bits are all assumed to be 0 (H'00).

Table 2.13 shows the accessible absolute address ranges.

Table 2.13 Absolute Address Access Ranges

Absolute
Address

Data area 8 bits

(@aa:8)

16 bits

(@aa:16)

32 bits

(@aa:32)

Program area 24 bits

(@aa:24)

32 bits

(@aa:32)

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Normal
Mode

A consecutive 256-byte area (the upper address is set in SBR)

H'0000 to
H'FFFF

H'000000 to

H'00000000 to

Middle
Mode

H'000000 to
H'007FFF,

H'FF8000 to
H'FFFFFF

H'FFFFFF

Advanced
Mode

H'00000000 to H'00007FFF,

H'FFFF8000 to H'FFFFFFFF

H'00000000 to H'FFFFFFFF

H'00000000 to H'00FFFFFF

H'00FFFFFF

Maximum
Mode

H'00000000 to
H'FFFFFFFF

Section 2 CPU

2.8.7 Immediate—#xx

The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the
instruction code.

This addressing mode has short formats in which 3- or 4-bit immediate data can be used.

When the size of immediate data is less than that of the destination operand value (byte, word, or
longword) the immediate data is zero-extended.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit
number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code,
for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction
code, for specifying a vector address.

2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC):

This mode is used in the Bcc and BSR instructions. The opera n d value is a 32-bit branch ad dress,
which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of
the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC
contents. The PC contents to which the displacement is added is the address of the first byte of the
next instruction, so the possible branching range is −126 to +128 bytes (−63 to +64 words) or

−32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting
value should be an even number. In advanced mode, only the lower 24 bits of this branch address
are valid; the upper 8 bits are all assumed to be 0 (H'00).

2.8.9 Program-Counter Relative with Index Register—
@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC)

This mode is used in the Bcc and BSR instructions. The opera n d value is a 32-bit branch ad dress,
which is the sum of the following operation result and the 32-bit address of the PC contents: the
contents of an address register specified by the register field in the instruction code (RnL, Rn, or
ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is
the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of
this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).

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2.8.10 Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The operand value is a branch address,
which is the contents of a memory location pointed to by an 8-bit absolute address in the
instruction code.

The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes).

In normal mode, the memory location is pointed to by word-size data and the branch address is 16
bits long. In other modes, the memory location is pointed to by longword-size data. In middle or
advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).

Note that the top part of the address range is also used as the exception handling vector area. A
vector address of an exception handling other than a reset or a CPU address error can be changed
by VBR.

Figure 2.15 shows an example of specification of a br anch address using this addressing mode.

Specified
by @aa:8

Branch address

(a) Normal Mode (b) Advanced Mode

Specified
by @aa:8

Figure 2.15 Branch Address Specification in Memory Indirect Mode

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Reserved

Branch address

Section 2 CPU

2.8.11 Extended Memory Indirect—@@vec:7

This mode can be used by the JMP and JSR instructions. The operand value is a branch address,
which is the contents of a memory location pointed to by the following operation result: the sum
of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4.

The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to
H'0003FF in other modes. In assembler notation, an address to store a branch address is specified.

In normal mode, the memory location is pointed to by word-size data and the branch address is 16
bits long. In other modes, the memory location is pointed to by longword-size data. In middle or
advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).

2.8.12 Effective Address Calculation

Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The
lower bits of the effective address are valid and the upper bit s are ign ore d (zero extended or sign
extended) according to the CPU operating mode.

The valid bits in middle mode are as follows:

• The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for

the transfer and operation instructions.

• The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended

for the branch instructions.

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Table 2.14 Effective Address Calculation for Transfer and Operation Instructions

No.

Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1

Immediate

IMM

Register direct

2

opoprm rn

Register indirect

3

op

r

4

Register indirect with 16-bit displacement

r

op

disp

Register indirect with 32-bit displacement

op

r

disp

31 0 31 0

General register contents

31 0

General register contents

31 15

Sign extension

31 0

General register contents

disp

disp

31 0

+

0

31 0

+

5

Index register indirect with 16-bit displacement

r

op

disp

Index register indirect with 32-bit displacement

r

op

Register indirect with post-increment or post-decrement

6

op

Register indirect with pre-increment or pre-decrement

op

8-bit absolute address

7

op

16-bit absolute address

32-bit absolute address

disp

r

r

aa

op

aa

op

aa

31 0

Zero extension
Contents of general register
(RL, R, or ER)

31 15

Sign extension

31 0

Zero extension
Contents of general register
(RL, R, or ER)

31

31

31

31 07

31 15

Sign extension

31

disp

General register contents

General register contents

SBR

aa

1, 2, or 4

disp

1, 2, or 4

1, 2, or 4

1, 2, or 4

aa

aa

×

31 0

+

0

×

31 0

0

+

0

31 0

±

0

31 0

±

31 0

31 0

0

0

31 0

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