Renesas H8S/2437 Hardware Manual

16

H8S/2437

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family / H8S / 2600 Series

H8S/2437 HD64F2437

Group

Rev.1.00

2003.9.19

Rev.1.00, 09/03, page ii of xxxviii

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs,
algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corp. without notice due to
product improvements or other reasons. It is therefore recommended that customers contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for
the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various
means, including the Renesas Technology Corp. Semiconductor home page
(http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on th e applicability of the information and products.
Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss
resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at stake.
Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product
distributor when considering the use of a product contained herein for any specific purposes,
such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or
undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported into a
country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev.1.00, 09/03, page iii of xxxviii

General Precautions on Handling of Product

1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is conn ected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.

Rev.1.00, 09/03, page iv of xxxviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev.1.00, 09/03, page v of xxxviii

Preface

This LSI is a microcomputer (MCU) made up of the H8S/2600 CPU with Renesas Technology­original architecture as its core, and the peripheral functions required to configure a system.

The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a
16-Mbyte linear address space. The instruction set of the H8S/2600 CPU maintains upward
compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition
from the H8/300, H8/300L, or H8/300H to the H8S/2600 CPU.

This LSI is equipped with the flash memory, RAM, two kinds of PWM timers (PWM and
PWMX), a 16-bit free-running timer (FRT), an 8-bit tim er ( TMR), a 16-bit timer pulse unit (TPU),
a watchdog timer (WDT), a timer connection, a serial communication interface (SCI), an I
interface 3 (IIC3), an A/D converter, and I/O ports as on-chip peripheral modules required for
system configuration.

TM

A flash memory (F-ZTAT

*) version is available for this LSI’s 256-kbyte ROM. The CPU and
the flash memory are connected to a 16-bit bus, enabling byte data and word data to be accessed in
a single state. This improves the instruction fetch and process speeds.

TM

Note: * F-ZTAT

is a trademark of Renesas Technology Corp.

Target Users: This manual was written for users who use th is LSI in the design of application

systems. Target users are expected to understand the fundamentals of electrical
circuits, logic circuits, and microcomputers.

2

C bus

Objective: This manual was written to explain the hardware functions and electrical

characteristics of this LSI to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.

Notes on Reading this Manual:

• In order to understand the overall functions of the chip

Read this manual in the order of the table of contents. This manual can be roughly categorized
into the descriptions on the CPU, system control functions, peripheral functions, and electrical
characteristics.

Rev.1.00, 09/03, page vi of xxxviii

• In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

• In order to understand the detailed function of a register whose name is known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 23,
List of Registers.

Rules: Register name: The following notation is used for cases when the same or a

similar function, e.g., serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel

number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B’xxxx, hexadecimal is H’xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/

H8S/2437 Group manuals:

Document Title Document No.

H8S/2437 Group Hardware Manual This manual
H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

User's manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual

H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-282
H8S, H8/300 Series High-performance Embedded Workshop, High-

performance Debugging Interface Tutorial
High-performance Embedded Workshop User's Manual ADE-702-201

Rev.1.00, 09/03, page vii of xxxviii

ADE-702-247

ADE-702-231

Rev.1.00, 09/03, page viii of xxxviii

Contents

Section 1 Overview........................................................................................... 1

1.1 Features.............................................................................................................................1

1.2 Internal Block Diagram.....................................................................................................2

1.3 Pin Description..................................................................................................................3

1.3.1 Pin Assignment....................................................................................................3

1.3.2 Pin Assignment in Each Operating Mode............................................................4

1.3.3 Pin Functions .......................................................................................................9

Section 2 CPU................................................................................................... 15

2.1 Features.............................................................................................................................15

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU..................................16

2.1.2 Differences from H8/300 CPU.............................................................................17

2.1.3 Differences from H8/300H CPU..........................................................................17

2.2 CPU Operating Modes......................................................................................................18

2.2.1 Normal Mode.......................................................................................................18

2.2.2 Advanced Mode...................................................................................................20

2.3 Address Space...................................................................................................................22

2.4 Registers............................................................................................................................23

2.4.1 General Registers.................................................................................................24

2.4.2 Program Counter (PC) .........................................................................................25

2.4.3 Extended Register (EXR)..................................................................................... 25

2.4.4 Condition-Code Register (CCR)..........................................................................26

2.4.5 Multiply-Accumulate Register (MAC)................................................................27

2.4.6 Initial Values of CPU Internal Registers..............................................................27

2.5 Data Formats.....................................................................................................................28

2.5.1 General Register Data Formats............................................................................28

2.5.2 Memory Data Formats.........................................................................................30

2.6 Instruction Set...................................................................................................................31

2.6.1 Table of Instructions Classified by Function.......................................................32

2.6.2 Basic Instruction Formats....................................................................................41

2.7 Addressing Modes and Effective Address Calculation.....................................................43

2.7.1 Register Direct—Rn.............................................................................................43

2.7.2 Register Indirect—@ERn....................................................................................43

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)..............43

2.7.4 Register Indirect with Post-Increment or Pre-Decrement

—@ERn+ or @-ERn...........................................................................................44

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................44

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32.................................................................45

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................45

Rev.1.00, 09/03, page ix of xxxviii

2.7.8 Memory Indirect—@@aa:8 ................................................................................45

2.7.9 Effective Address Calculation .............................................................................46

2.8 Processing States...............................................................................................................49

2.9 Usage Note........................................................................................................................50

2.9.1 Usage Notes on Bit-Wise Operation Instructions................................................50

Section 3 MCU Operating Modes.....................................................................51

3.1 Operating Mode Selection ................................................................................................51

3.2 Register Descriptions........................................................................................................52

3.2.1 Mode Control Register (MDCR).........................................................................52

3.2.2 System Control Register (SYSCR)......................................................................53

3.3 Operating Mode Descriptions ...........................................................................................54

3.3.1 Mode 7.................................................................................................................54

3.3.2 Pin Functions .......................................................................................................55

3.4 Memory Map ....................................................................................................................56

Section 4 Exception Handling...........................................................................57

4.1 Exception Handling Types and Priority............................................................................57

4.2 Exception Sources and Exception Vector Table............................................................... 58

4.3 Reset .................................................................................................................................59

4.3.1 Reset exception handling.....................................................................................59

4.3.2 Interrupts after Reset............................................................................................60

4.3.3 On-Chip Peripheral Functions after Reset Release..............................................60

4.4 Traces................................................................................................................................61

4.5 Interrupts...........................................................................................................................61

4.6 Trap Instruction.................................................................................................................62

4.7 Stack Status after Exception Handling..............................................................................63

4.8 Usage Note........................................................................................................................64

Section 5 Interrupt Controller............................................................................65

5.1 Features.............................................................................................................................65

5.2 Input/Output Pins..............................................................................................................67

5.3 Register Descriptions........................................................................................................67

5.3.1 Interrupt Control Register (INTCR) ....................................................................68

5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................69

5.3.3 IRQ Enable Register (IER)..................................................................................71

5.3.4 IRQ Sense Control Registers (ISCR)...................................................................72

5.3.5 IRQ Status Register (ISR)....................................................................................74

5.3.6 Software Standby Release IRQ Enable Register (SSIER)...................................75

5.4 Interrupt Sources...............................................................................................................75

5.4.1 External Interrupt Sources...................................................................................75

5.4.2 Internal Interrupts ................................................................................................76

5.5 Interrupt Exception Handling Vector Table......................................................................76

Rev.1.00, 09/03, page x of xxxviii

5.6 Interrupt Control Modes and Interrupt Operation.............................................................81

5.6.1 Interrupt Control Mode 0.....................................................................................81

5.6.2 Interrupt Control Mode 2.....................................................................................83

5.6.3 Interrupt Exception Handling Sequence..............................................................85

5.6.4 Interrupt Response Times....................................................................................87

5.7 Usage Notes......................................................................................................................88

5.7.1 Contention between Interrupt Generation and Disabling.....................................88

5.7.2 Instructions that Disable Interrupts......................................................................89

5.7.3 Times when Interrupts are Disabled ....................................................................89

5.7.4 Interrupts during Execution of EEPMOV Instruction..........................................89

5.7.5 IRQ Pin Select......................................................................................................89

5.7.6 Note on IRQ Status Register (ISR)......................................................................90

Section 6 Bus Controller (BSC)........................................................................ 91

6.1 Features.............................................................................................................................91

6.2 Input/Output Pins..............................................................................................................93

6.3 Register Descriptions........................................................................................................94

6.3.1 Bus Control Register (BCR)................................................................................94

6.3.2 Area Control Register (BCRA)............................................................................95

6.4 Bus Control.......................................................................................................................97

6.4.1 Bus Specifications................................................................................................97

6.4.2 External Address Area.........................................................................................100

6.4.3 Chip Select Signals..............................................................................................100

6.4.4 Address Strobe/Hold Signal.................................................................................101

6.4.5 Address Output....................................................................................................101

6.5 Bus Interface.....................................................................................................................102

6.5.1 Data Size and Data Alignment.............................................................................102

6.5.2 Valid Strobes........................................................................................................104

6.5.3 Basic Operation Timing in Normal Extended Mode............................................105

6.5.4 Basic Operation Timing in Multiplex Extended Mode........................................113

6.5.5 Wait Control ........................................................................................................125

6.6 Idle Cycle..........................................................................................................................128

Section 7 I/O Ports............................................................................................ 131

7.1 Port 0.................................................................................................................................137

7.1.1 Port 0 Register (PORT0)......................................................................................137

7.1.2 Pin Functions .......................................................................................................137

7.2 Port 1.................................................................................................................................139

7.2.1 Port 1 Data Direction Register (P1DDR).............................................................139

7.2.2 Port 1 Data Register (P1DR)................................................................................140

7.2.3 Port 1 Register (PORT1)......................................................................................140

7.2.4 Port 1 Pull-Up MOS Control Register (P1PCR)..................................................141

7.2.5 Pin Functions .......................................................................................................141

Rev.1.00, 09/03, page xi of xxxviii

7.2.6 Port 1 Input Pull-Up MOS States.........................................................................142

7.3 Port 2.................................................................................................................................143

7.3.1 Port 2 Data Direction Register (P2DDR).............................................................143

7.3.2 Port 2 Data Register (P2DR)................................................................................144

7.3.3 Port 2 Register (PORT2)......................................................................................144

7.3.4 Port 2 Pull-Up MOS Control Register (P2PCR)..................................................145

7.3.5 Pin Functions.......................................................................................................145

7.3.6 Port 2 Input Pull-Up MOS States.........................................................................154

7.4 Port 3.................................................................................................................................155

7.4.1 Port 3 Data Direction Register (P3DDR).............................................................155

7.4.2 Port 3 Data Register (P3DR)................................................................................156

7.4.3 Port 3 Register (PORT3)......................................................................................156

7.4.4 Port 3 Pull-Up MOS Control Register (P3PCR)..................................................157

7.4.5 Pin Functions.......................................................................................................157

7.4.6 Port 3 Input Pull-Up MOS States.........................................................................161

7.5 Port 4.................................................................................................................................162

7.5.1 Port 4 Data Direction Register (P4DDR).............................................................162

7.5.2 Port 4 Data Register (P4DR)................................................................................163

7.5.3 Port 4 Register (PORT4)......................................................................................163

7.5.4 Pin Functions.......................................................................................................164

7.6 Port 5.................................................................................................................................168

7.6.1 Port 5 Data Direction Register (P5DDR).............................................................168

7.6.2 Port 5 Data Register (P5DR)................................................................................169

7.6.3 Port 5 Register (PORT5)......................................................................................169

7.6.4 Pin Functions.......................................................................................................170

7.7 Port 6.................................................................................................................................173

7.7.1 Port 6 Data Direction Register (P6DDR).............................................................173

7.7.2 Port 6 Data Register (P6DR)................................................................................174

7.7.3 Port 6 Register (PORT6)......................................................................................174

7.7.4 Port 6 Pull-Up MOS Control Register (P6PCR)..................................................175

7.7.5 Port 6 Open-Drain Control Register (P6ODR)....................................................175

7.7.6 Pin Functions.......................................................................................................175

7.7.7 Port 6 Input Pull-Up MOS States.........................................................................181

7.8 Port 7.................................................................................................................................181

7.8.1 Port 7 Register (PORT7)......................................................................................181

7.8.2 Pin Functions.......................................................................................................182

7.9 Port 8.................................................................................................................................183

7.9.1 Port 8 Data Direction Register (P8DDR).............................................................183

7.9.2 Port 8 Data Register (P8DR)................................................................................184

7.9.3 Port 8 Register (PORT8)......................................................................................184

7.9.4 Pin Functions.......................................................................................................185

7.10 Port 9.................................................................................................................................189

7.10.1 Port 9 Data Direction Register (P9DDR).............................................................189

Rev.1.00, 09/03, page xii of xxxviii

7.10.2 Port 9 Data Register (P9DR)................................................................................190

7.10.3 Port 9 Register (PORT9)......................................................................................190

7.10.4 Port Function Control Register (PFCR)...............................................................191

7.10.5 Pin Functions .......................................................................................................192

7.11 Port A................................................................................................................................198

7.11.1 Port A Data Direction Register (PADDR)...........................................................198

7.11.2 Port A Data Register (PADR)..............................................................................199

7.11.3 Port A Register (PORTA)....................................................................................199

7.11.4 Pin Functions .......................................................................................................200

7.12 Port B................................................................................................................................205

7.12.1 Port B Data Direction Register (PBDDR)............................................................205

7.12.2 Port B Data Register (PBDR)..............................................................................206

7.12.3 Port B Register (PORTB) ....................................................................................206

7.12.4 Pin Functions .......................................................................................................207

7.13 Port C................................................................................................................................210

7.13.1 Port C Data Direction Register (PCDDR)............................................................210

7.13.2 Port C Data Register (PCDR)..............................................................................210

7.13.3 Port C Register (PORTC) ....................................................................................211

7.13.4 Pin Functions .......................................................................................................211

7.14 Change of Peripheral Function Pins..................................................................................214

7.14.1 Port Control Register 0 (PTCNT0)......................................................................214

7.14.2 Port Control Register 1 (PTCNT1)......................................................................215

7.14.3 Port Control Register 2 (PTCNT2)......................................................................216

Section 8 8-Bit PWM Timer (PWM)................................................................ 217

8.1 Features.............................................................................................................................217

8.2 Input/Output Pin................................................................................................................218

8.3 Register Descriptions........................................................................................................218

8.3.1 PWM Register Select (PWSL).............................................................................219

8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWDR0)..............................................220

8.3.3 PWM Data Polarity Register (PWDPR)..............................................................221

8.3.4 PWM Output Enable Register (PWOER)............................................................221

8.3.5 Peripheral Clock Select Register (PCSR) ............................................................222

8.4 Operation...........................................................................................................................223

Section 9 14-Bit PWM Timer (PWMX)........................................................... 225

9.1 Features.............................................................................................................................225

9.2 Input/Output Pins..............................................................................................................226

9.3 Register Descriptions........................................................................................................226

9.3.1 PWMX (D/A) Counters H and L (DACNTH and DACNTL).............................227

9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB).........................228

9.3.3 PWMX (D/A) Control Register (DACR).............................................................230

9.3.4 Peripheral Clock Select Register (PCSR) ............................................................231

Rev.1.00, 09/03, page xiii of xxxviii

9.4 Bus Master Interface.........................................................................................................231

9.5 Operation ..........................................................................................................................233

Section 10 16-Bit Free-Running Timer (FRT)..................................................239

10.1 Features.............................................................................................................................239

10.2 Input/Output Pins..............................................................................................................241

10.3 Register Descriptions........................................................................................................241

10.3.1 Free-Running Counter (FRC).............................................................................. 242

10.3.2 Output Compare Registers A and B (OCRA and OCRB) ...................................242

10.3.3 Input Capture Registers A to D (ICRA to ICRD)................................................242

10.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) .........................243

10.3.5 Output Compare Register DM (OCRDM)...........................................................243

10.3.6 Timer Interrupt Enable Register (TIER)..............................................................244

10.3.7 Timer Control/Status Register (TCSR)................................................................245

10.3.8 Timer Control Register (TCR).............................................................................248

10.3.9 Timer Output Compare Control Register (TOCR) ..............................................249

10.4 Operation ..........................................................................................................................251

10.4.1 Pulse Output.........................................................................................................251

10.5 Operation Timing..............................................................................................................252

10.5.1 FRC Increment Timing........................................................................................252

10.5.2 Output Compare Output Timing..........................................................................253

10.5.3 FRC Clear Timing ...............................................................................................253

10.5.4 Input Capture Input Timing.................................................................................254

10.5.5 Buffered Input Capture Input Timing..................................................................255

10.5.6 Timing of Input Capture Flag Setting..................................................................256

10.5.7 Timing of Output Compare Flag Setting .............................................................257

10.5.8 Timing of Overflow Flag Setting.........................................................................257

10.5.9 Automatic Addition Timing.................................................................................258

10.5.10 Mask Signal Generation Timing..........................................................................258

10.6 Interrupt Sources...............................................................................................................260

10.7 Usage Notes...................................................................................................................... 261

10.7.1 Conflict between FRC Write and Clear...............................................................261

10.7.2 Conflict between FRC Write and Increment........................................................262

10.7.3 Conflict between OCR Write and Compare-Match............................................. 263

10.7.4 Switching of Internal Clock and FRC Operation.................................................264

Section 11 8-Bit Timer (TMR)..........................................................................267

11.1 Features.............................................................................................................................267

11.2 Input/Output Pins..............................................................................................................270

11.3 Register Descriptions........................................................................................................271

11.3.1 Timer Counter (TCNT)........................................................................................273

11.3.2 Time Constant Register A (TCORA)...................................................................273

11.3.3 Time Constant Register B (TCORB)...................................................................273

Rev.1.00, 09/03, page xiv of xxxviii

11.3.4 Timer Control Register (TCR).............................................................................274

11.3.5 Timer Control/Status Register (TCSR)................................................................277

11.3.6 Input Capture Register (TICR)............................................................................282

11.3.7 Time Constant Register (TCORC).......................................................................282

11.3.8 Input Capture Registers R and F (TICRR and TICRF)........................................282

11.3.9 Timer Input Select Register (TISR).....................................................................283

11.4 Operation...........................................................................................................................283

11.4.1 Pulse Output.........................................................................................................283

11.5 Operation Timing..............................................................................................................284

11.5.1 TCNT Count Timing............................................................................................284

11.5.2 Timing of CMFA and CMFB Setting at Compare-Match...................................285

11.5.3 Timing of Timer Output at Compare-Match........................................................285

11.5.4 Timing of Counter Clear at Compare-Match.......................................................286

11.5.5 TCNT External Reset Timing..............................................................................286

11.5.6 Timing of Overflow Flag (OVF) Setting.............................................................286

11.6 TMR0 and TMR1 Cascaded Connection..........................................................................287

11.6.1 16-Bit Count Mode..............................................................................................287

11.6.2 Compare-Match Count Mode..............................................................................288

11.7 TMRY and TMRX Cascaded Connection........................................................................288

11.7.1 16-Bit Count Mode..............................................................................................288

11.7.2 Compare-Match Count Mode..............................................................................289

11.7.3 Input Capture Operation.......................................................................................289

11.8 Interrupt Sources...............................................................................................................291

11.9 Usage Notes......................................................................................................................292

11.9.1 Conflict between TCNT Write and Clear............................................................292

11.9.2 Conflict between TCNT Write and Increment.....................................................293

11.9.3 Conflict between TCOR Write and Compare-Match...........................................294

11.9.4 Conflict between Compare-Matches A and B......................................................294

11.9.5 Switching of Internal Clocks and TCNT Operation.............................................295

11.9.6 Mode Setting with Cascaded Connection ............................................................297

Section 12 16-Bit Timer Pulse Unit (TPU)....................................................... 299

12.1 Features.............................................................................................................................299

12.2 Input/Output Pins..............................................................................................................303

12.3 Register Descriptions........................................................................................................304

12.3.1 Timer Control Register (TCR).............................................................................305

12.3.2 Timer Mode Register (TMDR)............................................................................308

12.3.3 Timer I/O Control Register (TIOR).....................................................................310

12.3.4 Timer Interrupt Enable Register (TIER)..............................................................319

12.3.5 Timer Status Register (TSR)................................................................................320

12.3.6 Timer Counter (TCNT)........................................................................................323

12.3.7 Timer General Register (TGR)............................................................................323

12.3.8 Timer Start Register (TSTR)................................................................................323

Rev.1.00, 09/03, page xv of xxxviii

12.3.9 Timer Synchro Register (TSYR).........................................................................324

12.4 Interface to Bus Master.....................................................................................................325

12.4.1 16-Bit Registers...................................................................................................325

12.4.2 8-Bit Registers.....................................................................................................325

12.5 Operation ..........................................................................................................................327

12.5.1 Basic Functions....................................................................................................327

12.5.2 Synchronous Operation........................................................................................332

12.5.3 Buffer Operation..................................................................................................334

12.5.4 Cascaded Operation.............................................................................................337

12.5.5 PWM Modes........................................................................................................338

12.5.6 Phase Counting Mode .......................................................................................... 343

12.6 Interrupt Sources...............................................................................................................348

12.6.1 Interrupt Source and Priority...............................................................................348

12.6.2 A/D Converter Activation....................................................................................349

12.7 Operation Timing..............................................................................................................350

12.7.1 Input/Output Timing............................................................................................350

12.7.2 Interrupt Signal Timing........................................................................................ 354

12.8 Usage Notes...................................................................................................................... 357

Section 13 Timer Connection............................................................................365

13.1 Features.............................................................................................................................365

13.2 Input/Output Pins..............................................................................................................368

13.3 Register Descriptions........................................................................................................369

13.3.1 Timer Connection Register I (TCONRI) .............................................................369

13.3.2 Timer Connection Register O (TCONRO) ..........................................................372

13.3.3 Timer Connection Register S (TCONRS)............................................................375

13.3.4 Edge Sense Register (SEDGR)............................................................................ 377

13.3.5 Timer Extended Control Register (TECR) .......................................................... 379

13.4 Operation ..........................................................................................................................380

13.4.1 PWM Decoding (PDC Signal Generation)..........................................................380

13.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation).....................382

13.4.3 Measurement of 8-Bit Timer Divided Waveform Period ....................................385

13.4.4 2fH Modification of IHI Signal...........................................................................387

13.4.5 IVI Signal Fall Modification and IHI Synchronization .......................................389

13.4.6 Internal Synchronization Signal Generation

(IHG/IVG/CL4 Signal Generation).....................................................................391

13.4.7 HSYNCO Output.................................................................................................396

13.4.8 VSYNCO Output.................................................................................................397

13.4.9 CBLANK Output.................................................................................................398

Rev.1.00, 09/03, page xvi of xxxviii

Section 14 Duty Measurement Circuit.............................................................. 399

14.1 Features.............................................................................................................................399

14.2 Input/Output Pins..............................................................................................................401

14.3 Register Descriptions........................................................................................................402

14.3.1 Free-Running Counter (TWCNT)........................................................................402

14.3.2 Input Capture Register (TWICR).........................................................................402

14.3.3 Duty Measurement Control Register 1 (TWCR1) ...............................................403

14.3.4 Duty Measurement Control Register 2 (TWCR2) ...............................................404

14.4 Operation...........................................................................................................................406

14.4.1 Duty Measurement for External Event Signal .....................................................406

14.5 Operation Timing..............................................................................................................407

14.5.1 TWCNT Count Timing........................................................................................407

14.5.2 TWCNT Clear Timing by Setting START Bit ....................................................407

14.5.3 Count Start Timing for Duty Measurement .........................................................408

14.5.4 Capture Timing during Duty Measurement.........................................................408

14.5.5 Clear Timing for START Bit when Duty Measurement Ends.............................409

14.5.6 Set Timing for Duty Measurement End Flag (ENDF).........................................409

14.5.7 Set Timing for Overflow Flag (OVF)..................................................................410

14.6 Interrupt Sources...............................................................................................................410

14.7 Usage Notes......................................................................................................................411

14.7.1 Conflict between TWCNT Write and Increment.................................................411

14.7.2 Write to START Bit during Free-Running Counter Operation............................411

14.7.3 Switching of Internal Clock and TWCNT Operation ..........................................412

14.7.4 Switching of External Event Signal and Operation of Edge Detection Circuit....414

Section 15 Watchdog Timer (WDT)................................................................. 417

15.1 Features.............................................................................................................................417

15.2 Register Descriptions........................................................................................................418

15.2.1 Timer Counter (TCNT)........................................................................................418

15.2.2 Timer Control/Status Register (TCSR)................................................................418

15.3 Operation...........................................................................................................................420

15.3.1 Watchdog Timer Mode........................................................................................420

15.3.2 Interval Timer Mode............................................................................................421

15.3.3 Internal Reset Signal Generation Timing............................................................. 422

15.4 Interrupt Sources...............................................................................................................422

15.5 Usage Notes......................................................................................................................423

15.5.1 Notes on Register Access.....................................................................................423

15.5.2 Conflict between Timer Counter (TCNT) Write and Increment..........................424

15.5.3 Changing Values of CKS2 to CKS0 Bits.............................................................424

15.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................424

Rev.1.00, 09/03, page xvii of xxxviii

Section 16 Serial Communication Interface (SCI)............................................425

16.1 Features.............................................................................................................................425

16.2 Input/Output Pins..............................................................................................................427

16.3 Register Descriptions........................................................................................................428

16.3.1 Receive Shift Register (RSR) ..............................................................................428

16.3.2 Receive Data Register (RDR)..............................................................................428

16.3.3 Transmit Data Register (TDR).............................................................................428

16.3.4 Transmit Shift Register (TSR).............................................................................429

16.3.5 Serial Mode Register (SMR) ...............................................................................429

16.3.6 Serial Control Register (SCR)..............................................................................431

16.3.7 Serial Status Register (SSR)................................................................................433

16.3.8 Serial Interface Mode Register (SCMR)..............................................................435

16.3.9 Bit Rate Register (BRR)......................................................................................436

16.4 Operation in Asynchronous Mode....................................................................................442

16.4.1 Data Transfer Format...........................................................................................443

16.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous

Mode....................................................................................................................444

16.4.3 Clock....................................................................................................................445

16.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 446

16.4.5 Serial Data Transmission (Asynchronous Mode)................................................447

16.4.6 Serial Data Reception (Asynchronous Mode)......................................................449

16.5 Multiprocessor Communication Function.........................................................................453

16.5.1 Multiprocessor Serial Data Transmission............................................................455

16.5.2 Multiprocessor Serial Data Reception .................................................................456

16.6 Operation in Clocked Synchronous Mode........................................................................459

16.6.1 Clock....................................................................................................................459

16.6.2 SCI Initialization (Clocked Synchronous Mode).................................................459

16.6.3 Serial Data Transmission (Clocked Synchronous Mode)....................................460

16.6.4 Serial Data Reception (Clocked Synchronous Mode)..........................................463

16.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode).............................................................................465

16.7 Interrupt Sources...............................................................................................................467

16.8 Usage Notes...................................................................................................................... 469

16.8.1 Module Stop Mode Setting.................................................................................. 469

16.8.2 Break Detection and Processing..........................................................................469

16.8.3 Mark State and Break Sending............................................................................. 469

16.8.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only)....................................................................469

16.8.5 Relation between Writing to TDR and TDRE Flag.............................................469

16.8.6 SCI Operations during Mode Transitions............................................................470

16.8.7 Switching from SCK Pins to Port Pins ................................................................473

Rev.1.00, 09/03, page xviii of xxxviii

Section 17 I2C Bus Interface 3 (IIC3)............................................................... 475

17.1 Features.............................................................................................................................475

17.2 Input/Output Pins..............................................................................................................478

17.3 Register Descriptions........................................................................................................478

17.3.1 I

17.3.2 I

17.3.3 I

17.3.4 I

17.3.5 I

17.3.6 Slave Address Register (SAR).............................................................................487

17.3.7 Slave Address Register A (SARA)......................................................................487

17.3.8 Slave Address Register B (SARB).......................................................................488

17.3.9 Slave Address Mask Register (SAMR)................................................................ 488

17.3.10 I

17.3.11 I

17.3.12 I

17.3.13 I

17.4 Operation...........................................................................................................................491

17.4.1 I

17.4.2 Master Transmit Operation..................................................................................492

17.4.3 Master Receive Operation....................................................................................494

17.4.4 Slave Transmit Operation....................................................................................496

17.4.5 Slave Receive Operation......................................................................................498

17.4.6 Noise Canceler.....................................................................................................500

17.4.7 Example of Use....................................................................................................500

17.5 Interrupt Requests.............................................................................................................505

17.6 Bit Synchronous Circuit....................................................................................................506

2

C Bus Control Register A (ICCRA) ..................................................................479

2

C Bus Control Register B (ICCRB)...................................................................480

2

C Bus Mode Register (ICMR)...........................................................................482

2

C Bus Interrupt Enable Register (ICIER)..........................................................483

2

C Bus Status Register (ICSR)............................................................................485

2

C Bus Status Register A (ICSRA).....................................................................489

2

C Bus Transmit Data Register (ICDRT)............................................................ 489

2

C Bus Receive Data Register (ICDRR).............................................................489

2

C Bus Shift Register (ICDRS)...........................................................................490

2

C Bus Format.....................................................................................................491

Section 18 A/D Converter................................................................................. 507

18.1 Features.............................................................................................................................507

18.2 Input/Output Pins..............................................................................................................509

18.3 Register Descriptions........................................................................................................510

18.3.1 A/D Data Registers A to H (ADDRA to ADDRH)..............................................510

18.3.2 A/D Control/Status Register (ADCSR) ...............................................................511

18.3.3 A/D Control Register (ADCR) ............................................................................513

18.4 Operation...........................................................................................................................514

18.4.1 Single Mode.........................................................................................................514

18.4.2 Scan Mode ...........................................................................................................514

18.4.3 Input Sampling and A/D Conversion Time..........................................................515

18.4.4 External Trigger Input Timing.............................................................................516

18.5 Interrupt Source.................................................................................................................517

18.6 A/D Conversion Accuracy Definitions.............................................................................518

18.7 Usage Notes......................................................................................................................520

Rev.1.00, 09/03, page xix of xxxviii

18.7.1 Module Stop Mode Setting.................................................................................. 520

18.7.2 Permissible Signal Source Impedance.................................................................520

18.7.3 Influences on Absolute Accuracy........................................................................ 521

18.7.4 Setting Range of Analog Power Supply and Other Pins......................................521

18.7.5 Notes on Board Design........................................................................................521

18.7.6 Notes on Noise Countermeasures........................................................................521

Section 19 RAM................................................................................................523

Section 20 Flash Memory (0.18-µm F-ZTAT Version)....................................525

20.1 Features.............................................................................................................................525

20.1.1 Mode Transition...................................................................................................527

20.1.2 Mode Comparison................................................................................................528

20.1.3 Flash Memory MAT Configuration.....................................................................529

20.1.4 Block Division.....................................................................................................530

20.1.5 Programming/Erasing Interface...........................................................................531

20.2 Input/Output Pins..............................................................................................................533

20.3 Register Descriptions........................................................................................................533

20.3.1 Programming/Erasing Interface Registers ...........................................................534

20.3.2 Programming/Erasing Interface Parameters ........................................................541

20.4 On-Board Programming Mode ......................................................................................... 551

20.4.1 Boot Mode...........................................................................................................551

20.4.2 User Program Mode.............................................................................................555

20.4.3 User Boot Mode...................................................................................................565

20.4.4 Storable Area for Procedure Program and Program Data....................................568

20.5 Protection..........................................................................................................................578

20.5.1 Hardware Protection............................................................................................578

20.5.2 Software Protection..............................................................................................579

20.5.3 Error Protection....................................................................................................579

20.6 Switching between User MAT and User Boot MAT........................................................580

20.7 Programmer Mode............................................................................................................582

20.8 Serial Communication Interface Specification for Boot Mode.........................................583

20.9 Usage Notes...................................................................................................................... 608

Section 21 Clock Pulse Generator.....................................................................611

21.1 Register Description..........................................................................................................612

21.1.1 System Clock Control Register (SCKCR)...........................................................612

21.2 Oscillator...........................................................................................................................614

21.2.1 Connecting Crystal Resonator.............................................................................614

21.2.2 External Clock Input Method...............................................................................615

21.3 Duty Adjustment Circuit...................................................................................................617

21.4 Divider..............................................................................................................................617

21.5 Usage Notes...................................................................................................................... 617

Rev.1.00, 09/03, page xx of xxxviii

21.5.1 Note on Resonator................................................................................................617

21.5.2 Notes on Board Design........................................................................................617

21.5.3 Notes on Operation Confirmation........................................................................618

Section 22 Power-Down Modes ....................................................................... 619

22.1 Register Descriptions........................................................................................................622

22.1.1 Standby Control Register (SBYCR) ....................................................................622

22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)....................624

22.1.3 Extension Module Stop Control Registers H and L

(EXMSTPCRH, EXMSTPCRL).........................................................................625

22.2 Operation...........................................................................................................................626

22.2.1 Clock Division Mode...........................................................................................626

22.2.2 Sleep Mode..........................................................................................................626

22.2.3 Software Standby Mode.......................................................................................627

22.2.4 Hardware Standby Mode .....................................................................................630

22.2.5 Module Stop Mode ..............................................................................................631

22.3 φ Clock Output Control.....................................................................................................631

22.4 Usage Notes......................................................................................................................633

22.4.1 I/O Port State........................................................................................................633

22.4.2 Current Consumption during Oscillation Stabilization Standby Period...............633

22.4.3 On-Chip Peripheral Module Interrupts................................................................633

22.4.4 Writing to MSTPCR, EXMSTPCR.....................................................................633

22.4.5 Notes on Clock Division Mode............................................................................633

Section 23 List of Registers.............................................................................. 635

23.1 Register Addresses (Address Order).................................................................................636

23.2 Register Bits......................................................................................................................647

23.3 Register States in Each Operating Mode...........................................................................659

Section 24 Electrical Characteristics ................................................................ 669

24.1 Absolute Maximum Ratings.............................................................................................669

24.2 DC Characteristics ............................................................................................................670

24.3 AC Characteristics ............................................................................................................673

24.3.1 Clock Timing.......................................................................................................673

24.3.2 Control Signal Timing.........................................................................................675

24.3.3 Bus Timing ..........................................................................................................677

24.3.4 Timing of On-Chip Peripheral Modules..............................................................685

24.4 A/D Conversion Characteristics........................................................................................691

24.5 Flash Memory Characteristics...........................................................................................692

24.6 Usage Notes......................................................................................................................693

Rev.1.00, 09/03, page xxi of xxxviii

Appendix .........................................................................................................695

A. I/O Port States in Each Pin State.......................................................................................695

B. Product Lineup..................................................................................................................697

C. Package Dimensions.........................................................................................................698

Index .........................................................................................................699

Rev.1.00, 09/03, page xxii of xxxviii

Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram of H8S/2437 Group.................................................................2

Figure 1.2 Pin Assignment of H8S/2437 Group (FP-128B)...........................................................3

Figure 1.3 Sample Design of Reset Signals without Affection Each Other..................................14

Section 2 CPU

Figure 2.1 Exception-Handling Vector Table (Normal Mode).....................................................19

Figure 2.2 Stack Structure in Normal Mode.................................................................................19

Figure 2.3 Exception-Handling Vector Table (Advanced Mode).................................................20

Figure 2.4 Stack Structure in Advanced Mode.............................................................................21

Figure 2.5 Memory Map...............................................................................................................22

Figure 2.6 CPU Registers.............................................................................................................23

Figure 2.7 Usage of General Registers.........................................................................................24

Figure 2.8 Stack............................................................................................................................25

Figure 2.9 General Register Data Formats (1) ..............................................................................28

Figure 2.9 General Register Data Formats (2) ..............................................................................29

Figure 2.10 Memory Data Formats...............................................................................................30

Figure 2.11 Instruction Formats (Examples) ................................................................................42

Figure 2.12 Branch Address Specification in Memory Indirect Mode.........................................46

Figure 2.13 State Transitions........................................................................................................50

Section 3 MCU Operating Modes

Figure 3.1 Memory Map...............................................................................................................56

Section 4 Exception Handling

Figure 4.1 Reset Sequence............................................................................................................60

Figure 4.2 Stack Status after Exception Handling........................................................................63

Figure 4.3 Operation when SP Value is Odd................................................................................64

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller........................................................................66

Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0................................................................76

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0.....82

Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2.....84

Figure 5.5 Interrupt Exception Handling......................................................................................86

Figure 5.6 Contention between Interrupt Generation and Disabling ............................................88

Section 6 Bus Controller (BSC)

Figure 6.1 Block Diagram of Bus Controller................................................................................92

Figure 6.2 CSn Signal Output Polarity and Output Timing........................................................100

Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) .............................102

Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space) ...........................103

Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space.............................................................105

Rev. 1.00, 09/03, page xxiii of xxxviii

Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space.............................................................106

Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)...........................107

Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)............................108

Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ..................................109

Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access).........................110

Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)..........................111

Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................112

Figure 6.13 Bus Timing for 8-Bit, 2-State Data Access Space (With Address Wait) ................113

Figure 6.14 Bus Timing for 8-Bit, 2-State Data Access Space (Without Address Wait)...........114

Figure 6.15 Bus Timing for 8-Bit, 3-State Data Access Space (With Address Wait) ................115

Figure 6.16 Bus Timing for 16-Bit, 2-State Data Access Space (1)

(Even Byte Access, with Address Wait).................................................................116

Figure 6.17 Bus Timing for 16-Bit, 2-State Data Access Space (2)

(Even Byte Access, without Address Wait)............................................................117

Figure 6.18 Bus Timing for 16-Bit, 2-State Access Space (3)

(Odd Byte Access, with Address Wait)...................................................................118

Figure 6.19 Bus Timing for 16-Bit, 2-State Data Access Space (4)

(Odd Byte Access, without Address Wait).............................................................. 119

Figure 6.20 Bus Timing for 16-Bit, 2-State Data Access Space (5)

(Word Access, with Address Wait).........................................................................120

Figure 6.21 Bus Timing for 16-Bit, 2-State Data Access Space (6)

(Word Access, without Address Wait)....................................................................121

Figure 6.22 Bus Timing for 16-Bit, 3-State Data Access Space (1)

(Even Byte Access, with Address Wait).................................................................122

Figure 6.23 Bus Timing for 16-Bit, 3-State Data Access Space (2)

(Odd Byte Access, with Address Wait)...................................................................123

Figure 6.24 Bus Timing for 16-Bit, 3-State Data Access Space (3)

(Word Access, with Address Wait).........................................................................124

Figure 6.25 Example of Wait State Insertion Timing (Normal Extended Pin Wait Mode)........126

Figure 6.26 Example of Wait State Insertion Timing (Multiplex Extended Mode) ...................127

Figure 6.27 Examples of Idle Cycle Operation...........................................................................128

Section 8 8-Bit PWM Timer (PWM)

Figure 8.1 Block Diagram of PWM Timer.................................................................................217

Figure 8.2 Example of Additional Pulse Timing (When Upper 4 Bits in PWDR = 1000).........224

Section 9 14-Bit PWM Timer (PWMX)

Figure 9.1 Block Diagram of PWMX (D/A)..............................................................................225

Figure 9.2 PWMX (D/A) Operation...........................................................................................233

Figure 9.3 Output Waveform (OS = 0, DADR Corresponds to T
Figure 9.4 Output Waveform (OS = 1, DADR Corresponds to T

)............................................235

L

)...........................................236

H

Figure 9.5 D/A Data Register Configuration when CFS = 1......................................................236

Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1).................................................237

Rev. 1.00, 09/03, page xxiv of xxxviii

Section 10 16-Bit Free-Running Timer (FRT)

Figure 10.1 Block Diagram of 16-Bit Free-Running Timer.......................................................240

Figure 10.2 Example of Pulse Output.........................................................................................251

Figure 10.3 Increment Timing with Internal Clock Source........................................................252

Figure 10.4 Increment Timing with External Clock Source.......................................................252

Figure 10.5 Timing of Output Compare A Output .....................................................................253

Figure 10.6 Clearing of FRC by Compare-Match A Signal .......................................................253

Figure 10.7 Timing of Input Capture Input Signal (Usual Case)................................................254

Figure 10.8 Timing of Input Capture Input Signal (When ICRA to ICRD are Read)................254

Figure 10.9 Buffered Input Capture Timing...............................................................................255

Figure 10.10 Buffered Input Capture Timing (BUFEA = 1)......................................................256

Figure 10.11 Timing of Input Capture Flags (ICFA to ICFD) Setting .......................................256

Figure 10.12 Timing of Output Compare Flag (OCFA or OCFB) Setting.................................257

Figure 10.13 Timing of OVF Flag Setting..................................................................................257

Figure 10.14 OCRA Automatic Addition Timing......................................................................258

Figure 10.15 Timing of Input Capture Mask Signal Setting.......................................................258

Figure 10.16 Timing of Input Capture Mask Signal Clearing....................................................259

Figure 10.17 FRC Write-Clear Conflict .....................................................................................261

Figure 10.18 FRC Write-Increment Conflict..............................................................................262

Figure 10.19 Conflict between OCR Write and Compare-Match

(When Automatic Addition Function is not Used) ................................................263

Figure 10.20 Conflict between OCRAR/OCRAF Write and Compare-Match

(When Automatic Addition Function is Used)......................................................264

Section 11 8-Bit Timer (TMR)

Figure 11.1 Block Diagram of 8-Bit Timer (TMR0 and TMR1)................................................268

Figure 11.2 Block Diagram of 8-Bit Timer (TMRY and TMRX)..............................................269

Figure 11.3 Pulse Output Example.............................................................................................283

Figure 11.4 Count Timing for Internal Clock Input....................................................................284

Figure 11.5 Count Timing for External Clock Input...................................................................284

Figure 11.6 Timing of CMF Setting at Compare-Match ............................................................285

Figure 11.7 Timing of Toggled Timer Output by Compare-Match A Signal.............................285

Figure 11.8 Timing of Counter Clear by Compare-Match..........................................................286

Figure 11.9 Timing of Counter Clear by External Reset Input...................................................286

Figure 11.10 Timing of OVF Flag Setting..................................................................................287

Figure 11.11 Timing of Input Capture Operation.......................................................................289

Figure 11.12 Timing of Input Capture Signal

(When Input Capture Signal is Input during TICRR and TICRF Read)................290

Figure 11.13 Conflict between TCNT Write and Clear..............................................................292

Figure 11.14 Conflict between TCNT Write and Increment.......................................................293

Figure 11.15 Conflict between TCOR Write and Compare-Match............................................294

Rev. 1.00, 09/03, page xxv of xxxviii

Section 12 16-Bit Timer Pulse Unit (TPU)

Figure 12.1 Block Diagram of TPU............................................................................................300

Figure 12.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)]......................325

Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]..................325

Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]..............326

Figure 12.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] .......326

Figure 12.6 Example of Counter Operation Setting Procedure..................................................327

Figure 12.7 Free-Running Counter Operation............................................................................328

Figure 12.8 Periodic Counter Operation.....................................................................................329

Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match..............329

Figure 12.10 Example of 0 Output/1 Output Operation .............................................................330

Figure 12.11 Example of Toggle Output Operation ...................................................................330

Figure 12.12 Example of Setting Procedure for Input Capture Operation..................................331

Figure 12.13 Example of Input Capture Operation.....................................................................331

Figure 12.14 Example of Synchronous Operation Setting Procedure........................................332

Figure 12.15 Example of Synchronous Operation......................................................................333

Figure 12.16 Compare Match Buffer Operation.........................................................................334

Figure 12.17 Input Capture Buffer Operation.............................................................................334

Figure 12.18 Example of Buffer Operation Setting Procedure...................................................335

Figure 12.19 Example of Buffer Operation (1)...........................................................................335

Figure 12.20 Example of Buffer Operation (2)...........................................................................336

Figure 12.21 Cascaded Operation Setting Procedure .................................................................337

Figure 12.22 Example of Cascaded Operation (1)......................................................................338

Figure 12.23 Example of Cascaded Operation (2)......................................................................338

Figure 12.24 Example of PWM Mode Setting Procedure..........................................................340

Figure 12.25 Example of PWM Mode Operation (1).................................................................340

Figure 12.26 Example of PWM Mode Operation (2).................................................................341

Figure 12.27 Example of PWM Mode Operation (3).................................................................342

Figure 12.28 Example of Setting Procedure for Phase Counting Mode.....................................343

Figure 12.29 Example of Phase Counting Mode 1 Operation....................................................344

Figure 12.30 Example of Phase Counting Mode 2 Operation....................................................345

Figure 12.31 Example of Phase Counting Mode 3 Operation....................................................346

Figure 12.32 Example of Phase Counting Mode 4 Operation....................................................347

Figure 12.33 Count Timing in Internal Clock Operation............................................................350

Figure 12.34 Count Timing in External Clock Operation...........................................................350

Figure 12.35 Output Compare Output Timing............................................................................351

Figure 12.36 Input Capture Input Signal Timing........................................................................351

Figure 12.37 Counter Clear Timing (Compare Match) ..............................................................352

Figure 12.38 Counter Clear Timing (Input Capture)..................................................................352

Figure 12.39 Buffer Operation Timing (Compare Match)..........................................................353

Figure 12.40 Buffer Operation Timing (Input Capture) .............................................................353

Figure 12.41 TGI Interrupt Timing (Compare Match)...............................................................354

Rev. 1.00, 09/03, page xxvi of xxxviii

Figure 12.42 TGI Interrupt Timing (Input Capture)...................................................................355

Figure 12.43 TCIV Interrupt Setting Timing..............................................................................355

Figure 12.44 TCIU Interrupt Setting Timing..............................................................................356

Figure 12.45 Timing for Status Flag Clearing by CPU...............................................................356

Figure 12.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................357

Figure 12.47 Contention between TCNT Write and Clear Operations.......................................358

Figure 12.48 Contention between TCNT Write and Increment Operations...............................358

Figure 12.49 Contention between TGR Write and Compare Match...........................................359

Figure 12.50 Contention between Buffer Register Write and Compare Match..........................359

Figure 12.51 Contention between TGR Read and Input Capture...............................................360

Figure 12.52 Contention between TGR Write and Input Capture ..............................................360

Figure 12.53 Contention between Buffer Register Write and Input Capture..............................361

Figure 12.54 Contention between Overflow and Counter Clearing............................................362

Figure 12.55 Contention between TCNT Write and Overflow...................................................362

Section 13 Timer Connection

Figure 13.1 Schematic Diagram of Timer Connection...............................................................366

Figure 13.2 Block Diagram of Timer Connection......................................................................367

Figure 13.3 Block Diagram for PWM Decoding........................................................................380

Figure 13.4 Timing Chart for PWM Decoding...........................................................................381

Figure 13.5 Block Diagram for Clamp Waveform Generation...................................................383

Figure 13.6 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) ...............383

Figure 13.7 Timing Chart for Clamp Waveform Generation (CL3 Signal)................................384

Figure 13.8 Block Diagram for Measurement of 8-Bit Timer Divided Waveform Period.........385

Figure 13.9 Timing Chart for Measurement of IVI Signal and

IHI Signal Divided Waveform Periods ...................................................................386

Figure 13.10 Block Diagram for 2fH Modification of IHI Signal..............................................388

Figure 13.11 2fH Modification Timing Chart ............................................................................389

Figure 13.12 Block Diagram for IVI Signal Fall Modification and IHI Signal Operation.........390

Figure 13.13 Fall Modification and IHI Synchronization Timing Chart ....................................391

Figure 13.14 Block Diagram for IVG Signal Generation...........................................................392

Figure 13.15 Block Diagram for IHG Signal Generation...........................................................393

Figure 13.16 IVG Signal/IHG Signal/CL4 Signal Timing Chart................................................395

Figure 13.17 CBLANK Output Waveform Generation..............................................................398

Section 14 Duty Measurement Circuit

Figure 14.1 Block Diagram of Duty Measurement Circuit.........................................................400

Figure 14.2 Example of Duty Measurement for External Event Signal .....................................406

Figure 14.3 TWCNT Count Timing ...........................................................................................407

Figure 14.4 TWCNT Clear Timing by Setting START Bit........................................................407

Figure 14.5 Count Start Timing for Duty Measurement.............................................................408

Figure 14.6 Input Capture Timing during Duty Measurement...................................................408

Figure 14.7 Clear Timing for START Bit when Duty Measurement Ends.................................409

Figure 14.8 Set Timing for Duty Measurement End Flag (ENDF).............................................409

Rev. 1.00, 09/03, page xxvii of xxxviii

Figure 14.9 Set Timing for OVF Flag ........................................................................................410

Figure 14.10 TWCNT Write-Increment Conflict.......................................................................411

Figure 14.11 Write to START Bit during Free-Running Counter Operation.............................411

Section 15 Watchdog Timer (WDT)

Figure 15.1 Block Diagram of WDT..........................................................................................417

Figure 15.2 Watchdog Timer Mode (RST/NMI = 1) Operation.................................................420

Figure 15.3 Interval Timer Mode Operation...............................................................................421

Figure 15.4 OVF Flag Set Timing..............................................................................................421

Figure 15.5 Internal Reset Signal Generation Timing................................................................422

Figure 15.6 Writing to TCNT and TCSR...................................................................................423

Figure 15.7 Conflict between TCNT Write and Increment........................................................424

Section 16 Serial Communication Interface (SCI)

Figure 16.1 Block Diagram of SCI.............................................................................................426

Figure 16.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity,

Two Stop Bits) ........................................................................................................442

Figure 16.3 Receive Data Sampling Timing in Asynchronous Mode ........................................444

Figure 16.4 Relation between Output Clock and Transmit Data Phase

(Asynchronous Mode).............................................................................................445

Figure 16.5 Sample SCI Initialization Flowchart .......................................................................446

Figure 16.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit)....................................................447

Figure 16.7 Sample Serial Transmission Flowchart...................................................................448

Figure 16.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit)....................................................449

Figure 16.9 Sample Serial Reception Flowchart (1)...................................................................451

Figure 16.9 Sample Serial Reception Flowchart (2)...................................................................452

Figure 16.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)..........................................454

Figure 16.11 Sample Multiprocessor Serial Transmission Flowchart........................................455

Figure 16.12 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)..............................456

Figure 16.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................457

Figure 16.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................458

Figure 16.14 Data Format in Clocked Synchronous Communication (LSB-First).....................459

Figure 16.15 Sample SCI Initialization Flowchart .....................................................................460

Figure 16.16 Sample SCI Transmission Operation in Clocked Synchronous Mode..................461

Figure 16.17 Sample Serial Transmission Flowchart.................................................................462

Figure 16.18 Example of SCI Receive Operation in Clocked Synchronous Mode....................463

Figure 16.19 Sample Serial Reception Flowchart ......................................................................464

Figure 16.20 Sample Flowchart of Simultaneous Serial Transmission and Reception...............466

Figure 16.21 Sample Flowchart for Mode Transition during Transmission...............................470

Figure 16.22 Pin States during Transmission in Asynchronous Mode (Internal Clock).............471

Rev. 1.00, 09/03, page xxviii of xxxviii

Figure 16.23 Pin States during Transmission in Clocked Synchronous Mode

(Internal Clock).....................................................................................................471

Figure 16.24 Sample Flowchart for Mode Transition during Reception ....................................472

Figure 16.25 Switching from SCK Pins to Port Pins..................................................................473

Figure 16.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins..........473

2

Section 17 I

Figure 17.1 Block Diagram of I

C Bus Interface 3 (IIC3 )

2

C Bus Interface 3.....................................................................476

Figure 17.2 External Circuit Connections of I/O Pins................................................................477

Figure 17.3 I
Figure 17.4 I

2

C Bus Formats ......................................................................................................491

2

C Bus Timing........................................................................................................491

Figure 17.5 Operation Timing in Master Transmit Mode (1).....................................................493

Figure 17.6 Operation Timing in Master Transmit Mode (2).....................................................493

Figure 17.7 Operation Timing in Master Receive Mode (1).......................................................495

Figure 17.8 Operation Timing in Master Receive Mode (2).......................................................495

Figure 17.9 Operation Timing in Slave Transmit Mode (1).......................................................497

Figure 17.10 Operation Timing in Slave Transmit Mode (2).....................................................498

Figure 17.11 Operation Timing in Slave Receive Mode (1).......................................................499

Figure 17.12 Operation Timing in Slave Receive Mode (2).......................................................499

Figure 17.13 Block Diagram of Noise Canceler.........................................................................500

Figure 17.14 Sample Flowchart for Master Transmit Mode.......................................................501

Figure 17.15 Sample Flowchart for Master Receive Mode........................................................502

Figure 17.16 Sample Flowchart for Slave Transmit Mode.........................................................503

Figure 17.17 Sample Flowchart for Slave Receive Mode ..........................................................504

Figure 17.18 Timing of Bit Synchronous Circuit.......................................................................506

Section 18 A/D Converter

Figure 18.1 Block Diagram of A/D Converter............................................................................ 508

Figure 18.2 A/D Conversion Timing..........................................................................................515

Figure 18.3 External Trigger Input Timing ................................................................................517

Figure 18.4 A/D Conversion Accuracy Definitions....................................................................519

Figure 18.5 A/D Conversion Accuracy Definitions....................................................................519

Figure 18.6 Example of Analog Input Circuit ............................................................................520

Figure 18.7 Example of Analog Input Protection Circuit...........................................................522

Section 20 Flash Memory (0.18-µµµµm F-ZTAT Version)

Figure 20.1 Block Diagram of Flash Memory............................................................................526

Figure 20.2 Mode Transition of Flash Memory..........................................................................527

Figure 20.3 Flash Memory Configuration ..................................................................................529

Figure 20.4 Block Division of User MAT..................................................................................530

Figure 20.5 Overview of User Procedure Program.....................................................................531

Figure 20.6 System Configuration in Boot Mode.......................................................................552

Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI..................................................552

Figure 20.8 Overview of State Transition Diagram in Boot Mode.............................................554

Rev. 1.00, 09/03, page xxix of xxxviii

Figure 20.9 Overview of Programming/Erasing Flow................................................................555

Figure 20.10 RAM Map when Programming/Erasing is Executed ............................................556

Figure 20.11 Programming Procedure........................................................................................557

Figure 20.12 Erasing Procedure.................................................................................................. 562

Figure 20.13 Repeating Procedure of Erasing and Programming...............................................564

Figure 20.14 Procedure for Programming User MAT in User Boot Mode ................................566

Figure 20.15 Procedure for Erasing User MAT in User Boot Mode..........................................567

Figure 20.16 Transitions to Error Protection State.....................................................................580

Figure 20.17 Switching between User MAT and User Boot MAT ............................................581

Figure 20.18 Memory Map in Programmer Mode......................................................................582

Figure 20.19 Boot Program States..............................................................................................584

Figure 20.20 Bit-Rate-Adjustment Sequence.............................................................................585

Figure 20.21 Communication Protocol Format ..........................................................................586

Figure 20.22 New Bit-Rate Selection Sequence.........................................................................596

Figure 20.23 Programming Sequence .........................................................................................599

Figure 20.24 Erasure Sequence ..................................................................................................602

Section 21 Clock Pulse Generator

Figure 21.1 Block Diagram of Clock Pulse Generator...............................................................611

Figure 21.2 Typical Connection to Crystal Resonator................................................................614

Figure 21.3 Equivalent Circuit of Crystal Resonator..................................................................614

Figure 21.4 Example of External Clock Input............................................................................615

Figure 21.5 External Clock Input Timing...................................................................................616

Figure 21.6 Timing of Output Stabilization Delay Time for External Clock .............................616

Figure 21.7 Note on Board Design of Oscillation Circuit Section...............................................617

Section 22 Power-Down Modes

Figure 22.1 Mode Transitions.....................................................................................................621

Figure 22.2 Software Standby Mode Application Example.......................................................629

Figure 22.3 Hardware Standby Mode Timing............................................................................631

Section 24 Electrical Characteristics

Figure 24.1 Darlington Transistor Drive Circuit (Example).......................................................672

Figure 24.2 Output Load Circuit.................................................................................................673

Figure 24.3 System Clock Timing..............................................................................................674

Figure 24.4 Oscillation Stabilization Timing..............................................................................674

Figure 24.5 Oscillation Stabilization Timing (Exiting Software Standby Mode).......................675

Figure 24.6 Reset Input Timing..................................................................................................676

Figure 24.7 Interrupt Input Timing.............................................................................................676

Figure 24.8 Basic Bus Timing/2-State Access............................................................................678

Figure 24.9 Basic Bus Timing/3-State Access............................................................................679

Figure 24.10 Basic Bus Timing/3-State Access with One Wait State........................................680

Figure 24.11 Muliplex Bus Timing/2-State Access....................................................................682

Figure 24.12 Multiplex Bus Timing/3-State Access...................................................................683

Rev. 1.00, 09/03, page xxx of xxxviii

Figure 24.13 Multiplex Bus Timing/3-State Access with One Wait State..................................684

Figure 24.14 I/O Port Input/Output Timing................................................................................686

Figure 24.15 FRT Input/Output Timing .....................................................................................686

Figure 24.16 FRT Clock Input Timing.......................................................................................686

Figure 24.17 TPU Input/Output Timing.....................................................................................687

Figure 24.18 TPU Clock Input Timing.......................................................................................687

Figure 24.19 8-Bit Timer Output Timing ...................................................................................687

Figure 24.20 8-Bit Timer Clock Input Timing............................................................................687

Figure 24.21 8-Bit Timer Reset Input Timing............................................................................688

Figure 24.22 PWM, PWMX Output Timing ..............................................................................688

Figure 24.23 SCK Clock Input Timing.......................................................................................688

Figure 24.24 SCI Input/Output Timing (Clock Synchronous Mode) .........................................688

Figure 24.25 A/D Converter External Trigger Input Timing......................................................689

Figure 24.26 Input/Output Timing of I

2

C Bus Interface 3..........................................................690

Figure 24.27 Connection of VCL Capacitor................................................................................693

Appendix

Figure C.1 Package Dimensions (FP-128B)...............................................................................698

Rev. 1.00, 09/03, page xxxi of xxxviii

Rev. 1.00, 09/03, page xxxii of xxxviii

Tables

Section 1 Overview

Table 1.1 Pin Assignment in Each Operating Mode.....................................................................4

Table 1.2 Pin Functions ................................................................................................................9

Section 2 CPU

Table 2.1 Instruction Classification ............................................................................................31

Table 2.2 Operation Notation......................................................................................................32

Table 2.3 Data Transfer Instructions...........................................................................................33

Table 2.4 Arithmetic Operations Instructions (1).......................................................................34

Table 2.4 Arithmetic Operations Instructions (2).......................................................................35

Table 2.5 Logic Operations Instructions.....................................................................................36

Table 2.6 Shift Instructions.........................................................................................................36

Table 2.7 Bit Manipulation Instructions (1)................................................................................37

Table 2.7 Bit Manipulation Instructions (2)................................................................................38

Table 2.8 Branch Instructions.....................................................................................................39

Table 2.9 System Control Instructions........................................................................................40

Table 2.10 Block Data Transfer Instructions............................................................................41

Table 2.11 Addressing Modes ..................................................................................................43

Table 2.12 Absolute Address Access Ranges...........................................................................44

Table 2.13 Effective Address Calculation (1)...........................................................................47

Table 2.13 Effective Address Calculation (2)...........................................................................48

Section 3 MCU Operating Modes

Table 3.1 MCU Operating Mode Selection ................................................................................51

Table 3.2 Pin Functions in Each Operating Mode......................................................................55

Section 4 Exception Handling

Table 4.1 Exception Types and Priority......................................................................................57

Table 4.2 Exception Handling Vector Table...............................................................................58

Table 4.3 Status of CCR and EXR after Trace Exception Handling...........................................61

Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling..........................62

Section 5 Interrupt Controller

Table 5.1 Pin Configuration........................................................................................................67

Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities.....................................77

Table 5.3 Interrupt Control Modes .............................................................................................81

Table 5.4 Interrupt Response Times...........................................................................................87

Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses.........................87

Section 6 Bus Controller (BSC)

Table 6.1 Pin Configuration........................................................................................................93

Table 6.2 Address Range and External Address Area (Normal Extended Mode)......................97

Table 6.3 Bus Specifications for Normal Extended Bus Interface..............................................98

Rev. 1.00, 09/03, page xxxiii of xxxviii

Table 6.4 Address Range and External Address Area (Multiplex Extended Mode)...................99

Table 6.5 Bus Specifications for Multiplex Extended Bus Interface (Address Cycle)...............99

Table 6.6 Bus Specifications for Multiplex Extended Bus Interface (Data Cycle).....................99

Table 6.7 Data Buses Used and Valid Strobes..........................................................................104

Table 6.8 Pin States in Idle Cycle.............................................................................................129

Section 7 I/O Ports

Table 7.1 Port Functions (1).....................................................................................................132

Table 7.1 Port Functions (2).....................................................................................................133

Table 7.1 Port Functions (3).....................................................................................................134

Table 7.1 Port Functions (4).....................................................................................................135

Table 7.1 Port Functions (5).....................................................................................................136

Table 7.2 Port 1 Input Pull-Up MOS States..............................................................................142

Table 7.3 Port 2 Input Pull-Up MOS States..............................................................................154

Table 7.4 Port 3 Input Pull-Up MOS States..............................................................................161

Table 7.5 Port 6 Input Pull-Up MOS States..............................................................................181

Section 8 8-Bit PWM Timer (PWM)

Table 8.1 Pin Configuration......................................................................................................218

Table 8.2 Internal Clock Selection............................................................................................220

Table 8.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20 MHz ...220

Table 8.4 Duty Cycle of Basic Pulse........................................................................................223

Table 8.5 Position of Pulses Added to Basic Pulses.................................................................224

Section 9 14-Bit PWM Timer (PWMX)

Table 9.1 Pin Configuration......................................................................................................226

Table 9.2 Clock Selection of PWMX.......................................................................................231

Table 9.3 Access Method for Reading/Writing 16-Bit Registers .............................................232

Table 9.4 Settings and Operation (Examples when φ = 20 MHz).............................................234

Table 9.5 Locations of Additional Pulses Added to Base Pulse (when CFS = 1).....................238

Section 10 16-Bit Free-Running Timer (FRT)

Table 10.1 Pin Configuration..................................................................................................241

Table 10.2 FRT Interrupt Sources...........................................................................................260

Table 10.3 Switching of Internal Clock and FRC Operation ..................................................265

Section 11 8-Bit Timer (TMR)

Table 11.1 Pin Configuration..................................................................................................270

Table 11.2 Clock Input to TCNT and Count Condition..........................................................275

Table 11.3 Interrupt Sources of 8-Bit Timers TMR0, TMR1, TMRY, and TMRX ...............291

Table 11.4 Timer Output Priorities.........................................................................................295

Table 11.5 Switching of Internal Clocks and TCNT Operation.............................................. 295

Table 11.5 Switching of Internal Clocks and TCNT Operation (cont)...................................296

Rev. 1.00, 09/03, page xxxiv of xxxviii

Section 12 16-Bit Timer Pulse Unit (TPU)

Table 12.1 TPU Functions ......................................................................................................301

Table 12.2 Pin Configuration..................................................................................................303

Table 12.3 CCLR2 to CCLR0 (Channel 0).............................................................................306

Table 12.4 CCLR2 to CCLR0 (Channels 1 and 2) .................................................................306

Table 12.5 TPSC2 to TPSC0 (Channel 0) ..............................................................................307

Table 12.6 TPSC2 to TPSC0 (Channel 1) ..............................................................................307

Table 12.7 TPSC2 to TPSC0 (Channel 2) ..............................................................................308

Table 12.8 MD3 to MD0.........................................................................................................309

Table 12.9 TIORH_0 (Channel 0)..........................................................................................311

Table 12.10 TIORH_0 (Channel 0)..........................................................................................312

Table 12.11 TIORL_0 (Channel 0)...........................................................................................313

Table 12.12 TIORL_0 (Channel 0)...........................................................................................314

Table 12.13 TIOR_1 (Channel 1) .............................................................................................315

Table 12.14 TIOR_1 (Channel 1) .............................................................................................316

Table 12.15 TIOR_2 (Channel 2) .............................................................................................317

Table 12.16 TIOR_2 (Channel 2) .............................................................................................318

Table 12.17 Register Combinations in Buffer Operation..........................................................334

Table 12.18 Cascaded Combinations........................................................................................337

Table 12.19 PWM Output Registers and Output Pins ..............................................................339

Table 12.20 Clock Input Pins for Phase Counting Mode..........................................................343

Table 12.21 Up/Down-Count Conditions in Phase Counting Mode 1......................................344

Table 12.22 Up/Down-Count Conditions in Phase Counting Mode 2......................................345

Table 12.23 Up/Down-Count Conditions in Phase Counting Mode 3......................................346

Table 12.24 Up/Down-Count Conditions in Phase Counting Mode 4......................................347

Table 12.25 TPU Interrupts ......................................................................................................348

Section 13 Timer Connection

Table 13.1 Pin Configuration..................................................................................................368

Table 13.2 Synchronization Signal Connection Enable..........................................................371

Table 13.3 HSYNCO Output Selection..................................................................................374

Table 13.4 VSYNCO Output Selection..................................................................................374

Table 13.5 Examples of TCR Settings....................................................................................381

Table 13.6 Examples of TCORB (Pulse Width Threshold) Settings......................................381

Table 13.7 Examples of TCR and TCSR Settings..................................................................386

Table 13.8 Examples of TCR, TCSR, TCOR, and OCRDM Settings....................................388

Table 13.9 Examples of TCR, TCSR, and TCORB Settings..................................................391

Table 13.10 Examples of OCRAR, OCRAF, TOCR, TCORA, TCORB, TCR,

and TCSR Settings................................................................................................ 394

Table 13.11 HSYNCO Output Modes......................................................................................396

Table 13.12 VSYNCO Output Modes......................................................................................397

Rev. 1.00, 09/03, page xxxv of xxxviii

Section 14 Duty Measurement Circuit

Table 14.1 Pin Configuration..................................................................................................401

Table 14.2 Interrupt Sources for Duty Measurement Circuit..................................................410

Table 14.3 Switching of Internal Clock and TWCNT Operation...........................................412

Table 14.4 Switching of External Event Signal and Operation of Edge Detection Circuit.....414

Section 15 Watchdog Timer (WDT)

Table 15.1 Interrupt Source ....................................................................................................422

Section 16 Serial Communication Interface (SCI)

Table 16.1 Pin Configuration..................................................................................................427

Table 16.2 Relationships between N Setting in BRR and Bit Rate B.....................................436

Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)......437

Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)......438

Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3)......439

Table 16.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode)..........440

Table 16.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................440

Table 16.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode).....................441

Table 16.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)....441

Table 16.8 Serial Transfer Formats (Asynchronous Mode)....................................................443

Table 16.9 SSR Status Flags and Receive Data Handling......................................................450

Table 16.10 SCI Interrupt Sources............................................................................................468

Section 17 I

2

C Bus Interface 3 (IIC3 )

Table 17.1 Pin Configuration..................................................................................................478

Table 17.2 Transfer Rate.........................................................................................................480

Table 17.3 Interrupt Requests.................................................................................................505

Table 17.4 Time for Monitoring SCL.....................................................................................506

Section 18 A/D Converter

Table 18.1 Pin Configuration..................................................................................................509

Table 18.2 Analog Input Channels and Corresponding ADDR..............................................510

Table 18.3 A/D Conversion Time (Single Mode)...................................................................516

Table 18.4 A/D Conversion Time (Scan Mode).....................................................................516

Table 18.5 A/D Converter Interrupt Source............................................................................517

Table 18.6 Analog Pin Specifications.....................................................................................522

Section 20 Flash Memory (0.18-µµµµm F-ZTAT Version)

Table 20.1 Comparison of Programming Modes....................................................................528

Table 20.2 Pin Configuration..................................................................................................533

Table 20.3 Registers/Parameters and Target Modes...............................................................534

Table 20.4 Parameters and Target Modes...............................................................................542

Table 20.5 Setting On-Board Programming Mode.................................................................551

Rev. 1.00, 09/03, page xxxvi of xxxviii

Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment.............................553

Table 20.7 Executable MAT...................................................................................................569

Table 20.8 (1) Usable Area for Programming in User Program Mode.....................................570

Table 20.8 (2) Usable Area for Erasure in User Program Mode ..............................................572

Table 20.8 (3) Usable Area for Programming in User Boot Mode...........................................574

Table 20.8 (4) Usable Area for Erasure in User Boot Mode ....................................................576

Table 20.9 Hardware Protection .............................................................................................578

Table 20.10 Software Protection...............................................................................................579

Table 20.11 Inquiry/Selection Commands................................................................................587

Table 20.12 Programming/Erasing Commands........................................................................598

Table 20.13 Status Codes..........................................................................................................606

Table 20.14 Error Codes...........................................................................................................607

Section 21 Clock Pulse Generator

Table 21.1 Damping Resistor Values......................................................................................614

Table 21.2 Crystal Resonator Parameters...............................................................................614

Table 21.3 External Clock Input Conditions...........................................................................615

Table 21.4 Output Stabilization Delay Time for External Clock............................................616

Section 22 Power-Down Modes

Table 22.1 Operating Modes and Internal States of LSI.........................................................620

Table 22.2 Oscillation Stabilization Time Settings.................................................................628

Table 22.3 φ Pin State in Each Processing State.....................................................................632

Section 24 Electrical Characteristics

Table 24.1 Absolute Maximum Ratings.................................................................................669

Table 24.2 DC Characteristics ................................................................................................670

Table 24.3 Permissible Output Currents.................................................................................672

Table 24.4 Clock Timing........................................................................................................674

Table 24.5 Control Signal Timing ..........................................................................................675

Table 24.6 Bus Timing (Normal Extension)...........................................................................677

Table 24.7 Bus Timing (Multiplex Extension).......................................................................681

Table 24.8 Timing of On-Chip Peripheral Modules...............................................................685

2

Table 24.9 I

C Bus Interface Timing......................................................................................689

Table 24.10 A/D Conversion Characteristics

(AN15 to AN0 Input: 134/266-State Conversion)................................................691

Table 24.11 Flash Memory Characteristics...............................................................................692

Appendix

Table A.1 I/O Port States in Each Pin State...........................................................................695

Rev. 1.00, 09/03, page xxxvii of xxxviii

Rev. 1.00, 09/03, page xxxviii of xxxviii

Section 1 Overview

1.1 Features

• High-speed H8S/2600 central processing unit with an internal 16-bit architecture

Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
69 basic instructions
Multiply-and-accumulate instruction

• Various peripheral functions

8-bit PWM timer (PWM)
14-bit PWM timer (PWMX)
16-bit free-running timer (FRT)
8-bit timer (TMR)
16-bit timer pulse unit (TPU)
Watchdog timer (WDT)
Timer connection
Duty measurement circuit
Asynchronous or clocked synchronous serial communication interface (SCI)

2

I

C bus interface 3 (IIC3)

10-bit A/D converter

• On-chip memory

ROM Type Model ROM RAM Remarks

Flash memory
version

• General I/O ports

I/O pins: 94
Input-only pins: 16

• Supports various power-down modes

• Compact package

Package Code Body Size Pin Pitch

QFP-128 FP-128B 14.0 × 20.0 mm 0.5 mm

HD64F2437 256 kbytes 16 kbytes

Rev. 1.00, 09/03, page 1 of 704

1.2 Internal Block Diagram

Figure 1.1 shows the internal block diagram of the H8S/2437 Group.

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

EXTAL

XTAL

FWE

MD1

MD0

MD2

NMI

VCL

P00/AN8

P01/AN9
P02/AN10
P03/AN11

P04/AN12/
P05/AN13/
P06/AN14/
P07/AN15/

P10/PW0/A0/AD0
P11/PW1/A1/AD1
P12/PW2/A2/AD2
P13/PW3/A3/AD3
P14/PW4/A4/AD4
P15/PW5/A5/AD5
P16/PW6/A6/AD6
P17/PW7/A7/AD7

P20/TIOCA0/A8/AD8

P21/TIOCB0/A9/AD9
P22/TIOCC0/TCLKA/A10/AD10
P23/TIOCD0/TCLKB/A11/AD11

P24/TIOCA1/A12/AD12

P25/TIOCB1/TCLKC/A13/AD13

P26/TIOCA2/A14/AD14

P27/TIOCB2/TCLKD/A15/AD15

P30/ /D8
P31/

/D10

P32/
P33/

/D11
P34/D12
P35/D13
P36/D14
P37/D15

P40/ /FTIB_1

/FTIC_1

P41/
P42/

/TMI0_1
/TMIX_1

P43/

P44/

/TMIY_1/ExPW0
/TMI0_0/ExPW1

P45/
P46/

/TMIX_0/ExPW2
/TMIY_0/ExPW3

P47/

P50/SCK0
P51/TxD0
P52/RxD0
P53/SCK1

Port 5

Port 0

H8S/2600 CPU

Clock pulse generator

Port 1

Port 2

/D9

Port 3

Port 4

Flash memory

RAM

Interrupt controller

16-bit FRT 2 channels

8-bit TMR

4 channels

Timer connection

2 channels

Duty measurement circuit

Port C

14-bit PWM 2 channels

Port B

Bus controller

WDT

3 channels

TPU

8-bit PWM

IIC3

4 channels

SCI

5 channels

10-bit A/D

Internal address bus

Internal data bus

Peripheral data bus

Peripheral address bus

Port A

P54/TxD1
P55/RxD1
P56/TMO0_1/ExPW4
P57/TMO1_1/ExPW5

P60/FTOA_1/D0
P61/FTOB_1/D1
P62/TMOX_1/D2
P63/TMOY_1/D3

Port 6

P64/FTCI_1/D4
P65/SCK2/D5
P66/TxD2/D6
P67/RxD2/D7

P70/AN0
P71/AN1
P72/AN2
P73/AN3

Port 7

P74/AN4
P75/AN5
P76/AN6
P77/AN7

P80/SCL0/TxD3
P81/SDA0/RxD3
P82/SCL1/TxD4
P83/SDA1/RxD4

Port 8

P84/PWX0
P85/PWX1
P86/ExTIOCA0
P87/ExTIOCB0/

P90/ /ExTIOCB1/ExTCLKC
P91/

/ExTIOCA2

P92/

/ExTIOCB2/ExTCLKD

P93/

Port 9

P94/
P95/ /
P96/
P97/ /ExTIOCD0/ExTCLKB

AVCC
AVref
AVSS

Note: * Not supported by the on-chip emulator.

Figure 1.1 Internal Block Diagram of H8S/2437 Group

Rev. 1.00, 09/03, page 2 of 704

PC0/SCL2

PC2/SCL3

PC1/SDA2

PC3/SDA3

PC5*/ETCK

PC4*/ETMS

PC6*/ETDI

PC7*/ETDO

PB0/FTOA_0/VSYNCO

PB3/FTIA_1/VSYNCI_1

PB6/FTIA_0/VSYNCI_0

PB1/TMO1_0/HSYNCO

PB2/FTID_1/CSYNCI_1

PB5/FTID_0/CSYNCI_0

PB4/TMI1_1/HSYNCI_1

PA4/FTIC_0/CLAMPO

PB7/TMI1_0/HSYNCI_0

PA3/FTOB_0/CBLANK

PA0/TMOX_0/ExPW6/SCK3

PA1/TMOY_0/ExPW7/SCK4

PA2/TMO0_0/ExTIOCC0/ExTCLKA

/ExTIOCA1

PA7/

PA5/FTIB_0/VFBACKI

PA6/FTCI_0/HFBACKI

1.3 Pin Description

1.3.1 Pin Assignment

Figure 1.2 shows the pin assignment of the H8S/2437 Group.

/ExTIOCA1

P84/PWX0

P85/PWX1

P86/ExTIOCA0

PA7/

P87/ExTIOCB0/

VSS

PB7/TMI1_0/HSYNCI_0

PB6/FTIA_0/VSYNCI_0

VCC

PB5/FTID_0/CSYNCI_0

FP-128B

(Top view)

PB4/TMI1_1/HSYNCI_1

PB3/FTIA_1/VSYNCI_1

PC0/SCL2

PC1/SDA2

PC2/SCL3
P27/TIOCB2/TCLKD/A15/AD15
P25/TIOCB1/TCLKC/A13/AD13
P23/TIOCD0/TCLKB/A11/AD11

P22/TIOCC0/TCLKA/A10/AD10

PC3/SDA3
P26/TIOCA2/A14/AD14
P24/TIOCA1/A12/AD12

P21/TIOCB0/A9/AD9
P20/TIOCA0/A8/AD8

VCC
P17/PW7/A7/AD7
P16/PW6/A6/AD6

P15/PW5/A5/AD5
P14/PW4/A4/AD4
P13/PW3/A3/AD3
P12/PW2/A2/AD2
P11/PW1/A1/AD1
P10/PW0/A0/AD0

VSS

P37/D15
P36/D14
P35/D13
P34/D12

P80/SCL0/TxD3

P81/SDA0/RxD3

P82/SCL1/TxD4

P83/SDA1/RxD4

9998979695949392919089888786858483828180797877767574737271706968676665

102

101

100

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

123456789

PA0/TMOX_0/ExPW6/SCK3

PA1/TMOY_0/ExPW7/SCK4

PA2/TMO0_0/ExTIOCC0/ExTCLKA

PA3/FTOB_0/CBLANK

PA4/FTIC_0/CLAMPO

PA5/FTIB_0/VFBACKI

PA6/FTCI_0/HFBACKI

1011121314151617181920212223242526272829303132333435363738

/TMIY_0/ExPW3

/TMI0_0/ExPW1

/TMIY_1/ExPW0

P46/ /TMIX_0/ExPW2

P45/

P44/

P47/

AVref

PB2/FTID_1/CSYNCI_1

PB1/TMO1_0/HSYNCO

PB0/FTOA_0/VSYNCO

AVCC

P07/AN15/

P06/AN14/

P05/AN13/

P04/AN12/

P03/AN11

P02/AN10

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

P01/AN9
P00/AN8
P77/AN7
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
AVSS
VSS
P43/

/TMIX_1
P42/ /TMI0_1
P41/ /FTIC_1
P40/ /FTIB_1
P57/TMO1_1/ExPW5
P56/TMO0_1/ExPW4
P55/RxD1
P54/TxD1
P53/SCK1
P52/RxD0
P51/TxD0
P50/SCK0
ETDO/PC7*

P31/D9/

P30/D8/

P33/D11/

P32/D10/

Note: * Not supported by the on-chip emulator.

Figure 1.2 Pin Assignment of H8S/2437 Group (FP-128B)

P66/TxD2/D6

P67/RxD2/D7

P65/SCK2/D5

P64/FTCI_1/D4

VSS

P61/FTOB_1/D1

P60/FTOA_1/D0

P63/TMOY_1/D3

P62/TMOX_1/D2

VCC

P93/

P94/

/ExTIOCA2

P91/

/ExTIOCB1/ExTCLKC

P90/

P95/ /

/ExTIOCB2/ExTCLKD

P92/

MD0

MD1

MD2

P96/

FWE

P97/ /ExTIOCD0/ExTCLKB

NMI

VCL

VSS

VCC

XTAL

EXTAL

VSS

ETDI/PC6*

ETCK/PC5*

ETMS/PC4*

Rev. 1.00, 09/03, page 3 of 704

1.3.2 Pin Assignment in Each Operating Mode

Table 1.1 Pin Assignment in Each Operating Mode

Pin
No.

QFP­128

1 D11 P33/ExIRQ3 P33/ExIRQ3 D3
2 D10 P32/ExIRQ2 P32/ExIRQ2 D2
3 D9 P31/ExIRQ1 P31/ExIRQ1 D1
4 D8 P30/ExIRQ0 P30/ExIRQ0 D0
5 D7 P67/RxD2 P67/RxD2 NC
6 D6 P66/TxD2 P66/TxD2 NC
7 D5 P65/SCK2 P65/SCK2 NC
8 D4 P64/FTCI_1 P64/FTCI_1 NC
9 D3 P63/TMOY_1 P63/TMOY_1 NC
10 D2 P62/TMOX_1 P62/TMOX_1 NC
11 D1 P61/FTOB_1 P61/FTOB_1 NC
12 D0 P60/FTOA_1 P60/FTOA_1 NC
13 VSS VSS VSS
14 P90/LWR/ExTIOCB1/ExTCLKC P90/ExTIOCB1/ExTCLKC A16
15 P91/CS2/ExTIOCA2 P91/ExTIOCA2 A17
16 VCC VCC VCC
17 P92/CS1/ExTIOCB2/ExTCLKD P92/ExTIOCB2/ExTCLKD A18
18 RD P93 NC
19 HWR P94 NC
20 P95/AS AH P95 NC
21 P96/φ P96/φ NC
22 P97/WAIT/ExTIOCD0/ExTCLKB P97/ExTIOCD0/ExTCLKB NC
23 MD0 MD0 VSS
24 MD1 MD1 VCC
25 MD2 MD2 VCC
26 FWE FWE VCC
27 NMI NMI VCC

Extended Mode (EXPE = 1) Single-Chip Mode
Normal Multiplex (EXPE = 0)

Pin Name

Flash Memory
Programmer Mode

Rev. 1.00, 09/03, page 4 of 704

Pin
No.

QFP­128

28 RES RES RES
29 VSS VSS VSS
30 VCL VCL VCL
31 VCC VCC VCC
32 EXTAL EXTAL EXTAL
33 XTAL XTAL XTAL
34 VSS VSS VSS
35 ETMS/PC4* ETMS/PC4* NC
36 ETCK/PC5* ETCK/PC5* NC
37 STBY STBY VCC
38 ETDI/PC6* ETDI/PC6* NC
39 ETRST ETRST RES
40 ETDO/PC7* ETDO/PC7* NC
41 P50/SCK0 P50/SCK0 NC
42 P51/TxD0 P51/TxD0 NC
43 P52/RxD0 P52/RxD0 NC
44 P53/SCK1 P53/SCK1 NC
45 P54/TxD1 P54/TxD1 NC
46 P55/RxD1 P55/RxD1 NC
47 P56/TMO0_1/ExPW4 P56/TMO0_1/ExPW4 NC
48 P57/TMO1_1/ExPW5 P57/TMO1_1/ExPW5 NC
49 P40/IRQ0/FTIB_1 P40/IRQ0/FTIB_1 VCC
50 P41/IRQ1/FTIC_1 P41/IRQ1/FTIC_1 VCC
51 P42/IRQ2/TMI0_1 P42/IRQ2/TMI0_1 VCC
52 P43/IRQ3/TMIX_1 P43/IRQ3/TMIX_1 VCC
53 VSS VSS VSS
54 AVSS AVSS VSS
55 P70/AN0 P70/AN0 NC
56 P71/AN1 P71/AN1 NC
57 P72/AN2 P72/AN2 NC
58 P73/AN3 P73/AN3 NC

Extended Mode (EXPE = 1) Single-Chip Mode
Normal Multiplex (EXPE = 0)

Pin Name

Flash Memory
Programmer Mode

Rev. 1.00, 09/03, page 5 of 704

Pin
No.

QFP­128

59 P74/AN4 P74/AN4 NC
60 P75/AN5 P75/AN5 NC
61 P75/AN6 P75/AN6 NC
62 P77/AN7 P77/AN7 NC
63 P00/AN8 P00/AN8 WE
64 P01/AN9 P01/AN9 OE
65 P02/AN10 P02/AN10 CE
66 P03/AN11 P03/AN11 NC
67 P04/AN12/ExIRQ4 P04/AN12/ExIRQ4 NC
68 P05/AN13/ExIRQ5 P05/AN13/ExIRQ5 NC
69 P06/AN14/ExIRQ6 P06/AN14/ExIRQ6 NC
70 P07/AN15/ExIRQ7 P07/AN15/ExIRQ7 NC
71 AVCC AVCC VCC
72 AVref AVref VCC
73 P44/IRQ4/TMIY_1/ExPW0 P44/IRQ4/TMIY_1/ExPW0 VCC
74 P45/IRQ5/TMI0_0/ExPW1 P45/IRQ5/TMI0_0/ExPW1 VCC
75 P46/IRQ6/TMIX_0/ExPW2 P46/IRQ6/TMIX_0/ExPW2 VCC
76 P47/IRQ7/TMIY_0/ExPW3 P47/IRQ7/TMIY_0/ExPW3 VCC
77 PB0/FTOA_0/VSYNCO PB0/FTOA_0/VSYNCO NC
78 PB1/TMO1_0/HSYNCO PB1/TMO1_0/HSYNCO NC
79 PB2/FTID_1/CSYNCI_1 PB2/FTID_1/CSYNCI_1 NC
80 PB3/FTIA_1/VSYNCI_1 PB3/FTIA_1/VSYNCI_1 NC
81 PB4/TMI1_1/HSYNCI_1 PB4/TMI1_1/HSYNCI_1 NC
82 PB5/FTID_0/CSYNCI_0 PB5/FTID_0/CSYNCI_0 NC
83 VCC VCC VCC
84 PB6/FTIA_0/VSYNCI_0 PB6/FTIA_0/VSYNCI_0 NC
85 PB7/TMI1_0/HSYNCI_0 PB7/TMI1_0/HSYNCI_0 NC
86 VSS VSS VSS
87 P87/ExTIOCB0/ADTRG P87/ExTIOCB0/ADTRG NC
88 P86/ExTIOCA0 P86/ExTIOCA0 NC
89 P85/PWX1 P85/PWX1 NC

Extended Mode (EXPE = 1) Single-Chip Mode
Normal Multiplex (EXPE = 0)

Pin Name

Flash Memory
Programmer Mode

Rev. 1.00, 09/03, page 6 of 704

Pin
No.

QFP­128

90 P84/PWX0 P84/PWX0 NC
91 PA7/CS3/ExTIOCA1 PA7/ExTIOCA1 NC
92 PA6/FTCI_0/HFBACKI PA6/FTCI_0/HFBACKI NC
93 PA5/FTIB_0/VFBACKI PA5/FTIB_0/VFBACKI NC
94 PA4/FTIC_0/CLAMPO PA4/FTIC_0/CLAMPO NC
95 PA3/FTOB_0/CBLANK PA3/FTOB_0/CBLANK NC
96 PA2/TMO0_0/ExTIOCC0/

97 PA1/TMOY_0/ExPW7/SCK4 PA1/TMOY_0/ExPW7/SCK4 NC
98 PA0/TMOX_0/ExPW6/SCK3 PA0/TMOX_0/ExPW6/SCK3 VCC
99 P83/SDA1/RxD4 P83/SDA1/RxD4 NC
100 P82/SCL1/TxD4 P82/SCL1/TxD4 NC
101 P81/SDA0/RxD3 P81/SDA0/RxD3 NC
102 P80/SCL0/TxD3 P80/SCL0/TxD3 NC
103 PC0/SCL2 PC0/SCL2 NC
104 PC1/SDA2 PC1/SDA2 NC
105 PC2/SCL3 PC2/SCL3 NC
106 PC3/SDA3 PC3/SDA3 NC
107 P27/A15 AD15 P27/TIOCB2/TCLKD A15
108 P26/A14 AD14 P26/TIOCA2 A14
109 P25/A13 AD13 P25/TIOCB1/TCLKC A13
110 P24/A12 AD12 P24/TIOCA1 A12
111 P23/A11 AD11 P23/TIOCD0/TCLKB A11
112 P22/A10 AD10 P22/TIOCC0/TCLKA A10
113 P21/A9 AD9 P21/TIOCB0 A9
114 P20/A8 AD8 P20/TIOCA0 A8
115 VCC VCC VCC
116 P17/A7 AD7 P17/PW7 A7
117 P16/A6 AD6 P16/PW6 A6
118 VSS VSS VSS
119 P15/A5 AD5 P15/PW5 A5

Extended Mode (EXPE = 1) Single-Chip Mode
Normal Multiplex (EXPE = 0)

PA2/TMO0_0/ExTIOCC0/

ExTCLKA

ExTCLKA

Pin Name

Flash Memory
Programmer Mode

VSS

Rev. 1.00, 09/03, page 7 of 704

Pin
No.

QFP­128

120 P14/A4 AD4 P14/PW4 A4
121 P13/A3 AD3 P13/PW3 A3
122 P12/A2 AD2 P12/PW2 A2
123 P11/A1 AD1 P11/PW1 A1
124 P10/A0 AD0 P10/PW0 A0
125 D15 P37 P37 D7
126 D14 P36 P36 D6
127 D13 P35 P35 D5
128 D12 P34 P34 D4

Note: * Not supported by the on-chip emulator.

Extended Mode (EXPE = 1) Single-Chip Mode
Normal Multiplex (EXPE = 0)

Pin Name

Flash Memory
Programmer Mode

Rev. 1.00, 09/03, page 8 of 704

1.3.3 Pin Functions

Table 1.2 Pin Functions

Type Symbol Pin No. I/O Name and Function

Power
supply

Clock XTAL 33 Input
EXTAL 32 Input

φ 21 Output Supplies the system clock to external devices.
Operating

mode control

System
control

STBY 37 Input When this pin is low, a transition is made to

FWE 26 Input Pin for use by flash memory.
Address bus A15 to A8

Data bus D15 to D8

data
multiplex
bus

VCC 16, 31,

83, 115

VCL 30 Input External capacitance pin for internal step-down

VSS 13, 29,

34, 53,
86, 118

MD2
MD1
MD0

RES 28 Input Reset pin. When this pin is low, the chip is reset.

A7 to A0

D7 to D0
AD15 to AD8 107 to 114 I/O Upper 8-bit, 16-bit bus Address/
AD7 to AD0 116, 117,

25
24
23

107 to 114,
116, 117,
119 to 124

125 to 4
5 to 12

119 to 124

Input Power supply pins. Connect all these pins to the

system power supply.

power. Connect this pin to Vss through an
external capacitor (that is located near this pin)
to stabilize internal step-down.

Input Ground pins. Connect all these pins to the

system power supply (0V).

For connection to a crystal resonator. An
external clock can be supplied from the EXTAL
pin. For an example of crystal resonator
connection, see section 21, Clock Pulse
Generator.

Input These pins set the operating mode. Inputs at

these pins should not be changed during
operation.

hardware standby mode.

Output Address output pins

I/O Bidirectional data bus

I/O Lower 16-bit bus

Rev. 1.00, 09/03, page 9 of 704

Type Symbol Pin No. I/O Name and Function

Bus control WAIT 22 Input Requests insertion of a wait state in the bus

cycle when accessing an external 3-state
address space.

RD 18 Output This pin is low when the external address space

is being read.

HWR 19 Output This pin is low when the external address space

is to be written to, and the upper half of the data
bus is enabled.

LWR 14 Output This pin is low when the external address space

is to be written to, and the lower half of the data
bus is enabled.

AS 20 Output This pin is low when address output on the

address bus is valid.
CS3 to CS1 91, 15, 17 Output Chip select signals for areas 3 to 1.
AH 20 Output Address latch signal for address/data multiplex

bus.
Interrupts

On-chip
emulator

NMI 27 Input Nonmaskable interrupt request input pin
IRQ7 to IRQ0 76 to 73

52 to 49

ExIRQ7 to
ExIRQ0

ETRST*

70 to 67
1 to 4

2

39 Input
ETMS 35 Input
ETDO 40 Output
ETDI 38 Input
ETCK 36 Input

Input These pins request a maskable interrupt.

Selectable to which pin of IRQn or ExIRQn to
input IRQ7 to IRQ0 interrupts.

Interface pins for the on-chip emulator.
Reset by holding the ETRST pin to low when
activating the H-UDI. At this time, the ETRST pin
should be held low for 20 clocks of ETCK. For
details, see section 24, Electrical
Characteristics. Then, to activate the H-UDI, the
ETRST pin should be set to 1 and desired
values should be set to the ETCK, ETMS, and
ETDI pins. When in the normal operation without
activating the H-UDI, the ETRST, ETCK, ETMS,
and ETDI pins should be set to 1 or high­impedance. Since these pins are internally
pulled up, care should be taken in the standby
state.

8-bit PWM
timer (PWM)

PW7 to PW0 116, 117,

119, 124

ExPW7 to
ExPW0

97, 98,
48, 47,

Output Pulse output pins for the PWM timer.

Selectable from which pin of PWn or ExPWn to
output PW5 to PW0.

76 to 73

Rev. 1.00, 09/03, page 10 of 704

Type Symbol Pin No. I/O Name and Function

14-bit PWM
timer
(PWMX)

16-bit free­running
timer (FRT)

8-bit timer
(TMR0,
TMR1,
TMRX,
TMRY)

PWX0
PWX1

FTCI_0
FTCI_1

FTOA_0
FTOA_1
FTOB_0
FTOB_1

FTIA_0 to
FTID_0
FTIA_1 to
FTID_1

TMO0_0
TMO0_1
TMO1_0
TMO1_1
TMOX_0
TMOX_1
TMOY_0
TMOY_1

TMI0_0
TMI0_1
TMI1_0
TMI1_1
TMIX_0
TMIX_1
TMIY_0
TMIY_1

90
89

92
8

77
12
95
11

84, 93,
94, 82
80, 49,
50, 79

96
47
78
48
98
10
97
9

74
51
85
81
75
52
76
73

Output Pulse output pins for PWM D/A

Input External event input pins

Output Output compare output pins

Input Input capture input pins

Output Waveform output pins with output compare

function

Input External event input pins and counter reset input

pins

Rev. 1.00, 09/03, page 11 of 704

Type Symbol Pin No. I/O Name and Function

16-bit timer
pulse unit
(TPU)

TIOCA0

TIOCA1

TIOCA2

Timer
connection

VSYNCO

Serial
communi­cation
interface
(SCI)

RxD0 to RxD4 43, 46, 5,

SCK0 to

TCLKA to
TCLKD
ExTCLKA to
ExTCLKD

TIOCB0
TIOCC0
TIOCD0
ExTIOCA0
ExTIOCB0
ExTIOCC0
ExTIOCD0

TIOCB1
ExTIOCA1
ExTIOCB1

TIOCB2
ExTIOCA2
ExTIOCB2

VSYNCI_0
VSYNCI_1
HSYNCI_0
HSYNCI_1
CSYNCI_0
CSYNCI_1
HFBACKI
VFBACKI

HSYNCO
CLAMPO
CBLANK

TxD0 to TxD4 42, 45, 6,

SCK4

107, 109,
111, 112
96, 22,
14, 17

114
113
112
111
88
87
96
22

110
109
91
14

108
107
15
17

84
80
85
81
82
79
92
93

77
78
94
95

102, 100

101, 99
41, 44, 7,

79, 97

Input External clock input pins. Selectable to which pin

of TCLKn or ExTCLKn to input external clocks.

I/O Input capture input/output compare output/PWM

output pins for TGR0A to TGR0D. Selectable
to/from which pin of TIOCn0 or ExTIOCn0 to
input/output input capture, output compare, and
PWM.

I/O Input capture input/output compare output/PWM

output pins for TGR1A to TGR1D. Selectable
to/from which pin of TIOCn1 or ExTIOCn1 to
input/output input capture, output compare, and
PWM.

I/O Input capture input/output compare output/PWM

output pins for TGR2A to TGR2D. Selectable
to/from which pin of TIOCn2 or ExTIOCn2 to
input/output input capture, output compare, and
PWM.

Input Synchronization signal input pins for the timer

connection

Output Synchronization signal output pins for the timer

connection

Output Transmit data output pins

Input Receive data input pins

I/O Clock input/output pins.

Rev. 1.00, 09/03, page 12 of 704

Type Symbol Pin No. I/O Name and Function

2

I2C bus
interface 3
(IIC3)

SCL0, SCL1
SCL2, SCL3

SDA0, SDA1
SDA2, SDA3

102, 100
103, 105

101, 99
104, 106

I/O I

I/O I

C clock input/output pins. These pins can drive

a bus directly with the NMOS open drain output.

2

C data input/output pins. These pins can drive

a bus directly with the NMOS open drain output.

AN15 to AN0 70 to 55 Input Analog input pins A/D

converter

ADTRG 87 Input External trigger input pin to start A/D conversion

AVCC 71 Input Analog power supply pin for the A/D converter.

When the A/D converter is not used, this pin
should be connected to the system power supply
(+3.3 V).

AVref 72 Input Reference power supply pin for the A/D

converter. When the A/D converter is not used,
this pin should be connected to the system
power supply (+3.3 V).

AVSS 54 Input Ground pin for the A/D converter. This pin

should be connected to the system power supply

(0 V).
I/O ports P07 to P00 70 to 63 Input Eight input pins
P17 to P10 116, 117,

I/O Eight input/output pins

119 to 124
P27 to P20 107 to 114 I/O Eight input/output pins
P37 to P30 125 to 4 I/O Eight input/output pins
P47 to P40 76 to 73,

I/O Eight input/output pins

52 to 49
P57 to P50 48 to 41 I/O Eight input/output pins
P67 to P60 5 to 12 I/O Eight input/output pins
P77 to P70 62 to 55 Input Eight input pins
P87 to P80 87 to 90

I/O Eight input/output pins

99 to 102
P97 to P90 22 to 14 I/O Eight input/output pins
PA7 to PA0 91 to 98 I/O Eight input/output pins
PB7 to PB0 85, 84,

I/O Eight input/output pins

82 to 77
PC7 to PC4*1 40, 38,

Input Four input pins

36, 35
PC3 to PC0 106 to 103 I/O Four input/output pins

Rev. 1.00, 09/03, page 13 of 704

Notes: 1. Not supported by the on-chip emulator.

2. Following precautions are required on the power-on reset signal that is applied to the
ETRST pin.
The reset signal must be applied at a power-on.
Apart the power-on reset circuit from this LSI to prevent the ETRST pin of the board
tester from affecting the operation of this LSI.
Apart the power-on reset circuit from this LSI to prevent the system reset of this LSI
from affecting the ETRST pin of the board tester.

Figure1.3 shows an example of design in which signals for reset do not affect each other.

Board edge pin

System
reset

Power-on
reset circuit

This LSI

Figure 1.3 Sample Design of Reset Signals without Affection Each Other

Rev. 1.00, 09/03, page 14 of 704

Section 2 CPU

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1 Features

• Upward-compatible with H8/300 and H8/300H CPUs

Can execute H8/300 and H8/300H object programs

• General-register architecture

Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-nine basic instructions

8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Multiply-accumulate instruction

• Eight addressing modes

Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]

• 16-Mbyte address space

Program: 16 Mbytes
Data: 16 Mbytes

• High-speed operation

All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 3 states
16 ÷ 8-bit register-register divide: 12 states
16 × 16-bit register-register multiply: 4 states
32 ÷ 16-bit register-register divide: 20 states

CPUS260A_020020020300

Rev. 1.00, 09/03, page 15 of 704

• Two CPU operating modes

Normal mode*
Advanced mode

• Power-down state

Transition to power-down state by SLEEP instruction
CPU clock speed selection

Note: Normal mode is not available in this LSI.

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration

The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.

• The number of execution states of the MULXU and MULXS instructions

Execution States
Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs,Rd 3 12
MULXU.W Rs,ERd 4 20
MULXS MULXS.B Rs,Rd 4 13
MULXS.W Rs,ERd 5 21

In addition, there are differences in addr ess space, CCR and EXR register functions, power-d own
modes, etc., depending on the model.

Rev. 1.00, 09/03, page 16 of 704

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.

• More general registers and control registers

Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.

• Expanded address space

Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.

• Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
A multiply-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multip le r e gisters have been added.
A test and set instruction has been added.

• Higher speed

Basic instructions execute twice as fast.

Note: Normal mode is not available in this LSI.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.

• Additional control register

One 8-bit and two 32-bit control registers have been added.

• Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.
A multiply-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multip le r e gisters have been added.
A test and set instruction has been added.

• Higher speed

Basic instructions execute twice as fast.

Rev. 1.00, 09/03, page 17 of 704

2.2 CPU Operating Modes

The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.

2.2.1 Normal Mode

The exception-handling vector table and stack have the same structure as in the H8/300 CPU.

• Address Space

The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.

When En is used as a 16-bit register it can contain any value, even when the corresponding
general register (Rn) is used as an address register. If the general register is referenced in the
register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a
carry or borrow occurs, however, the value in the corresponding extended register (En) will be
affected.

• Instruction Set

All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.

• Exception-handling Vector Table and Memory Indirect Branch Addresses

In normal mode the top area starting at H'0000 is allocated to the exception-handling vector
table. One branch address is stored per 16 bits. The exception-handling vector table in normal
mode is shown in figure 2.1. For details of the exception-handling vector table, see section 4,
Exception Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception-handling vector table.

• Stack Structure

When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack
in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the
stack in interrupt control mode 0. For details, see section 4, Exception Handling.

Note: Normal mode is not available in this LSI.

Rev. 1.00, 09/03, page 18 of 704

H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B

Reset exception-handling vector

(Reserved for system use)

(Reserved for system use)

Exception-handling vector 1

Exception-handling vector 2

Exception-handling
vector table

Figure 2.1 Exception-Handling Vector Table (Normal Mode)

SP

Notes:

1. When EXR is not used, it is not stored on the stack.

2. SP when EXR is not used.

3. lgnored when returning.

PC

(16 bits)

Figure 2.2 Stack Structure in Normal Mode

(SP

SP

1

EXR*

2

*

)

Reserved*
CCR
CCR*

(16 bits)

(b) Exception Handling(a) Subroutine Branch

PC

1

,

3

*

3

Rev. 1.00, 09/03, page 19 of 704

2.2.2 Advanced Mode

• Address Space

Linear access is provided to a 16-Mbyte maximum address space.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.

• Instruction Set

All instructions and addressing modes can be used.

• Exception-handling Vector Table and Memory Indirect Branch Addresses

In advanced mode the top area starting at H'00000000 is allocated to the exception-handling
vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch
address is stored in the lower 24 bits (figure 2.3). For details of the exception-handling vector
table, see section 4, Exception Handling.

H'00000000

Reset exception-handling vector
H'00000003
H'00000004

H'00000007
H'00000008

H'0000000B
H'0000000C

H'00000010

Reserved

Reserved

(Reserved for system use)

Exception-handling

vector table

(Reserved for system use)

Reserved

Exception-handling vector 1

Figure 2.3 Exception-Handling Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address.

Rev. 1.00, 09/03, page 20 of 704

In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch
address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch
addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of
this range is also used for the exception-handling vector table.

• Stack Structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not
pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception
Handling.

1

EXR*
Reserved*
CCR

PC

(24 bits)

1

,

3

*

SP

Reserved

PC

(24 bits)

SP

(SP

2

*

)

(a) Subroutine Branch (b) Exception Handling

Notes:1. When EXR is not used, it is not stored on the stack.

2. SP when EXR is not used.

3. Ignored when returning.

Figure 2.4 Stack Structure in Advanced Mode

Rev. 1.00, 09/03, page 21 of 704

2.3 Address Space

Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.

H'0000

64-kbyte 16-Mbyte

H'FFFF

Note: * Normal mode cannot be used in this LSI.

H'00000000

H'00FFFFFF

H'FFFFFFFF

Figure 2.5 Memory Map

Note: Normal mode is not available in this LSI.

Program area

Data area

Cannnot be
used in this LSI

(b) Advanced Mode(a) Normal Mode*

Rev. 1.00, 09/03, page 22 of 704

2.4 Registers

The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit
extended register (EXR), an 8-bit condition code register ( CCR), and a 64-bit multiply-accumulate
register (MAC).

General Registers (Rn) and Extended Registers (En)

15 0 7 0 7 0
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)

E0
E1
E2
E3
E4
E5
E6
E7

R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H

R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L

Control Registers (CR)

23

63 3241

MAC

31 0

Sign extension

MACL

[Legend]

Stack pointer

SP:

Program counter

PC:

Extended register

EXR:

Trace bit

T:

Interrupt mask bits

I2 to I0:

Condition-code register

CCR:

Interrupt mask bit

I:

User bit or interrupt mask bit*

UI:

Note: * UI cannot be used as an interrupt mask bit in this LSI.

Figure 2.6 CPU Registers

PC

76543210

T I2I1I0

EXR

----

76543210

CCR

IUIHUNZVC

H:

Half-carry flag

U:

User bit

N:

Negative flag

Z:

Zero flag

V:

Overflow flag

C:

Carry flag

MAC:

Multiply-accumulate register

0

MACH

Rev. 1.00, 09/03, page 23 of 704

2.4.1 General Registers

The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register . Figure 2.7 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.

The usage of each register can be selected independently.

General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.

• Address registers

• 32-bit registers

ER registers

(ER0 to ER7)

Figure 2.7 Usage of General Registers

Rev. 1.00, 09/03, page 24 of 704

• 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Free area

SP (ER7)

Stack area

Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instructio n the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least signif icant PC bit is regarded as 0.)

2.4.3 Extended Register (EXR)

EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC
instructions. When these instructions except for the STC instruction is executed, all inter r upts
including NMI will be masked for three states after execution is co mpleted.

Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

When this bit is set to 1, a trace exception-handling is
started each time an instruction is executed. When
this bit is cleared to 0, instructions are executed in
sequence.

6 to 3  All 1  Reserved

These bits are always read as 1.

2
1
0

I2
I1
I0

1
1
1

R/W
R/W
R/W

These bits designate the interrupt mask level (0 to 7).
For details, refer to section 5, Interrupt Controller.

Rev. 1.00, 09/03, page 25 of 704

2.4.4 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.

Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 by hardware at the start of an exception-handling
sequence. For details, refer to section 5, Interrupt
Controller.

6 UI Undefined R/W User Bit or Interrupt Mask Bit

Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions. This bit
cannot be used as an interrupt mask bit in this LSI.

5 H Undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or
NEG.L instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to 0
otherwise.

4 U Undefined R/W User Bit

Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit of data as a
sign bit.

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.

Rev. 1.00, 09/03, page 26 of 704

Bit Bit Name Initial Value R/W Description

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to indicate a carry

The carry flag is also used as a bit accumulator by bit
manipulation instructions.

2.4.5 Multiply-Accumulate Register (MAC)

This 64-bit register stores the results of multiply-accumulate operation s. It consists of two 32-bit
registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a
sign extension.

2.4.6 Initial Values of CPU Internal Registers

When the reset exception handling loads the start address from the vector address, PC is
initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1. Howev e r,
the general registers and the other CCR bits ar e not initialized. The initial value of SP (E R7) is
undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a
reset.

Rev. 1.00, 09/03, page 27 of 704

2.5 Data Formats

The H8S/2600 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data formats in general registers.

Data Type Register Number Data Format

70

65432710

Don't care

1-bit data

RnH

1-bit data

4-bit BCD data

4-bit BCD data

Byte data

Byte data

RnL

RnH

RnL

RnH

RnL

Don't care

7043

Upper Lower

Don't care

70

MSB LSB

Don't care

70

65432710

Don't care

7043

Upper Lower

70

MSB LSB

Figure 2.9 General Register Data Formats (1)

Don't care

Rev. 1.00, 09/03, page 28 of 704

Data Type Data FormatRegister Number

Word data

Word data

15 0

MSB LSB

Longword data

31 16

MSB

Rn

En

ERn

En Rn

[Legend]

General register ER

ERn:

General register E

En:

General register R

Rn:

General register RH

RnH:

General register RL

RnL:

Most significant bit

MSB:

Least significant bit

LSB :

Figure 2.9 General Register Data Formats (2)

15 0

MSB LSB

15 0

LSB

Rev. 1.00, 09/03, page 29 of 704

2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.

When ER7 is used as an address register to access the stack, the operand size should be word size
or longword size.

Data T ype Address

70

1-bit data

Byte data

Word data

Longword data Address 2N

Address L

Address L

Address 2M
Address 2M+1

Address 2N+1
Address 2N+2
Address 2N+3

76 543210

MSB

MSB

MSB

Figure 2.10 Memory Data Formats

Data Format

LSB

LSB

LSB

Rev. 1.00, 09/03, page 30 of 704

2.6 Instruction Set

The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2.1.

Table 2.1 Inst ruction Classification

Function Instructions Size Types

Data transfer MOV B/W/L 5
POP*1, PUSH*1 W/L
LDM, STM L
MOVFPE*3, MOVTPE*3 B

ADD, SUB, CMP, NEG B/W/L 23 Arithmetic

operations
INC, DEC B/W/L

ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
EXTU, EXTS W/L
TAS
MAC, LDMAC, STMAC, CLRMAC —
Logic operations AND, OR, XOR, NOT B/W/L 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

Branch Bcc*2, JMP, BSR, JSR, RTS — 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9
Block data transfer EEPMOV — 1
Total: 69

Notes: B: byte size; W: word size; L: longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in this LSI.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

@-SP respectively. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn
and MOV.L ERn, @-SP respectively.

ADDX, SUBX, DAA, DAS B

4

*

B

B 14

BIAND, BOR, BIOR, BXOR, BIXOR

Rev. 1.00, 09/03, page 31 of 704

2.6.1 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notation

Symbol Description

Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
MAC Multiply-accumulate register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division

∧ Logical AND
∨ Logical OR
⊕ Logical exclusive OR
→ Move

~ NOT (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Rev. 1.00, 09/03, page 32 of 704

Table 2.3 Data Transfer Instructions

Instruction Size* Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Transfers data between two general registers or between a general

register and memory, or transfers immediate data to a general register.
MOVFPE B Cannot be used in this LSI.
MOVTPE B Cannot be used in this LSI.
POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to

MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to

MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
LDM L @SP+ → Rn (register list)

Pops two or more general registers from the stack.
STM L Rn (register list) → @–SP

Pushes two or more general registers onto the stack.

Note: Size refers to the operand size.
B: Byte
W: Word
L: Longword

Rev. 1.00, 09/03, page 33 of 704

Table 2.4 Arithmetic Operations Instructions (1)

Instruction Size* Function

ADD
SUB

ADDX
SUBX

INC
DEC

ADDS
SUBS

DAA
DAS

MULXU B/W Rd × Rs → Rd

MULXS B/W Rd × Rs → Rd

DIVXU B/W Rd ÷ Rs → Rd

Note: Size refers to the operand size.
B: Byte
W: Word
L: Longword

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate b yte data can not
be subtracted from byte data in a general register. Use the SUBX or ADD
instruction.)

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on byte data in two
general registers, or on immediate data and data in a general register.

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands can
be incremented or decremented by 1 only)

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

B Rd (decimal adjust) → Rd

Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.

Performs unsigned multiplication on data in two general registers.
Either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs signed multiplication on data in two general registers.
Either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs unsigned division on data in two general registers.
Either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or
32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

Rev. 1.00, 09/03, page 34 of 704

Table 2.4 Arithmetic Operations Instructions (2)

Instruction Size*1 Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers.

Either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or

32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general

register or with immediate data, and sets CCR bits according to the

result.
NEG B/W/L 0 – Rd → Rd

Takes the two's comple ment (arithmetic complement) of data in a

general register.
EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by padding with zeros on the

left.
EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by extending the sign bit.
TAS*2 B @ERd – 0, 1 → (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.
MAC — (EAs) × (EAd) + MAC → MAC

Performs signed multiplication on memory contents and adds the result

to the multiply-accumulate register. The following operations can be

performed:

16 bits × 16 bits + 32 bits → 32 bits, saturating

16 bits × 16 bits + 42 bits → 42 bits, non-saturating
CLRMAC — 0 → MAC

Clears the multiply-accumulate register to zero.
LDMAC

STMAC

Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

L Rs → MAC, MAC → Rd

Transfers data between a general register and a multiply-ac c um ulate

register.

Rev. 1.00, 09/03, page 35 of 704

Table 2.5 Logic Operations Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another
general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another
general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and
another general register or immediate data.

NOT B/W/L ~ (Rd) → (Rd)

Takes the one's complement (logical complement) of general register
contents.

Note: Size refers to the operand size.
B: Byte
W: Word
L: Longword

Table 2.6 Shift Inst ructions

Instruction Size* Function

SHAL
SHAR

SHLL
SHLR

ROTL
ROTR

ROTXL
ROTXR

Note: Size refers to the operand size.
B: Byte
W: Word
L: Longword

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.

B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.

B/W/L Rd (rotate) → Rd

Rotates general register contents.
1-bit or 2-bit rotation is possible.

B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.

Rev. 1.00, 09/03, page 36 of 704

Table 2.7 Bit Manipulation Instructions (1)

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The

bit number is specified by 3-bit immediate data or the lower three bits of

a general register.
BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The

bit number is specified by 3-bit immediate data or the lower three bits of

a general register.
BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd >)

Inverts a specified bit in a general register or memory operand. The bit

number is specified by 3-bit immediate data or the lower three bits of a

general register.
BTST B ~ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets

or clears the Z flag accordingly. The bit number is specified by 3-bit

immediate data or the lowe r three bits of a general register.
BAND

BIAND

BOR

BIOR

Note: Size refers to the operand size.
B: Byte

B

B

B

B

C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general register or memory

operand and stores the result in the carry flag.

C ∧ [~ (<bit-No.> of <EAd>)] → C

ANDs the carry flag with the inverse of a specified bit in a general

register or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general register or memory

operand and stores the result in the carry flag.

C ∨ [~ (<bit-No.> of <EAd>)] → C

ORs the carry flag with the inverse of a specified bit in a general

register or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

Rev. 1.00, 09/03, page 37 of 704

Table 2.7 Bit Manipulation Instructions (2)

Instruction Size*1 Function

BXOR

BIXOR

BLD

BILD

BST

BIST

Note: Size refers to the operand size.
B: Byte

B

B

B

B

B

B

C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.

C ⊕ [~ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memo ry operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.

(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to
the carry flag.

~ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.

C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.

~ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.

Rev. 1.00, 09/03, page 38 of 704

Table 2.8 Branch Instructions

Instruction Size Function

Bcc — Branches to a specified address if a specified condition is true. The

branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC (BHS) Carry clear

(high or same)
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP — Branches unconditionally to a specified addre ss .
BSR — Branches to a subroutine at a specified address.
JSR — Branches to a subroutine at a specified address.
RTS — Returns from a subroutine

C = 0

Rev. 1.00, 09/03, page 39 of 704

Table 2.9 System Control Instructions

Instruction Size* Function

TRAPA — Starts trap-instruction exception handling.
RTE — Returns from an exception-handling routine.
SLEEP — Causes a transition to a power-down state.
LDC B/W (EAs) → CCR, (EAs) → EXR

Transfers the contents of a general register or memory, or immediate
data to CCR or EXR. Although CCR and EXR are 8-bit registers, word­size transfers are performed between them and memory. The upper 8
bits are valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with immediate data.

NOP — PC + 2 → PC

Only increments the program counter.

Note: Size refers to the operand size.
B: Byte
W: Word

Rev. 1.00, 09/03, page 40 of 704

Table 2.10 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B

EEPMOV.W

—

—

if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;

if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;

Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.

Execution of the next instruction begins as soon as the transfer is
completed.

2.6.2 Basic Instruction Formats

The H8S/2600 Series instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).

Figure 2.11 shows examples of instruction formats.

Rev. 1.00, 09/03, page 41 of 704

• Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.

• Register Field

Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.

• Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition Field

Specifies the branching condition of Bcc instructions.

(1) Operation field only

op

(2) Operation field and register fields

op

(3) Operation field, register fields, and effective address extension

op

EA (disp)

rn

rn rm

rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16, etc.

Figure 2.11 Instruction Formats (Examples)

Rev. 1.00, 09/03, page 42 of 704

2.7 Addressing Modes and Effective Address Calculation

The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address
modes are different in each instruction.

Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNO T, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)
4 Register indirect with post-increment

Register indirect with pre-decrement
5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8

@ERn+
@–ERn

2.7.1 Register Direct—Rn

The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing
the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to
E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.7.2 Register Indirect—@ERn

The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction code, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.

Rev. 1.00, 09/03, page 43 of 704

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn

Register indirect with post-increment—@ERn+:

The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for by te access, 2 for word transfer instruction, or 4 for
longword transfer instruction. For word or longword transfer instruction, the register value should
be even.

Register indirect with pre-decrement—@-ERn:

The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The resu lt is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For word or longword transfer instruction, the register value should be even.

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32

The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).

Table 2.12 Absolute Address Access Ranges

Absolute Address Normal Mode* Advanced Mode

Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF
32 bits (@aa:32) H'000000 to H'FFFFFF
Program instruction

address

Note: * Not available in this LSI.

Rev. 1.00, 09/03, page 44 of 704

24 bits (@aa:24)

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32

The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as
an operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data imp licitly . Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch
address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to
be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the
next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –
32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value
should be an even number.

2.7.8 Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).

In normal mode the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode the memory operand is a longword operand, the first byte of which is assumed to
be all 0 (H'00). Note that the first part of the address range is also the exception-handling vector
area. For further details, refer to section 4, Exception Handling.

If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)

Note: Norm al m ode is not available in this LSI.

Rev. 1.00, 09/03, page 45 of 704

Specified
by @aa:8

Branch address

Specified
by @aa:8

Reserved

Branch address

(a) Normal Mode

Note: * Normal mode is not available in this LSI.

*

(a) Advanced Mode

Figure 2.12 Branch Address Specification in Memory Indirect Mode

2.7.9 Effective Address Calculation

Table 2.13 indicates how effective addresses (EA) are calculated in each addressing mode. In
normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit
address.

Note: Norm al m ode is not available in this LSI.

Rev. 1.00, 09/03, page 46 of 704

Table 2.13 Effective Address Calculation (1)

No

Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1

Register direct (Rn)

op

rm

rn

2

Register indirect (@ERn)

op

r

Register indirect with displacement

3

@

(d:16,ERn) or @(d:32,ERn)

op

r

Register indirect with post-increment or

4

pre-decrement

•Register indirect with post-increment @ERn+

op

r

•Register indirect with pre-decrement @-ERn

op

r

disp

31

General register contents

31

General register contents

31

Sign extension

31

General register contents

31

General register contents

Operand Size
Byte
Word
Longword

Offset

1
2
4

disp

1, 2, or 4

1, 2, or 4

Operand is general register contents.

312331

0

Don't care

0

312331
Don't care

0

312331

0

Don't care

0

31

31
Don't care

24

24

24

23

24

0

0

0

0

Rev. 1.00, 09/03, page 47 of 704

Table 2.13 Effective Address Calculation (2)

Addressing Mode and Instruction Format

No

5

Absolute address

@aa:8

op

abs

Effective Address Calculation Effective Address (EA)

312331

Don't care

7

0

24

H'FFFF

8

@aa:16

@aa:24

op

@

aa:32

6

Immediate

#xx:8/#xx:16/#xx:32

7

Program-counter relative
@(d:8,PC)/@(d:16,PC)

8

Memory indirect @

• Normal mode*

op

24

23

Sign extension

16

H'00

16

15

15

0

0

0

0

0

31

0

0

0

0

31

Don't care

24

312331

Don't care

312331

24

Don't care

Operand is immediate data.

312331

24

Don't care

312331

24

Don't care

op

op

op

op

@aa:8

abs

abs

abs

abs

IMM

disp

23

PC contents

23

Sign

extension

31

H'000000

disp

78

abs

15

Memory contents

• Advanced mode

op

abs

Note: * Normal mode is not available in this LSI.

Rev. 1.00, 09/03, page 48 of 704

31

H'000000

31

Memory contents

0

78

abs

31

23

31

24

Don't care

0

0

2.8 Processing States

The H8S/2600 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.

• Reset State

The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes
low, all current processing stops and the CPU enters the reset state. All interrupts are masked
in the reset state. Reset exception handling starts when the RES signal changes from low to
high. For details, refer to section 4, Exception Handling.

The reset state can also be entered by a watchdog timer overflow.

• Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception-handling vector table and
branches to that address. For further details, refer to section 4, Exception Handling.

• Program Execution State

In this state the CPU executes program instructions in sequence.

• Bus-Released State

In a product which has a bus mastership other than the CPU, such as a direct memory access
controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when
the bus has been released in response to a bus request from a bus mastership other than the
CPU. While the bus is released, the CPU halts operations.

• Program stop state

This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further
details, refer to section 22, Power-Down Modes.

Rev. 1.00, 09/03, page 49 of 704

End of bus request

Bus request

Program execution state

SSBY = 1

SLEEP instruction

Bus request

nd of bus request

E

Bus-released state

End of exception handling

Exception

handling state

= High

Reset state

Reset state

Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever goes low.

A transition can also be made to the reset state when the watchdog timer overflows.

2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.

3. For details, refer to section 22, Power-Down Modes.

*1

Interrupt request

Request for exception handling

External interrupt request

= High,

= Low

SSBY = 0

SLEEP

instruction

Sleep mode

Software standby

mode

Hardware standby

*2

mode

Power down state

*3

Figure 2.13 State Transitions

2.9 Usage Note

2.9.1 Usage Notes on Bit-Wise Operation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in bytes, operate the
data in bit units, and write the result of the bit unit op eration in bits again. Therefore, special care
is necessary to use these instructions for the registers and the ports that include write-only bit.

The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time,
if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the
flag beforehand.

Rev. 1.00, 09/03, page 50 of 704

Section 3 MCU Operating Modes

3.1 Operating Mode Selection

This LSI has four operating modes (modes 1, 3, 5, and 7). These modes are determined by the
mode pin settings (MD2, MD1, and MD0). For normal program execution mode, the mode pins
must be set to mode 7. Do not change the mode pins while in the middle of an operation. Table 3.1
shows the MCU operating mode selection.

Table 3.1 MCU Operating Mode Selection

MCU Operating
Mode MD2 MD1 MD0

1 0 0 1 Boot mode Flash memory programming/erasing
3 0 1 1 Emulation On-chip emulation mode
5 1 0 1 User boot mode Flash memory programming/erasing
7 1 1 1 Advanced Single-chip mode with on-chip ROM

CPU Operating
Mode Description

enable extended mode

Modes 0, 2, 4, and 6 are not available with this LSI.

After a reset in mode 7, the operation is started in sin gle-chip mode. It is possible to shift to
extended mode when the EXPE bit in MDCR is set to 1.

Modes 1 and 5 are boot modes for flash memory programming/erasing. For details, refer to section
20, Flash Memory (0.18-µm F-ZTAT Version).

Mode 3 is on-chip emulation mode. The JTAG interface is controlled by the on-chip emulator, on­chip emulation is possible.

Rev. 1.00, 09/03, page 51 of 704

3.2 Register Descriptions

The following registers are related to the operating mode.

• Mode control register (MDCR)

• System control register (SYSCR)

3.2.1 Mode Control Register (MDCR)

MDCR monitors the current operating mode and operating mode settings.

Bit Bit Name Initial Value R/W Descriptions

7 EXPE 0 R/W Extended Mode Enable

Extended Mode Set Up
0: Single-chip mode

1: Extended mode
6 to 3  All 0 R Reserved
2
1
0

Note: * Determined by pins MD2 to MD0.

MDS2
MDS1
MDS0

*
*
*

R
R
R

Mode Select 2 to 0

These bits indicate the input levels at pins MD2 to

MD0 (the current operating mode). Bits MDS2 to

MDS0 correspond to MD2 to MD0. MDS2 to

MDS0 are read-only bits and they cannot be

written to

The mode pin (MD2 to MD0) input levels are

latched into these bits when MDCR is read.

These latches are canceled by a reset

Rev. 1.00, 09/03, page 52 of 704

3.2.2 System Control Register (SYSCR)

SYSCR selects saturating calculation for the MAC instruction, and controls reset source monitor,
Ram address space, and on-chip flash memory control.

Bit Bit Name Initial Value R/W Descriptions

7 MACS 0 R/W MAC Saturation

Selects either saturating or non-saturating calculation
for the MAC instruction.

0: Non-saturating calculation for MAC instruction
1: Saturating calculation for MAC instruction

6 to 4  All 0 R/W Reserved

The initial value should not be changed.

3 XRST 1 R External Reset

Indicates reset source. Reset occurs as external reset
input or watchdog timer overflow.

0: Generated by watchdog timer overflow
1: Generated by external reset

2 FLASHE 0 R/W Flash Memory Control Register Enable

Controls CPU access to the flash memory control
registers (FCCS, FPCS, FECS, FKEY, FMATS, and
FTDAR).

0: Flash memory control registers are not selected
1: Flash memory control registers are selected

1  0 R/W Reserved

The initial value should not be changed.

0 RAME 1 R/W RAM Enable

Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset status is released.

0: On-chip RAM is disabl ed
1: On-chip RAM is enabled

Rev. 1.00, 09/03, page 53 of 704

3.3 Operating Mode Descriptions

3.3.1 Mode 7

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The initial mode after a reset is single-chip mode, to use the external address space, set the EXPE
bit in MDCR to 1.

Normal Extended Mode:

After a reset, ports 1 and 2 become input ports.

The address bus can be output when the corresponding port data direction register (DDR) is set to

1. Port 3 is a data bus, part of port 9 and port A become a bus control signal. When the ABWn bit
in BCRAn is cleared to 0, port 6 becomes the data bus. (n = 1 to 3)

Multiplex Extended Mode:

When using an 8-bit bus, regardless of the data direction register (DDR) setting of port 2, it
becomes an address output and data input/output port. Port 1 can be used as a general port.

When using a 16-bit bus, regardless of the data direction register (DDR) setting of port 1 or 2, they
become address output and data input/output ports.

Rev. 1.00, 09/03, page 54 of 704

3.3.2 Pin Functions

The pin functions of ports 1 to 3, 6, 9, and A change according to operating modes. Table 3.2
shows the pin functions in each operating mode.

Table 3.2 Pin Functions in Each Operating Mode

Mode 7

Port Normal Extended Mode Multiplex Extended Mode

Port 1 P*/A P*/AD
Port 2 P*/A P*/AD
Port 3 P*/D P*
Port 6 P*/D P*
Port 9 P*/C P*/C
Port A PA7 P*/C P*/C

[Legend]
P: Input/output port
A: Address bus output
D: Data bus input/output
AD: Address data multiplex input/output
C: Control signals, clock input/output
Note: * After a reset

Rev. 1.00, 09/03, page 55 of 704

3.4 Memory Map

Figure 3.1 shows a memory map.

ROM : 256 kbytes, RAM : 16 kbytes ROM : 256kbytes, RAM : 16kbytes

Mode 7 (EXPE = 1)
Advanced mode
External mode with on-chip ROM enabled

Mode 7 (EXPE = 0)
Advanced mode
Single-chip mode

H'000000

H'03FFFF

H'040000

H'07FFFF
H'080000

H'FBFFFF
H'FC0000
H'FCFFFF

H'FD0000
H'FDFFFF
H'FE0000
H'FEFFFF
H'FF0000

H'FF6000

H'FF9FFF
H'FFA000

H'FFBFFF
H'FFC000

H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80

H'FFFFFF

On-chip ROM

Reserved

External

address space

Area 1
Area 2

Area 3

Reserved

On-chip RAM

16384 bytes

Reserved

Internal I/O register 2

Reserved

Internal I/O register 1

*

*

H'000000

H'03FFFF
H'040000

H'07FFFF
H'080000

H'FF0000

H'FF6000

H'FF9FFF
H'FFA000

H'FFBFFF
H'FFC000

H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80

H'FFFFFF

On-chip ROM

Reserved

Reserved

Reserved

On-chip RAM

16384 bytes

Reserved

Internal I/O register 2

Reserved

Internal I/O register 1

Note :

*

This area can be specified as an external address area by clearing the RAME bit in SYSCR to 0.

Rev. 1.00, 09/03, page 56 of 704

Figure 3.1 Memory Map

Section 4 Exception Handling

4.1 Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.

Table 4.1 Exception Types and Priority

Priority Exception Type Start of Exception Handling

High Reset Starts immediately after a low-to-high transition at the RES

pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low

Trace*1 Starts when execution of the current instruction or exception

handling ends, if the trace (T) bit in the EXR is set to 1.

Direct transition*2 Starts when the direct transition occurs by execution of the

SLEEP instruction.

Interrupt Starts when execution of the current instruction or exception

handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on completion
of reset exception handling.

Low Trap instruction Started by execution of a trap instruction (TRAPA)

Trap instruction exception handling requests are accepted at
all times in program ex ecution state.

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not

executed after execution of an RTE instruction.

2. Not available in this LSI.

Rev. 1.00, 09/03, page 57 of 704

4.2 Exception Sources and Exception Vector Table

Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.

Table 4.2 Exception HandlingVector Table

Vector Address*1
Exception Source Vector Number Normal Mode*

Power-on reset 0 H'0000 to H'0001 H'0000 to H'0003
Manual reset*3 1 H'0002 to H'0003 H'0004 to H'0007
Reserved for system use 2 H'0004 to H'0005 H'0008 to H'000B
3 H'0006 to H'0007 H'000C to H'000F
4 H'0008 to H'0009 H'0010 to H'0013
Trace 5 H'000A to H'000B H'0014 to H'0017
Interrupt (direct transition)*3 6 H'000C to H'000D H'0018 to H'001B
Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F
Trap instruction (#0) 8 H'0010 to H'0011 H'0020 to H'0023

(#1) 9 H'0012 to H'0013 H'0024 to H'0027
(#2) 10 H'0014 to H'0015 H'0028 to H'002B

(#3) 11 H'0016 to H'0017 H'002C to H'002F
Reserved for system use 12 H'0018 to H'0019 H'0030 to H'0033
13 H'001A to H'001B H'0034 to H'0037
14 H'001C to H'001D H'0038 to H'003B
15 H'001E to H'001F H'003C to H'003F
External interrupt IRQ0 16 H'0020 to H'0021 H'0040 to H'0043
IRQ1 17 H'0022 to H'0023 H'0044 to H'0047
IRQ2 18 H'0024 to H'0025 H'0048 to H'004B
IRQ3 19 H'0026 to H'0027 H'004C to H'004F
IRQ4 20 H'0028 to H'0029 H'0050 to H'0053
IRQ5 21 H'002A to H'002B H'0054 to H'0057
IRQ6 22 H'002C to H'002D H'0058 to H'005B
IRQ7 23 H'002E to H'002F H'005C to H'005F
Internal interrupt*4 24


127

H'0030 to H'0031

H'00FE to H'00FF

2

Advanced Mode

H'0060 to H'0063

H'01FC to H'01FF

Rev. 1.00, 09/03, page 58 of 704

Notes: 1. Lower 16 bits of the address.

2. Not available in this LSI.

3. Not available in this LSI. Becomes reserved for system use.

4. For details on internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.

4.3 Reset

A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the re gisters of on-chip peripheral modules.

The chip can also be reset by overflow of the watchdog timer. For details see section 15,
Watchdog Timer (WDT).

The interrupt control mode is 0 immediately after reset.

4.3.1 Reset exception handling

When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip peripheral modules are

initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.

2. The reset exception-handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Figure 4.1 shows an example of th e reset sequence.

Rev. 1.00, 09/03, page 59 of 704

Vector fetch

φ

Internal
processing

Prefetch of first
program instruction

Internal
address bus

Internal read
signal

Internal write
signal

Internal data
bus

(1)(3) Reset exception-handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception-handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction

(1)

High

(2) (4) (6)

(3) (5)

Figure 4.1 Reset Sequence

4.3.2 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash . To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, mak e sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).

4.3.3 On-Chip Peripheral Functions after Reset Release

After reset release, the module stop contro l register ( M STPCR, EXMSTPCR) is initialized and all
modules enter module stop mode.

Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when module stop mode is exited.

Rev. 1.00, 09/03, page 60 of 704

4.4 Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5,
Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows
the state of CCR and E X R a fter execution of trace exception handling. Trace mode is canceled by
clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control
is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.
Trace exception-handling is not carried out after execution of the RTE instruction.

Interrupts are accepted even within the trace exception-handling routine.

Table 4.3 Status of CCR and EXR after Trace Exception Handling

CCR EXR
Interrupt Control Mode I UI I2 to I0 T

0 Trace exception handling cannot be used.
2 1   0

[Legend]
1: Set to 1
0: Cleared to 0
: Retains value prior to execution.

4.5 Interrupts

Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. For details on the source that starts interrupt exception handling and
the vector address, refer to section 5, Interrupt Controller.

The interrupt exception handling is as follows:

1. The values in the program counter (PC), condition code register (CCR), an d extended register

(EXR) are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution starts from that address.

Rev. 1.00, 09/03, page 61 of 704

4.6 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.

The trap instruction exception handling is as follows:

1. The values in the program counter (PC), condition code register (CCR), an d extended register
(EXR) are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.

Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.

Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling

CCR EXR
Interrupt Control Mode I UI I2 to I0 T

0 1   
2 1   0

[Legend]
1: Set to 1
0: Cleared to 0
: Retains value prior to execution.

Rev. 1.00, 09/03, page 62 of 704