RENESAS H8S-2378R User Manual

REJ09B0109-0500

The revision list can be viewed directly by clicking the title page.

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

H8S/2378, H8S/2378R Group

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family/H8S/2300 Series

Rev. 5.00 Revision Date: Nov 18, 2005

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Rev. 5.00 Nov 18, 2005 page ii of lxii

General Precautions on Handling of Product

1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.

3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.

Rev. 5.00 Nov 18, 2005 page iii of lxii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Main Revisions and Additions in this Edition (only for revised versions)

5. Contents

6. Overview

7. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section.

8. List of Registers

9. Electrical Characteristics

10.Appendix

The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual.

11.Index

Rev. 5.00 Nov 18, 2005 page iv of lxii

Preface

The H8S/2378 Group and H8S/2378R Group microcomputers (MCU) made up of the H8S/2000 CPU employing Renesas Technology's original architecture as their cores, and the peripheral functions required to con fig ure a sys tem.

The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space.

This LSI is equipped with direct memory access controller (DMAC and EXDMAC) and data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication interface (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as on-chip peripheral modules required for system configuration. I can also be included as an optional interface.

A high functionality bus controller is also provided, enabling fast and easy connection of DRAM and other kinds of memory.

A single-power flash memory (F-ZTAT

) version is available for this LSI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change.

C bus interface 2 (IIC2)

This manual describes this LSI's hardware.

Note: * F-ZTAT is a trademark of Renesas Technology Corp.

Target Users: This manual was written for users who will be using this LSI in the design of

application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of this LSI to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instru ction se t.

Notes on reading this manual:

In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.

Rev. 5.00 Nov 18, 2005 page v of lxii

In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual. For the execution state of each instruction in this LSI, see Appendix D, Bus State during

Execution of Instructions.

In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 25, List of Registers.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel

number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal:

xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require. http://www.renesas.com/

H8S/2378 Group and H8S/2378R Group manuals:

Manual Title Document No.

H8S/2378 Group,H8S/2378R Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139-0300O

User's manuals for development tools:

Manual Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual

H8S, H8/300 Series Simulator/Debugger User's Manual REJ10B0211-0200 H8S, H8/300 Series High-performance Embedded Workshop,

High-performance Debugging Interface Tutorial High-performance Embedded Workshop User's Manual REJ10J0886-0300

Rev. 5.00 Nov 18, 2005 page vi of lxii

REJ10B0058-0100H

ADE-702-231

Main Revisions for this Edition

Item Page Revisions (See Manual for Details)

All  LGA package newly added

1.1 Features 1 Description amended

• On-chip memory

ROM Type Model

Flash memory version HD64F2378B

2 • General I/O ports

I/O pins: Input-only pins: 17

• Compact package

Package (Code) Body Size Pin Pitch

FP-144 FP-144H (FP-144HV*) 22.0 LGA-145 TLP-145V

× 22.0 mm 0.5 mm

9.0 × 9.0 mm 0.65 mm

1.3.1 Pin Arrangement Figure 1.11 Pin

Arrangement (TLP145V: Top View)

1.3.2 Pin Arrangement in Each Operating Mode

Table 1.1 Pin Arrangement in Each Operating Mode

1.3.3 Pin Functions Table 1.2 Pin

Functions

4.6 Trap Instruction Exception Handling

Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling

13 Newly added

14 to 19 LGA-145 added, Pin No. 145 added

20 to 34 LGA-145 added

93 Table amended

Interrupt Control Mode

0  2  0

I2 to I0 T

EXR

Rev. 5.00 Nov 18, 2005 page vii of lxii

Item Page Revisions (See Manual for Details)

7.4.2 Activation by External Request

303 Note * added

If an external request (

DREQ

pin) is specified as a DMAC activation source, the relevant port should be set to input mode in advance*.

Note: * If the relevant port is set as an output pin for another function, DMA transfers using the channel in question cannot be guaranteed.

15.3.9 Bit Rate Register (BRR)

Table 15.3 BBR Settings for Various Bit Rates (Asynchronous Mode)

Table 15.4 Maximum Bit Rate for Each

747 Table amended

25 30 33

Bit Rate (bit/s)

110

3 110 –0.02 3 132 0.13 3 145 0.33 3 154 0.23

150

3 80 –0.47 3 97 –0.35 3 106 0.39 3 113 –0.06

300

2 162 0.15 2 194 0.16 2 214 –0.07 2 227 –0.06

600

2 80 –0.47 2 97 –0.35 2 106 0.39 2 113 –0.06

1200

1 162 0.15 1 194 0.16 1 214 –0.07 1 227 –0.06

2400

1 80 –0.47 1 97 –0.35 1 106 0.39 1 113 –0.06

4800

0 162 0.15 0 194 0.16 0 214 –0.07 0 227 –0.06

9600

0 80 –0.47 0 97 –0.35 0 106 0.39 0 113 –0.06

19200

0 40 –0.76 0 48 –0.35 0 53 –0.54 0 56 –0.06

31250

0 24 0.00 0 29 0.00 0 32 0.00 0 34 0.00

38400

0 19 1.73 0 23 1.73 0 26 –0.54 0 27 1.73

Note: * Supported on the H8S/2378 and H8S/2378R only.

748

φ (MHz) Maximum Bit Rate (bit/s) n N

Operating Frequency φ (MHz)

Error

(%)

1093750 0 0

Error (%) N

Frequency (Asynchronous Mode)

Error (%)

n N

Error (%)

Table 15.5 Maximum Bit Rate with External

749

φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)

Clock Input (Asynchronous Mode)

Rev. 5.00 Nov 18, 2005 page viii of lxii

8.7500 546875

Item Page Revisions (See Manual for Details)

15.3.9 Bit Rate Register (BRR)

Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

750

Table amended

Operating Frequency φ (MHz)

Bit Rate (bit/s)

110

250 3 124 —— 3 249

500 2 249 —— 3 124 —— 3 233

1 k 2 124 —— 2 249 —— 3 97 3 116 3 128 3 136

2.5 k 1 199 1 249 2 99 2 124 2 155 2 187 2 205 2 218

5 k 1 99 1 124 1 199 1 249 2 77 2 93 2 102 2 108

10 k 0 199 0 249 1 99 1 124 1 155 1 187 1 205 1 218

25 k 0 79 0 99 0 159 0 199 0 249 1 74 1 82 1 87

50 k 0 39 0 49 0 79 0 99 0 124 0 149 0 164 0 174

100 k 0 19 0 24 0 39 0 49 0 62 0 74 0 82 0 87

250 k 0 7 0 9 0 15 0 19 0 24 0 29 0 32 0 34

500 k 0 3 0 4 0 7 0 9 —— 014 —— —

1 M 0 1 0 3 0 4 —— —— —— ———

2.5 M 0 0

5 M 0*—— —— —— ——

8101620253033

nN nN nN nN nN nN nN nN

01 —— 02 —— ——

Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)

Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S =

372) Table 15.9 Maximum

Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372)

751

752

φ (MHz)

External Input Clock (MHz)

Maximum Bit Rate (bit/s)

20 3.3333 3333333.3

25 4.1667 4166666.7

30 5.0000 5000000.0

33 5.5000 5500000.0

Bit Rate (bit/s)

9600 0 3 5.01 0 4 7.59 0 4 1.99

5.8336 5833625.0

Operating Frequency φ (MHz)

30.00 33.00

Error (%) n N

35.00

Error (%)

Maximum Bit

φ (MHz)

Rate (bit/s) n N

20.00 26882 0 0

25.00 33602 0 0

30.00 40323 0 0

33.00 44355 0 0

35.00

47043 0 0

Rev. 5.00 Nov 18, 2005 page ix of lxii

Item Page Revisions (See Manual for Details)

15.8 IrDA Operation

Table 15.12 Settings of Bits IrCKS2 to IrCKS0

794 Table amended

Operating Frequency φ (MHz) 78.13 19.53 9.77 4.88 3.26 1.63

2400 9600 19200 38400 57600 115200

110 110 110 110 110 —

Bit Rate (bps) (Above)/Bit Period × 3/16 (µs) (Below)

Section 16 I2C Bus Interface 2 (IIC2) (Option)

16.3.1 I2C Bus Control Register A (ICCRA)

Table 16.2 Transfer Rate

805 Description of 2. deleted

810 Table amended

Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate

CKS3 CKS2 CKS1 CKS0

Clock

0 φ/28 286 kHz 357 kHz 714 kHz 893 kHz 1179 kHz 1250 kHz0 1 φ/40 200 kHz 250 kHz 500 kHz 625 kHz 825 kHz 0 φ/48 167 kHz 208 kHz 417 kHz 521 kHz 688 kHz 729 kHz 1 φ/64 125 kHz 156 kHz 313 kHz 391 kHz 516 kHz 0 φ/168 47.6 kHz 59.5 kHz 119 kHz 149 kHz 196 kHz 208 kHz0 1 φ/100 80.0 kHz 100 kHz 200 kHz 250 kHz 330 kHz 0 φ/112 71.4 kHz 89.3 kHz 179 kHz 223 kHz 295 kHz 313 kHz 1 φ/128 62.5 kHz 78.1 kHz 156 kHz 195 kHz 258 kHz 0 φ/56 143 kHz 179 kHz 357 kHz 446 kHz 589 kHz 625 kHz0 1 φ/80 100 kHz 125 kHz 250 kHz 313 kHz 413 kHz 0 φ/96 83.3 kHz 104 kHz 208 kHz 260 kHz 344 kHz 365 kHz 1 φ/128 62.5 kHz 78.1 kHz 156 kHz 195 kHz 258 kHz 0 φ/336 23.8 kHz 29.8 kHz 59.5 kHz 74.4 kHz 98.2 kHz 104 kHz0 1 φ/200 40.0 kHz 50.0 kHz 100 kHz 125 kHz 165 kHz 0 φ/224 35.7 kHz 44.6 kHz 89.3 kHz 112 kHz 147 kHz 156 kHz 1 φ/256 31.3 kHz 39.1 kHz 78.1 kHz 97.7 kHz 129 kHz

φ = 8 MHz

φ = 10 MHz

φ = 20 MHz

φ = 25 MHz

φ = 33 MHz

φ = 35 MHz

875 kHz

547 kHz

350 kHz

273 kHz

438 kHz

273 kHz

175 kHz

137 kHz

Rev. 5.00 Nov 18, 2005 page x of lxii

Item Page Revisions (See Manual for Details)

16.3.5 I

C Bus Status

817 Table amended

Bit

Initial

Bit

Name

Value R/W Description

3 STOP 0 R/W Stop condition detection flag

[Setting condition]

•

In master mode, when a stop condition is detected after frame transfer

•In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR

[Clearing condition]

•When 0 is written in STOP after reading STOP = 1

16.7 Usage Notes 837 Newly added

17.1 Features 839 Description amended — Conversion time: 7.4 µs per channel (at 35 MHz operation)

21.1 Features 897

Description of User branch function added

21.3.2 Programming/

Erasing Interface Parameter

Table 21.4 Parameter and Target Modes

915, 916 Description amended

When download, initialization, or on-chip program is executed, registers of the CPU except for ER0 and ER1 are stored.

Table amended

Name of Parameter

Flash programm ing/ erasing frequency control

Flash user bra nch address set

Flash multi purpose addr ess area

Flash multi purpose data destinatio n area

Abbrevi a-

Down

tion

Load

FPEFEQ

—

FUBRA

—

FMPAR R/W Undefined ER1 of

—

FMPDR R/W Undefined ER0 of

Initializa-

Program-

tion

ming Er asure R/W

—

Initial Value

R/W Undefined ER0 of

R/W Undefined ER1 of

Allocation

CPU

Rev. 5.00 Nov 18, 2005 page xi of lxii

Item Page Revisions (See Manual for Details)

21.3.2 Programming/ Erasing Interface Parameter

(2) Programming/ Erasing Initialization

918 (a) Flash programming/erasing frequency parameter (FPEFEQ:

general resister ER0 of CPU) Description amended This parameter sets the operating frequency of the CPU and

enables the user branch function.

Bit

Name

FUBF15 to

31 to

FUBF0

15 to 0 F15 to F0 — R/W Frequency Set

Initial Value R/W Description

—

R/W Set to H'AAFF if the user branch function is enabled by

the flash user branch enable bit. Otherwise, set to H'0000.

Set the operating frequency of the CPU. The setting value must be calculated as the following methods.

1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places.

2. The value multiplied by 100 is converted to the binary digit and is written to the FPEFEQ parameter (general register ER0).

For example, when the operating frequency of the CPU

35.000 MHz, the value is as follows.

1. The number to three decimal places of 35.000 is rounded and the value is thus

2. The formula that 35.00 × 100 = 3500 is converted to the binary digit and B'0000,1101,

H'0DAC) is set to R0.

(

919 (b) Flash user branch address setting parameter (FUBRA:

general register ER1 of CPU) Added

920

Table amended

Bit

Initial

Name

Value R/W Description

7 to 3  Unused

Return 0

2 BR  R/W User Branch Error Detect (BR)

Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programmi ng/erasing program which has been downloaded.

0: User branch address setting

is normal

1: User branch address setting

is abnormal

35.00.

1010,1100

Rev. 5.00 Nov 18, 2005 page xii of lxii

Item Page Revisions (See Manual for Details)

21.3.2 Programming/ Erasing Interface Parameter

(2) Programming/ Erasing Initialization

922 (3) Programming Execution

Table amended

Bit

Initial

Name

Value R/W Description

5EE R/W Programming Execution Error

Detect 1 is returned to this bit when the

specified data could not be written because the user MAT was not erased or when flashmemory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT.

If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT are not rewritten. Programming of the user boot MAT should be performed in boot mode or PROM mode.

0: Programming has ended 1: Programming has ended

normally abnormally (programmi ng

result is not guaranteed)

(4) Erasur e Execution 924 (a) Flash erase blo ck select parameter (FEBS: general register

ER0 of CPU) Description amended This parameter specifies the erase-block number.

Bit

7 to 0 EBN7 to

Initial

Name

Value R/W Description

— R/W Erase Block Number

EBN0

Set an erase-block number within the range from 0 to 15. H'00 corresponds to the EB0 block and H'0F corresponds to the EB15 block. An error occurs if a number outside the range from H'00 to H'0F is set..

Rev. 5.00 Nov 18, 2005 page xiii of lxii

Item Page Revisions (See Manual for Details)

21.3.2 Programming/ Erasing Interface Parameter

(4) Erasure Execution

924, 925 (b) Flash pass/fail parameter (FPFR: general register R0L of

CPU) Table amended

Bit

5EE R/W Erasure Execution Error Detect

Initial

Name

Value R/W Description

MD  R/W Programming Mode Related

Setting Error Detect Returns the check result of

whether the error protection state is entered. The error protection state is entered, 1 is written to this bit. The error protection state can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 21.5.3, Error Protection.

0: FLER setting is normal

(FLER = 0)

1: FLER = 1 and programming

cannot be performed

1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT are not erased. Erasing of the user boot MAT should be performed in boot mode or PROM mode.

0: Erasure has ended normally 1: Erasure has ended

on returning from the

abnormally (erasure result is not guaranteed)

Rev. 5.00 Nov 18, 2005 page xiv of lxii

Item Page Revisions (See Manual for Details)

21.4.2 User Program

933 Figure amended

Mode (2) Programming

Procedure in User Program Mode

Figure 21.11 Programming Procedure

DPFR = 0?

Set the FPEFEQ, FUBRA

parameter

Initialization

JSR FTDAR setting + 32

Initialization

FPFR = 0?

Yes

Download error processing

Initialization error processing

936 Description amended

6.The FPEFEQ and FUBRA parameters are set for initialization.

The allowable setting range for the FPEFEQ parameter is 8 MHz to 35 MHz. When the ...

— Set the user branch destination address as the FUBRA parameter (general register ER1) and the user branch enable bits (FUBE15 to FUBE0) as the FPEFEQ parameter (general register ER0). Set FUBRA and FUBE15 to FUBE0 to 0 if the user branch function is not required.

Do use programmable user MAT as the user branch destination. Also, do not use an area containing a downloaded internal program as the user branch destination. After user branch processing completes, use the RTS instruction to return to programming processing.

For details, see the descriptions in 21.3.2 (2) (a), Flash programming/erasing frequency parameter (FPEFEQ), and

21.3.2 (2) (b), Flash user branch address setting parameter

(FUBRA). — The general registers other than ER0, ER1 are held in the

initialization program.

FPFR = 0?

Yes

Required data

programming is

completed?

Yes

Programming finished

processing

JSR FTDAR setting + 16

FPFR = 0?

Yes

Clear FKEY to 0

End programming procedure program

13.

Clear FKEY and

programming

error processing

14.

15.

16.

Clear FKEY and

programming

error processing

17.

Rev. 5.00 Nov 18, 2005 page xv of lxii

Item Page Revisions (See Manual for Details)

21.4.2 User Program Mode

(2) Programming Procedure in User Program Mode

938, 939 Description amended

12. Programming  The general registers other than ER0 and ER1 are held in

the programming program.

15. Execution of Programming Finished Processing — Data is stored in a general register other than ER0, ER1 by

the programming finished program. : — Only perform programming finished processing once per

block. Even if multiple 128-byte programming operations have been performed to the same block, programming finished processing should only be carried out once. (Due not perform programming finished processing multiple times.) If it is necessary to reprogram blocks within a previously programmed area on which programming finished processing has been performed, first erase the blocks in question and then reprogram them.

— Programming finished processing should be performed on all blocks containing areas that have been programmed after initialization processing. For example, if programming finished processing is to be carried out once after programming blocks EB1 to EB3, programming finished processing should be performed individually on EB1, EB2, and EB3.

939 Description added

16. Determine the FPFR (general-purpose register R0L) value returned by the programming program.

(3) Erasing Procedure

940 Figure amended

in User Program Mode Figure 21.12 Erasing

Procedure

Set the FPEFEQ, FUBRA

parameter

Initialization

JSR FTDAR setting

+ 32

941 Description amended

• The general registers other than ER0, ER1 are held in the erasing program.

Rev. 5.00 Nov 18, 2005 page xvi of lxii

Item Page Revisions (See Manual for Details)

21.4.3 User Boot

943 Figure amended

Mode Figure 21.13

Procedure for

Programming finished

processing

JSR FTDAR setting + 16

Programming User MAT in User Boot Mode

FPFR = 0 ?

Yes

Clear FKEY to 0

Clear FKEY and programming

error processing*

Set FMATS to H'AA to

select user boot MAT

End programming procedure program

21.8 Serial Communication Interface Specification for Boot Mode

(4) Inquiry and Selection States

966

• Response, H'31, (one byte): Response to the clock-mode inquiry

• Size (one byte): Amount of data that represents modes

21.9 Usage Notes 988 Description amended The programming … or less. Accordingly, when the CPU clock

frequency is 35 MHz, …

23.5.1 Notes on Clock

Pulse Generator

998 Note amended

Note: * 35 MHz for the H8S/2378 and H8S/2378R

MAT

switchover

Rev. 5.00 Nov 18, 2005 page xvii of lxii

Item Page Revisions (See Manual for Details)

24.2.3 Software Standby Mode

Table 24.2 Oscillation Stabilization Time Settings

1011 Table amended

STS3 STS2 STS1 STS0

0000Reserved ———————µs

1 Reserved ———————

1 0 Reserved ———————

1 Reserved ———————

100Reserved ———————

164 1.8 1.9 2.6 3.2 4.9 6.4 8.0

1 0 512 15.0 15.5 20.5 25.6 39.4 51.2 64.0

1 1024 29.3 31.0 41.0 51.2 78.8 102.4 128.0

10002048 58.5 62.1 81.9 102.4 157.5 204.8 256.0

1 4096 0.12 0.12 0.16 0.20 0.32 0.41 0.51 ms

1 0 16384 0.47 0.50 0.66 0.82 1.26 1.64 2.05

1 32765 0.94 0.99 1.31 1.64 2.52 3.28 4.10

1 0 0 65536 1.87 1.99 2.62 3.28 5.04 6.55 8.19

1 131072 3.74 3.97 5.24 6.55 10.08 13.11 16.38

1 0 262144 7.49 7.94 10.49 13.11 20.16 26.21 32.77

1 524288 14.98 15.89 20.97 26.21 40.33 52.43 65.54

Standby Time

33 25 20 13 10 8 Unit

[MHz]

26.2.2 DC Characteristics

Table 26.15 DC Characteristics

Table 26.16 DC Characteristics

Table 26.17 Permissible Output Currents

1072 Table amended and Note *4 added

Item Symbol Min. Typ. Max. Unit

voltage

All output pins V

P32 to P34

— 0.4 V IOL = 1.6 mAOutput low

— ——0.5 V IOL = 8.0 mA

Notes: 4. When used as SCL0, SCL1, SDA0, and SDA1.

1074 Table amended and Note *5 added

Item Symbol Min. Typ. Max. Unit

VCC start voltage

VCC rise slope

Notes: 5. Applies when

— — V

CCstart

— — ms/V

RES

pin is low level at power-on.

Table amended

Item Symbol Min. Typ. Max. Unit

current (per pin)

all output pins

IIC output pins — — 8.0

Test Conditions

Test

0.8

——2.0 mAPermissible output low Other than IIC pins

Conditions

Rev. 5.00 Nov 18, 2005 page xviii of lxii

Item Page Revisions (See Manual for Details)

26.2.3 AC

Characteristics Table 26.18 Clock

Timing

1075 Table amended

Conditions: …φ = 8 MHz to

Item Symbol Min. Max. Unit Test Conditions

Clock cycle time t

35 MHz, …

28.5 125 ns Figure 26.2

cyc

Table 26.19 Control Signal Timing

Table 26.20 Bus Timing (1)

Table 26.21 Bus Timing (2)

Table 26.22 DMAC and EXDMAC Timing

Table 26.23 Timing of On-Chip Peripheral Modules

26.2.4 A/D Conversion

Characteristics Table 26.24 A/D

Conversion Characteristics

26.2.5 D/A Conversion

Characteristics Table 26.25 D/A

Conversion Characteristics

1076 Conditions: …φ = 8 MHz to 35 MHz, …

1077

1079 Table amended

35 MHz, …

25 — ns

WTS

1 — ns

WTH

1080

Conditions: …φ = 8 MHz to

Item Symbol Min. Max. Unit Test Conditions

WAIT setup time t

WAIT hold time t

1081 Conditions: …φ = 8 MHz to 35 MHz, …

1082

1084 Table amended

Conditions: …φ = 8 MHz to 35 MHz, …

Item Min. Typ. Max. Unit

Resolution 10 10 10 Bit Conversion time 7.4 —— µs

Conditions: …φ = 8 MHz to 35 MHz, …

Figures 26.9 and

26.15

Rev. 5.00 Nov 18, 2005 page xix of lxii

Item Page Revisions (See Manual for Details)

B. Product Lineup 1125 Table amended

Product Type Name Model Marking

H8S/2378 Group

H8S/2378 F-ZTAT

version

H8S/2377 HD64F2377 HD64F2377VFQ

H8S/2376 HD6432376 HD6432376VFQ

HD64F2378

Package

B HD64F2378B 144-pin LGA

HD64F2378BVFQ

(Code)

(TLP-145V*) 144-pin QFP (FP-144H, FP144HV*)

C Package Dimensions

Figure C.2 Package Dimensions (TLP-145V)

1127 Newly added

Rev. 5.00 Nov 18, 2005 page xx of lxii

Section 1 Over v iew............................................................................................................. 1

1.1 Features............................................................................................................................. 1

1.2 Block Diagram.................................................................................................................. 3

1.3 Pin Description................................................................................................................. 8

1.3.1 Pin Arrangement.............................................................................................. 8

1.3.2 Pin Arrangement in Each Operating Mode...................................................... 14

1.3.3 Pin Functions................................................................................................... 20

Section 2 CPU...................................................................................................................... 35

2.1 Features............................................................................................................................. 35

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU.............................. 36

2.1.2 Differences from H8/300 CPU ........................................................................ 37

2.1.3 Differences from H8/300H CPU ..................................................................... 37

2.2 CPU Operating Modes...................................................................................................... 38

2.2.1 Normal Mode................................................................................................... 38

2.2.2 Advanced Mode............................................................................................... 40

2.3 Address Space................................................................................................................... 42

2.4 Register Configuration...................................................................................................... 43

2.4.1 General Registers............................................................................................. 44

2.4.2 Program Counter (PC)..................................................................................... 45

2.4.3 Extended Control Register (EXR)................................................................... 45

2.4.4 Condition-Code Register (CCR)...................................................................... 46

2.4.5 Initial Register Values..................................................................................... 47

2.5 Data Formats..................................................................................................................... 47

2.5.1 General Register Data Formats........................................................................ 48

2.5.2 Memory Data Formats..................................................................................... 50

2.6 Instruction Set................................................................................................................... 51

2.6.1 Table of Instructions Classified by Function................................................... 52

2.6.2 Basic Instruction Formats................................................................................ 61

2.7 Addressing Modes and Effective Address Calculation..................................................... 62

2.7.1 Register Direct—Rn........................................................................................ 63

2.7.2 Register Indirect—@ERn................................................................................ 63

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).......... 63

2.7.4 Register Indirect with Post-Increm ent or Pre-Dec reme nt

—@ERn+ or @-ERn....................................................................................... 63

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 ............................... 64

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32............................................................. 64

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)............................... 65

Rev. 5.00 Nov 18, 2005 page xxi of lxii

2.7.8 Memory Indirect—@@aa:8............................................................................ 65

2.7.9 Effective Address Calculation ......................................................................... 66

2.8 Processing States .............................................................................................................. 68

2.9 Usage Note ....................................................................................................................... 69

2.9.1 Note on Bit Manipulation Instructions ............................................................ 69

Section 3 MCU Ope r ating Modes.................................................................................. 71

3.1 Operating Mode Selection................................................................................................ 71

3.2 Register Descriptions........................................................................................................72

3.2.1 Mode Control Register (MDCR)..................................................................... 72

3.2.2 System Control Register (SYSCR).................................................................. 72

3.3 Operating Mode Descriptions........................................................................................... 75

3.3.1 Mode 1............................................................................................................. 75

3.3.2 Mode 2............................................................................................................. 75

3.3.3 Mode 3............................................................................................................. 75

3.3.4 Mode 4............................................................................................................. 75

3.3.5 Mode 5............................................................................................................. 76

3.3.6 Mode 7............................................................................................................. 76

3.3.7 Pin Functions................................................................................................... 77

3.4 Memory Map in Each Operating Mode............................................................................ 78

Section 4 Exception Handling......................................................................................... 87

4.1 Exception Handling Types and Priority............................................................................ 87

4.2 Exception Sources and Exception Vector Table............................................................... 87

4.3 Reset ................................................................................................................................. 89

4.3.1 Reset Exception Handling............................................................................... 89

4.3.2 Interrupts after Reset........................................................................................ 91

4.3.3 On-Chip Peripheral Functions after Reset Release.......................................... 91

4.4 Trace Exception Handling................................................................................................ 92

4.5 Interrupt Exception Handling ........................................................................................... 92

4.6 Trap Instruction Exception Handling................................................................................ 93

4.7 Stack Status after Exception Handling.............................................................................. 94

4.8 Usage Note ....................................................................................................................... 95

Section 5 Inte r r upt Controller.......................................................................................... 97

5.1 Features............................................................................................................................. 97

5.2 Input/Output Pins.............................................................................................................. 99

5.3 Register Descriptions........................................................................................................99

5.3.1 Interrupt Control Register (INTCR) ................................................................ 100

5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)........................................ 100

5.3.3 IRQ Enable Register (IER).............................................................................. 102

Rev. 5.00 Nov 18, 2005 page xxii of lxii

5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)................................. 104

5.3.5 IRQ Status Register (ISR)................................................................................ 110

5.3.6 IRQ Pin Select Register (ITSR)....................................................................... 111

5.3.7 Software Standby Release IRQ Enable Register (SSIER)............................... 113

5.4 Interrupt Sources............................................................................................................... 114

5.4.1 External Interrupts........................................................................................... 114

5.4.2 Internal Interrupts............................................................................................ 115

5.5 Interrupt Exception Handling Vector Table...................................................................... 115

5.6 Interrupt Control Modes and Interrupt Operation............................................................. 121

5.6.1 Interrupt Control Mode 0................................................................................. 121

5.6.2 Interrupt Control Mode 2................................................................................. 123

5.6.3 Interrupt Exception Handling Sequence.......................................................... 124

5.6.4 Interrupt Response Times................................................................................ 126

5.6.5 DTC and DMAC Activation by Interrupt........................................................ 127

5.7 Usage Notes...................................................................................................................... 128

5.7.1 Conflict between Interrupt Generation and Disabling..................................... 128

5.7.2 Instructions that Disable Interrupts.................................................................. 129

5.7.3 Times when Interrupts are Disabled................................................................ 129

5.7.4 Interrupts during Execution of EEPMOV Instruction..................................... 129

5.7.5 Change of IRQ Pin Select Register (ITSR) Setting......................................... 129

5.7.6 IRQ Status Register (ISR)................................................................................ 130

Section 6 Bus Co ntr o l ler (BSC)...................................................................................... 131

6.1 Features............................................................................................................................. 131

6.2 Input/Output Pins.............................................................................................................. 133

6.3 Register Descriptions........................................................................................................ 136

6.3.1 Bus Width Control Register (ABWCR)........................................................... 137

6.3.2 Access State Control Register (ASTCR)......................................................... 137

6.3.3 Wait Control Registers AH, AL, BH, and BL

(WTCRAH, WTCRAL, WTCRBH, and WTCRBL) ...................................... 138

6.3.4 Read Strobe Timing Control Register (RDNCR) ............................................ 144

6.3.5

6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)

6.3.7 Bus Control Register (BCR)............................................................................ 148

6.3.8 DRAM Control Register (DRAMCR)............................................................. 150

6.3.9 DRAM Access Control Register (DRACCR).................................................. 158

6.3.10 Refresh Control Register (REFCR)................................................................. 161

6.3.11 Refresh Timer Counter (RTCNT).................................................................... 164

6.3.12 Refresh Time Constant Register (RTCOR)..................................................... 164

6.4 Bus Control....................................................................................................................... 165

Assertion Period Control Registers H, L (CSACRH, CSACRL)............... 145

Area 1 Burst ROM Interface Control Register (BROMCRL) ......................... 147

Rev. 5.00 Nov 18, 2005 page xxiii of lxii

6.4.1 Area Division................................................................................................... 165

6.4.2 Bus Specifications ........................................................................................... 166

6.4.3 Memory Interfaces........................................................................................... 168

6.4.4 Chip Select Signals.......................................................................................... 169

6.5 Basic Bus Interface........................................................................................................... 170

6.5.1 Data Size and Data Alignment......................................................................... 170

6.5.2 Valid Strobes ................................................................................................... 172

6.5.3 Basic Timing.................................................................................................... 172

6.5.4 Wait Control.................................................................................................... 181

6.5.5 Read Strobe (

6.5.6 Extension of Chip Select (

) Timing................................................................................ 182

) Assertion Period ............................................. 183

6.6 DRAM Interface............................................................................................................... 185

6.6.1 Setting DRAM Space ...................................................................................... 185

6.6.2 Address Multiplexing...................................................................................... 185

6.6.3 Data Bus .......................................................................................................... 186

6.6.4 Pins Used for DRAM Interface ....................................................................... 187

6.6.5 Basic Timing.................................................................................................... 188

6.6.6 Column Address Output Cycle Control........................................................... 189

6.6.7 Row Address Output State Control.................................................................. 190

6.6.8 Precharge State Control................................................................................... 192

6.6.9 Wait Control.................................................................................................... 193

6.6.10 Byte Access Control........................................................................................ 196

6.6.11 Burst Operation................................................................................................ 197

6.6.12 Refresh Control................................................................................................ 202

6.6.13 DMAC and EXDMAC Single Address Transfer Mode and

DRAM Interface.............................................................................................. 207

6.7 Synchronous DRAM Interface......................................................................................... 210

6.7.1 Setting Continuous Synchronous DRAM Space............................................. 210

6.7.2 Address Multiplexing...................................................................................... 211

6.7.3 Data Bus .......................................................................................................... 212

6.7.4 Pins Used for Synchronous DRAM Interface.................................................. 212

6.7.5 Synchronous DRAM Clock............................................................................. 214

6.7.6 Basic Timing.................................................................................................... 214

6.7.7 CAS Latency Control...................................................................................... 216

6.7.8 Row Address Output State Control.................................................................. 218

6.7.9 Precharge State Count...................................................................................... 219

6.7.10 Bus Cycle Control in Write Cycle................................................................... 221

6.7.11 Byte Access Control........................................................................................ 222

6.7.12 Burst Operation................................................................................................ 225

6.7.13 Refresh Control................................................................................................ 228

6.7.14 Mode Register Setting of Synchronous DRAM.............................................. 234

Rev. 5.00 Nov 18, 2005 page xxiv of lxii

6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous

DRAM Interface.............................................................................................. 235

6.8 Burst ROM Interface ........................................................................................................ 240

6.8.1 Basic Timing.................................................................................................... 240

6.8.2 Wait Control.................................................................................................... 242

6.8.3 Write Access.................................................................................................... 242

6.9 Idle Cycle.......................................................................................................................... 243

6.9.1 Operation......................................................................................................... 243

6.9.2 Pin States in Idle Cycle.................................................................................... 262

6.10 Write Data Buffer Function.............................................................................................. 262

6.11 Bus Release....................................................................................................................... 263

6.11.1 Operation......................................................................................................... 264

6.11.2 Pin States in External Bus Released State....................................................... 265

6.11.3 Transiti on Timing............................................................................................ 266

6.12 Bus Arbitration ................................................................................................................. 268

6.12.1 Operation......................................................................................................... 268

6.12.2 Bus Transfe r Timing........................................................................................ 269

6.13 Bus Controller Operation in Reset.................................................................................... 270

6.14 Usage Notes...................................................................................................................... 271

6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode......... 271

6.14.2 External Bus Release Function and Software Standby.................................... 271

6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing........... 271

6.14.4

6.14.5 Notes on Usage of the Synchronous DRAM................................................... 272

BREQO

Output Timing................................................................................... 272

Section 7 DMA Controller (DMAC)............................................................................. 273

7.1 Features............................................................................................................................. 273

7.2 Input/Output Pins.............................................................................................................. 275

7.3 Register Descriptions........................................................................................................ 275

7.3.1 Memory Address Registers (MARA and MARB)........................................... 277

7.3.2 I/O Address Registers (IOARA and IOARB).................................................. 277

7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) .............................. 278

7.3.4 DMA Control Registers (DMACRA and DMACRB)..................................... 279

7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)......... 287

7.3.6 DMA Write Enable Register (DMAWER)...................................................... 298

7.3.7 DMA Terminal Control Register (DMATCR)................................................ 300

7.4 Activation Sources............................................................................................................ 301

7.4.1 Activation by Internal Interrupt Request ......................................................... 302

7.4.2 Activation by External Request....................................................................... 303

7.4.3 Activation by Auto-Request............................................................................ 303

7.5 Operation .......................................................................................................................... 303

Rev. 5.00 Nov 18, 2005 page xxv of lxii

7.5.1 Transfer Modes................................................................................................ 303

7.5.2 Sequential Mode.............................................................................................. 306

7.5.3 Idle Mode......................................................................................................... 308

7.5.4 Repeat Mode.................................................................................................... 310

7.5.5 Single Address Mode....................................................................................... 314

7.5.6 Normal Mode................................................................................................... 317

7.5.7 Block Transfer Mode....................................................................................... 320

7.5.8 Basic Bus Cycles............................................................................................. 325

7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles........................................... 326

7.5.10 DMA Transfer (Single Address Mode) Bus Cycles ........................................ 334

7.5.11 Write Data Buffer Function............................................................................. 340

7.5.12 Multi-Channel Operation................................................................................. 341

7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,

and EXDMAC................................................................................................. 343

7.5.14 DMAC and NMI Interrupts............................................................................. 344

7.5.15 Forced Termi nation of DMA C Operation....................................................... 345

7.5.16 Clearing Full Address Mode............................................................................ 346

7.6 Interrupt Sources............................................................................................................... 347

7.7 Usage Notes...................................................................................................................... 348

7.7.1 DMAC Register Access during Operation ...................................................... 348

7.7.2 Module Stop .................................................................................................... 349

7.7.3 Write Data Buffer Function............................................................................. 350

7.7.4

7.7.5 Activation by Falling Edge on

7.7.6 Activation Source Acceptance......................................................................... 352

7.7.7 Internal Interrupt after End of Transfer ........................................................... 352

7.7.8 Channel Re-Setting.......................................................................................... 352

TEND

Output .................................................................................................. 350

DREQ

Pin....................................................... 351

Section 8 EXDMA Controller (EXDMAC)................................................................ 353

8.1 Features............................................................................................................................. 353

8.2 Input/Output Pins.............................................................................................................. 355

8.3 Register Descriptions........................................................................................................ 356

8.3.1 EXDMA Source Address Register (EDSAR).................................................. 356

8.3.2 EXDMA Destination Address Register (EDDAR).......................................... 356

8.3.3 EXDMA Transfer Count Register (EDTCR)................................................... 357

8.3.4 EXDMA Mode Control Register (EDMDR)................................................... 359

8.3.5 EXDMA Address Control Register (EDACR)................................................ 364

8.4 Operation .......................................................................................................................... 368

8.4.1 Transfer Modes................................................................................................ 368

8.4.2 Address Modes................................................................................................ 369

8.4.3 DMA Transfer Requests.................................................................................. 373

Rev. 5.00 Nov 18, 2005 page xxvi of lxii

8.4.4 Bus Modes....................................................................................................... 373

8.4.5 Transfer Modes................................................................................................ 375

8.4.6 Repeat Area Function...................................................................................... 377

8.4.7 Registers during DMA Transfer Operation ..................................................... 379

8.4.8 Channel Priority Order .................................................................................... 384

8.4.9 EXDMAC Bus Cycles (Dual Address Mode)................................................. 387

8.4.10 EXDMAC Bus Cycles (Single Address Mode)............................................... 394

8.4.11 Examples of Operation Timing in Each Mode ................................................ 399

8.4.12 Ending DMA Transfer..................................................................................... 412

8.4.13 Relationship between EXDMAC and Other Bus Masters............................... 413

8.5 Interrupt Sources............................................................................................................... 414

8.6 Usage Notes...................................................................................................................... 416

8.6.1 EXDMAC Register Access during Operation................................................. 416

8.6.2 Module Stop State ........................................................................................... 416

8.6.3

8.6.4 Activation Source Acceptance......................................................................... 417

8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR.................................. 417

8.6.6

EDREQ

ETEND

Pin Falling Edge Activation .............................................................. 416

Pin and CBR Refresh Cycle............................................................... 417

Section 9 Data Transfer Controller (DTC)................................................................... 419

9.1 Features............................................................................................................................. 419

9.2 Register Descriptions........................................................................................................ 421

9.2.1 DTC Mode Register A (MRA) ........................................................................ 421

9.2.2 DTC Mode Register B (MRB)......................................................................... 423

9.2.3 DTC Source Address Register (SAR).............................................................. 423

9.2.4 DTC Destination Address Register (DAR)...................................................... 423

9.2.5 DTC Transfer Count Register A (CRA).......................................................... 424

9.2.6 DTC Transfer Count Register B (CRB)........................................................... 424

9.2.7 DTC Enable Registers A to H (DTCERA to DTCERH)................................. 424

9.2.8 DTC Vector Register (DTVECR).................................................................... 425

9.3 Activation Sources............................................................................................................ 426

9.4 Location of Register Information and DTC Vector Table................................................ 427

9.5 Operation .......................................................................................................................... 431

9.5.1 Normal Mode................................................................................................... 434

9.5.2 Repeat Mode.................................................................................................... 435

9.5.3 Block Transfer Mode....................................................................................... 436

9.5.4 Chain Transfer................................................................................................. 437

9.5.5 Interrupt Sources.............................................................................................. 438

9.5.6 Operation Timing............................................................................................. 438

9.5.7 Number of DTC Execution States ................................................................... 439

9.6 Procedures for Using DTC ............................................................................................... 441

Rev. 5.00 Nov 18, 2005 page xxvii of lxii

9.6.1 Activation by Interrupt .................................................................................... 441

9.6.2 Activation by Software.................................................................................... 441

9.7 Examples of Use of the DTC............................................................................................ 442

9.7.1 Normal Mode................................................................................................... 442

9.7.2 Chain Transfer................................................................................................. 443

9.7.3 Chain Transfer when Counter = 0.................................................................... 444

9.7.4 Software Activation......................................................................................... 446

9.8 Usage Notes...................................................................................................................... 446

9.8.1 Module Stop Mode Setting.............................................................................. 446

9.8.2 On-Chip RAM................................................................................................. 446

9.8.3 DTCE Bit Setting............................................................................................. 447

9.8.4 DMAC Transfer End Interrupt ........................................................................ 447

9.8.5 Chain Transfer................................................................................................. 447

Section 10 I/O Ports............................................................................................................ 449

10.1 Port 1................................................................................................................................. 460

10.1.1 Port 1 Data Direction Register (P1DDR)......................................................... 460

10.1.2 Port 1 Data Register (P1DR)........................................................................... 460

10.1.3 Port 1 Register (PORT1) ................................................................................. 461

10.1.4 Pin Functions for H8S/2378R Group, H8S/2378, H8S/2377, H8S/2375,

and H8S/2373.................................................................................................. 462

10.1.5 Pin Functions for H8S/2376............................................................................ 472

10.2 Port 2................................................................................................................................. 480

10.2.1 Port 2 Data Direction Register (P2DDR)......................................................... 480

10.2.2 Port 2 Data Register (P2DR)........................................................................... 481

10.2.3 Port 2 Register (PORT2) ................................................................................. 481

10.2.4 Pin Functions for the H8S/2378R Group, H8S/2378, H8S/2377, H8S/2375,

and H8S/2373.................................................................................................. 482

10.2.5 Pin Functions for the H8S/2376....................................................................... 490

10.3 Port 3................................................................................................................................. 498

10.3.1 Port 3 Data Direction Register (P3DDR)......................................................... 498

10.3.2 Port 3 Data Register (P3DR)........................................................................... 499

10.3.3 Port 3 Register (PORT3) ................................................................................. 499

10.3.4 Port 3 Open Drain Control Register (P3ODR)................................................ 500

10.3.5 Port Function Control Register 2 (PFCR2)...................................................... 501

10.3.6 Pin Functions for the H8S/2378R Group, H8S/2378, H8S/2377, H8S/2375,

and H8S/2373.................................................................................................. 502

10.3.7 Pin Functions for H8S/2376............................................................................ 505

10.4 Port 4................................................................................................................................. 508

10.4.1 Port 4 Register (PORT4) ................................................................................. 508

10.4.2 Pin Functions................................................................................................... 509

Rev. 5.00 Nov 18, 2005 page xxviii of lxii

10.5 Port 5................................................................................................................................. 510

10.5.1 Port 5 Data Direction Register (P5DDR)......................................................... 510

10.5.2 Port 5 Data Register (P5DR)........................................................................... 510

10.5.3 Port 5 Register (PORT5) ................................................................................. 511

10.5.4 Pin Functions................................................................................................... 511

10.6 Port 6................................................................................................................................. 513

10.6.1 Port 6 Data Direction Register (P6DDR)......................................................... 513

10.6.2 Port 6 Data Register (P6DR)........................................................................... 514

10.6.3 Port 6 Register (PORT6) ................................................................................. 514

10.6.4 Pin Functions for H8S/2378R Group, H8S/2378, H8S/2377, H8S/2375,

and H8S/2373.................................................................................................. 515

10.6.5 Pin Functions for H8S/2376............................................................................ 518

10.7 Port 8................................................................................................................................. 520

10.7.1 Port 8 Data Direction Register (P8DDR)......................................................... 520

10.7.2 Port 8 Data Register (P8DR)........................................................................... 521

10.7.3 Port 8 Register (PORT8) ................................................................................. 521

10.7.4 Pin Functions for H8S/2378R Group, H8S/2378, H8S/2377, H8S/2375,

and H8S/2373.................................................................................................. 522

10.7.5 Pin Functions for H8S/2376............................................................................ 526

10.8 Port 9................................................................................................................................. 528

10.8.1 Port 9 Register (PORT9) ................................................................................. 528

10.8.2 Pin Functions................................................................................................... 529

10.9 Port A................................................................................................................................ 530

10.9.1 Port A Data Direction Register (PADDR)....................................................... 530

10.9.2 Port A Data Register (PADR).......................................................................... 531

10.9.3 Port A Register (PORTA)................................................................................ 531

10.9.4 Port A Pull-Up MOS Control Register (PAPCR)............................................ 532

10.9.5 Port A Open Drain Control Register (PAODR)............................................... 532

10.9.6 Port Function Control Register 1 (PFCR1)...................................................... 532

10.9.7 Pin Functions................................................................................................... 534

10.9.8 Port A Input Pull-Up MOS States.................................................................... 535

10.10 Port B................................................................................................................................ 536

10.10.1 Port B Data Direction Register (PBDDR) ....................................................... 536

10.10.2 Port B Data Register (PBDR).......................................................................... 537

10.10.3 Port B Register (PORTB)................................................................................ 537

10.10.4 Port B Pull-Up MOS Control Register (PBPCR) ............................................ 538

10.10.5 Pin Functions................................................................................................... 538

10.10.6 Port B Input Pull-Up MOS States.................................................................... 539

10.11 Port C................................................................................................................................ 540

10.11.1 Port C Data Direction Register (PCDDR) ....................................................... 540

10.11.2 Port C Data Register (PCDR).......................................................................... 541

Rev. 5.00 Nov 18, 2005 page xxix of lxii

10.11.3 Port C Register (PORTC)................................................................................ 541

10.11.4 Port C Pull-Up MOS Control Register (PCPCR) ............................................ 542

10.11.5 Pin Functions................................................................................................... 542

10.11.6 Port C Input Pull-Up MOS States.................................................................... 543

10.12 Port D................................................................................................................................ 544

10.12.1 Port D Data Direction Register (PDDDR)....................................................... 544

10.12.2 Port D Data Register (PDDR).......................................................................... 545

10.12.3 Port D Register (PORTD)................................................................................ 545

10.12.4 Port D Pull-up Control Register (PDPCR)...................................................... 546

10.12.5 Pin Functions................................................................................................... 546

10.12.6 Port D Input Pull-Up MOS States.................................................................... 547

10.13 Port E................................................................................................................................ 548

10.13.1 Port E Data Direction Register (PEDDR)........................................................ 548

10.13.2 Port E Data Register (PEDR)........................................................................... 549

10.13.3 Port E Register (PORTE)................................................................................. 549

10.13.4 Port E Pull-up Control Register (PEPCR)....................................................... 550

10.13.5 Pin Functions................................................................................................... 550

10.13.6 Port E Input Pull-Up MOS States.................................................................... 551

10.14 Port F ................................................................................................................................ 551

10.14.1 Port F Data Direction Register (PFDDR)........................................................ 552

10.14.2 Port F Data Register (PFDR)........................................................................... 554

10.14.3 Port F Register (PORTF)................................................................................. 554

10.14.4 Pin Functions for H8S/2378R Group, H8S/2378, H8S/2377, H8S/2375,

and H8S/2373.................................................................................................. 555

10.14.5 Pin Functions for H8S/2376 ............................................................................ 559

10.15 Port G................................................................................................................................ 562

10.15.1 Port G Data Direction Register (PGDDR)....................................................... 562

10.15.2 Port G Data Register (PGDR).......................................................................... 563

10.15.3 Port G Register (PORTG)................................................................................ 563

10.15.4 Port Function Control Register 0 (PFCR0)...................................................... 564

10.15.5 Pin Functions for H8S/2378R Group, H8S/2378, H8S/2377, H8S/2375,

and H8S/2373.................................................................................................. 564

10.15.6 Pin Functions for H8S/2376 ............................................................................ 567

10.16 Port H................................................................................................................................ 570

10.16.1 Port H Data Direction Register (PHDDR)....................................................... 570

10.16.2 Port H Data Register (PHDR).......................................................................... 573

10.16.3 Port H Register (PORTH)................................................................................ 573

10.16.4 Pin Functions for H8S/2378R Group, H8S/2378, H8S/2377, H8S/2375,

and H8S/2373.................................................................................................. 574

10.16.5 Pin Functions for H8S/2376................................................................................ 576

Rev. 5.0 0 Nov 18, 2005 p age xxx of lxii

+ 1191 hidden pages

RENESAS H8S-2378R User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Precautions on Handling of Product

Configuration of This Manual

Preface

Main Revisions for this Edition

Contents