Renesas H8S/2368 Series, H8S Series, H8S/2300 Series Hardware Manual

H8S/2368

The revision list can be viewed directly by clicking the title page.

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

Group

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family/H8S/2300 Series

Rev.2.00

2003.5.23

Renesas 16-Bit Single-Chip Microcomputer

H8S/Family/H8S/2300 Series

H8S/2368 Group

Hardware Manual

REJ09B0050-0200O

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliabl e, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or propert y da mage. Remember to give due consideration to safety when making your circuit designs, with appropriate measu res such as (i) placement of substitutive, auxiliar y circuits, (ii) use of nonflammable materia l or (iii) preve n tio n agai n st any malf unc tio n or mishap.

Notes regar ding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.

2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party 's rights, originating in th e u se of any product data, diagrams, charts, programs, algorithms, or circuit applicatio n examples contained in these materials.

3. All information contained in these materials, including product data, diag rams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product informati o n be fore purc ha sing a produc t listed herein. The informa tion descri bed here may c o ntain techni c al inaccuracies or typ og r aphical err ors. Renesas Technology Corp oration assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas .com).

4. When usi ng any or all of the informat i on containe d i n th e s e ma terials, inc luding prod uct data, diagrams, chart s, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corpora tion assumes no responsibilit y for any damage, liability or ot her loss resulting from the information contained herein.

5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Te chnology Corporation product dis tributor when considering the use of a product contained herein for any specific purposes, such as apparat us or system s for tra nsp or ta tio n, veh icul ar, medica l, aer o space, nucle ar, or unders ea repeater use.

6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.

7. If these products o r technologies are sub ject to the Japanese exp ort contro l restrictions, they must be exported under a l i cense from the Japanese govern ment and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export contro l laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corporation for further details on these materials or the products contained the rein.

Rev. 2.00, 05/03, page iv of lii

General Precautions on Handling of Product

1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction m ay occur.

3. Processing before Initializatio n Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.

Rev. 2.00, 05/03, page v of lii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Ed ition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see th e actual locations in this manual.

11.Index

Rev. 2.00, 05/03, page vi of lii

Preface

The H8S/2368 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas Technology’s original architecture as their cores, and the peripheral functions required to configure a system.

The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a 16-Mbyte linear address space.

This LSI is equipped with direct memory access controller (DMAC) and data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), 8-bit timers (TMR), a watchdog timer (WDT), serial communication interfaces (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as onchip peripheral modules required for system configuration. I included as an optional interface.

A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM and other kinds of memory.

A single-power flash memory (F-ZTAT

) version is available for this LSI's ROM. This provides flexibility as it can be reprogrammed in no time to cope with all situ ations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change.

C bus interface 2 (IIC2) can also be

Note: F-ZTAT

is a trademark of Renesas Technology Corp.

Target Users: This manual was written for users who will be using the H8S/2368 Group in the

design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware function s and electrical

characteristics of the H8S/2368 Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instru ction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.

Rev. 2.00, 05/03, page vii of lii

• In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

For the execution state of each instruction in this LSI, see Appendix D, Bus State during Execution of Instructions.

• In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse un it or ser ial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel

number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require. http://www.renesas.com/

H8S/2368 Group manuals:

Manual Title ADE No.

H8S/2368 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

User's manuals for development tools:

Manual Title ADE No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual

H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-282 H8S, H8/300 Series Hi-Performance Embedded Workshop, HDI Tutorial ADE-702-231 Hi-Performance Embedded Workshop User's Manual ADE-702-201

Rev. 2.00, 05/03, page viii of lii

ADE-702-247

Main Revisions and Additions in this Edition

Item Page Revision (See Manual for Details)

All H8S/2366 added.

1.1 Features 1 Table amended.

ROM Type Model ROM RAM Remarks

Flash memory version HD64F2367 384 kbytes 24 kbytes

Masked ROM version HD6432365 256 kbytes 16 kbytes

ROMless version HD6412363 16 kbytes

1.2 Block Diagram Figure 1.1 Internal Block

Diagram

of H8S/2367,

H8S/2365, and H8S/2363

Description added in the 2nd line. Figures 1.1 and 1.2 show the internal block diagrams

of this LSI. Figure and its title amended. (Error) I2C bus interface (option) →

(Correction) I

Figure 1.2 Internal Block

4 Newly added.

Diagram of H8S/2366

1.3.1 Pin Arrangement 5 Description added in the 3rd line. Figures 1.3 to 1.6 show the pin arrangements of this

LSI.

Figure 1.3 Pin Arrangement of H8S/2367, H8S/2365, and

Pin names of pins 70 and 71 amended and note added to pin 30.

H8S/2363

HD64F2366 384 kbytes 30 kbytes In planning stage

C bus interface 2 (option)

Figure 1.4 Pin Arrangement of H8S/2366

PF6/

PF5/

PF4/

PF3/

PF2/ /

757473727170696867666564636261

2627282930

EMLE*

PA4/A20/

PA5/A21/

PA6/A22/

PA7/A23/ /

Note: * This is an emulator enable pin. Normally, this

pin should be set to low. If this pin goes high in the flash memory version, the on-chip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and WDTOVF function only for the on-chip emulator.

6 Newly added.

PF1/ /

PF0/ /

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Rev. 2.00, 05/03, page ix of lii

Item Page Revision (See Manual for Details)

1.3.1 Pin Arrangement Figure 1.5 Pin Arrangement

7 Pin name of pin 86 amended and note added to pin

34. of H8S/2367, H8S/2365, and H8S/2363

EXTAL

XTAL

VSSPF7/φPLLVSSPLLVCCPF6/

908988878685848382

303132333435363738

PA4/A20/

PA5/A21/

PA6/A22/

PF5/

PF4/

PF3/

PF2/ /

PF1/ /

PF0/ /

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

VSSNC*1VCCPE7/D7

75747677787980

VSSV

NMI

EMLE*

PA7/A23/ /

737271706968676665

Notes: *1The NC pin should be fixed to Vss or should

be open. This is an emulator enable pin. Normally,

this pin should be set to low. If this pin goes high in the flash memory version, the onchip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and WDTOVF function only for the on-chip emulator.

Figure 1.6 Pin Arrangement

8 Newly added.

of H8S/2366

3.3.6 Pin Functions Table 3.2 Pin Functions in

61 Note *2 added

Note: *2 Setting not allowed on no-ROM versions.

Each Operating Mode

3.4 Memory Map in Each

64, 65 Newly added.

Operating Mode Figure 3.3

H8S/2366

Memory Map (1) Figure 3.4

H8S/2366

Memory Map (2) Figure 3.7 H8S/2363

Memory Map

5.1 Features Figure 5.1 Block Diagram

68 Figure amended.

(Error) H′FF6000 → (Correction) H′FF

80 Register name amended.

(Error) ISCR → (Correction) ISCR

of Interrupt Controller

5.3 Register Descriptions 81 Register name amended in the 6th line.

L (ISCRL)

5.3.4 IRQ Sense Control Register

L (ISCRL)

• IRQ sense control register

85 Title amended.

Description amended in the 2nd line. (Error) ISCR → (Correction) ISCR

8000

Rev. 2.00, 05/03, page x of lii

Item Page Revision (See Manual for Details)

5.4.1 External Interrupts 90 Description amended in the 13th line. Using ISCR

L, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0.

6.8.1 Operation 187 Description added in the 1st line. Table 6.7 shows whether an idle cycle is inserted or

not in mixed access to normal space and DRAM.

Section 9 I/O Ports Table 9.1 Port Functions

300 Description of port 2 amended.

(Error) General I/O port also functioning as PPG outputs, TPU I/Os,

TMR I/Os, and bus control I/Os →

(Correction) General I/O port also functioning as PPG

9.1.4 Pin Functions

• P13/PO11*

KB/TEND1*

• P12/PO10*

KA/TEND0*

• P11/PO9*

DREQ1*

/TIOCD0/TCL

/TIOCC0/TCL

/TIOCB0/

outputs, TPU I/Os, and

309 Description amended in the 5th line.

(Error) bit TEEI → (Correction) bit TEE

310 Description amended in the 5th line.

(Error) bit TEEO → (Correction) bit TEE

311 Description amended in the 3rd line.

…(by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0

TMR I/Os

in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0),…

9.2.4 Pin Functions

• P24/PO4*

/TIOCA4/

RxD4/TMO0

318 Description amended in the 3rd line.

The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4

, and bits CCLR1 and CCLR0 in TCR4), bit NDER4*1 in NDERL, bit RE in SCI_4, bit P24DDR, and bit OS3 to OS0 in TCSRO of TMR.

Table amended.

RE 0 1

9.3.5 Port Function Control Register 2 (PFCR2)

TPU channel 4 settings

OS3 to OS0 All 0 Not all 0 —

P24DDR — 0 1 1 — —

NDER4 — — 0 1 — —

Pin function TIOCA4 output

326 Note added.

Note: * In the H8S/2366, this bit is reserved. This bit

(1) in table below (2) in table below

P24

output

TIOCA4 input*

PO4

output*

input

is always read as 1 and the write value should always be 1.

9.3.6 Pin Functions

• P35/SCK1/SCL0/(OE)*

327 Amended.

(Error) C/A → (Correction) C/A

—

TMO0 output

RXD4 input

Rev. 2.00, 05/03, page xi of lii

Item Page Revision (See Manual for Details)

9.6.4 Pin Functions

• P81/TxD3

9.8.6 Port Function Control Register 0 (PFCR0)

338 Amended.

(Error) TxD3 input → (Correction) TxD3

344 Bit table amended.

Bit Bit Name Initial Value R/W Description

7CS7E 1 R/W

6CS6E 1 R/W

5CS5E 1 R/W

4CS4E 1 R/W

3CS3E 1 R/W

2CS2E 1 R/W

1CS1E 1 R/W

0CS0E 1 R/W

to enable

Enable/disable corresponding

0: Set as I/O port.

1: Set as

output pin.

output

output.

(n = 7 to 0)

9.14.4 Pin Functions

• PG3/CS3/RAS3*, PG2/CS2/RAS2*

14.3.9 Bit Rate Register

(BRR) Table 14.3 BRR Settings

for Various Bit Rates (Asynchronous Mode)

Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)

Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)

Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)

Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372)

372 Table amended.

Operating

mode

EXPE — 01

CSnE 0 1 — 01

RMTS2* to RMTS0*

PGnDDR 0 1 0 1 — 010101—

PGn

function

input

1, 2, 4 7

— Area n is in

normal space

PGn

output

PGn input

output

Area n is in DRAM* space

output

——Area n is in

PGn

input

output

input

PGn

output

normal space

PGn input

output

Area n is in DRAM* space

output

529 Values when operating frequency φ is 2 MHz to

7.3728 MHz deleted.

531 Values when operating frequency φ is 2 MHz to

7.3728 MHz deleted.

532 Values when operating frequency φ is 2 MHz to

7.3728 MHz deleted.

533 Values when operating frequency φ is 2 MHz and

4 MHz deleted.

534 Values when operating frequency φ is 2 MHz, 4 MHz,

and 6 MHz deleted.

535 Values when operating frequency φ is 7.1424 MHz

deleted.

Rev. 2.00, 05/03, page xii of lii

Item Page Revision (See Manual for Details)

14.3.9 Bit Rate Register (BRR)

536 Values when operating frequency φ is 7.1424 MHz

deleted.

Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372)

14.8 IrDA Operation Table 14.12 Settings of Bits

IrCKS2 to IrCKS0

579 Values when operating frequency φ is 2 MHz to

7.3728 MHz deleted. Values when operating frequency φ is 30 MHz and

33 MHz deleted.

Operating Frequency φ (MHz)

25 110 110 110 110 110  30 110 110 110 110 110  33 110 110 110 110 110 

2400 9600 19200 38400 57600 115200

78.13 19.53 9.77 4.88 3.26 1.63

Bit Rate (bps) (Above)/Bit Period × 3/16 (ms) (Below)

16.1 Features 619 Description amended in the 7th line.

• Conversion time:

8.1 µs per channel (at 33 MHz

operation)

Figure 16.1 Block Diagram

620 Figure amended.

of A/D Converter

AVCC

16.3.3 A/D Control Register (ADCR)

Vref

AVSS

625 Description added in the 3rd line.

ADCR enables A/D conversion start by an external

10-bit A/D

trigger input. It also sets the A/D converter operating mode and the

A/D conversion time.

17.3.2 D/A Control Register 23 (DACR23)

Table 17.2 Control of D/A Conversion

640 Table amended.

(Error) DAOE1 → (Correction) DAOE (Error) DAOE0 → (Correction) DAOE

Section 18 RAM 643 Table amended.

Product Type Name ROM Type

H8S/2368 Series

HD64F2367 Flash memory version 24 kbytes H'FF6000 to H'FFBFFF

HD64F2366 30 kbytes H'FF4800 to H'FFBFFF

HD6432365 Masked ROM version 16 kbytes H'FF8000 to H'FFBFFF

HD641363 ROMless version

3 2

RAM Capacitance

RAM Address

Rev. 2.00, 05/03, page xiii of lii

Item Page Revision (See Manual for Details)

19.1 Features

• Size

• Flash memory emulation

by RAM

645 Table amended.

Product Classification ROM Size ROM Address

H8S/2368 Series HD64F2367

HD64F2366

Note * added Note: * This function is not supported by the

384 kbytes H'000000 to H'05FFFF (Modes 3, 4, and 7)

H8S/2367 or H8S/2366.

19.3 Block Configuration

651 Note deleted.

Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)

19.5.5 RAM Emulation

656 Note added.

Note: This function is not supported by the

H8S/2367 or H8S/2366.

19.7 Flash Memory

Emulation in RAM

662 Note added.

Note: This function is not supported by the

H8S/2367 or H8S/2366.

663 Note 4 added.

Note: 4. This function is not supported by the

H8S/2367 or H8S/2366.

19.8.2 Erase/Erase-Verify 666 Description amended in the 8th line.

4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc.

21.1.1 System Clock Control Register (SCKCR)

677 Bits 2, 1, and 0 discription amended.

Bit Bit Name Initial Value R/W Description

SCK2

SCK1

SCK0

0 0 0

R/W

System Clock Select 2 to 0

R/W

Select the division ratio.

R/W

000: 1/1

001: 1/2

010: 1/4

011: Setting prohibited

100: Setting prohibited

101: Setting prohibited

11X: Setting prohibited

21.2.1 Connecting a Crystal Oscillator

Rev. 2.00, 05/03, page xiv of lii

678 Description added in the 6th line.

An AT-cut parallel-resonance type should be used. When a clock is supplied with a crystal resonator

connected, the frequency of the crystal resonator should be 8 MHz to 25 MHz.

Item Page Revision (See Manual for Details)

21.2.2 External Clock Input 679 Description added in the 5th line. Table 21.3 shows the input conditions for the external

clock. The frequency of an external clock to be input should

be 8 MHz to 25 MHz.

21.4 Frequency Divider 681 Description amended in the 11th line. The frequency divider divides the PLL output clock to

generate a 1/2 or 1/4 clock.

21.5.3 Notes on Board

Design

682 Description of

values.) deleted.

(Values are preliminary recommended

Figure 21.7 Recommended External Circuitry for PLL Circuit

Section 22 Power-Down Modes

Table 22.1 Operating Modes and Internal States of the LSI

684 Table amended.

High

Operating State

interrupts

Peripheral functions

Speed Mode

NMIExternal

Functions Functions Functions Functions Functions Functions Halted

IRQ0 to 7

A/D Functions Functions Functions Halted

SCI Functions Functions Functions Halted*

IIC2 Functions Functions Functions Halted*

Clock Division Mode

Sleep Mode

Module Stop Mode

(Retained)

(Reset/ Retained)

Notes added. Notes: *3 TDR, SSR, and RDR are halted (reset)

and other registers are halted (retained).

*4 BC2 to BC0 are halted (reset) and other

registers are halted (retained).

22.2.1 Clock Division Mode 690 Description amended in the 5th line. In clock division mode, the CPU, bus masters, and

on-chip peripheral functions all operate on the operating clock (

1/2 or 1/4) specified by bits SCK2 to

SCK0.

22.4.6 Notes on Clock

697 Newly added.

Division Mode

23.1 Register Addresses

(Address Order)

701 IRQ sense control register H deleted.

IRQ pin select register ITSR 16 H'FE16 INT 16 2

Software standby release IRQ enable register

IRQ sense control register L ISCRL 16 H'FE1C INT 16 2

Abbreviation Bit No. Address Module

SSIER 16 H'FE18 INT 16 2

All Module Clock Stop Mode

Halted (Retained)

Halted* (Reset/ Retained)

Software Standby Mode

Halted (Retained)

Halted* (Reset/ Retained)

Data Width

Hardware Standby Mode

Halted (Reset)

Access States

Rev. 2.00, 05/03, page xv of lii

Item Page Revision (See Manual for Details)

23.2 Register Bits 710 Table amended.

————————

CRA

————————

CRB

————————

ICCRA_0 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0

ICCRB_0 BBSY SCP SDAO — SCLO — IICRST —

ICCRA_1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0

ICCRB_1 BBSY SCP SDAO — SCLO — IICRST —

716 *1 deleted after DTC module

(Error) DTC

→ (Correction) DTC

717 Table amended.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 DTC

INTCR ——INTM1 INTM0 NMIEG ———INT

————————IER

IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E

————————ISR

IRQ7F IRQ6F IRQ5F IRQ4 F IRQ3F IRQ2F IRQ1F IRQ0F

SBYCR SSBY OPE ——STS3 STS2 STS1 STS0

SCKCR PSTOP ———STCS SCK2 SCK1 SCK0

SYSCR ————FLSHE — EXPE RAME

23.3 Register States in Each Operating Mode

725 Table amended.

TDR_3 Initialized — — SSR_3 Initialized — — Initialized Initialized Initialized Initialized RDR_3 Initialized — — Initialized Initialized Initialized Initialized TDR_4 Initialized — — — Initialized Initialized Initialized Initialized SSR_4 Initialized — — Initialized Initialized Initialized Initialized RDR_4 Initialized — — Initialized Initialized Initialized Initialized

Reset

HighSpeed

— —

Clock Division

Module Stop

All Module Clock Stop

Sleep

— Initialized Initialized Initialized Initialized

Software Standby

Hardware Standby

IIC2_0

IIC2_1

SYSTEM

Module

SCI_3

SCI_4

Rev. 2.00, 05/03, page xvi of lii

726 Register name amended and deleted.

(Error) DRACCRH → (Correction)

DRACCR

DRACCRL deleted.

728 Table amended.

Reset

Name

— — ———— ——

PORT1

PORT2

— — ———— ——

PORT3

— — ———— ——

PORT4

— — ———— ——

PORT5

— — ———— ——

PORT8

— — ———— ——

PORT9

— — ———— ——

PORTA

— — ———— ——

PORTB

— — ———— ——

PORTC

— — ———— ——

PORTD

— — ———— ——

PORTE

— — ———— ——

PORTF

— — ———— ——

PORTG

— — ———— ——

HighSpeed

Clock Division Sleep

Module Stop

All Module Clock Stop

Software Standby

Hardware Standby Module

PORT

Item Page Revision (See Manual for Details)

23.3 Register States in

Each Operating Mode

729 Table amended.

TDR_ Initialized

0 ——— SSR_0 RDR_0 TDR_1 SSR_1 RDR_1 TDR_2 SSR_2 RDR_2

High-

Reset

Speed

———

Initialized

———

Initialized

———

Initialized Initialized

——— ———

Initialized

———

Initialized

———

Initialized

———

Initialized

Clock Division

Module

Sleep

All Module

Stop

Clock Stop

Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized

Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized

Software Standby

Hardware Standby

Module

SCI_0

SCI_1

SCI_2

24.1.1 Absolute Maximum Ratings

Table 24.1 Absolute Maximum Ratin gs

24.1.2 DC Characteristics Table 24.2 DC

Characteristics (1)

Table 24.3 DC Characteristics (2)

24.1.3 AC Characteristics Figure 24.15 DRAM

Access Timing: Two-State Burst Access

733 Table amended.

Item Symbol Value Unit

Input voltage (except ports 4, 9) V

Input voltage (ports 4, 9) V

733 Table amended.

Item Symbol Min Typ Max Unit

Schmitt

Ports 1, 2, and 4*2,

trigger input

P50 to P53* PA4 to PA7*

voltage

735, 736

Table amended.

Item Symbol Min Typ Max Unit

Current

Normal operation I

dissipation*

Sleep mode — 55

Standby mode*

During A/D and D/A conversion

power supply

Idle — 0.01 5.0 µA

current

During A/D and D/A conversion

power supply

Idle — 0.01 5.0 µA

current

RAM standby voltage V

Note *4 amended and note *5 deleted. Notes: *4ICC depends on VCC and f as follows:

max = 1.0 (mA) + 0.95 (mA/(MHz × V)) ×

× f (normal operation)

max = 1.0 (mA) + 0.8 (mA/(MHz × V)) ×

× f (sleep mode)

754 Note amended.

Notes: DACK timing: when DDS =

RAS timing: when RAST =

–0.3 to VCC +0.3 V

–0.3 to AVCC +0.3 V

–

VCC × 0.2 —— V

VT+——VCC × 0.7 V

VT+ – VT–VCC × 0.07 —— V

*4— 75

RAM

(3.3 V)

— 0.01 10 µATa ≤ 50˚C

——80µA 50˚C < T

—0.3

(3.0 V)

—2.0

(3.0 V)

2.0 — — V

Test Conditions

Test

115 mA f = 33 MHz

95 mA f = 33 MHz

2.0 mAAnalog

3.5 mAReference

Conditions

Rev. 2.00, 05/03, page xvii of lii

Item Page Revision (See Manual for Details)

24.1.3 AC Characteristics Figure 24.16 DRAM

Access Timing: Three-Stat e

755 Note amended.

Notes: DACK timing: when DDS = 0

RAS timing: when RAST =

Access (RAST = 1)

24.1.4 A/D Conversion Characteristics

Table 24.11 A/D

768 Table amended.

Item Min Typ Max Unit

Quantization error ——±0.5 LSB

Absolute accuracy ——±6.0 LSB

Conversion Characteristics

24.2.1 Absolute Maximum Ratings

Table 24.13 Absolute Maximum Ratin gs

24.2.2 DC Characteristics Table 24.14 DC

Characteristics (1)

24.2.2 DC Characteristics Table 24.15 DC Characteristics (2)

769 Table amended.

Item Symbol Value Unit

Power supply voltage V

Input voltage (except ports 4, 9) V

Input voltage (ports 4, 9) V

770 Table amended.

Item Symbol Min Typ Max Unit

Schmitt

Ports 1, 2, and 4*2, P50 to P53* PA4 to PA7*

trigger input voltage

771, 772 Table amended.

Item Symbol Min Typ Max Unit

Normal operation I

Current

dissipation*

Sleep mode — 55

Standby mode*

During A/D and D/A conversion

power supply

Idle — 0.01 5.0 µA

current

During A/D and D/A conversion

power supply

Idle — 0.01 0.5 µA

current

RAM standby voltage V

–0.3 to +4.0 V

PLLV

–0.3 to VCC +0.3 V

–0.3 to AVCC +0.3 V

–

VCC × 0.2 —— V

VT+——VCC × 0.7 V

VT+ – VT–VCC × 0.07 —— V

*4— 75

RAM

(3.3 V)

— 0.01 10 µATa ≤ 50˚C

——80 µA50˚C < T

—

0.3 (3.0 V)

— 2.0

(3.0 V)

2.0 —— V

Note *4 amended and note *5 deleted.

depends on VCC and f as follows:

max = 1.0 (mA) + 0.95 (mA/(MHz × V)) ×

× f (normal operation)

max = 1.0 (mA) + 0.8 (mA/(MHz × V)) ×

× f (sleep mode)

24.2.3 A/D Conversion Characteristics

Table 24.23 A/D Conversion Characteristics

Notes: *4I

780 Table amended.

Item Min Typ Max Unit

Resolution 10 10 10 Bit

Conversion time 8.1 ——µs

Quantization error ——±0.5 LSB

Absolute accuracy ——±6.0 LSB

Test Conditions

Test

115 mA f = 33 MHz

95 mA f = 33 MHz

2.0 mAAnalog

3.5 mAReference

Conditions

Rev. 2.00, 05/03, page xviii of lii

Item Page Revision (See Manual for Details)

Appendix A. I/O Port States in Each Pin State

785 Port name amended.

(Error) P35 → (Correction) P35/(OE)

790 Table amended.

Port Name

PF0/

MCU Operating Mode Reset

1, 2, 4, 7 T T [

Hardware Standby Mode

Software Standby Mode

input]

output,

[ OPE = 0] T

output,

[ OPE = 1] H [Other than the above] Keep

Bus Release State

[

input]

output]

[ T [Other than the above] Keep

Program Execution State Sleep Mode

[

input]

[ output]

[Other than the above] I/O port

Appendix B. Product Lineup

Appendix C. Package Dimensions

Figure C.2 Package Dimensions (FP-128B)

792 Table amended.

Product Type Name Model Marking Package (Code)

H8S/2367 F-ZTAT version HD64F2367 HD64F2367

H8S/2366 F-ZTAT version HD64F2366 HD64F2366

H8S/2365 Masked ROM version HD6432365 HD6432365

H8S/2363 ROMless version HD6412363 HD6412363

794 Figure replaced.

22.0 ± 0.2

102

103

16.0 ± 0.2

128

*0.22 ± 0.05

0.20 ± 0.04

0.10

0.5

0.75 0.75

+0.15

2.70

−0.10

0.10

3.15 Max

*0.17 ± 0.05

0.15 ± 0.04

120-pin TFP (TFP-120, TFP-120V*)

128-pin QFP (FP-128B, FP-128BV*)

1.0

0.5 ± 0.2

0° − 8°

Rev. 2.00, 05/03, page xix of lii

Rev. 2.00, 05/03, page xx of lii

Section 1 Overview........................................................................................... 1

1.1 Features............................................................................................................................. 1

1.2 Block Diagram.................................................................................................................. 3

1.3 Pin Description.................................................................................................................. 5

1.3.1 Pin Arrangement.................................................................................................. 5

1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 9

1.3.3 Pin Functions ....................................................................................................... 14

Section 2 CPU................................................................................................... 21

2.1 Features............................................................................................................................. 21

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 22

2.1.2 Differences from H8/300 CPU ............................................................................ 23

2.1.3 Differences from H8/300H CPU.......................................................................... 23

2.2 CPU Operating Modes...................................................................................................... 24

2.2.1 Normal Mode....................................................................................................... 24

2.2.2 Advanced Mode................................................................................................... 25

2.3 Address Space................................................................................................................... 28

2.4 Register Configuration...................................................................................................... 29

2.4.1 General Registers................................................................................................. 30

2.4.2 Program Counter (PC) ......................................................................................... 31

2.4.3 Extended Control Register (EXR) ....................................................................... 31

2.4.4 Condition-Code Register (CCR).......................................................................... 32

2.4.5 Initial Register Values.......................................................................................... 34

2.5 Data Formats..................................................................................................................... 34

2.5.1 General Register Data Formats............................................................................ 34

2.5.2 Memory Data Formats ......................................................................................... 36

2.6 Instruction Set................................................................................................................... 37

2.6.1 Table of Instructions Classified by Function ....................................................... 38

2.6.2 Basic Instruction Formats .................................................................................... 47

2.7 Addressing Modes and Effective Address Calculation..................................................... 48

2.7.1 Register Direct—Rn............................................................................................. 49

2.7.2 Register Indirect—@ERn.................................................................................... 49

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 49

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.. 49

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 49

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 50

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC).................................... 50

2.7.8 Memory Indirect—@@aa:8 ................................................................................ 50

2.7.9 Effective Address Calculation ............................................................................. 51

Rev. 2.00, 05/03, page xxi of lii

2.8 Processing States............................................................................................................... 54

2.9 Usage Note........................................................................................................................ 55

2.9.1 Note on Bit Manipulation Instructions................................................................. 55

Section 3 MCU Operating Modes..................................................................... 57

3.1 Operating Mode Selection ................................................................................................ 57

3.2 Register Descriptions........................................................................................................58

3.2.1 Mode Control Register (MDCR) ......................................................................... 58

3.2.2 System Control Register (SYSCR)...................................................................... 58

3.3 Operating Mode Descriptions........................................................................................... 60

3.3.1 Mode 1................................................................................................................. 60

3.3.2 Mode 2................................................................................................................. 60

3.3.3 Mode 3................................................................................................................. 60

3.3.4 Mode 4................................................................................................................. 60

3.3.5 Mode 7................................................................................................................. 61

3.3.6 Pin Functions ....................................................................................................... 61

3.4 Memory Map in Each Operating Mode............................................................................ 62

Section 4 Exception Handling........................................................................... 69

4.1 Exception Handling Types and Priority............................................................................ 69

4.2 Exception Sources and Exception Vector Table............................................................... 69

4.3 Reset ....................................................................................................................... .......... 71

4.3.1 Reset Exception Handling ................................................................................... 71

4.3.2 Interrupts after Reset............................................................................................ 73

4.3.3 On-Chip Peripheral Functions after Reset Release.............................................. 73

4.4 Traces ................................................................................................................................ 74

4.5 Interrupts........................................................................................................................... 74

4.6 Trap Instruction................................................................................................................. 75

4.7 Stack Status after Exception Handling.............................................................................. 76

4.8 Usage Notes...................................................................................................................... 77

Section 5 Interrupt Controller............................................................................ 79

5.1 Features............................................................................................................................. 79

5.2 Input/Output Pins.............................................................................................................. 81

5.3 Register Descriptions........................................................................................................81

5.3.1 Interrupt Control Register (INTCR) .................................................................... 82

5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 82

5.3.3 IRQ Enable Register (IER).................................................................................. 84

5.3.4 IRQ Sense Control Register L (ISCRL)............................................................... 85

5.3.5 IRQ Status Register (ISR).................................................................................... 88

5.3.6 IRQ Pin Select Register (ITSR)........................................................................... 89

5.3.7 Software Standby Release IRQ Enable Register (SSIER)................................... 90

5.4 Interrupt Sources............................................................................................................... 90

Rev. 2.00, 05/03, page xxii of lii

5.4.1 External Interrupts ............................................................................................... 90

5.4.2 Internal Interrupts................................................................................................. 91

5.5 Interrupt Exception Handling Vector Table...................................................................... 92

5.6 Interrupt Control Modes and Interrupt Operation............................................................. 97

5.6.1 Interrupt Control Mode 0..................................................................................... 97

5.6.2 Interrupt Control Mode 2..................................................................................... 99

5.6.3 Interrupt Exception Handling Sequence .............................................................. 100

5.6.4 Interrupt Response Times .................................................................................... 102

5.6.5 DTC and DMAC* Activation by Interrupt.......................................................... 103

5.7 Usage Notes ...................................................................................................................... 103

5.7.1 Contention between Interrupt Generation and Disabling ..................................... 103

5.7.2 Instructions that Disable Interrupts...................................................................... 104

5.7.3 Times when Interrupts are Disabled .................................................................... 104

5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 104

5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ............................................. 105

5.7.6 Note on IRQ Status Register (ISR)...................................................................... 105

Section 6 Bus Controller (BSC)........................................................................ 107

6.1 Features............................................................................................................................. 107

6.2 Input/Output Pins.............................................................................................................. 109

6.3 Register Descriptions........................................................................................................ 110

6.3.1 Bus Width Control Register (ABWCR)............................................................... 111

6.3.2 Access State Control Register (ASTCR) ............................................................. 111

6.3.3 Wait Control Registers AH, AL, BH, and BL

(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)........................................... 112

6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................ 117

6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL) ................... 118

6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)

Area 1 Burst ROM Interface Control Register (BROMCRL).............................. 120

6.3.7 Bus Control Register (BCR)................................................................................ 121

6.3.8 DRAM Control Register (DRAMCR) ................................................................. 123

6.3.9 DRAM Access Control Register (DRACCR)...................................................... 128

6.3.10 Refresh Control Register (REFCR)..................................................................... 129

6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 132

6.3.12 Refresh Time Constant Register (RTCOR)......................................................... 132

6.4 Operation .......................................................................................................................... 132

6.4.1 Area Division....................................................................................................... 132

6.4.2 Bus Specifications ................................................................................................ 134

6.4.3 Memory Interfaces............................................................................................... 136

6.4.4 Chip Select Signals .............................................................................................. 137

6.5 Basic Bus Interface........................................................................................................... 138

6.5.1 Data Size and Data Alignment............................................................................. 138

6.5.2 Valid Strobes........................................................................................................ 139

Rev. 2.00, 05/03, page xxiii of lii

6.5.3 Basic Timing........................................................................................................ 140

6.5.4 Wait Control ........................................................................................................ 148

6.5.5 Read Strobe (RD) Timing.................................................................................... 149

6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. 150

6.6 DRAM Interface ............................................................................................................... 152

6.6.1 Setting DRAM Space........................................................................................... 152

6.6.2 Address Multiplexing .......................................................................................... 152

6.6.3 Data Bus............................................................................................................... 153

6.6.4 Pins Used for DRAM Interface............................................................................ 154

6.6.5 Basic Timing........................................................................................................ 155

6.6.6 Column Address Output Cycle Control............................................................... 156

6.6.7 Row Address Output State Control...................................................................... 156

6.6.8 Precharge State Control ....................................................................................... 159

6.6.9 Wait Control ........................................................................................................ 160

6.6.10 Byte Access Control ............................................................................................ 163

6.6.11 Burst Operation.................................................................................................... 164

6.6.12 Refresh Control.................................................................................................... 168

6.6.13 DMAC Single Address Transfer Mode and DRAM Interface............................. 173

6.7 Burst ROM Interface......................................................................................................... 176

6.7.1 Basic Timing........................................................................................................ 176

6.7.2 Wait Control ........................................................................................................ 178

6.7.3 Write Access........................................................................................................ 178

6.8 Idle Cycle.......................................................................................................................... 179

6.8.1 Operation ............................................................................................................. 179

6.8.2 Pin States in Idle Cycle........................................................................................ 189

6.9 Write Data Buffer Function .............................................................................................. 189

6.10 Bus Release....................................................................................................................... 190

6.10.1 Operation ............................................................................................................. 190

6.10.2 Pin States in External Bus Released State............................................................ 192

6.10.3 Transition Timing................................................................................................ 193

6.11 Bus Arbitration ................................................................................................................. 194

6.11.1 Operation ............................................................................................................. 194

6.11.2 Bus Transfer Timing............................................................................................ 195

6.12 Bus Controller Operation in Reset.................................................................................... 196

6.13 Usage Notes ...................................................................................................................... 196

6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 196

6.13.2 External Bus Release Function and Software Standby........................................ 196

6.13.3 External Bus Release Function and CBR Refreshing.......................................... 196

6.13.4 BREQO Output Timing....................................................................................... 197

Section 7 DMA Controller (DMAC).................................................................199

7.1 Features............................................................................................................................. 199

7.2 Input/Output Pins.............................................................................................................. 201

Rev. 2.00, 05/03, page xxiv of lii

7.3 Register Descriptions........................................................................................................ 201

7.3.1 Memory Address Registers (MARA and MARB)............................................... 202

7.3.2 I/O Address Registers (IOARA and IOARB)...................................................... 203

7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) .................................. 203

7.3.4 DMA Control Registers (DMACRA and DMACRB)......................................... 204

7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)............. 211

7.3.6 DMA Write Enable Register (DMAWER).......................................................... 223

7.3.7 DMA Terminal Control Register (DMATCR)..................................................... 225

7.4 Activation Sources............................................................................................................ 226

7.4.1 Activation by Internal Interrupt Request.............................................................. 226

7.4.2 Activation by External Request ........................................................................... 227

7.4.3 Activation by Auto-Request................................................................................. 227

7.5 Operation .......................................................................................................................... 228

7.5.1 Transfer Modes.................................................................................................... 228

7.5.2 Sequential Mode .................................................................................................. 230

7.5.3 Idle Mode............................................................................................................. 232

7.5.4 Repeat Mode........................................................................................................ 234

7.5.5 Single Address Mode........................................................................................... 237

7.5.6 Normal Mode....................................................................................................... 240

7.5.7 Block Transfer Mode........................................................................................... 243

7.5.8 Basic Bus Cycles.................................................................................................. 249

7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles............................................... 249

7.5.10 DMA Transfer (Single Address Mode) Bus Cycles............................................. 257

7.5.11 Write Data Buffer Function ................................................................................. 263

7.5.12 Multi-Channel Operation..................................................................................... 264

7.5.13 Relation between DMAC and External Bus Requests and Refresh Cycles......... 265

7.5.14 DMAC and NMI Interrupts.................................................................................. 266

7.5.15 Forced Termination of DMAC Operation............................................................ 266

7.5.16 Clearing Full Address Mode................................................................................ 267

7.6 Interrupt Sources............................................................................................................... 268

7.7 Usage Notes ...................................................................................................................... 269

7.7.1 DMAC Register Access during Operation........................................................... 269

7.7.2 Module Stop......................................................................................................... 271

7.7.3 Write Data Buffer Function ................................................................................. 271

7.7.4 TEND Output....................................................................................................... 271

7.7.5 Activation by Falling Edge on DREQ Pin........................................................... 272

7.7.6 Activation Source Acceptance............................................................................. 273

7.7.7 Internal Interrupt after End of Transfer................................................................ 273

7.7.8 Channel Re-Setting .............................................................................................. 273

Section 8 Data Transfer Controller (DTC) ....................................................... 275

8.1 Features............................................................................................................................. 275

8.2 Register Descriptions........................................................................................................ 276

Rev. 2.00, 05/03, page xxv of lii

8.2.1 DTC Mode Register A (MRA) ............................................................................ 277

8.2.2 DTC Mode Register B (MRB)............................................................................. 278

8.2.3 DTC Source Address Register (SAR).................................................................. 278

8.2.4 DTC Destination Address Register (DAR).......................................................... 278

8.2.5 DTC Transfer Count Register A (CRA).............................................................. 278

8.2.6 DTC Transfer Count Register B (CRB)............................................................... 279

8.2.7 DTC Enable Registers A to G (DTCERA to DTCERG) ..................................... 279

8.2.8 DTC Vector Register (DTVECR)........................................................................ 279

8.3 Activation Sources............................................................................................................ 280

8.4 Location of Register Information and DTC Vector Table................................................ 281

8.5 Operation .......................................................................................................................... 284

8.5.1 Normal Mode....................................................................................................... 286

8.5.2 Repeat Mode........................................................................................................ 287

8.5.3 Block Transfer Mode........................................................................................... 288

8.5.4 Chain Transfer ..................................................................................................... 289

8.5.5 Interrupts.............................................................................................................. 290

8.5.6 Operation Timing................................................................................................. 291

8.5.7 Number of DTC Execution States ....................................................................... 292

8.6 Procedures for Using DTC................................................................................................ 293

8.6.1 Activation by Interrupt......................................................................................... 293

8.6.2 Activation by Software ........................................................................................ 293

8.7 Examples of Use of the DTC............................................................................................ 293

8.7.1 Normal Mode....................................................................................................... 293

8.7.2 Chain Transfer ..................................................................................................... 294

8.7.3 Chain Transfer when Counter = 0........................................................................ 295

8.7.4 Software Activation ............................................................................................. 296

8.8 Usage Notes...................................................................................................................... 297

8.8.1 Module Stop Mode Setting.................................................................................. 297

8.8.2 On-Chip RAM ..................................................................................................... 297

8.8.3 DTCE Bit Setting................................................................................................. 297

8.8.4 DMAC Transfer End Interrupt............................................................................. 297

8.8.5 Chain Transfer ..................................................................................................... 297

Section 9 I/O Ports.............................................................................................299

9.1 Port 1................................................................................................................................. 303

9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 303

9.1.2 Port 1 Data Register (P1DR)................................................................................ 304

9.1.3 Port 1 Register (PORT1)...................................................................................... 304

9.1.4 Pin Functions ....................................................................................................... 305

9.2 Port 2................................................................................................................................. 313

9.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 313

9.2.2 Port 2 Data Register (P2DR)................................................................................ 313

9.2.3 Port 2 Register (PORT2)...................................................................................... 314

Rev. 2.00, 05/03, page xxvi of lii

9.2.4 Pin Functions ....................................................................................................... 315

9.3 Port 3................................................................................................................................. 323

9.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 323

9.3.2 Port 3 Data Register (P3DR)................................................................................ 324

9.3.3 Port 3 Register (PORT3)...................................................................................... 324

9.3.4 Port 3 Open Drain Control Register (P3ODR)..................................................... 325

9.3.5 Port Function Control Register 2 (PFCR2).......................................................... 326

9.3.6 Pin Functions ....................................................................................................... 327

9.4 Port 4................................................................................................................................. 330

9.4.1 Port 4 Register (PORT4)...................................................................................... 330

9.4.2 Pin Functions ....................................................................................................... 331

9.5 Port 5................................................................................................................................. 333

9.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 333

9.5.2 Port 5 Data Register (P5DR)................................................................................ 333

9.5.3 Port 5 Register (PORT5)...................................................................................... 334

9.5.4 Pin Functions ....................................................................................................... 334

9.6 Port 8................................................................................................................................. 336

9.6.1 Port 8 Data Direction Register (P8DDR)............................................................. 336

9.6.2 Port 8 Data Register (P8DR)................................................................................ 337

9.6.3 Port 8 Register (PORT8)...................................................................................... 337

9.6.4 Pin Functions ....................................................................................................... 338

9.7 Port 9................................................................................................................................. 339

9.7.1 Port 9 Register (PORT9)...................................................................................... 339

9.7.2 Pin Functions ....................................................................................................... 339

9.8 Port A................................................................................................................................ 340

9.8.1 Port A Data Direction Register (PADDR)........................................................... 341

9.8.2 Port A Data Register (PADR).............................................................................. 342

9.8.3 Port A Register (PORTA).................................................................................... 342

9.8.4 Port A MOS Pull-Up Control Register (PAPCR)................................................ 343

9.8.5 Port A Open Drain Control Register (PAODR)................................................... 343

9.8.6 Port Function Control Register 0 (PFCR0).......................................................... 344

9.8.7 Port Function Control Register 1 (PFCR1).......................................................... 344

9.8.8 Pin Functions ....................................................................................................... 345

9.8.9 Port A MOS Input Pull-Up States........................................................................ 347

9.9 Port B................................................................................................................................ 348

9.9.1 Port B Data Direction Register (PBDDR)............................................................ 348

9.9.2 Port B Data Register (PBDR) .............................................................................. 349

9.9.3 Port B Register (PORTB) .................................................................................... 349

9.9.4 Port B MOS Pull-Up Control Register (PBPCR)................................................. 350

9.9.5 Pin Functions ....................................................................................................... 350

9.9.6 Port B MOS Input Pull-Up States........................................................................ 351

9.10 Port C ................................................................................................................................ 352

9.10.1 Port C Data Direction Register (PCDDR)............................................................ 352

Rev. 2.00, 05/03, page xxvii of lii

9.10.2 Port C Data Register (PCDR).............................................................................. 353

9.10.3 Port C Register (PORTC).................................................................................... 353

9.10.4 Port C MOS Pull-Up Control Register (PCPCR) ................................................ 354

9.10.5 Pin Functions....................................................................................................... 354

9.10.6 Port C MOS Input Pull-Up States........................................................................ 355

9.11 Port D................................................................................................................................ 356

9.11.1 Port D Data Direction Register (PDDDR)........................................................... 356

9.11.2 Port D Data Register (PDDR).............................................................................. 356

9.11.3 Port D Register (PORTD).................................................................................... 357

9.11.4 Port D Pull-up Control Register (PDPCR)........................................................... 357

9.11.5 Pin Functions....................................................................................................... 358

9.11.6 Port D MOS Input Pull-Up States........................................................................ 358

9.12 Port E ................................................................................................................................ 359

9.12.1 Port E Data Direction Register (PEDDR)............................................................ 359

9.12.2 Port E Data Register (PEDR)............................................................................... 360

9.12.3 Port E Register (PORTE)..................................................................................... 360

9.12.4 Port E Pull-up Control Register (PEPCR) ........................................................... 361

9.12.5 Pin Functions....................................................................................................... 361

9.12.6 Port E MOS Input Pull-Up States........................................................................ 362

9.13 Port F ................................................................................................................................ 362

9.13.1 Port F Data Direction Register (PFDDR) ............................................................ 363

9.13.2 Port F Data Register (PFDR)............................................................................... 364

9.13.3 Port F Register (PORTF)..................................................................................... 364

9.13.4 Pin Functions....................................................................................................... 365

9.14 Port G................................................................................................................................ 368

9.14.1 Port G Data Direction Register (PGDDR)........................................................... 368

9.14.2 Port G Data Register (PGDR).............................................................................. 370

9.14.3 Port G Register (PORTG).................................................................................... 370

9.14.4 Pin Functions....................................................................................................... 371

Section 10 16-Bit Timer Pulse Unit (TPU).......................................................373

10.1 Features............................................................................................................................. 373

10.2 Input/Output Pins.............................................................................................................. 377

10.3 Register Descriptions........................................................................................................ 378

10.3.1 Timer Control Register (TCR)............................................................................. 380

10.3.2 Timer Mode Register (TMDR)............................................................................ 385

10.3.3 Timer I/O Control Register (TIOR)..................................................................... 386

10.3.4 Timer Interrupt Enable Register (TIER).............................................................. 404

10.3.5 Timer Status Register (TSR)................................................................................ 406

10.3.6 Timer Counter (TCNT)........................................................................................ 408

10.3.7 Timer General Register (TGR)............................................................................ 409

10.3.8 Timer Start Register (TSTR) ............................................................................... 409

10.3.9 Timer Synchronous Register (TSYR).................................................................. 410

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10.4 Operation .......................................................................................................................... 411

10.4.1 Basic Functions.................................................................................................... 411

10.4.2 Synchronous Operation........................................................................................ 416

10.4.3 Buffer Operation.................................................................................................. 418

10.4.4 Cascaded Operation............................................................................................. 422

10.4.5 PWM Modes........................................................................................................ 424

10.4.6 Phase Counting Mode.......................................................................................... 429

10.5 Interrupts........................................................................................................................... 435

10.6 DTC Activation................................................................................................................. 437

10.7 DMAC Activation............................................................................................................. 437

10.8 A/D Converter Activation................................................................................................. 437

10.9 Operation Timing.............................................................................................................. 438

10.9.1 Input/Output Timing............................................................................................ 438

10.9.2 Interrupt Signal Timing........................................................................................ 441

10.10 Usage Notes ...................................................................................................................... 444

10.10.1 Module Stop Mode Setting.................................................................................. 444

10.10.2 Input Clock Restrictions ...................................................................................... 444

10.10.3 Caution on Cycle Setting..................................................................................... 445

10.10.4 Contention between TCNT Write and Clear Operations..................................... 445

10.10.5 Contention between TCNT Write and Increment Operations.............................. 446

10.10.6 Contention between TGR Write and Compare Match......................................... 447

10.10.7 Contention between Buffer Register Write and Compare Match........................ 447

10.10.8 Contention between TGR Read and Input Capture.............................................. 448

10.10.9 Contention between TGR Write and Input Capture............................................. 449

10.10.10 Contention between Buffer Register Write and Input Capture........................ 449

10.10.11 Contention between Overflow/Underflow and Counter Clearing.................... 450

10.10.12 Contention between TCNT Write and Overflow/Underflow........................... 451

10.10.13 Multiplexing of I/O Pins.................................................................................. 451

10.10.14 Interrupts and Module Stop Mode................................................................... 451

Section 11 Programmable Pulse Generator (PPG) ........................................... 453

11.1 Features............................................................................................................................. 453

11.2 Input/Output Pins.............................................................................................................. 455

11.3 Register Descriptions ........................................................................................................ 455

11.3.1 Next Data Enable Registers H, L (NDERH, NDERL)......................................... 456

11.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 457

11.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 458

11.3.4 PPG Output Control Register (PCR).................................................................... 460

11.3.5 PPG Output Mode Register (PMR)...................................................................... 461

11.4 Operation .......................................................................................................................... 463

11.4.1 Output Timing...................................................................................................... 464

11.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 465

11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 466

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11.4.4 Non-Overlapping Pulse Output............................................................................ 467

11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output.............................. 468

11.4.6 Example of Non-Overlapping Pulse Output

(Example of Four-Phase Complementary Non-Overlapping Output) ................. 469

11.4.7 Inverted Pulse Output .......................................................................................... 471

11.4.8 Pulse Output Triggered by Input Capture ............................................................ 472

11.5 Usage Notes ...................................................................................................................... 472

11.5.1 Module Stop Mode Setting.................................................................................. 472

11.5.2 Operation of Pulse Output Pins............................................................................ 472

Section 12 8-Bit Timers (TMR) ........................................................................473

12.1 Features............................................................................................................................. 473

12.2 Input/Output Pins.............................................................................................................. 475

12.3 Register Descriptions........................................................................................................ 475

12.3.1 Timer Counter (TCNT)........................................................................................ 475

12.3.2 Time Constant Register A (TCORA)................................................................... 476

12.3.3 Time Constant Register B (TCORB)................................................................... 476

12.3.4 Timer Control Register (TCR)............................................................................. 476

12.3.5 Timer Control/Status Register (TCSR)................................................................ 478

12.4 Operation .......................................................................................................................... 481

12.4.1 Pulse Output......................................................................................................... 481

12.5 Operation Timing.............................................................................................................. 482

12.5.1 TCNT Incrementation Timing............................................................................. 482

12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs................. 483

12.5.3 Timing of Timer Output when Compare-Match Occurs...................................... 483

12.5.4 Timing of Compare Match Clear......................................................................... 484

12.5.5 Timing of TCNT External Reset.......................................................................... 484

12.5.6 Timing of Overflow Flag (OVF) Setting............................................................. 485

12.6 Operation with Cascaded Connection............................................................................... 485

12.6.1 16-Bit Counter Mode........................................................................................... 485

12.6.2 Compare Match Count Mode............................................................................... 486

12.7 Interrupts........................................................................................................................... 486

12.7.1 Interrupt Sources and DTC Activation ................................................................ 486

12.7.2 A/D Converter Activation.................................................................................... 487

12.8 Usage Notes ...................................................................................................................... 488

12.8.1 Contention between TCNT Write and Clear........................................................ 488

12.8.2 Contention between TCNT Write and Increment................................................ 488

12.8.3 Contention between TCOR Write and Compare Match...................................... 489

12.8.4 Contention between Compare Matches A and B................................................. 490

12.8.5 Switching of Internal Clocks and TCNT Operation ............................................ 491

12.8.6 Mode Setting with Cascaded Connection............................................................ 493

12.8.7 Interrupts in Module Stop Mode.......................................................................... 493

Rev. 2.00, 05/03, page xxx of lii

+ 845 hidden pages

Renesas H8S/2368 Series, H8S Series, H8S/2300 Series Hardware Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Cautions

General Precautions on Handling of Product

Configuration of This Manual

Preface

Main Revisions and Additions in this Edition

Contents