Renesas H8S/2368 Series, H8S Series, H8S/2300 Series Hardware Manual

H8S/2368

The revision list can be viewed directly by clicking the title page.

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

Group

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family/H8S/2300 Series

Rev.2.00

2003.5.23

Renesas 16-Bit Single-Chip Microcomputer

H8S/Family/H8S/2300 Series

H8S/2368 Group

Hardware Manual

REJ09B0050-0200O

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliabl e, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or propert y da mage. Remember to give due consideration to safety when making your circuit designs, with appropriate measu res such as (i) placement of substitutive, auxiliar y circuits, (ii) use of nonflammable materia l or (iii) preve n tio n agai n st any malf unc tio n or mishap.

Notes regar ding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.

2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party 's rights, originating in th e u se of any product data, diagrams, charts, programs, algorithms, or circuit applicatio n examples contained in these materials.

3. All information contained in these materials, including product data, diag rams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product informati o n be fore purc ha sing a produc t listed herein. The informa tion descri bed here may c o ntain techni c al inaccuracies or typ og r aphical err ors. Renesas Technology Corp oration assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas .com).

4. When usi ng any or all of the informat i on containe d i n th e s e ma terials, inc luding prod uct data, diagrams, chart s, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corpora tion assumes no responsibilit y for any damage, liability or ot her loss resulting from the information contained herein.

5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Te chnology Corporation product dis tributor when considering the use of a product contained herein for any specific purposes, such as apparat us or system s for tra nsp or ta tio n, veh icul ar, medica l, aer o space, nucle ar, or unders ea repeater use.

6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.

7. If these products o r technologies are sub ject to the Japanese exp ort contro l restrictions, they must be exported under a l i cense from the Japanese govern ment and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export contro l laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corporation for further details on these materials or the products contained the rein.

Rev. 2.00, 05/03, page iv of lii

General Precautions on Handling of Product

1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction m ay occur.

3. Processing before Initializatio n Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.

Rev. 2.00, 05/03, page v of lii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Ed ition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see th e actual locations in this manual.

11.Index

Rev. 2.00, 05/03, page vi of lii

Preface

The H8S/2368 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas Technology’s original architecture as their cores, and the peripheral functions required to configure a system.

The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a 16-Mbyte linear address space.

This LSI is equipped with direct memory access controller (DMAC) and data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), 8-bit timers (TMR), a watchdog timer (WDT), serial communication interfaces (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as onchip peripheral modules required for system configuration. I included as an optional interface.

A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM and other kinds of memory.

A single-power flash memory (F-ZTAT

) version is available for this LSI's ROM. This provides flexibility as it can be reprogrammed in no time to cope with all situ ations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change.

C bus interface 2 (IIC2) can also be

Note: F-ZTAT

is a trademark of Renesas Technology Corp.

Target Users: This manual was written for users who will be using the H8S/2368 Group in the

design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware function s and electrical

characteristics of the H8S/2368 Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instru ction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.

Rev. 2.00, 05/03, page vii of lii

• In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

For the execution state of each instruction in this LSI, see Appendix D, Bus State during Execution of Instructions.

• In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse un it or ser ial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel

number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require. http://www.renesas.com/

H8S/2368 Group manuals:

Manual Title ADE No.

H8S/2368 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

User's manuals for development tools:

Manual Title ADE No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual

H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-282 H8S, H8/300 Series Hi-Performance Embedded Workshop, HDI Tutorial ADE-702-231 Hi-Performance Embedded Workshop User's Manual ADE-702-201

Rev. 2.00, 05/03, page viii of lii

ADE-702-247

Main Revisions and Additions in this Edition

Item Page Revision (See Manual for Details)

All H8S/2366 added.

1.1 Features 1 Table amended.

ROM Type Model ROM RAM Remarks

Flash memory version HD64F2367 384 kbytes 24 kbytes

Masked ROM version HD6432365 256 kbytes 16 kbytes

ROMless version HD6412363 16 kbytes

1.2 Block Diagram Figure 1.1 Internal Block

Diagram

of H8S/2367,

H8S/2365, and H8S/2363

Description added in the 2nd line. Figures 1.1 and 1.2 show the internal block diagrams

of this LSI. Figure and its title amended. (Error) I2C bus interface (option) →

(Correction) I

Figure 1.2 Internal Block

4 Newly added.

Diagram of H8S/2366

1.3.1 Pin Arrangement 5 Description added in the 3rd line. Figures 1.3 to 1.6 show the pin arrangements of this

LSI.

Figure 1.3 Pin Arrangement of H8S/2367, H8S/2365, and

Pin names of pins 70 and 71 amended and note added to pin 30.

H8S/2363

HD64F2366 384 kbytes 30 kbytes In planning stage

C bus interface 2 (option)

Figure 1.4 Pin Arrangement of H8S/2366

PF6/

PF5/

PF4/

PF3/

PF2/ /

757473727170696867666564636261

2627282930

EMLE*

PA4/A20/

PA5/A21/

PA6/A22/

PA7/A23/ /

Note: * This is an emulator enable pin. Normally, this

pin should be set to low. If this pin goes high in the flash memory version, the on-chip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and WDTOVF function only for the on-chip emulator.

6 Newly added.

PF1/ /

PF0/ /

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Rev. 2.00, 05/03, page ix of lii

Item Page Revision (See Manual for Details)

1.3.1 Pin Arrangement Figure 1.5 Pin Arrangement

7 Pin name of pin 86 amended and note added to pin

34. of H8S/2367, H8S/2365, and H8S/2363

EXTAL

XTAL

VSSPF7/φPLLVSSPLLVCCPF6/

908988878685848382

303132333435363738

PA4/A20/

PA5/A21/

PA6/A22/

PF5/

PF4/

PF3/

PF2/ /

PF1/ /

PF0/ /

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

VSSNC*1VCCPE7/D7

75747677787980

VSSV

NMI

EMLE*

PA7/A23/ /

737271706968676665

Notes: *1The NC pin should be fixed to Vss or should

be open. This is an emulator enable pin. Normally,

this pin should be set to low. If this pin goes high in the flash memory version, the onchip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and WDTOVF function only for the on-chip emulator.

Figure 1.6 Pin Arrangement

8 Newly added.

of H8S/2366

3.3.6 Pin Functions Table 3.2 Pin Functions in

61 Note *2 added

Note: *2 Setting not allowed on no-ROM versions.

Each Operating Mode

3.4 Memory Map in Each

64, 65 Newly added.

Operating Mode Figure 3.3

H8S/2366

Memory Map (1) Figure 3.4

H8S/2366

Memory Map (2) Figure 3.7 H8S/2363

Memory Map

5.1 Features Figure 5.1 Block Diagram

68 Figure amended.

(Error) H′FF6000 → (Correction) H′FF

80 Register name amended.

(Error) ISCR → (Correction) ISCR

of Interrupt Controller

5.3 Register Descriptions 81 Register name amended in the 6th line.

L (ISCRL)

5.3.4 IRQ Sense Control Register

L (ISCRL)

• IRQ sense control register

85 Title amended.

Description amended in the 2nd line. (Error) ISCR → (Correction) ISCR

8000

Rev. 2.00, 05/03, page x of lii

Item Page Revision (See Manual for Details)

5.4.1 External Interrupts 90 Description amended in the 13th line. Using ISCR

L, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0.

6.8.1 Operation 187 Description added in the 1st line. Table 6.7 shows whether an idle cycle is inserted or

not in mixed access to normal space and DRAM.

Section 9 I/O Ports Table 9.1 Port Functions

300 Description of port 2 amended.

(Error) General I/O port also functioning as PPG outputs, TPU I/Os,

TMR I/Os, and bus control I/Os →

(Correction) General I/O port also functioning as PPG

9.1.4 Pin Functions

• P13/PO11*

KB/TEND1*

• P12/PO10*

KA/TEND0*

• P11/PO9*

DREQ1*

/TIOCD0/TCL

/TIOCC0/TCL

/TIOCB0/

outputs, TPU I/Os, and

309 Description amended in the 5th line.

(Error) bit TEEI → (Correction) bit TEE

310 Description amended in the 5th line.

(Error) bit TEEO → (Correction) bit TEE

311 Description amended in the 3rd line.

…(by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0

TMR I/Os

in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0),…

9.2.4 Pin Functions

• P24/PO4*

/TIOCA4/

RxD4/TMO0

318 Description amended in the 3rd line.

The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4

, and bits CCLR1 and CCLR0 in TCR4), bit NDER4*1 in NDERL, bit RE in SCI_4, bit P24DDR, and bit OS3 to OS0 in TCSRO of TMR.

Table amended.

RE 0 1

9.3.5 Port Function Control Register 2 (PFCR2)

TPU channel 4 settings

OS3 to OS0 All 0 Not all 0 —

P24DDR — 0 1 1 — —

NDER4 — — 0 1 — —

Pin function TIOCA4 output

326 Note added.

Note: * In the H8S/2366, this bit is reserved. This bit

(1) in table below (2) in table below

P24

output

TIOCA4 input*

PO4

output*

input

is always read as 1 and the write value should always be 1.

9.3.6 Pin Functions

• P35/SCK1/SCL0/(OE)*

327 Amended.

(Error) C/A → (Correction) C/A

—

TMO0 output

RXD4 input

Rev. 2.00, 05/03, page xi of lii

Item Page Revision (See Manual for Details)

9.6.4 Pin Functions

• P81/TxD3

9.8.6 Port Function Control Register 0 (PFCR0)

338 Amended.

(Error) TxD3 input → (Correction) TxD3

344 Bit table amended.

Bit Bit Name Initial Value R/W Description

7CS7E 1 R/W

6CS6E 1 R/W

5CS5E 1 R/W

4CS4E 1 R/W

3CS3E 1 R/W

2CS2E 1 R/W

1CS1E 1 R/W

0CS0E 1 R/W

to enable

Enable/disable corresponding

0: Set as I/O port.

1: Set as

output pin.

output

output.

(n = 7 to 0)

9.14.4 Pin Functions

• PG3/CS3/RAS3*, PG2/CS2/RAS2*

14.3.9 Bit Rate Register

(BRR) Table 14.3 BRR Settings

for Various Bit Rates (Asynchronous Mode)

Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)

Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)

Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)

Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372)

372 Table amended.

Operating

mode

EXPE — 01

CSnE 0 1 — 01

RMTS2* to RMTS0*

PGnDDR 0 1 0 1 — 010101—

PGn

function

input

1, 2, 4 7

— Area n is in

normal space

PGn

output

PGn input

output

Area n is in DRAM* space

output

——Area n is in

PGn

input

output

input

PGn

output

normal space

PGn input

output

Area n is in DRAM* space

output

529 Values when operating frequency φ is 2 MHz to

7.3728 MHz deleted.

531 Values when operating frequency φ is 2 MHz to

7.3728 MHz deleted.

532 Values when operating frequency φ is 2 MHz to

7.3728 MHz deleted.

533 Values when operating frequency φ is 2 MHz and

4 MHz deleted.

534 Values when operating frequency φ is 2 MHz, 4 MHz,

and 6 MHz deleted.

535 Values when operating frequency φ is 7.1424 MHz

deleted.

Rev. 2.00, 05/03, page xii of lii

Item Page Revision (See Manual for Details)

14.3.9 Bit Rate Register (BRR)

536 Values when operating frequency φ is 7.1424 MHz

deleted.

Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372)

14.8 IrDA Operation Table 14.12 Settings of Bits

IrCKS2 to IrCKS0

579 Values when operating frequency φ is 2 MHz to

7.3728 MHz deleted. Values when operating frequency φ is 30 MHz and

33 MHz deleted.

Operating Frequency φ (MHz)

25 110 110 110 110 110  30 110 110 110 110 110  33 110 110 110 110 110 

2400 9600 19200 38400 57600 115200

78.13 19.53 9.77 4.88 3.26 1.63

Bit Rate (bps) (Above)/Bit Period × 3/16 (ms) (Below)

16.1 Features 619 Description amended in the 7th line.

• Conversion time:

8.1 µs per channel (at 33 MHz

operation)

Figure 16.1 Block Diagram

620 Figure amended.

of A/D Converter

AVCC

16.3.3 A/D Control Register (ADCR)

Vref

AVSS

625 Description added in the 3rd line.

ADCR enables A/D conversion start by an external

10-bit A/D

trigger input. It also sets the A/D converter operating mode and the

A/D conversion time.

17.3.2 D/A Control Register 23 (DACR23)

Table 17.2 Control of D/A Conversion

640 Table amended.

(Error) DAOE1 → (Correction) DAOE (Error) DAOE0 → (Correction) DAOE

Section 18 RAM 643 Table amended.

Product Type Name ROM Type

H8S/2368 Series

HD64F2367 Flash memory version 24 kbytes H'FF6000 to H'FFBFFF

HD64F2366 30 kbytes H'FF4800 to H'FFBFFF

HD6432365 Masked ROM version 16 kbytes H'FF8000 to H'FFBFFF

HD641363 ROMless version

3 2

RAM Capacitance

RAM Address

Rev. 2.00, 05/03, page xiii of lii

Item Page Revision (See Manual for Details)

19.1 Features

• Size

• Flash memory emulation

by RAM

645 Table amended.

Product Classification ROM Size ROM Address

H8S/2368 Series HD64F2367

HD64F2366

Note * added Note: * This function is not supported by the

384 kbytes H'000000 to H'05FFFF (Modes 3, 4, and 7)

H8S/2367 or H8S/2366.

19.3 Block Configuration

651 Note deleted.

Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)

19.5.5 RAM Emulation

656 Note added.

Note: This function is not supported by the

H8S/2367 or H8S/2366.

19.7 Flash Memory

Emulation in RAM

662 Note added.

Note: This function is not supported by the

H8S/2367 or H8S/2366.

663 Note 4 added.

Note: 4. This function is not supported by the

H8S/2367 or H8S/2366.

19.8.2 Erase/Erase-Verify 666 Description amended in the 8th line.

4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc.

21.1.1 System Clock Control Register (SCKCR)

677 Bits 2, 1, and 0 discription amended.

Bit Bit Name Initial Value R/W Description

SCK2

SCK1

SCK0

0 0 0

R/W

System Clock Select 2 to 0

R/W

Select the division ratio.

R/W

000: 1/1

001: 1/2

010: 1/4

011: Setting prohibited

100: Setting prohibited

101: Setting prohibited

11X: Setting prohibited

21.2.1 Connecting a Crystal Oscillator

Rev. 2.00, 05/03, page xiv of lii

678 Description added in the 6th line.

An AT-cut parallel-resonance type should be used. When a clock is supplied with a crystal resonator

connected, the frequency of the crystal resonator should be 8 MHz to 25 MHz.

Item Page Revision (See Manual for Details)

21.2.2 External Clock Input 679 Description added in the 5th line. Table 21.3 shows the input conditions for the external

clock. The frequency of an external clock to be input should

be 8 MHz to 25 MHz.

21.4 Frequency Divider 681 Description amended in the 11th line. The frequency divider divides the PLL output clock to

generate a 1/2 or 1/4 clock.

21.5.3 Notes on Board

Design

682 Description of

values.) deleted.

(Values are preliminary recommended

Figure 21.7 Recommended External Circuitry for PLL Circuit

Section 22 Power-Down Modes

Table 22.1 Operating Modes and Internal States of the LSI

684 Table amended.

High

Operating State

interrupts

Peripheral functions

Speed Mode

NMIExternal

Functions Functions Functions Functions Functions Functions Halted

IRQ0 to 7

A/D Functions Functions Functions Halted

SCI Functions Functions Functions Halted*

IIC2 Functions Functions Functions Halted*

Clock Division Mode

Sleep Mode

Module Stop Mode

(Retained)

(Reset/ Retained)

Notes added. Notes: *3 TDR, SSR, and RDR are halted (reset)

and other registers are halted (retained).

*4 BC2 to BC0 are halted (reset) and other

registers are halted (retained).

22.2.1 Clock Division Mode 690 Description amended in the 5th line. In clock division mode, the CPU, bus masters, and

on-chip peripheral functions all operate on the operating clock (

1/2 or 1/4) specified by bits SCK2 to

SCK0.

22.4.6 Notes on Clock

697 Newly added.

Division Mode

23.1 Register Addresses

(Address Order)

701 IRQ sense control register H deleted.

IRQ pin select register ITSR 16 H'FE16 INT 16 2

Software standby release IRQ enable register

IRQ sense control register L ISCRL 16 H'FE1C INT 16 2

Abbreviation Bit No. Address Module

SSIER 16 H'FE18 INT 16 2

All Module Clock Stop Mode

Halted (Retained)

Halted* (Reset/ Retained)

Software Standby Mode

Halted (Retained)

Halted* (Reset/ Retained)

Data Width

Hardware Standby Mode

Halted (Reset)

Access States

Rev. 2.00, 05/03, page xv of lii

Item Page Revision (See Manual for Details)

23.2 Register Bits 710 Table amended.

————————

CRA

————————

CRB

————————

ICCRA_0 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0

ICCRB_0 BBSY SCP SDAO — SCLO — IICRST —

ICCRA_1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0

ICCRB_1 BBSY SCP SDAO — SCLO — IICRST —

716 *1 deleted after DTC module

(Error) DTC

→ (Correction) DTC

717 Table amended.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 DTC

INTCR ——INTM1 INTM0 NMIEG ———INT

————————IER

IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E

————————ISR

IRQ7F IRQ6F IRQ5F IRQ4 F IRQ3F IRQ2F IRQ1F IRQ0F

SBYCR SSBY OPE ——STS3 STS2 STS1 STS0

SCKCR PSTOP ———STCS SCK2 SCK1 SCK0

SYSCR ————FLSHE — EXPE RAME

23.3 Register States in Each Operating Mode

725 Table amended.

TDR_3 Initialized — — SSR_3 Initialized — — Initialized Initialized Initialized Initialized RDR_3 Initialized — — Initialized Initialized Initialized Initialized TDR_4 Initialized — — — Initialized Initialized Initialized Initialized SSR_4 Initialized — — Initialized Initialized Initialized Initialized RDR_4 Initialized — — Initialized Initialized Initialized Initialized

Reset

HighSpeed

— —

Clock Division

Module Stop

All Module Clock Stop

Sleep

— Initialized Initialized Initialized Initialized

Software Standby

Hardware Standby

IIC2_0

IIC2_1

SYSTEM

Module

SCI_3

SCI_4

Rev. 2.00, 05/03, page xvi of lii

726 Register name amended and deleted.

(Error) DRACCRH → (Correction)

DRACCR

DRACCRL deleted.

728 Table amended.

Reset

Name

— — ———— ——

PORT1

PORT2

— — ———— ——

PORT3

— — ———— ——

PORT4

— — ———— ——

PORT5

— — ———— ——

PORT8

— — ———— ——

PORT9

— — ———— ——

PORTA

— — ———— ——

PORTB

— — ———— ——

PORTC

— — ———— ——

PORTD

— — ———— ——

PORTE

— — ———— ——

PORTF

— — ———— ——

PORTG

— — ———— ——

HighSpeed

Clock Division Sleep

Module Stop

All Module Clock Stop

Software Standby

Hardware Standby Module

PORT

Item Page Revision (See Manual for Details)

23.3 Register States in

Each Operating Mode

729 Table amended.

TDR_ Initialized

0 ——— SSR_0 RDR_0 TDR_1 SSR_1 RDR_1 TDR_2 SSR_2 RDR_2

High-

Reset

Speed

———

Initialized

———

Initialized

———

Initialized Initialized

——— ———

Initialized

———

Initialized

———

Initialized

———

Initialized

Clock Division

Module

Sleep

All Module

Stop

Clock Stop

Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized

Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized

Software Standby

Hardware Standby

Module

SCI_0

SCI_1

SCI_2

24.1.1 Absolute Maximum Ratings

Table 24.1 Absolute Maximum Ratin gs

24.1.2 DC Characteristics Table 24.2 DC

Characteristics (1)

Table 24.3 DC Characteristics (2)

24.1.3 AC Characteristics Figure 24.15 DRAM

Access Timing: Two-State Burst Access

733 Table amended.

Item Symbol Value Unit

Input voltage (except ports 4, 9) V

Input voltage (ports 4, 9) V

733 Table amended.

Item Symbol Min Typ Max Unit

Schmitt

Ports 1, 2, and 4*2,

trigger input

P50 to P53* PA4 to PA7*

voltage

735, 736

Table amended.

Item Symbol Min Typ Max Unit

Current

Normal operation I

dissipation*

Sleep mode — 55

Standby mode*

During A/D and D/A conversion

power supply

Idle — 0.01 5.0 µA

current

During A/D and D/A conversion

power supply

Idle — 0.01 5.0 µA

current

RAM standby voltage V

Note *4 amended and note *5 deleted. Notes: *4ICC depends on VCC and f as follows:

max = 1.0 (mA) + 0.95 (mA/(MHz × V)) ×

× f (normal operation)

max = 1.0 (mA) + 0.8 (mA/(MHz × V)) ×

× f (sleep mode)

754 Note amended.

Notes: DACK timing: when DDS =

RAS timing: when RAST =

–0.3 to VCC +0.3 V

–0.3 to AVCC +0.3 V

–

VCC × 0.2 —— V

VT+——VCC × 0.7 V

VT+ – VT–VCC × 0.07 —— V

*4— 75

RAM

(3.3 V)

— 0.01 10 µATa ≤ 50˚C

——80µA 50˚C < T

—0.3

(3.0 V)

—2.0

(3.0 V)

2.0 — — V

Test Conditions

Test

115 mA f = 33 MHz

95 mA f = 33 MHz

2.0 mAAnalog

3.5 mAReference

Conditions

Rev. 2.00, 05/03, page xvii of lii

Item Page Revision (See Manual for Details)

24.1.3 AC Characteristics Figure 24.16 DRAM

Access Timing: Three-Stat e

755 Note amended.

Notes: DACK timing: when DDS = 0

RAS timing: when RAST =

Access (RAST = 1)

24.1.4 A/D Conversion Characteristics

Table 24.11 A/D

768 Table amended.

Item Min Typ Max Unit

Quantization error ——±0.5 LSB

Absolute accuracy ——±6.0 LSB

Conversion Characteristics

24.2.1 Absolute Maximum Ratings

Table 24.13 Absolute Maximum Ratin gs

24.2.2 DC Characteristics Table 24.14 DC

Characteristics (1)

24.2.2 DC Characteristics Table 24.15 DC Characteristics (2)

769 Table amended.

Item Symbol Value Unit

Power supply voltage V

Input voltage (except ports 4, 9) V

Input voltage (ports 4, 9) V

770 Table amended.

Item Symbol Min Typ Max Unit

Schmitt

Ports 1, 2, and 4*2, P50 to P53* PA4 to PA7*

trigger input voltage

771, 772 Table amended.

Item Symbol Min Typ Max Unit

Normal operation I

Current

dissipation*

Sleep mode — 55

Standby mode*

During A/D and D/A conversion

power supply

Idle — 0.01 5.0 µA

current

During A/D and D/A conversion

power supply

Idle — 0.01 0.5 µA

current

RAM standby voltage V

–0.3 to +4.0 V

PLLV

–0.3 to VCC +0.3 V

–0.3 to AVCC +0.3 V

–

VCC × 0.2 —— V

VT+——VCC × 0.7 V

VT+ – VT–VCC × 0.07 —— V

*4— 75

RAM

(3.3 V)

— 0.01 10 µATa ≤ 50˚C

——80 µA50˚C < T

—

0.3 (3.0 V)

— 2.0

(3.0 V)

2.0 —— V

Note *4 amended and note *5 deleted.

depends on VCC and f as follows:

max = 1.0 (mA) + 0.95 (mA/(MHz × V)) ×

× f (normal operation)

max = 1.0 (mA) + 0.8 (mA/(MHz × V)) ×

× f (sleep mode)

24.2.3 A/D Conversion Characteristics

Table 24.23 A/D Conversion Characteristics

Notes: *4I

780 Table amended.

Item Min Typ Max Unit

Resolution 10 10 10 Bit

Conversion time 8.1 ——µs

Quantization error ——±0.5 LSB

Absolute accuracy ——±6.0 LSB

Test Conditions

Test

115 mA f = 33 MHz

95 mA f = 33 MHz

2.0 mAAnalog

3.5 mAReference

Conditions

Rev. 2.00, 05/03, page xviii of lii

Item Page Revision (See Manual for Details)

Appendix A. I/O Port States in Each Pin State

785 Port name amended.

(Error) P35 → (Correction) P35/(OE)

790 Table amended.

Port Name

PF0/

MCU Operating Mode Reset

1, 2, 4, 7 T T [

Hardware Standby Mode

Software Standby Mode

input]

output,

[ OPE = 0] T

output,

[ OPE = 1] H [Other than the above] Keep

Bus Release State

[

input]

output]

[ T [Other than the above] Keep

Program Execution State Sleep Mode

[

input]

[ output]

[Other than the above] I/O port

Appendix B. Product Lineup

Appendix C. Package Dimensions

Figure C.2 Package Dimensions (FP-128B)

792 Table amended.

Product Type Name Model Marking Package (Code)

H8S/2367 F-ZTAT version HD64F2367 HD64F2367

H8S/2366 F-ZTAT version HD64F2366 HD64F2366

H8S/2365 Masked ROM version HD6432365 HD6432365

H8S/2363 ROMless version HD6412363 HD6412363

794 Figure replaced.

22.0 ± 0.2

102

103

16.0 ± 0.2

128

*0.22 ± 0.05

0.20 ± 0.04

0.10

0.5

0.75 0.75

+0.15

2.70

−0.10

0.10

3.15 Max

*0.17 ± 0.05

0.15 ± 0.04

120-pin TFP (TFP-120, TFP-120V*)

128-pin QFP (FP-128B, FP-128BV*)

1.0

0.5 ± 0.2

0° − 8°

Rev. 2.00, 05/03, page xix of lii

Rev. 2.00, 05/03, page xx of lii

Section 1 Overview........................................................................................... 1

1.1 Features............................................................................................................................. 1

1.2 Block Diagram.................................................................................................................. 3

1.3 Pin Description.................................................................................................................. 5

1.3.1 Pin Arrangement.................................................................................................. 5

1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 9

1.3.3 Pin Functions ....................................................................................................... 14

Section 2 CPU................................................................................................... 21

2.1 Features............................................................................................................................. 21

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 22

2.1.2 Differences from H8/300 CPU ............................................................................ 23

2.1.3 Differences from H8/300H CPU.......................................................................... 23

2.2 CPU Operating Modes...................................................................................................... 24

2.2.1 Normal Mode....................................................................................................... 24

2.2.2 Advanced Mode................................................................................................... 25

2.3 Address Space................................................................................................................... 28

2.4 Register Configuration...................................................................................................... 29

2.4.1 General Registers................................................................................................. 30

2.4.2 Program Counter (PC) ......................................................................................... 31

2.4.3 Extended Control Register (EXR) ....................................................................... 31

2.4.4 Condition-Code Register (CCR).......................................................................... 32

2.4.5 Initial Register Values.......................................................................................... 34

2.5 Data Formats..................................................................................................................... 34

2.5.1 General Register Data Formats............................................................................ 34

2.5.2 Memory Data Formats ......................................................................................... 36

2.6 Instruction Set................................................................................................................... 37

2.6.1 Table of Instructions Classified by Function ....................................................... 38

2.6.2 Basic Instruction Formats .................................................................................... 47

2.7 Addressing Modes and Effective Address Calculation..................................................... 48

2.7.1 Register Direct—Rn............................................................................................. 49

2.7.2 Register Indirect—@ERn.................................................................................... 49

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 49

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.. 49

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 49

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 50

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC).................................... 50

2.7.8 Memory Indirect—@@aa:8 ................................................................................ 50

2.7.9 Effective Address Calculation ............................................................................. 51

Rev. 2.00, 05/03, page xxi of lii

2.8 Processing States............................................................................................................... 54

2.9 Usage Note........................................................................................................................ 55

2.9.1 Note on Bit Manipulation Instructions................................................................. 55

Section 3 MCU Operating Modes..................................................................... 57

3.1 Operating Mode Selection ................................................................................................ 57

3.2 Register Descriptions........................................................................................................58

3.2.1 Mode Control Register (MDCR) ......................................................................... 58

3.2.2 System Control Register (SYSCR)...................................................................... 58

3.3 Operating Mode Descriptions........................................................................................... 60

3.3.1 Mode 1................................................................................................................. 60

3.3.2 Mode 2................................................................................................................. 60

3.3.3 Mode 3................................................................................................................. 60

3.3.4 Mode 4................................................................................................................. 60

3.3.5 Mode 7................................................................................................................. 61

3.3.6 Pin Functions ....................................................................................................... 61

3.4 Memory Map in Each Operating Mode............................................................................ 62

Section 4 Exception Handling........................................................................... 69

4.1 Exception Handling Types and Priority............................................................................ 69

4.2 Exception Sources and Exception Vector Table............................................................... 69

4.3 Reset ....................................................................................................................... .......... 71

4.3.1 Reset Exception Handling ................................................................................... 71

4.3.2 Interrupts after Reset............................................................................................ 73

4.3.3 On-Chip Peripheral Functions after Reset Release.............................................. 73

4.4 Traces ................................................................................................................................ 74

4.5 Interrupts........................................................................................................................... 74

4.6 Trap Instruction................................................................................................................. 75

4.7 Stack Status after Exception Handling.............................................................................. 76

4.8 Usage Notes...................................................................................................................... 77

Section 5 Interrupt Controller............................................................................ 79

5.1 Features............................................................................................................................. 79

5.2 Input/Output Pins.............................................................................................................. 81

5.3 Register Descriptions........................................................................................................81

5.3.1 Interrupt Control Register (INTCR) .................................................................... 82

5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 82

5.3.3 IRQ Enable Register (IER).................................................................................. 84

5.3.4 IRQ Sense Control Register L (ISCRL)............................................................... 85

5.3.5 IRQ Status Register (ISR).................................................................................... 88

5.3.6 IRQ Pin Select Register (ITSR)........................................................................... 89

5.3.7 Software Standby Release IRQ Enable Register (SSIER)................................... 90

5.4 Interrupt Sources............................................................................................................... 90

Rev. 2.00, 05/03, page xxii of lii

5.4.1 External Interrupts ............................................................................................... 90

5.4.2 Internal Interrupts................................................................................................. 91

5.5 Interrupt Exception Handling Vector Table...................................................................... 92

5.6 Interrupt Control Modes and Interrupt Operation............................................................. 97

5.6.1 Interrupt Control Mode 0..................................................................................... 97

5.6.2 Interrupt Control Mode 2..................................................................................... 99

5.6.3 Interrupt Exception Handling Sequence .............................................................. 100

5.6.4 Interrupt Response Times .................................................................................... 102

5.6.5 DTC and DMAC* Activation by Interrupt.......................................................... 103

5.7 Usage Notes ...................................................................................................................... 103

5.7.1 Contention between Interrupt Generation and Disabling ..................................... 103

5.7.2 Instructions that Disable Interrupts...................................................................... 104

5.7.3 Times when Interrupts are Disabled .................................................................... 104

5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 104

5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ............................................. 105

5.7.6 Note on IRQ Status Register (ISR)...................................................................... 105

Section 6 Bus Controller (BSC)........................................................................ 107

6.1 Features............................................................................................................................. 107

6.2 Input/Output Pins.............................................................................................................. 109

6.3 Register Descriptions........................................................................................................ 110

6.3.1 Bus Width Control Register (ABWCR)............................................................... 111

6.3.2 Access State Control Register (ASTCR) ............................................................. 111

6.3.3 Wait Control Registers AH, AL, BH, and BL

(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)........................................... 112

6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................ 117

6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL) ................... 118

6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)

Area 1 Burst ROM Interface Control Register (BROMCRL).............................. 120

6.3.7 Bus Control Register (BCR)................................................................................ 121

6.3.8 DRAM Control Register (DRAMCR) ................................................................. 123

6.3.9 DRAM Access Control Register (DRACCR)...................................................... 128

6.3.10 Refresh Control Register (REFCR)..................................................................... 129

6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 132

6.3.12 Refresh Time Constant Register (RTCOR)......................................................... 132

6.4 Operation .......................................................................................................................... 132

6.4.1 Area Division....................................................................................................... 132

6.4.2 Bus Specifications ................................................................................................ 134

6.4.3 Memory Interfaces............................................................................................... 136

6.4.4 Chip Select Signals .............................................................................................. 137

6.5 Basic Bus Interface........................................................................................................... 138

6.5.1 Data Size and Data Alignment............................................................................. 138

6.5.2 Valid Strobes........................................................................................................ 139

Rev. 2.00, 05/03, page xxiii of lii

6.5.3 Basic Timing........................................................................................................ 140

6.5.4 Wait Control ........................................................................................................ 148

6.5.5 Read Strobe (RD) Timing.................................................................................... 149

6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. 150

6.6 DRAM Interface ............................................................................................................... 152

6.6.1 Setting DRAM Space........................................................................................... 152

6.6.2 Address Multiplexing .......................................................................................... 152

6.6.3 Data Bus............................................................................................................... 153

6.6.4 Pins Used for DRAM Interface............................................................................ 154

6.6.5 Basic Timing........................................................................................................ 155

6.6.6 Column Address Output Cycle Control............................................................... 156

6.6.7 Row Address Output State Control...................................................................... 156

6.6.8 Precharge State Control ....................................................................................... 159

6.6.9 Wait Control ........................................................................................................ 160

6.6.10 Byte Access Control ............................................................................................ 163

6.6.11 Burst Operation.................................................................................................... 164

6.6.12 Refresh Control.................................................................................................... 168

6.6.13 DMAC Single Address Transfer Mode and DRAM Interface............................. 173

6.7 Burst ROM Interface......................................................................................................... 176

6.7.1 Basic Timing........................................................................................................ 176

6.7.2 Wait Control ........................................................................................................ 178

6.7.3 Write Access........................................................................................................ 178

6.8 Idle Cycle.......................................................................................................................... 179

6.8.1 Operation ............................................................................................................. 179

6.8.2 Pin States in Idle Cycle........................................................................................ 189

6.9 Write Data Buffer Function .............................................................................................. 189

6.10 Bus Release....................................................................................................................... 190

6.10.1 Operation ............................................................................................................. 190

6.10.2 Pin States in External Bus Released State............................................................ 192

6.10.3 Transition Timing................................................................................................ 193

6.11 Bus Arbitration ................................................................................................................. 194

6.11.1 Operation ............................................................................................................. 194

6.11.2 Bus Transfer Timing............................................................................................ 195

6.12 Bus Controller Operation in Reset.................................................................................... 196

6.13 Usage Notes ...................................................................................................................... 196

6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 196

6.13.2 External Bus Release Function and Software Standby........................................ 196

6.13.3 External Bus Release Function and CBR Refreshing.......................................... 196

6.13.4 BREQO Output Timing....................................................................................... 197

Section 7 DMA Controller (DMAC).................................................................199

7.1 Features............................................................................................................................. 199

7.2 Input/Output Pins.............................................................................................................. 201

Rev. 2.00, 05/03, page xxiv of lii

7.3 Register Descriptions........................................................................................................ 201

7.3.1 Memory Address Registers (MARA and MARB)............................................... 202

7.3.2 I/O Address Registers (IOARA and IOARB)...................................................... 203

7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) .................................. 203

7.3.4 DMA Control Registers (DMACRA and DMACRB)......................................... 204

7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)............. 211

7.3.6 DMA Write Enable Register (DMAWER).......................................................... 223

7.3.7 DMA Terminal Control Register (DMATCR)..................................................... 225

7.4 Activation Sources............................................................................................................ 226

7.4.1 Activation by Internal Interrupt Request.............................................................. 226

7.4.2 Activation by External Request ........................................................................... 227

7.4.3 Activation by Auto-Request................................................................................. 227

7.5 Operation .......................................................................................................................... 228

7.5.1 Transfer Modes.................................................................................................... 228

7.5.2 Sequential Mode .................................................................................................. 230

7.5.3 Idle Mode............................................................................................................. 232

7.5.4 Repeat Mode........................................................................................................ 234

7.5.5 Single Address Mode........................................................................................... 237

7.5.6 Normal Mode....................................................................................................... 240

7.5.7 Block Transfer Mode........................................................................................... 243

7.5.8 Basic Bus Cycles.................................................................................................. 249

7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles............................................... 249

7.5.10 DMA Transfer (Single Address Mode) Bus Cycles............................................. 257

7.5.11 Write Data Buffer Function ................................................................................. 263

7.5.12 Multi-Channel Operation..................................................................................... 264

7.5.13 Relation between DMAC and External Bus Requests and Refresh Cycles......... 265

7.5.14 DMAC and NMI Interrupts.................................................................................. 266

7.5.15 Forced Termination of DMAC Operation............................................................ 266

7.5.16 Clearing Full Address Mode................................................................................ 267

7.6 Interrupt Sources............................................................................................................... 268

7.7 Usage Notes ...................................................................................................................... 269

7.7.1 DMAC Register Access during Operation........................................................... 269

7.7.2 Module Stop......................................................................................................... 271

7.7.3 Write Data Buffer Function ................................................................................. 271

7.7.4 TEND Output....................................................................................................... 271

7.7.5 Activation by Falling Edge on DREQ Pin........................................................... 272

7.7.6 Activation Source Acceptance............................................................................. 273

7.7.7 Internal Interrupt after End of Transfer................................................................ 273

7.7.8 Channel Re-Setting .............................................................................................. 273

Section 8 Data Transfer Controller (DTC) ....................................................... 275

8.1 Features............................................................................................................................. 275

8.2 Register Descriptions........................................................................................................ 276

Rev. 2.00, 05/03, page xxv of lii

8.2.1 DTC Mode Register A (MRA) ............................................................................ 277

8.2.2 DTC Mode Register B (MRB)............................................................................. 278

8.2.3 DTC Source Address Register (SAR).................................................................. 278

8.2.4 DTC Destination Address Register (DAR).......................................................... 278

8.2.5 DTC Transfer Count Register A (CRA).............................................................. 278

8.2.6 DTC Transfer Count Register B (CRB)............................................................... 279

8.2.7 DTC Enable Registers A to G (DTCERA to DTCERG) ..................................... 279

8.2.8 DTC Vector Register (DTVECR)........................................................................ 279

8.3 Activation Sources............................................................................................................ 280

8.4 Location of Register Information and DTC Vector Table................................................ 281

8.5 Operation .......................................................................................................................... 284

8.5.1 Normal Mode....................................................................................................... 286

8.5.2 Repeat Mode........................................................................................................ 287

8.5.3 Block Transfer Mode........................................................................................... 288

8.5.4 Chain Transfer ..................................................................................................... 289

8.5.5 Interrupts.............................................................................................................. 290

8.5.6 Operation Timing................................................................................................. 291

8.5.7 Number of DTC Execution States ....................................................................... 292

8.6 Procedures for Using DTC................................................................................................ 293

8.6.1 Activation by Interrupt......................................................................................... 293

8.6.2 Activation by Software ........................................................................................ 293

8.7 Examples of Use of the DTC............................................................................................ 293

8.7.1 Normal Mode....................................................................................................... 293

8.7.2 Chain Transfer ..................................................................................................... 294

8.7.3 Chain Transfer when Counter = 0........................................................................ 295

8.7.4 Software Activation ............................................................................................. 296

8.8 Usage Notes...................................................................................................................... 297

8.8.1 Module Stop Mode Setting.................................................................................. 297

8.8.2 On-Chip RAM ..................................................................................................... 297

8.8.3 DTCE Bit Setting................................................................................................. 297

8.8.4 DMAC Transfer End Interrupt............................................................................. 297

8.8.5 Chain Transfer ..................................................................................................... 297

Section 9 I/O Ports.............................................................................................299

9.1 Port 1................................................................................................................................. 303

9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 303

9.1.2 Port 1 Data Register (P1DR)................................................................................ 304

9.1.3 Port 1 Register (PORT1)...................................................................................... 304

9.1.4 Pin Functions ....................................................................................................... 305

9.2 Port 2................................................................................................................................. 313

9.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 313

9.2.2 Port 2 Data Register (P2DR)................................................................................ 313

9.2.3 Port 2 Register (PORT2)...................................................................................... 314

Rev. 2.00, 05/03, page xxvi of lii

9.2.4 Pin Functions ....................................................................................................... 315

9.3 Port 3................................................................................................................................. 323

9.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 323

9.3.2 Port 3 Data Register (P3DR)................................................................................ 324

9.3.3 Port 3 Register (PORT3)...................................................................................... 324

9.3.4 Port 3 Open Drain Control Register (P3ODR)..................................................... 325

9.3.5 Port Function Control Register 2 (PFCR2).......................................................... 326

9.3.6 Pin Functions ....................................................................................................... 327

9.4 Port 4................................................................................................................................. 330

9.4.1 Port 4 Register (PORT4)...................................................................................... 330

9.4.2 Pin Functions ....................................................................................................... 331

9.5 Port 5................................................................................................................................. 333

9.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 333

9.5.2 Port 5 Data Register (P5DR)................................................................................ 333

9.5.3 Port 5 Register (PORT5)...................................................................................... 334

9.5.4 Pin Functions ....................................................................................................... 334

9.6 Port 8................................................................................................................................. 336

9.6.1 Port 8 Data Direction Register (P8DDR)............................................................. 336

9.6.2 Port 8 Data Register (P8DR)................................................................................ 337

9.6.3 Port 8 Register (PORT8)...................................................................................... 337

9.6.4 Pin Functions ....................................................................................................... 338

9.7 Port 9................................................................................................................................. 339

9.7.1 Port 9 Register (PORT9)...................................................................................... 339

9.7.2 Pin Functions ....................................................................................................... 339

9.8 Port A................................................................................................................................ 340

9.8.1 Port A Data Direction Register (PADDR)........................................................... 341

9.8.2 Port A Data Register (PADR).............................................................................. 342

9.8.3 Port A Register (PORTA).................................................................................... 342

9.8.4 Port A MOS Pull-Up Control Register (PAPCR)................................................ 343

9.8.5 Port A Open Drain Control Register (PAODR)................................................... 343

9.8.6 Port Function Control Register 0 (PFCR0).......................................................... 344

9.8.7 Port Function Control Register 1 (PFCR1).......................................................... 344

9.8.8 Pin Functions ....................................................................................................... 345

9.8.9 Port A MOS Input Pull-Up States........................................................................ 347

9.9 Port B................................................................................................................................ 348

9.9.1 Port B Data Direction Register (PBDDR)............................................................ 348

9.9.2 Port B Data Register (PBDR) .............................................................................. 349

9.9.3 Port B Register (PORTB) .................................................................................... 349

9.9.4 Port B MOS Pull-Up Control Register (PBPCR)................................................. 350

9.9.5 Pin Functions ....................................................................................................... 350

9.9.6 Port B MOS Input Pull-Up States........................................................................ 351

9.10 Port C ................................................................................................................................ 352

9.10.1 Port C Data Direction Register (PCDDR)............................................................ 352

Rev. 2.00, 05/03, page xxvii of lii

9.10.2 Port C Data Register (PCDR).............................................................................. 353

9.10.3 Port C Register (PORTC).................................................................................... 353

9.10.4 Port C MOS Pull-Up Control Register (PCPCR) ................................................ 354

9.10.5 Pin Functions....................................................................................................... 354

9.10.6 Port C MOS Input Pull-Up States........................................................................ 355

9.11 Port D................................................................................................................................ 356

9.11.1 Port D Data Direction Register (PDDDR)........................................................... 356

9.11.2 Port D Data Register (PDDR).............................................................................. 356

9.11.3 Port D Register (PORTD).................................................................................... 357

9.11.4 Port D Pull-up Control Register (PDPCR)........................................................... 357

9.11.5 Pin Functions....................................................................................................... 358

9.11.6 Port D MOS Input Pull-Up States........................................................................ 358

9.12 Port E ................................................................................................................................ 359

9.12.1 Port E Data Direction Register (PEDDR)............................................................ 359

9.12.2 Port E Data Register (PEDR)............................................................................... 360

9.12.3 Port E Register (PORTE)..................................................................................... 360

9.12.4 Port E Pull-up Control Register (PEPCR) ........................................................... 361

9.12.5 Pin Functions....................................................................................................... 361

9.12.6 Port E MOS Input Pull-Up States........................................................................ 362

9.13 Port F ................................................................................................................................ 362

9.13.1 Port F Data Direction Register (PFDDR) ............................................................ 363

9.13.2 Port F Data Register (PFDR)............................................................................... 364

9.13.3 Port F Register (PORTF)..................................................................................... 364

9.13.4 Pin Functions....................................................................................................... 365

9.14 Port G................................................................................................................................ 368

9.14.1 Port G Data Direction Register (PGDDR)........................................................... 368

9.14.2 Port G Data Register (PGDR).............................................................................. 370

9.14.3 Port G Register (PORTG).................................................................................... 370

9.14.4 Pin Functions....................................................................................................... 371

Section 10 16-Bit Timer Pulse Unit (TPU).......................................................373

10.1 Features............................................................................................................................. 373

10.2 Input/Output Pins.............................................................................................................. 377

10.3 Register Descriptions........................................................................................................ 378

10.3.1 Timer Control Register (TCR)............................................................................. 380

10.3.2 Timer Mode Register (TMDR)............................................................................ 385

10.3.3 Timer I/O Control Register (TIOR)..................................................................... 386

10.3.4 Timer Interrupt Enable Register (TIER).............................................................. 404

10.3.5 Timer Status Register (TSR)................................................................................ 406

10.3.6 Timer Counter (TCNT)........................................................................................ 408

10.3.7 Timer General Register (TGR)............................................................................ 409

10.3.8 Timer Start Register (TSTR) ............................................................................... 409

10.3.9 Timer Synchronous Register (TSYR).................................................................. 410

Rev. 2.00, 05/03, page xxviii of lii

10.4 Operation .......................................................................................................................... 411

10.4.1 Basic Functions.................................................................................................... 411

10.4.2 Synchronous Operation........................................................................................ 416

10.4.3 Buffer Operation.................................................................................................. 418

10.4.4 Cascaded Operation............................................................................................. 422

10.4.5 PWM Modes........................................................................................................ 424

10.4.6 Phase Counting Mode.......................................................................................... 429

10.5 Interrupts........................................................................................................................... 435

10.6 DTC Activation................................................................................................................. 437

10.7 DMAC Activation............................................................................................................. 437

10.8 A/D Converter Activation................................................................................................. 437

10.9 Operation Timing.............................................................................................................. 438

10.9.1 Input/Output Timing............................................................................................ 438

10.9.2 Interrupt Signal Timing........................................................................................ 441

10.10 Usage Notes ...................................................................................................................... 444

10.10.1 Module Stop Mode Setting.................................................................................. 444

10.10.2 Input Clock Restrictions ...................................................................................... 444

10.10.3 Caution on Cycle Setting..................................................................................... 445

10.10.4 Contention between TCNT Write and Clear Operations..................................... 445

10.10.5 Contention between TCNT Write and Increment Operations.............................. 446

10.10.6 Contention between TGR Write and Compare Match......................................... 447

10.10.7 Contention between Buffer Register Write and Compare Match........................ 447

10.10.8 Contention between TGR Read and Input Capture.............................................. 448

10.10.9 Contention between TGR Write and Input Capture............................................. 449

10.10.10 Contention between Buffer Register Write and Input Capture........................ 449

10.10.11 Contention between Overflow/Underflow and Counter Clearing.................... 450

10.10.12 Contention between TCNT Write and Overflow/Underflow........................... 451

10.10.13 Multiplexing of I/O Pins.................................................................................. 451

10.10.14 Interrupts and Module Stop Mode................................................................... 451

Section 11 Programmable Pulse Generator (PPG) ........................................... 453

11.1 Features............................................................................................................................. 453

11.2 Input/Output Pins.............................................................................................................. 455

11.3 Register Descriptions ........................................................................................................ 455

11.3.1 Next Data Enable Registers H, L (NDERH, NDERL)......................................... 456

11.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 457

11.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 458

11.3.4 PPG Output Control Register (PCR).................................................................... 460

11.3.5 PPG Output Mode Register (PMR)...................................................................... 461

11.4 Operation .......................................................................................................................... 463

11.4.1 Output Timing...................................................................................................... 464

11.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 465

11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 466

Rev. 2.00, 05/03, page xxix of lii

11.4.4 Non-Overlapping Pulse Output............................................................................ 467

11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output.............................. 468

11.4.6 Example of Non-Overlapping Pulse Output

(Example of Four-Phase Complementary Non-Overlapping Output) ................. 469

11.4.7 Inverted Pulse Output .......................................................................................... 471

11.4.8 Pulse Output Triggered by Input Capture ............................................................ 472

11.5 Usage Notes ...................................................................................................................... 472

11.5.1 Module Stop Mode Setting.................................................................................. 472

11.5.2 Operation of Pulse Output Pins............................................................................ 472

Section 12 8-Bit Timers (TMR) ........................................................................473

12.1 Features............................................................................................................................. 473

12.2 Input/Output Pins.............................................................................................................. 475

12.3 Register Descriptions........................................................................................................ 475

12.3.1 Timer Counter (TCNT)........................................................................................ 475

12.3.2 Time Constant Register A (TCORA)................................................................... 476

12.3.3 Time Constant Register B (TCORB)................................................................... 476

12.3.4 Timer Control Register (TCR)............................................................................. 476

12.3.5 Timer Control/Status Register (TCSR)................................................................ 478

12.4 Operation .......................................................................................................................... 481

12.4.1 Pulse Output......................................................................................................... 481

12.5 Operation Timing.............................................................................................................. 482

12.5.1 TCNT Incrementation Timing............................................................................. 482

12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs................. 483

12.5.3 Timing of Timer Output when Compare-Match Occurs...................................... 483

12.5.4 Timing of Compare Match Clear......................................................................... 484

12.5.5 Timing of TCNT External Reset.......................................................................... 484

12.5.6 Timing of Overflow Flag (OVF) Setting............................................................. 485

12.6 Operation with Cascaded Connection............................................................................... 485

12.6.1 16-Bit Counter Mode........................................................................................... 485

12.6.2 Compare Match Count Mode............................................................................... 486

12.7 Interrupts........................................................................................................................... 486

12.7.1 Interrupt Sources and DTC Activation ................................................................ 486

12.7.2 A/D Converter Activation.................................................................................... 487

12.8 Usage Notes ...................................................................................................................... 488

12.8.1 Contention between TCNT Write and Clear........................................................ 488

12.8.2 Contention between TCNT Write and Increment................................................ 488

12.8.3 Contention between TCOR Write and Compare Match...................................... 489

12.8.4 Contention between Compare Matches A and B................................................. 490

12.8.5 Switching of Internal Clocks and TCNT Operation ............................................ 491

12.8.6 Mode Setting with Cascaded Connection............................................................ 493

12.8.7 Interrupts in Module Stop Mode.......................................................................... 493

Rev. 2.00, 05/03, page xxx of lii

Section 13 Watchdog Timer ............................................................................. 495

13.1 Features............................................................................................................................. 495

13.2 Input/Output Pin........................................................................................................... ..... 496

13.3 Register Descriptions ........................................................................................................ 497

13.3.1 Timer Counter (TCNT)........................................................................................ 497

13.3.2 Timer Control/Status Register (TCSR)................................................................ 497

13.3.3 Reset Control/Status Register (RSTCSR)............................................................ 499

13.4 Operation .......................................................................................................................... 500

13.4.1 Watchdog Timer Mode........................................................................................ 500

13.4.2 Interval Timer Mode............................................................................................ 501

13.5 Interrupts........................................................................................................................... 502

13.6 Usage Notes ...................................................................................................................... 502

13.6.1 Notes on Register Access..................................................................................... 502

13.6.2 Contention between Timer Counter (TCNT) Write and Increment..................... 503

13.6.3 Changing Value of CKS2 to CKS0...................................................................... 504

13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 504

13.6.5 Internal Reset in Watchdog Timer Mode............................................................. 504

13.6.6 System Reset by WDTOVF Signal...................................................................... 505

Section 14 Serial Communication Interface (SCI, IrDA)................................. 507

14.1 Features............................................................................................................................. 507

14.2 Input/Output Pins.............................................................................................................. 509

14.3 Register Descriptions ........................................................................................................ 510

14.3.1 Receive Shift Register (RSR) .............................................................................. 511

14.3.2 Receive Data Register (RDR).............................................................................. 511

14.3.3 Transmit Data Register (TDR)............................................................................. 511

14.3.4 Transmit Shift Register (TSR)............................................................................. 512

14.3.5 Serial Mode Register (SMR)................................................................................ 512

14.3.6 Serial Control Register (SCR).............................................................................. 516

14.3.7 Serial Status Register (SSR) ................................................................................ 520

14.3.8 Smart Card Mode Register (SCMR).................................................................... 527

14.3.9 Bit Rate Register (BRR) ...................................................................................... 528

14.3.10 IrDA Control Register (IrCR).............................................................................. 537

14.3.11 Serial Extension Mode Register (SEMR)............................................................ 538

14.4 Operation in Asynchronous Mode.................................................................................... 540

14.4.1 Data Transfer Format........................................................................................... 540

14.4.2 Receive Data Sampling Timing and Reception Margin

in Asynchronous Mode........................................................................................ 542

14.4.3 Clock.................................................................................................................... 543

14.4.4 SCI Initialization (Asynchronous Mode)............................................................. 544

14.4.5 Data Transmission (Asynchronous Mode)........................................................... 545

14.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 547

14.5 Multiprocessor Communication Function ......................................................................... 551

Rev. 2.00, 05/03, page xxxi of lii

14.5.1 Multiprocessor Serial Data Transmission............................................................ 552

14.5.2 Multiprocessor Serial Data Reception ................................................................. 554

14.6 Operation in Clocked Synchronous Mode........................................................................ 558

14.6.1 Clock.................................................................................................................... 558

14.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 559

14.6.3 Serial Data Transmission (Clocked Synchronous Mode).................................... 560

14.6.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 563

14.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode)............................................................................. 565

14.7 Operation in Smart Card Interface Mode.......................................................................... 567

14.7.1 Pin Connection Example ..................................................................................... 567

14.7.2 Data Format (Except for Block Transfer Mode).................................................. 567

14.7.3 Block Transfer Mode........................................................................................... 569

14.7.4 Receive Data Sampling Timing and Reception Margin....................................... 569

14.7.5 Initialization......................................................................................................... 570

14.7.6 Data Transmission (Except for Block Transfer Mode)........................................ 571

14.7.7 Serial Data Reception (Except for Block Transfer Mode)................................... 574

14.7.8 Clock Output Control........................................................................................... 575

14.8 IrDA Operation................................................................................................................. 577

14.9 SCI Interrupts.................................................................................................................... 580

14.9.1 Interrupts in Normal Serial Communication Interface Mode.............................. 580

14.9.2 Interrupts in Smart Card Interface Mode............................................................. 581

14.10 Usage Notes...................................................................................................................... 583

14.10.1 Module Stop Mode Setting.................................................................................. 583

14.10.2 Break Detection and Processing .......................................................................... 583

14.10.3 Mark State and Break Sending ............................................................................ 583

14.10.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only).................................................................... 583

14.10.5 Relation between Writes to TDR and the TDRE Flag......................................... 584

14.10.6 Restrictions on Use of DMAC* or DTC.............................................................. 584

14.10.7 Operation in Case of Mode Transition................................................................. 584

Section 15 I2C Bus Interface2 (IIC2) (Option)..................................................589

15.1 Features............................................................................................................................. 589

15.2 Input/Output Pins.............................................................................................................. 591

15.3 Register Descriptions........................................................................................................ 592

15.3.1 I

15.3.2 I

15.3.3 I

15.3.4 I

15.3.5 I

15.3.6 Slave Address Register (SAR)............................................................................. 601

15.3.7 I

Rev. 2.00, 05/03, page xxxii of lii

C Bus Control Register A (ICCRA).................................................................. 593

C Bus Control Register B (ICCRB)................................................................... 594

C Bus Mode Register (ICMR)........................................................................... 596

C Bus Interrupt Enable Register (ICIER).......................................................... 597

C Bus Status Register (ICSR)............................................................................ 599

C Bus Transmit Data Register (ICDRT)............................................................ 601

15.3.8 I2C Bus Receive Data Register (ICDRR) ............................................................. 601

15.3.9 I

15.4 Operation .......................................................................................................................... 602

15.4.1 I

C Bus Shift Register (ICDRS) ........................................................................... 601

C Bus Format..................................................................................................... 602

15.4.2 Master Transmit Operation.................................................................................. 603

15.4.3 Master Receive Operation.................................................................................... 605

15.4.4 Slave Transmit Operation.................................................................................... 607

15.4.5 Slave Receive Operation...................................................................................... 609

15.4.6 Noise Canceler..................................................................................................... 611

15.4.7 Example of Use.................................................................................................... 611

15.5 Interrupt Request............................................................................................................... 616

15.6 Bit Synchronous Circuit.................................................................................................... 616

Section 16 A/D Converter................................................................................. 619

16.1 Features............................................................................................................................. 619

16.2 Input/Output Pins.............................................................................................................. 621

16.3 Register Descriptions ........................................................................................................ 622

16.3.1 A/D Data Registers A to H (ADDRA to ADDRH).............................................. 622

16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 623

16.3.3 A/D Control Register (ADCR) ............................................................................ 625

16.4 Operation .......................................................................................................................... 626

16.4.1 Single Mode......................................................................................................... 626

16.4.2 Scan Mode ........................................................................................................... 626

16.4.3 Input Sampling and A/D Conversion Time......................................................... 627

16.4.4 External Trigger Input Timing............................................................................. 629

16.5 Interrupts........................................................................................................................... 629

16.6 A/D Conversion Precision Definitions.............................................................................. 630

16.7 Usage Notes ...................................................................................................................... 632

16.7.1 Module Stop Mode Setting.................................................................................. 632

16.7.2 Permissible Signal Source Impedance................................................................. 632

16.7.3 Influences on Absolute Precision......................................................................... 633

16.7.4 Setting Range of Analog Power Supply and Other Pins...................................... 633

16.7.5 Notes on Board Design........................................................................................ 633

16.7.6 Notes on Noise Countermeasures........................................................................ 634

Section 17 D/A Converter................................................................................. 637

17.1 Features............................................................................................................................. 637

17.2 Input/Output Pins.............................................................................................................. 639

17.3 Register Descriptions ........................................................................................................ 639

17.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)............................................ 639

17.3.2 D/A Control Register 23 (DACR23).................................................................... 639

17.4 Operation .......................................................................................................................... 641

17.5 Usage Notes ...................................................................................................................... 642

Rev. 2.00, 05/03, page xxxiii of lii

17.5.1 Setting for Module Stop Mode ............................................................................ 642

17.5.2 D/A Output Hold Function in Software Standby Mode....................................... 642

Section 18 RAM................................................................................................643

Section 19 Flash Memory (F-ZTAT Version)...................................................645

19.1 Features............................................................................................................................. 645

19.2 Mode Transitions .............................................................................................................. 646

19.3 Block Configuration ......................................................................................................... 650

19.4 Input/Output Pins.............................................................................................................. 652

19.5 Register Descriptions........................................................................................................ 652

19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 652

19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 654

19.5.3 Erase Block Register 1 (EBR1)........................................................................... 654

19.5.4 Erase Block Register 2 (EBR2)........................................................................... 655

19.5.5 RAM Emulation Register (RAMER)................................................................... 656

19.6 On-Board Programming Modes........................................................................................ 657

19.6.1 Boot Mode........................................................................................................... 658

19.6.2 User Program Mode............................................................................................. 661

19.7 Flash Memory Emulation in RAM ................................................................................... 662

19.8 Flash Memory Programming/Erasing............................................................................... 664

19.8.1 Program/Program-Verify..................................................................................... 664

19.8.2 Erase/Erase-Verify............................................................................................... 666

19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 666

19.9 Program/Erase Protection ................................................................................................. 668

19.9.1 Hardware Protection............................................................................................ 668

19.9.2 Software Protection.............................................................................................. 668

19.9.3 Error Protection ................................................................................................... 668

19.10 Programmer Mode............................................................................................................ 669

19.11 Power-Down States for Flash Memory............................................................................. 669

19.12 Usage Notes...................................................................................................................... 669

Section 20 Mask ROM......................................................................................673

Section 21 Clock Pulse Generator.....................................................................675

21.1 Register Descriptions........................................................................................................ 675

21.1.1 System Clock Control Register (SCKCR)........................................................... 675

21.1.2 PLL Control Register (PLLCR)........................................................................... 677

21.2 Oscillator........................................................................................................................... 678

21.2.1 Connecting a Crystal Oscillator........................................................................... 678

21.2.2 External Clock Input............................................................................................ 679

21.3 PLL Circuit ....................................................................................................................... 680

21.4 Frequency Divider ............................................................................................................ 681

Rev. 2.00, 05/03, page xxxiv of lii

21.5 Usage Notes ...................................................................................................................... 681

21.5.1 Notes on Clock Pulse Generator.......................................................................... 681

21.5.2 Notes on Oscillator .............................................................................................. 681

21.5.3 Notes on Board Design........................................................................................ 682

Section 22 Power-Down Modes ....................................................................... 683

22.1 Register Descriptions ........................................................................................................ 686

22.1.1 Standby Control Register (SBYCR) .................................................................... 686

22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 688

22.1.3 Extension Module Stop Control Registers H and L

(EXMSTPCRH, EXMSTPCRL).......................................................................... 689

22.2 Operation .......................................................................................................................... 690

22.2.1 Clock Division Mode........................................................................................... 690

22.2.2 Sleep Mode.......................................................................................................... 690

22.2.3 Software Standby Mode....................................................................................... 691

22.2.4 Hardware Standby Mode ..................................................................................... 693

22.2.5 Module Stop Mode .............................................................................................. 694

22.2.6 All-Module-Clocks-Stop Mode........................................................................... 695

22.3 φ Clock Output Control..................................................................................................... 695

22.4 Usage Notes ...................................................................................................................... 696

22.4.1 I/O Port Status...................................................................................................... 696

22.4.2 Current Dissipation during Oscillation Stabilization Standby Period.................. 696

22.4.3 DMAC/DTC Module Stop................................................................................... 696

22.4.4 On-Chip Peripheral Module Interrupts................................................................ 696

22.4.5 Writing to MSTPCR, EXMSTPCR ..................................................................... 696

22.4.6 Notes on Clock Division Mode............................................................................ 697

Section 23 List of Registers.............................................................................. 699

23.1 Register Addresses (Address Order)................................................................................. 700

23.2 Register Bits...................................................................................................................... 710

23.3 Register States in Each Operating Mode........................................................................... 723

Section 24 Electrical Characteristics ................................................................ 733

24.1 Electrical Characteristics of Masked ROM and ROMless Versions................................. 733

24.1.1 Absolute Maximum Ratings................................................................................ 733

24.1.2 DC Characteristics............................................................................................... 734

24.1.3 AC Characteristics............................................................................................... 737

24.1.4 A/D Conversion Characteristics........................................................................... 768

24.1.5 D/A Conversion Characteristics........................................................................... 768

24.2 Electrical Characteristics of F-ZTAT Version.................................................................. 769

24.2.1 Absolute Maximum Ratings................................................................................ 769

24.2.2 DC Characteristics............................................................................................... 770

24.2.3 A/D Conversion Characteristics........................................................................... 780

Rev. 2.00, 05/03, page xxxv of lii

24.2.4 D/A Conversion Characteristics........................................................................... 780

24.3 Flash Memory Characteristics .......................................................................................... 781

24.4 Usage Note........................................................................................................................ 783

Appendix ............................................................................................................785

A. I/O Port States in Each Pin State....................................................................................... 785

B. Product Lineup.................................................................................................................. 792

C. Package Dimensions ......................................................................................................... 793

D. Bus State during Execution of Instructions....................................................................... 795

Index ................................................................................................................... 817

Rev. 2.00, 05/03, page xxxvi of lii

Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram of H8S/2367, H8S/2365, and H8S/2363 ............................. 3

Figure 1.2 Internal Block Diagram of H8S/2366........................................................................ 4

Figure 1.3 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363........................................5

Figure 1.4 Pin Arrangement of H8S/2366...................................................................................6

Figure 1.5 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363........................................7

Figure 1.6 Pin Arrangement of H8S/2366...................................................................................8

Section 2 CPU

Figure 2.1 Exception Vector Table (Normal Mode) .................................................................25

Figure 2.2 Stack Structure in Normal Mode .............................................................................25

Figure 2.3 Exception Vector Table (Advanced Mode) .............................................................26

Figure 2.4 Stack Structure in Advanced Mode .........................................................................27

Figure 2.5 Memory Map ...........................................................................................................28

Figure 2.6 CPU Internal Registers ............................................................................................29

Figure 2.7 Usage of General Registers...................................................................................... 30

Figure 2.8 Stack ........................................................................................................................31

Figure 2.9 General Register Data Formats (1) ..........................................................................34

Figure 2.9 General Register Data Formats (2) ..........................................................................35

Figure 2.10 Memory Data Formats .............................................................................................36

Figure 2.11 Instruction Formats (Examples)...............................................................................48

Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ....................51

Figure 2.13 State Transitions....................................................................................................... 55

Section 3 MCU Operating Modes

Figure 3.1 H8S/2367 Memory Map (1).....................................................................................62

Figure 3.2 H8S/2367 Memory Map (2).....................................................................................63

Figure 3.3 H8S/2366 Memory Map (1).....................................................................................64

Figure 3.4 H8S/2366 Memory Map (2).....................................................................................65

Figure 3.5 H8S/2365 Memory Map (1).....................................................................................66

Figure 3.6 H8S/2365 Memory Map (2).....................................................................................67

Figure 3.7 H8S/2363 Memory Map .......................................................................................... 68

Section 4 Exception Handling

Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled) ...........................72

Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled) ..........................73

Figure 4.3 Stack Status after Exception Handling.....................................................................76

Figure 4.4 Operation when SP Value Is Odd ............................................................................77

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller ....................................................................80

Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ..........................................................91

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance

in Interrupt Control Mode 0..................................................................................... 98

Rev. 2.00, 05/03, page xxxvii of lii

Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance

in Interrupt Control Mode 2................................................................................... 100

Figure 5.5 Interrupt Exception Handling ................................................................................101

Figure 5.6 Contention between Interrupt Generation and Disabling.......................................104

Section 6 Bus Controller (BSC)

Figure 6.1 Block Diagram of Bus Controller.......................................................................... 108

Figure 6.2 Read Strobe Negation Timing

(Example of 3-State Access Space) ....................................................................... 117

Figure 6.3 CS and Address Assertion Period Extension

(Example of 3-State Access Space and RDNn = 0)............................................... 119

Figure 6.4 RAS Signal Assertion Timing

(2-State Column Address Output Cycle, Full Access)...........................................127

Figure 6.5 Area Divisions .......................................................................................................133

Figure 6.6 CSn Signal Output Timing (n = 0 to 7).................................................................. 137

Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space).......................... 138

Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space) ........................139

Figure 6.9 Bus Timing for 8-Bit, 2-State Access Space..........................................................140

Figure 6.10 Bus Timing for 8-Bit, 3-State Access Space.......................................................... 141

Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)......... 142

Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) ..........143

Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................... 144

Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)......... 145

Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) ..........146

Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................... 147

Figure 6.17 Example of Wait State Insertion Timing ...............................................................149

Figure 6.18 Example of Read Strobe Timing............................................................................ 150

Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended.................... 151

Figure 6.20 DRAM Basic Access Timing (RAST = 0, CAST = 0) ..........................................155

Figure 6.21 Example of Access Timing with 3-State Column Address Output Cycle

(RAST = 0) ............................................................................................................ 156

Figure 6.22 Example of Access Timing when RAS Signal Goes Low

from Beginning of T

State (CAST = 0) ................................................................157

Figure 6.23 Example of Timing with One Row Address Output Maintenance State

(RAST = 0, CAST = 0).......................................................................................... 158

Figure 6.24 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0)..... 159

Figure 6.25 Example of Wait State Insertion Timing (2-State Column Address Output)......... 161

Figure 6.26 Example of Wait State Insertion Timing (3-State Column Address Output)......... 162

Figure 6.27 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) ........163

Figure 6.28 Example of 2-CAS DRAM Connection................................................................. 164

Figure 6.29 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0)..............................165

Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1)..............................166

Figure 6.31 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0)....... 167

Figure 6.32 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0)............ 168

Rev. 2.00, 05/03, page xxxviii of lii

Figure 6.33 RTCNT Operation .................................................................................................169

Figure 6.34 Compare Match Timing ......................................................................................... 169

Figure 6.35 CBR Refresh Timing .............................................................................................170

Figure 6.36 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) ............... 170

Figure 6.37 Example of CBR Refresh Timing (CBRM = 1).....................................................171

Figure 6.38 Self-Refresh Timing...............................................................................................172

Figure 6.39 Example of Timing when Precharge Time after Self-Refreshing is Extended

by 2 States..............................................................................................................173

Figure 6.40 Example of DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0)......... 174

Figure 6.41 Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1)......... 175

Figure 6.42 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle)............177

Figure 6.43 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle)............178

Figure 6.44 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)...........179

Figure 6.45 Example of Idle Cycle Operation (Write after Read).............................................180

Figure 6.46 Example of Idle Cycle Operation (Read after Write) ............................................181

Figure 6.47 Relationship between Chip Select (CS) and Read (RD) ........................................ 182

Figure 6.48 Example of DRAM Full Access after External Read (CAST = 0) ........................182

Figure 6.49 Example of Idle Cycle Operation in RAS Down Mode

(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)......... 183

Figure 6.50 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)

(IDLC = 0, RAST = 0, CAST = 0) ........................................................................183

Figure 6.51 Example of Idle Cycle Operation after DRAM Access

(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)......... 184

Figure 6.52 Example of Idle Cycle Operation after DRAM Access

(Write after Read) (IDLC = 0, RAST = 0, CAST = 0) ..........................................185

Figure 6.53 Example of Idle Cycle Operation after DRAM Write Access

(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0).......................................................186

Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read

and Write Accesses to DRAM Space in RAS Down Mode...................................188

Figure 6.55 Example of Timing when Write Data Buffer Function is Used............................. 190

Figure 6.56 Bus Released State Transition Timing................................................................... 193

Section 7 DMA Controller (DMAC)

Figure 7.1 Block Diagram of DMAC...................................................................................... 200

Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)............................................224

Figure 7.3 Operation in Sequential Mode ...............................................................................231

Figure 7.4 Example of Sequential Mode Setting Procedure....................................................232

Figure 7.5 Operation in Idle Mode.......................................................................................... 233

Figure 7.6 Example of Idle Mode Setting Procedure.............................................................. 234

Figure 7.7 Operation in Repeat mode......................................................................................236

Figure 7.8 Example of Repeat Mode Setting Procedure ......................................................... 237

Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified) ...........239

Figure 7.10 Example of Single Address Mode Setting Procedure

(When Sequential Mode is Specified)....................................................................240

Rev. 2.00, 05/03, page xxxix of lii

Figure 7.11 Operation in Normal Mode.................................................................................... 242

Figure 7.12 Example of Normal Mode Setting Procedure ........................................................ 243

Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) ...............................................245

Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ...............................................246

Figure 7.15 Operation Flow in Block Transfer Mode............................................................... 247

Figure 7.16 Example of Block Transfer Mode Setting Procedure ............................................248

Figure 7.17 Example of DMA Transfer Bus Timing ................................................................249

Figure 7.18 Example of Short Address Mode Transfer ............................................................250

Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)......................................... 251

Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) ........................................ 252

Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)......................... 253

Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer ............... 254

Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer ... 255

Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer ..................256

Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer ......257

Figure 7.26 Example of Single Address Mode Transfer (Byte Read)....................................... 258

Figure 7.27 Example of Single Address Mode (Word Read) Transfer..................................... 258

Figure 7.28 Example of Single Address Mode Transfer (Byte Write)...................................... 259

Figure 7.29 Example of Single Address Mode Transfer (Word Write) .................................... 260

Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer... 261

Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer...... 262

Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function ................ 263

Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function.............. 264

Figure 7.34 Example of Multi-Channel Transfer ...................................................................... 265

Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted

by NMI Interrupt....................................................................................................266

Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation .....................267

Figure 7.37 Example of Procedure for Clearing Full Address Mode........................................ 268

Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt..................................... 269

Figure 7.39 DMAC Register Update Timing............................................................................ 270

Figure 7.40 Contention between DMAC Register Update and CPU Read ...............................270

Figure 7.41 Example in which Low Level is Not Output at TEND Pin....................................272

Section 8 Data Transfer Controller (DTC)

Figure 8.1 Block Diagram of DTC.......................................................................................... 276

Figure 8.2 Block Diagram of DTC Activation Source Control............................................... 281

Figure 8.3 Correspondence between DTC Vector Address and Register Information............282

Figure 8.4 Correspondence between DTC Vector Address and Register Information............282

Figure 8.5 Flowchart of DTC Operation................................................................................. 285

Figure 8.6 Memory Mapping in Normal Mode....................................................................... 287

Figure 8.7 Memory Mapping in Repeat Mode........................................................................ 288

Figure 8.8 Memory Mapping in Block Transfer Mode........................................................... 289

Figure 8.9 Operation of Chain Transfer.................................................................................. 290

Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode).................. 291

Rev. 2.00, 05/03, page xl of lii

Figure 8.11 DTC Operation Timing

(Example of Block Transfer Mode, with Block Size of 2) ...................................291

Figure 8.12 DTC Operation Timing (Example of Chain Transfer)........................................... 291

Figure 8.13 Chain Transfer when Counter = 0.......................................................................... 296

Section 10 16-Bit Timer Pulse Unit (TPU)

Figure 10.1 Block Diagram of TPU ..........................................................................................376

Figure 10.2 Example of Counter Operation Setting Procedure.................................................411

Figure 10.3 Free-Running Counter Operation........................................................................... 412

Figure 10.4 Periodic Counter Operation ...................................................................................413

Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match ............413

Figure 10.6 Example of 0 Output/1 Output Operation.............................................................. 414

Figure 10.7 Example of Toggle Output Operation....................................................................414

Figure 10.8 Example of Setting Procedure for Input Capture Operation .................................. 415

Figure 10.9 Example of Input Capture Operation .....................................................................416

Figure 10.10 Example of Synchronous Operation Setting Procedure......................................... 417

Figure 10.11 Example of Synchronous Operation ......................................................................418

Figure 10.12 Compare Match Buffer Operation .........................................................................419

Figure 10.13 Input Capture Buffer Operation............................................................................. 419

Figure 10.14 Example of Buffer Operation Setting Procedure ...................................................420

Figure 10.15 Example of Buffer Operation (1)...........................................................................421

Figure 10.16 Example of Buffer Operation (2)...........................................................................422

Figure 10.17 Cascaded Operation Setting Procedure.................................................................. 423

Figure 10.18 Example of Cascaded Operation (1) ......................................................................423

Figure 10.19 Example of Cascaded Operation (2) ......................................................................424

Figure 10.20 Example of PWM Mode Setting Procedure........................................................... 426

Figure 10.21 Example of PWM Mode Operation (1).................................................................. 427

Figure 10.22 Example of PWM Mode Operation (2).................................................................. 427

Figure 10.23 Example of PWM Mode Operation (3).................................................................. 428

Figure 10.24 Example of Phase Counting Mode Setting Procedure ...........................................429

Figure 10.25 Example of Phase Counting Mode 1 Operation..................................................... 430

Figure 10.26 Example of Phase Counting Mode 2 Operation..................................................... 431

Figure 10.27 Example of Phase Counting Mode 3 Operation..................................................... 432

Figure 10.28 Example of Phase Counting Mode 4 Operation..................................................... 433

Figure 10.29 Phase Counting Mode Application Example......................................................... 434

Figure 10.30 Count Timing in Internal Clock Operation............................................................ 438

Figure 10.31 Count Timing in External Clock Operation........................................................... 438

Figure 10.32 Output Compare Output Timing............................................................................439

Figure 10.33 Input Capture Input Signal Timing ........................................................................ 439

Figure 10.34 Counter Clear Timing (Compare Match)............................................................... 440

Figure 10.35 Counter Clear Timing (Input Capture)...................................................................440

Figure 10.36 Buffer Operation Timing (Compare Match)..........................................................440

Figure 10.37 Buffer Operation Timing (Input Capture)..............................................................441

Figure 10.38 TGI Interrupt Timing (Compare Match)................................................................ 441

Rev. 2.00, 05/03, page xli of lii

Figure 10.39 TGI Interrupt Timing (Input Capture) ...................................................................442

Figure 10.40 TCIV Interrupt Setting Timing .............................................................................. 442

Figure 10.41 TCIU Interrupt Setting Timing .............................................................................. 443

Figure 10.42 Timing for Status Flag Clearing by CPU............................................................... 443

Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC Activation................................ 444

Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode................. 445

Figure 10.45 Contention between TCNT Write and Clear Operations ....................................... 446

Figure 10.46 Contention between TCNT Write and Increment Operations................................446

Figure 10.47 Contention between TGR Write and Compare Match........................................... 447

Figure 10.48 Contention between Buffer Register Write and Compare Match ..........................448

Figure 10.49 Contention between TGR Read and Input Capture................................................ 448

Figure 10.50 Contention between TGR Write and Input Capture............................................... 449

Figure 10.51 Contention between Buffer Register Write and Input Capture.............................. 450

Figure 10.52 Contention between Overflow and Counter Clearing............................................ 450

Figure 10.53 Contention between TCNT Write and Overflow................................................... 451

Section 11 Programmable Pulse Generator (PPG)

Figure 11.1 Block Diagram of PPG ..........................................................................................454

Figure 11.2 Overview Diagram of PPG ....................................................................................463

Figure 11.3 Timing of Transfer and Output of NDR Contents (Example)................................464

Figure 11.4 Setup Procedure for Normal Pulse Output (Example)........................................... 465

Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output) ...................................466

Figure 11.6 Non-Overlapping Pulse Output.............................................................................. 467

Figure 11.7 Non-Overlapping Operation and NDR Write Timing............................................468

Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)........................... 469

Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) .............. 470

Figure 11.10 Inverted Pulse Output (Example)...........................................................................471

Figure 11.11 Pulse Output Triggered by Input Capture (Example) ............................................ 472

Section 12 8-Bit Timers (TMR)

Figure 12.1 Block Diagram of 8-Bit Timer Module .................................................................474

Figure 12.2 Example of Pulse Output .......................................................................................482

Figure 12.3 Count Timing for Internal Clock Input.................................................................. 482

Figure 12.4 Count Timing for External Clock Input.................................................................483

Figure 12.5 Timing of CMF Setting.......................................................................................... 483

Figure 12.6 Timing of Timer Output......................................................................................... 484

Figure 12.7 Timing of Compare Match Clear ........................................................................... 484

Figure 12.8 Timing of Clearance by External Reset .................................................................485

Figure 12.9 Timing of OVF Setting ..........................................................................................485

Figure 12.10 Contention between TCNT Write and Clear..........................................................488

Figure 12.11 Contention between TCNT Write and Increment.................................................. 489

Figure 12.12 Contention between TCOR Write and Compare Match ........................................490

Section 13 Watchdog Timer

Figure 13.1 Block Diagram of WDT ........................................................................................ 496

Figure 13.2 Operation in Watchdog Timer Mode..................................................................... 501

Rev. 2.00, 05/03, page xlii of lii

Figure 13.3 Operation in Interval Timer Mode ......................................................................... 502

Figure 13.4 Writing to TCNT, TCSR, and RSTCSR ............................................................... 503

Figure 13.5 Contention between TCNT Write and Increment ..................................................504

Figure 13.6 Circuit for System Reset by WDTOVF Signal (Example) ....................................505

Section 14 Serial Communication Interface (SCI, IrDA)

Figure 14.1 Block Diagram of SCI ...........................................................................................508

Figure 14.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) ................................................540

Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode....................................... 542

Figure 14.4 Relation between Output Clock and Transfer Data Phase

(Asynchronous Mode) ...........................................................................................543

Figure 14.5 Sample SCI Initialization Flowchart...................................................................... 544

Figure 14.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit)...................................................545

Figure 14.7 Sample Serial Transmission Flowchart.................................................................. 546

Figure 14.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit)...................................................547

Figure 14.9 Sample Serial Reception Data Flowchart (1)......................................................... 549

Figure 14.9 Sample Serial Reception Data Flowchart (2)......................................................... 550

Figure 14.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)........................................... 552

Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart.........................................553

Figure 14.12 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ..............................555

Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1) ........................................556

Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2) ........................................557

Figure 14.14 Data Format in Clocked Synchronous Communication (For LSB-First)...............558

Figure 14.15 Sample SCI Initialization Flowchart......................................................................559

Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode................... 561

Figure 14.17 Sample Serial Transmission Flowchart.................................................................. 562

Figure 14.18 Example of SCI Operation in Reception................................................................563

Figure 14.19 Sample Serial Reception Flowchart....................................................................... 564

Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations....... 566

Figure 14.21 Schematic Diagram of Smart Card Interface Pin Connections.............................. 567

Figure 14.22 Normal Smart Card Interface Data Format............................................................ 568

Figure 14.23 Direct Convention (SDIR = SINV = O/E = 0)....................................................... 568

Figure 14.24 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 568

Figure 14.25 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Bit Rate)...............................................................570

Figure 14.26 Retransfer Operation in SCI Transmit Mode.........................................................572

Figure 14.27 TEND Flag Generation Timing in Transmission Operation.................................. 572

Figure 14.28 Example of Transmission Processing Flow ........................................................... 573

Figure 14.29 Retransfer Operation in SCI Receive Mode...........................................................574

Rev. 2.00, 05/03, page xliii of lii

Figure 14.30 Example of Reception Processing Flow ................................................................575

Figure 14.31 Timing for Fixing Clock Output Level.................................................................. 575

Figure 14.32 Clock Halt and Restart Procedure.......................................................................... 576

Figure 14.33 Block Diagram of IrDA ......................................................................................... 577

Figure 14.34 IrDA Transmit/Receive Operations .......................................................................578

Figure 14.35 Example of Synchronous Transmission Using DTC .............................................584

Figure 14.36 Sample Flowchart for Mode Transition during Transmission ...............................586

Figure 14.37 Port Pin States during Mode Transition

(Internal Clock, Asynchronous Transmission) ......................................................587

Figure 14.38 Port Pin States during Mode Transition

(Internal Clock, Synchronous Transmission)......................................................... 587

Figure 14.39 Sample Flowchart for Mode Transition during Reception.....................................588

Section 15 I

Figure 15.1 Block Diagram of I

C Bus Interface2 (IIC2) (Option)

C Bus Interface2.................................................................... 590

Figure 15.2 External Circuit Connections of I/O Pins...............................................................591

Figure 15.3 I Figure 15.4 I

C Bus Formats..................................................................................................... 602

C Bus Timing...................................................................................................... 602

Figure 15.5 Master Transmit Mode Operation Timing 1 .......................................................... 604

Figure 15.6 Master Transmit Mode Operation Timing 2 .......................................................... 604

Figure 15.7 Master Receive Mode Operation Timing 1............................................................ 606

Figure 15.8 Master Receive Mode Operation Timing 2............................................................ 606

Figure 15.9 Slave Transmit Mode Operation Timing 1 ............................................................608

Figure 15.10 Slave Transmit Mode Operation Timing 2 ............................................................609

Figure 15.11 Slave Receive Mode Operation Timing 1.............................................................. 610

Figure 15.12 Slave Receive Mode Operation Timing 2.............................................................. 610

Figure 15.13 Block Diagram of Noise Canceler .........................................................................611

Figure 15.14 Sample Flowchart for Master Transmit Mode....................................................... 612

Figure 15.15 Sample Flowchart for Master Receive Mode.........................................................613

Figure 15.16 Sample Flowchart for Slave Transmit Mode ......................................................... 614

Figure 15.17 Sample Flowchart for Slave Receive Mode........................................................... 615

Figure 15.18 Timing of the Bit Synchronous Circuit.................................................................. 616

Section 16 A/D Converter

Figure 16.1 Block Diagram of A/D Converter.......................................................................... 620

Figure 16.2 A/D Conversion Timing ........................................................................................627

Figure 16.3 External Trigger Input Timing............................................................................... 629

Figure 16.4 A/D Conversion Precision Definitions ..................................................................631

Figure 16.5 A/D Conversion Precision Definitions ..................................................................631

Figure 16.6 Example of Analog Input Circuit........................................................................... 632

Figure 16.7 Example of Analog Input Protection Circuit .........................................................634

Section 17 D/A Converter

Figure 17.1 Block Diagram of D/A Converter.......................................................................... 638

Figure 17.2 Example of D/A Converter Operation ...................................................................642

Section 19 Flash Memory (F-ZTAT Version)

Rev. 2.00, 05/03, page xliv of lii

Figure 19.1 Block Diagram of Flash Memory .........................................................................646

Figure 19.2 Flash Memory State Transitions ............................................................................647

Figure 19.3 Boot Mode .............................................................................................................648

Figure 19.4 User Program Mode...............................................................................................649

Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7).....................651

Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode.......................661

Figure 19.7 Flowchart for Flash Memory Emulation in RAM.................................................. 662

Figure 19.8 Example of RAM Overlap Operation ....................................................................663

Figure 19.9 Program/Program-Verify Flowchart ...................................................................... 665

Figure 19.10 Erase/Erase-Verify Flowchart................................................................................ 667

Figure 19.11 Power-On/Off Timing............................................................................................ 671

Figure 19.12 Mode Transition Timing

(Example: Boot Mode → User Mode ↔ User Program Mode) ............................ 672

Section 20 Mask ROM

Figure 20.1 Block Diagram of 256-kbyte Mask ROM (HD6432365) ......................................673

Section 21 Clock Pulse Generator

Figure 21.1 Block Diagram of Clock Pulse Generator.............................................................. 675

Figure 21.2 Connection of Crystal Oscillator (Example).......................................................... 678

Figure 21.3 Crystal Oscillator Equivalent Circuit ..................................................................... 678

Figure 21.4 External Clock Input (Examples)........................................................................... 679

Figure 21.5 External Clock Input Timing .................................................................................680

Figure 21.6 Note on Oscillator Board Design ...........................................................................682

Figure 21.7 Recommended External Circuitry for PLL Circuit................................................ 682

Section 22 Power-Down Modes

Figure 22.1 Mode Transitions ...................................................................................................685

Figure 22.2 Software Standby Mode Application Example......................................................693

Figure 22.3 Hardware Standby Mode Timing........................................................................... 694

Section 24 Electrical Characteristics

Figure 24.1 Output Load Circuit ...............................................................................................737

Figure 24.2 System Clock Timing ............................................................................................738

Figure 24.3 Oscillation Stabilization Timing (1) ......................................................................739

Figure 24.3 Oscillation Stabilization Timing (2) ......................................................................739

Figure 24.4 Reset Input Timing ................................................................................................740

Figure 24.5 Interrupt Input Timing ...........................................................................................741

Figure 24.6 Basic Bus Timing: Two-State Access....................................................................745

Figure 24.7 Basic Bus Timing: Three-State Access..................................................................746

Figure 24.8 Basic Bus Timing: Three-State Access, One Wait ................................................747

Figure 24.9 Basic Bus Timing: Two-State Access (CS Assertion Period Extended)................ 748

Figure 24.10 Basic Bus Timing: Three-State Access (CS Assertion Period Extended).............. 749

Figure 24.11 Burst ROM Access Timing: One-State Burst Access............................................750

Figure 24.12 Burst ROM Access Timing: Two-State Burst Access ...........................................751

Figure 24.13 DRAM Access Timing: Two-State Access............................................................752

Figure 24.14 DRAM Access Timing: Two-State Access, One Wait ..........................................753

Rev. 2.00, 05/03, page xlv of lii

Figure 24.15 DRAM Access Timing: Two-State Burst Access.................................................. 754

Figure 24.16 DRAM Access Timing: Three-State Access (RAST = 1) .....................................755

Figure 24.17 DRAM Access Timing: Three-State Burst Access................................................ 756

Figure 24.18 CAS-Before-RAS Refresh Timing ........................................................................757

Figure 24.19 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion)............................ 757

Figure 24.20 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0)............. 757

Figure 24.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1)............. 758

Figure 24.22 External Bus Release Timing.................................................................................758

Figure 24.23 External Bus Request Output Timing.................................................................... 759

Figure 24.24 DMAC Single Address Transfer Timing: Two-State Access ................................ 760

Figure 24.25 DMAC Single Address Transfer Timing: Three-State Access .............................. 761

Figure 24.26 DMAC TEND Output Timing ...............................................................................761

Figure 24.27 DMAC DREQ Input Timing .................................................................................762

Figure 24.28 I/O Port Input/Output Timing ................................................................................ 764

Figure 24.29 PPG Output Timing ...............................................................................................764

Figure 24.30 TPU Input/Output Timing......................................................................................764

Figure 24.31 TPU Clock Input Timing ....................................................................................... 765

Figure 24.32 8-Bit Timer Output Timing.................................................................................... 765

Figure 24.33 8-Bit Timer Clock Input Timing............................................................................ 765

Figure 24.34 8-Bit Timer Reset Input Timing.............................................................................765

Figure 24.35 WDT Output Timing .............................................................................................766

Figure 24.36 SCK Clock Input Timing....................................................................................... 766

Figure 24.37 SCI Input/Output Timing: Synchronous Mode...................................................... 766

Figure 24.38 A/D Converter External Trigger Input Timing...................................................... 766

Figure 24.39 I

C Bus Interface Input/Output Timing (Option)................................................... 767

Appendix

Figure C.1 Package Dimensions (TFP-120) ............................................................................793

Figure C.2 Package Dimensions (FP-128B) ............................................................................ 794

Figure D.1 Timing of Address Bus, RD, HWR, and LWR

(8-bit bus, 3-state access, no wait)......................................................................... 796

Rev. 2.00, 05/03, page xlvi of lii

Tables

Section 1 Overview

Table 1.1 Pin Arrangement in Each Operating Mode................................................................9

Table 1.2 Pin Functions ...........................................................................................................14

Section 2 CPU

Table 2.1 Instruction Classification ......................................................................................... 37

Table 2.2 Operation Notation...................................................................................................38

Table 2.3 Data Transfer Instructions........................................................................................39

Table 2.4 Arithmetic Operations Instructions.......................................................................... 40

Table 2.5 Logic Operations Instructions..................................................................................42

Table 2.6 Shift Instructions...................................................................................................... 42

Table 2.7 Bit Manipulation Instructions ..................................................................................43

Table 2.8 Branch Instructions..................................................................................................45

Table 2.9 System Control Instructions.....................................................................................46

Table 2.10 Block Data Transfer Instructions .............................................................................47

Table 2.11 Addressing Modes ...................................................................................................48

Table 2.12 Absolute Address Access Ranges ............................................................................ 50

Table 2.13 Effective Address Calculation ................................................................................. 52

Section 3 MCU Operating Modes

Table 3.1 MCU Operating Mode Selection .............................................................................57

Table 3.2 Pin Functions in Each Operating Mode ...................................................................61

Section 4 Exception Handling

Table 4.1 Exception Types and Priority................................................................................... 69

Table 4.2 Exception Handling Vector Table............................................................................70

Table 4.3 Status of CCR and EXR after Trace Exception Handling........................................74

Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling.......................75

Section 5 Interrupt Controller

Table 5.1 Pin Configuration.....................................................................................................81

Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities..................................93

Table 5.3 Interrupt Control Modes ..........................................................................................97

Table 5.4 Interrupt Response Times ......................................................................................102

Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses .................... 102

Section 6 Bus Controller (BSC)

Table 6.1 Pin Configuration...................................................................................................109

Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)........................................135

Table 6.3 Data Buses Used and Valid Strobes.......................................................................139

Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space ............ 152

Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing.... 153

Table 6.6 DRAM Interface Pins ............................................................................................154

Table 6.7 Idle Cycles in Mixed Accesses to Normal Space and DRAM ............................... 187

Table 6.8 Pin States in Idle Cycle .......................................................................................... 189

Rev. 2.00, 05/03, page xlvii of lii

Table 6.9 Pin States in Bus Released State............................................................................ 192

Section 7 DMA Controller (DMAC)

Table 7.1 Pin Configuration...................................................................................................201

Table 7.2 Short Address Mode and Full Address Mode (Channel 0).................................... 202

Table 7.3 DMAC Activation Sources.................................................................................... 226

Table 7.4 DMAC Transfer Modes......................................................................................... 228

Table 7.5 Register Functions in Sequential Mode .................................................................230

Table 7.6 Register Functions in Idle Mode............................................................................ 233

Table 7.7 Register Functions in Repeat Mode....................................................................... 235

Table 7.8 Register Functions in Single Address Mode.......................................................... 238

Table 7.9 Register Functions in Normal Mode...................................................................... 241

Table 7.10 Register Functions in Block Transfer Mode.......................................................... 244

Table 7.11 DMAC Channel Priority Order.............................................................................. 264

Table 7.12 Interrupt Sources and Priority Order...................................................................... 268

Section 8 Data Transfer Controller (DTC)

Table 8.1 Relationship between Activation Sources and DTCER Clearing .......................... 281

Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................ 283

Table 8.3 Chain Transfer Conditions..................................................................................... 286

Table 8.4 Register Function in Normal Mode .......................................................................286

Table 8.5 Register Function in Repeat Mode ........................................................................287

Table 8.6 Register Function in Block Transfer Mode............................................................288

Table 8.7 DTC Execution Status ...........................................................................................292

Table 8.8 Number of States Required for Each Execution Status..........................................292

Section 9 I/O Ports

Table 9.1 Port Functions........................................................................................................ 300

Table 9.2 MOS Input Pull-Up States (Port A).......................................................................347

Table 9.3 MOS Input Pull-Up States (Port B) ....................................................................... 351

Table 9.4 MOS Input Pull-Up States (Port C) .......................................................................355

Table 9.5 MOS Input Pull-Up States (Port D)....................................................................... 358

Table 9.6 MOS Input Pull-Up States (Port E) .......................................................................362

Section 10 16-Bit Timer Pulse Unit (TPU)

Table 10.1 TPU Functions .......................................................................................................374

Table 10.2 Pin Configuration................................................................................................... 377

Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3) ..................................................................381

Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) .........................................................381

Table 10.5 TPSC2 to TPSC0 (Channel 0) ...............................................................................382

Table 10.6 TPSC2 to TPSC0 (Channel 1) ...............................................................................382

Table 10.7 TPSC2 to TPSC0 (Channel 2) ...............................................................................383

Table 10.8 TPSC2 to TPSC0 (Channel 3) ...............................................................................383

Table 10.9 TPSC2 to TPSC0 (Channel 4) ...............................................................................384

Table 10.10 TPSC2 to TPSC0 (Channel 5) ...............................................................................384

Table 10.11 MD3 to MD0 .........................................................................................................386

Table 10.12 TIORH_0 ............................................................................................................... 388

Rev. 2.00, 05/03, page xlviii of lii

Table 10.13 TIORL_0................................................................................................................389

Table 10.14 TIOR_1.................................................................................................................. 390

Table 10.15 TIOR_2.................................................................................................................. 391

Table 10.16 TIORH_3 ...............................................................................................................392

Table 10.17 TIORL_3................................................................................................................393

Table 10.18 TIOR_4.................................................................................................................. 394

Table 10.19 TIOR_5.................................................................................................................. 395

Table 10.20 TIORH_0 ...............................................................................................................396

Table 10.21 TIORL_0................................................................................................................397

Table 10.22 TIOR_1.................................................................................................................. 398

Table 10.23 TIOR_2.................................................................................................................. 399

Table 10.24 TIORH_3 ...............................................................................................................400

Table 10.25 TIORL_3................................................................................................................401

Table 10.26 TIOR_4.................................................................................................................. 402

Table 10.27 TIOR_5.................................................................................................................. 403

Table 10.28 Register Combinations in Buffer Operation...........................................................418

Table 10.29 Cascaded Combinations......................................................................................... 422

Table 10.30 PWM Output Registers and Output Pins ...............................................................425

Table 10.31 Clock Input Pins in Phase Counting Mode ............................................................429

Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1....................................... 430

Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2....................................... 431

Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3...................................... 432

Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4....................................... 433

Table 10.36 TPU Interrupts .......................................................................................................436

Section 11 Programmable Pulse Generator (PPG)

Table 11.1 Pin Configuration...................................................................................................455

Section 12 8-Bit Timers (TMR)

Table 12.1 Pin Configuration...................................................................................................475

Table 12.2 Clock Input to TCNT and Count Condition...........................................................478

Table 12.3 8-Bit Timer Interrupt Sources ................................................................................ 487

Table 12.4 Timer Output Priorities ..........................................................................................490

Table 12.5 Switching of Internal Clock and TCNT Operation ................................................ 492

Section 13 Watchdog Timer

Table 13.1 Pin Configuration...................................................................................................496

Table 13.2 WDT Interrupt Source ...........................................................................................502

Section 14 Serial Communication Interface (SCI, IrDA)

Table 14.1 Pin Configuration...................................................................................................509

Table 14.2 Relationships between N Setting in BRR and Bit Rate B ...................................... 528

Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode)..................................529

Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ...........................531

Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) .................532

Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... 533

Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .....534

Rev. 2.00, 05/03, page xlix of lii

Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)

(when n = 0 and S = 372).......................................................................................535

Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)

(when S = 372).......................................................................................................536

Table 14.10 Serial Transfer Formats (Asynchronous Mode).....................................................541

Table 14.11 SSR Status Flags and Receive Data Handling ....................................................... 548

Table 14.12 Settings of Bits IrCKS2 to IrCKS0........................................................................ 579

Table 14.13 SCI Interrupt Sources............................................................................................. 581

Table 14.14 Interrupt Sources.................................................................................................... 582

Section 15 I

C Bus Interface2 (IIC2) (Option)

Table 15.1 Pin Configuration................................................................................................... 591

Table 15.2 Transfer Rate ......................................................................................................... 594

Table 15.3 Interrupt Requests .................................................................................................. 616

Table 15.4 Time for monitoring SCL ......................................................................................617

Section 16 A/D Converter

Table 16.1 Pin Configuration................................................................................................... 621

Table 16.2 Analog Input Channels and Corresponding ADDR Registers ...............................622

Table 16.3 A/D Conversion Time (Single Mode)....................................................................628

Table 16.4 A/D Conversion Time (Scan Mode) ......................................................................628

Table 16.5 A/D Converter Interrupt Source............................................................................. 629

Table 16.6 Analog Pin Specifications...................................................................................... 635

Section 17 D/A Converter

Table 17.1 Pin Configuration................................................................................................... 639

Table 17.2 Control of D/A Conversion.................................................................................... 640

Section 19 Flash Memory (F-ZTAT Version)

Table 19.1 Differences between Boot Mode and User Program Mode ...................................647

Table 19.2 Pin Configuration................................................................................................... 652

Table 19.3 Erase Blocks ..........................................................................................................656

Table 19.4 Setting On-Board Programming Mode.................................................................. 657

Table 19.5 Boot Mode Operation ............................................................................................660

Table 19.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate

is Possible ..............................................................................................................661

Table 19.7 Flash Memory Operating States............................................................................. 669

Section 21 Clock Pulse Generator

Table 21.1 Damping Resistance Value .................................................................................... 678

Table 21.2 Crystal Oscillator Characteristics........................................................................... 679

Table 21.3 External Clock Input Conditions ........................................................................... 680

Section 22 Power-Down Modes

Table 22.1 Operating Modes and Internal States of the LSI.................................................... 684

Table 22.2 Oscillation Stabilization Time Settings.................................................................. 692

Table 22.3 φ Pin State in Each Processing State...................................................................... 695

Section 24 Electrical Characteristics

Table 24.1 Absolute Maximum Ratings ..................................................................................733

Rev. 2.00, 05/03, page l of lii

Table 24.2 DC Characteristics (1)............................................................................................ 734

Table 24.3 DC Characteristics (2)............................................................................................ 735

Table 24.4 Permissible Output Currents ..................................................................................736

Table 24.5 Clock Timing ......................................................................................................... 738

Table 24.6 Control Signal Timing ...........................................................................................740

Table 24.7 Bus Timing (1)....................................................................................................... 742

Table 24.8 Bus Timing (2)....................................................................................................... 743

Table 24.9 DMAC Timing.......................................................................................................759

Table 24.10 Timing of On-Chip Peripheral Modules ................................................................762

Table 24.11 A/D Conversion Characteristics.............................................................................768

Table 24.12 D/A Conversion Characteristics.............................................................................768

Table 24.13 Absolute Maximum Ratings ..................................................................................769

Table 24.14 DC Characteristics (1)............................................................................................770

Table 24.15 DC Characteristics (2)............................................................................................771

Table 24.16 Permissible Output Currents.................................................................................. 772

Table 24.17 Clock Timing ......................................................................................................... 773

Table 24.18 Control Signal Timing ...........................................................................................774

Table 24.19 Bus Timing (1).......................................................................................................775

Table 24.20 Bus Timing (2).......................................................................................................776

Table 24.21 DMAC Timing....................................................................................................... 777

Table 24.22 Timing of On-Chip Peripheral Modules ................................................................778

Table 24.23 A/D Conversion Characteristics.............................................................................780

Table 24.24 D/A Conversion Characteristics.............................................................................780

Table 24.25 Flash Memory Characteristics ...............................................................................781

Appendix

Table D.1 Execution State of Instructions ..............................................................................797

Rev. 2.00, 05/03, page li of lii

Rev. 2.00, 05/03, page lii of lii

Section 1 Overview

1.1 Features

• High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions

• Various peripheral functions DMA controller (DMAC)* Data transfer controller (DTC) 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG)* 8-bit timer (TMR) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI)

C bus interface 2 (IIC2) 10-bit A/D converter 8-bit D/A converter Clock pulse generator

Note: * Not supported by the H8S/2366.

• On-chip memory

ROM Type Model ROM RAM Remarks

Flash memory version HD64F2367 384 kbytes 24 kbytes

HD64F2366 384 kbytes 30 kbytes In planning stage Masked ROM version HD6432365 256 kbytes 16 kbytes ROMless version HD6412363  16 kbytes

• General I/O ports

I/O pins: 84 Input-only pins: 10

• Supports various power-down states

• Compact package

Rev. 2.00, 05/03, page 1 of 820

Package Code Body Size Pin Pitch

TFP-120 TFP-120 (TFP-120V*) 14.0 × 14.0 mm 0.4 mm QFP-128 FP-128B (FP-128BV*) 14.0 × 20.0 mm 0.5 mm Note: *Pb free version

Rev. 2.00, 05/03, page 2 of 820

1.2 Block Diagram

Figures 1.1 and 1.2 show the internal block diagrams of this LSI.

PF2/ /

PF1//

PF0/ /

PG4/ /

PG3/ / PG2/ /

EXTAL

PF7/ PF6/ PF5/

PF4/

PF3/

PG6/ PG5/

PG1/ PG0/

P85/SCK3

P83/RxD3 P81/TxD3

MD2 MD1 MD0

XTAL

EMLE

NMI

VCCVCCVCCVCCVCCPLLVCCPLLVSSVSSVSSVSSVSSVSSV

Port FPort GPort 8

PLL

Clock

pulse

generator

Interrupt controller

ROM

(Flash memory

Mask ROM)

RAM

TPU × 6 channels

PPG

TMR × 2 channels

PD7/D15

PD6/D14

PD5/D13

Port D Port E

H8S/2000 CPU

PE7/D7

PE6/D6

PD1/D9

PD0/D8

Internal data bus

WDT

× 5 channels

PE5/D5

Internal address bus

PD4/D12

PD3/D11

DTC

DMAC

SCI

PD2/D10

I2C bus interface 2 (option)

8-bit D/A converter

10-bit A/D converter

PE4/D4

PE3/D3

PE2/D2

PE1/D1

Bus controller

Peripheral data bus

PE0/D0

PA7/A23/ / PA6/A22/ PA5/A21/ PA4/A20/ PA3/A19

Port APort BPort CPort 5 Port 3

PA2/A18 PA1/A17 PA0/A16

PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8

PC7/A7 PC6/A6

Peripheral address bus

PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0

P35/SCK1/SCL0/( ) P34/SCK0/SCK4/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD

P53/ P52/SCK2/ P51/RxD2/ P50/TxD2/

Port 1

P10/PO8/TIOCA0/

P11/PO9/TIOCB0/

P14/PO12/TIOCA1/

P12/PO10/TIOCC0/TCLKA/

P13/PO11/TIOCD0/TCLKB/

P15/PO13/TIOCB1/TCLKC/

Port 2 Port 4 Port 9

Vref

AVCCAV

P46/AN6/()P45/AN5/()P44/AN4/()P43/AN3/()P42/AN2/()P41/AN1/()P40/AN0/(

P16/PO14/TIOCA2

P20/PO0/TIOCA3/TMRI0

P21/PO1/TIOCB3/TMRI1

P22/PO2/TIOCC3/TMCI0

P17/PO15/TIOCB2/TCLKD

P24/PO4/TIOCA4/RxD4/TMO0

P23/PO3/TIOCD3/TxD4/TMCI1

P26/PO6/TIOCA5

P27/PO7/TIOCB5

P25/PO5/TIOCB4/TMO1

P47/AN7/( )

)

P95/AN13/DA3

P94/AN12/DA2

Note: * The ROMless version has no on-chip ROM.

Figure 1.1 Internal Block Diagram of H8S/2367, H8S/2365, and H8S/2363

Rev. 2.00, 05/03, page 3 of 820

PG4/ /

PF6/ PF5/

PF4/

PF3/

PF2/ PF1

PF0/

PG6/

PG5/

PG3/ PG2/ PG1/ PG0/

P85/SCK3 P83/RxD3 P81/TxD3

MD2

MD1

MD0

EXTAL

XTAL

EMLE

PF7/

VCCVCCVCCVCCVCCPLLVCCPLLVSSVSSVSSVSSVSSVSSV

NMI

Port FPort GPort 8

PLL

Clock

pulse

generator

Interrupt controller

ROM

(Flash memory)

RAM

TPU × 6 channels

TMR × 2 channels

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

Port D Port E

H8S/2000 CPU

DTC

SCI

I2C bus interface 2 (option)

8-bit D/A converter

10-bit A/D converter

PE7/D7

PE6/D6

PD1/D9

PD0/D8

Internal data bus

WDT

× 5 channels

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

Internal address bus

Bus controller

Peripheral data bus

PE0/D0

PA7/A23/ / PA6/A22/ PA5/A21/ PA4/A20/ PA3/A19

Port APort BPort CPort 5 Port 3

PA2/A18 PA1/A17 PA0/A16

PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8

PC7/A7 PC6/A6

Peripheral address bus

PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0

P35/SCK1/SCL0 P34/SCK0/SCK4/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD

P53/ P52/SCK2/ P51/RxD2/ P50/TxD2/

P10/TIOCA0

P11/TIOCB0

Figure 1.2 Internal Block Diagram of H8S/2366

Rev. 2.00, 05/03, page 4 of 820

Port 1 Port 2 Port 4 Port 9

)

P95/AN13/DA3

P14/TIOCA1

P16/TIOCA2

P12/TIOCC0/TCLKA

P13/TIOCD0/TCLKB

P15/TIOCB1/TCLKC

P17/TIOCB2/TCLKD

P20/TIOCA3/TMRI0

P25/TIOCB4/TMO1

P21/TIOCB3/TMRI1

P22/TIOCC3/TMCI0

P24/TIOCA4/RxD4/TMO0

P23/TIOCD3/TxD4/TMCI1

Vref

P26/TIOCA5

P27/TIOCB5

AVCCAV

P46/AN6/()P45/AN5/()P44/AN4/()P43/AN3/()P42/AN2/()P41/AN1/()P40/AN0/(

P47/AN7/( )

P94/AN12/DA2

1.3 Pin Description

1.3.1 Pin Arrangement

Figures 1.3 to 1.6 show the pin arrangements of this LSI.

PG1/

PG0/

VSSP81/TxD3

P83/RxD3

VCCVCCEXTAL

XTAL

VSSPF7/φ

PLLVSSPLLV

PF5/

PF4/

PF3/

PF2/ /

PF1/ /

PF0/ /

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PF6/

9089888786858483828180797877767574737271706968676665646362

MD0 MD1

Vref

91 92 93

94 95

)

100

)

101

)

102

)

103 104 105

106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

1234567891011121314151617181920212223242526272829

MD2

PC0/A0

PC1/A1

PC2/A2

PC3/A3

PC4/A4

PC5/A5

PC6/A6

TFP-120

(Top view)

PB0/A8

PB1/A9

PC7/A7

PB2/A10

PB3/A11

PB4/A12

PB5/A13

PB6/A14

PB7/A15

PA0/A16

PA1/A17

PA2/A18

PA3/A19

PG2/ /

PG3/ /

P40/AN0/( P41/AN1/( P42/AN2/( P43/AN3/( P44/AN4/( P45/AN5/( P46/AN6/( P47/AN7/(

P94/AN12/DA2 P95/AN13/DA3

PG4/ /

PG5/

PG6/ P50/TxD2/ P51/RxD2/

P52/SCK2/

P53/ /

P35/SCK1/SCL0/( )

P34/SCK0/SCK4/SDA0

P33/RxD1/SCL1

P32/RxD0/IrRxD/SDA1

P31/TxD1

P30/TxD0/IrTxD

Note: * This is an emulator enable pin. Normally, this pin should be set to low. If this pin goes high in the flash memory version,

the on-chip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and

PD0/D8

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

EMLE*

PA5/A21/

PA6/A22/

PA4/A20/

PA7/A23/ /

function only for the on-chip emulator.

V PE7/D7

V PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 P85/SCK3 P27/PO7/TIOCB5 P26/PO6/TIOCA5 P25/PO5/TIOCB4/TMO1 P24/PO4/TIOCA4/TMO0/RxD4 P23/PO3/TIOCD3/TMCI1/TxD4 P22/PO2/TIOCC3/TMCI0 P21/PO1/TIOCB3/TMRI1 P20/PO0/TIOCA3/TMRI0 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC/ P14/PO12/TIOCA1/ P13/PO11/TIOCD0/TCLKB/ P12/PO10/TIOCC0/TCLKA/ P11/PO9/TIOCB0/ P10/PO8/TIOCA0/ V

NMI

Figure 1.3 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363

Rev. 2.00, 05/03, page 5 of 820

PG1/

PG0/

VSSP81/TxD3

P83/RxD3

VCCVCCEXTAL

XTAL

VSSPF7/φ

PLLVSSPLLV

PF6/

PF5/

9089888786858483828180797877767574737271706968676665646362

MD0 MD1

Vref

91 92 93

94 95

)

100

)

101

)

102

)

103 104 105

106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

TFP-120

(Top view)

PG2/

PG3/

P40/AN0/( P41/AN1/( P42/AN2/( P43/AN3/( P44/AN4/( P45/AN5/( P46/AN6/( P47/AN7/(

P94/AN12/DA2 P95/AN13/DA3

PG4/ /

PG5/

PG6/

P50/TxD2/ P51/RxD2/ P52/SCK2/

P53/ /

P35/SCK1/SCL0

P34/SCK0/SCK4/SDA0

P33/RxD1/SCL1

P32/RxD0/IrRxD/SDA1

P31/TxD1

P30/TxD0/IrTxD

1234567891011121314151617181920212223242526272829

MD2

PC0/A0

PC1/A1

PC2/A2

PC3/A3

PC4/A4

PC5/A5

PC6/A6

PB0/A8

PC7/A7

PB1/A9

PB2/A10

PB3/A11

PB4/A12

Note: * This pin should be set to low and should not be changed during operation.

PF4/

PF3/

PF2/

PB5/A13

PB6/A14

PB7/A15

PF1/

PF0/

PD7/D15

PA0/A16

PA1/A17

PD6/D14

PD5/D13

PD4/D12

PA2/A18

PA3/A19

PA4/A20/

PD3/D11

PD2/D10

PD1/D9

PA5/A21/

PA6/A22/

PA7/A23/ /

PD0/D8

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

P85/SCK3

P27/TIOCB5

P26/TIOCA5

P25/TIOCB4/TMO1

P24/TIOCA4/TMO0/RxD4

P23/TIOCD3/TMCI1/TxD4

P22/TIOCC3/TMCI0

P21/TIOCB3/TMRI1

P20/TIOCA3/TMRI0

P17/TIOCB2/TCLKD

P16/TIOCA2

P15/TIOCB1/TCLKC

P14/TIOCA1

P13/TIOCD0/TCLKB

P12/TIOCC0/TCLKA

P11/TIOCB0

P10/TIOCA0

NMI

32 31

EMLE*

Figure 1.4 Pin Arrangement of H8S/2366

Rev. 2.00, 05/03, page 6 of 820

PG3/ /

PG2/ /

VSSVSSPG1/

PG0/

VSSP81/TxD3

P83/RxD3

VCCVCCEXTAL

XTAL

VSSPF7/φPLLVSSPLLVCCPF6/

PC0/A0

PC1/A1

PC2/A2

PC3/A3

919092939495969798

898887868584838281

PC4/A4

PC5/A5

PC6/A6

PC7/A7

FP-128B

(Top view)

PB0/A8

100

101

P40/AN0/( P41/AN1/( P42/AN2/( P43/AN3/( P44/AN4/( P45/AN5/( P46/AN6/( P47/AN7/(

P94/AN12/DA2 P95/AN13/DA3

PG4/ /

PG5/

PG6/

P50/TxD2/ P51/RxD2/ P52/SCK2/

P53/ /

P35/SCK1/SCL0/( )

P34/SCK0/SCK4/SDA0

P33/RxD1/SCL1

P32/RxD0/IrRxD/SDA1

P31/TxD1

P30/TxD0/IrTxD

Notes: *1 The NC pin should be fixed to Vss or should be open.

*2 This is an emulator enable pin. Normally, this pin should be set to low. If this pin goes high in the flash memory version, the on-chip emulator function is

enabled. At this time, pins P53, PG4, PG5, PG6, and

102

103

Vref

104

)

105

)

106

)

107

)

108

)

109

)

110

)

111

)

112 113 114

115 116 117 118 119 120 121 122 123 124 125 126 127 128

12345678910111213141516171819202122232425262728293031323334353637

SSVSS

MD0

MD1

MD2

PF5/

PF4/

PF3/

PF2/ /

PF1/ /

PF0/ /

PD7/D15

PD6/D14

PD5/D13

PD4/D12

75747677787980

737271706968676665

PB1/A9

PB2/A10

PB3/A11

PB4/A12

PB5/A13

PB6/A14

PB7/A15

PA0/A16

PA1/A17

PA2/A18

PA3/A19

PA4/A20/

function only for the on-chip emulator.

PD3/D11

PD2/D10

PD1/D9

PA5/A21/

PA6/A22/

PA7/A23/ /

PD0/D8

VSSNC*1VCCPE7/D7

VSSV

EMLE*

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

P85/SCK3

P27/PO7/TIOCB5

P26/PO6/TIOCA5

P25/PO5/TIOCB4/TMO1

P24/PO4/TIOCA4/TMO0/RxD4

P23/PO3/TIOCD3/TMCI1/TxD4

P22/PO2/TIOCC3/TMCI0

P21/PO1/TIOCB3/TMRI1

P20/PO0/TIOCA3/TMRI0

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2

P15/PO13/TIOCB1/TCLKC/

P14/PO12/TIOCA1/

P13/PO11/TIOCD0/TCLKB/

P12/PO10/TIOCC0/TCLKA/

P11/PO9/TIOCB0/ P10/PO8/TIOCA0/

NMI

Figure 1.5 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363

Rev. 2.00, 05/03, page 7 of 820

PG3/

PG2/

VSSVSSPG1/

PG0/

VSSP81/TxD3

P83/RxD3

VCCVCCEXTAL

PC0/A0

PC1/A1

PC2/A2

PC3/A3

919092939495969798

PC4/A4

100

101

P40/AN0/( P41/AN1/( P42/AN2/( P43/AN3/( P44/AN4/( P45/AN5/( P46/AN6/( P47/AN7/(

P94/AN12/DA2 P95/AN13/DA3

PG4/ /

PG5/ PG6/

P50/TxD2/

P51/RxD2/

P52/SCK2/

P53/ /

P35/SCK1/SCL0

P34/SCK0/SCK4/SDA0

P33/RxD1/SCL1

P32/RxD0/IrRxD/SDA1

P31/TxD1

P30/TxD0/IrTxD

Notes: *1 The NC pin should be fixed to Vss or should be open.

*2 This pin should be set to low and should not be changed during operation.

102

103

Vref

104

)

105

)

106

)

107

)

108

)

109

)

110

)

111

)

112 113 114

115 116 117 118 119 120 121 122 123 124 125 126 127 128

12345678910111213141516171819202122232425262728293031323334353637

SSVSS

MD0

MD1

MD2

Figure 1.6 Pin Arrangement of H8S/2366

XTAL

VSSPF7/φPLLVSSPLLVCCPF6/

898887868584838281

FP-128B

(Top view)

PB0/A8

PB1/A9

PC5/A5

PC6/A6

PC7/A7

PB2/A10

PB3/A11

PF5/

PB4/A12

PB5/A13

PF4/

PF3/

PB6/A14

PF2/

PF1/

PB7/A15

PA0/A16

PF0/

PD7/D15

PA1/A17

PD6/D14

PD5/D13

75747677787980

PA2/A18

PA3/A19

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

VSSNC*1VCCPE7/D7

737271706968676665

VSSV

EMLE*

PA5/A21/

PA6/A22/

PA4/A20/

PA7/A23/ /

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

P85/SCK3

P27/TIOCB5

P26/TIOCA5

P25/TIOCB4/TMO1

P24/TIOCA4/TMO0/RxD4

P23/TIOCD3/TMCI1/TxD4

P22/TIOCC3/TMCI0

P21/TIOCB3/TMRI1

P20/TIOCA3/TMRI0

P17/TIOCB2/TCLKD

P16/TIOCA2

P15/TIOCB1/TCLKC

P14/TIOCA1

P13/TIOCD0/TCLKB

P12/TIOCC0/TCLKA

P11/TIOCB0 P10/TIOCA0

NMI

Rev. 2.00, 05/03, page 8 of 820

1.3.2 Pin Arrangement in Each Operating Mode

Table 1.1 Pin Arrangement in Each Operating Mode

Pin No. Pin Name

TFP-120 QFP-128 Mode 1 Mode 2 Mode 4

EXPE = 1 EXPE = 0

1 5 MD2 MD2 MD2 MD2 MD2 Vss 2 6 Vcc Vcc Vcc Vcc Vcc Vcc 3 7 A0 A0 PC0/A0 PC0/A0 PC0 A0 4 8 A1 A1 PC1/A1 PC1/A1 PC1 A1 5 9 A2 A2 PC2/A2 PC2/A2 PC2 A2 6 10 A3 A3 PC3/A3 PC3/A3 PC3 A3 7 11 A4 A4 PC4/A4 PC4/A4 PC4 A4 8 12 Vss Vss Vss Vss Vss Vss

9 13 A5 A5 PC5/A5 PC5/A5 PC5 A5 10 14 A6 A6 PC6/A6 PC6/A6 PC6 A6 11 15 A7 A7 PC7/A7 PC7/A7 PC7 A7 12 16 A8 A8 PB0/A8 PB0/A8 PB0 A8 13 17 A9 A9 PB1/A9 PB1/A9 PB1 A9 14 18 A10 A10 PB2/A10 PB2/A10 PB2 A10 15 19 A11 A11 PB3/A11 PB3/A11 PB3 A11 16 20 A12 A12 PB4/A12 PB4/A12 PB4 A12 17 21 Vss Vss Vss Vss Vss Vss 18 22 A13 A13 PB5/A13 PB5/A13 PB5 A13 19 23 A14 A14 PB6/A14 PB6/A14 PB6 A14 20 24 A15 A15 PB7/A15 PB7/A15 PB7 A15 21 25 A16 A16 PA0/A16 PA0/A16 PA0 A16 22 26 Vss Vss Vss Vss Vss Vss 23 27 A17 A17 PA1/A17 PA1/A17 PA1 A17 24 28 A18 A18 PA2/A18 PA2/A18 PA2 A18 25 29 A19 A19 PA3/A19 PA3/A19 PA3 NC 26 30 A20/IRQ4 A20/IRQ4 PA4/A20/IRQ4 PA4/A20/IRQ4 PA4/IRQ4 NC 27 31 PA5/A21/IRQ5 PA5/A21/IRQ5 PA5/A21/IRQ5 PA5/IRQ5 PA5/IRQ5 NC 28 32 PA6/A22/IRQ6 PA6/A22/IRQ6 PA6/A22/IRQ6 PA6/IRQ6 PA6/IRQ6 NC 29 33 PA7/A23/CS7/

IRQ7

PA7/A23/CS7/ IRQ7

PA7/CS7/ IRQ7

Mode 7

PA7/IRQ7 NC

Flash Memory Programmer Mode

Rev. 2.00, 05/03, page 9 of 820

Pin No. Pin Name

TFP-120 QFP-128 Mode 1 Mode 2 Mode 4

EXPE = 1 EXPE = 0

30 34 EMLE EMLE EMLE EMLE EMLE EMLE

 35 Vss Vss Vss Vss Vss Vss  36 Vss Vss Vss Vss Vss Vss

31 37 WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF NC 32 38 NMI NMI NMI NMI NMI Vcc 33 39 Vcc Vcc Vcc Vcc Vcc Vcc 34 40 P10/PO8*/

TIOCA0/DREQ0*

35 41 P11/PO9*/

TIOCB0/DREQ1*

36 42 P12/PO10*/

TIOCC0/TCLKA/

TEND0*

37 43 P13/PO11*/

TIOCD0/TCLKB/

TEND1*

38 44 P14/PO12*/

TIOCA1/DACK0*

39 45 P15/PO13*/

TIOCB1/TCLKC/

DACK1*

40 46 P16/PO14*/

TIOCA2

41 47 P17/PO15*/

TIOCB2/TCLKD

42 48 P20/PO0*/

TIOCA3/TMRI0

43 49 P21/PO1*/

TIOCB3/TMRI1

44 50 P22/PO2*/

TIOCC3/TMCI0

45 51 P23/PO3*/

TIOCD3/TMCI1/ TxD4

46 52 P24/PO4*/

TIOCA4/TMO0/ RxD4

P10/PO8*/ TIOCA0/DREQ0*

P11/PO9*/ TIOCB0/DREQ1*

P12/PO10*/ TIOCC0/TCLKA/

TEND0*

P13/PO11*/ TIOCD0/TCLKB/

TEND1*

P14/PO12*/ TIOCA1/DACK0*

P15/PO13*/ TIOCB1/TCLKC/

DACK1*

P16/PO14*/ TIOCA2

P17/PO15*/ TIOCB2/TCLKD

P20/PO0*/ TIOCA3/(TMRI0)

P21/PO1*/ TIOCB3/TMRI1

P22/PO2*/ TIOCC3/TMCI0

P23/PO3*/ TIOCD3/TMCI1/ TxD4

P24/PO4*/ TIOCA4/TMO0/ RxD4

P10/PO8*/ TIOCA0/DREQ0*

P11/PO9*/ TIOCB0/DREQ1*

P12/PO10*/ TIOCC0/TCLKA/

TEND0*

P13/PO11*/ TIOCD0/TCLKB/

TEND1*

P14/PO12*/ TIOCA1/DACK0*

P15/PO13*/ TIOCB1/TCLKC/

DACK1*

P16/PO14*/ TIOCA2

P17/PO15*/ TIOCB2/TCLKD

P20/PO0*/ TIOCA3/(TMRI0)

P21/PO1*/ TIOCB3/TMRI1

P22/PO2*/ TIOCC3/TMCI0

P23/PO3*/ TIOCD3/TMCI1/ TxD4

P24/PO4*/ TIOCA4/TMO0/ RxD4

P10/PO8*/ TIOCA0/DREQ0*

P11/PO9*/ TIOCB0/DREQ1*

P12/PO10*/ TIOCC0/TCLKA/

TEND0*

P13/PO11*/ TIOCD0/TCLKB/

TEND1*

P14/PO12*/ TIOCA1/DACK0*

P15/PO13*/ TIOCB1/TCLKC/

DACK1*

P16/PO14*/ TIOCA2

P17/PO15*/ TIOCB2/TCLKD

P20/PO0*/ TIOCA3/(TMRI0)

P21/PO1*/ TIOCB3/TMRI1

P22/PO2*/ TIOCC3/TMCI0

P23/PO3*/ TIOCD3/TMCI1/ TxD4

P24/PO4*/ TIOCA4/TMO0/ RxD4

Mode 7

P10/PO8*/ TIOCA0/DREQ0*

P11/PO9*/ TIOCB0/DREQ1*

P12/PO10*/ TIOCC0/TCLKA/

TEND0*

P13/PO11*/ TIOCD0/TCLKB/

TEND1*

P14/PO12*/ TIOCA1/DACK0*

P15/PO13*/ TIOCB1/TCLKC/

DACK1*

P16/PO14*/ TIOCA2

P17/PO15*/ TIOCB2/TCLKD

P20/PO0*/ TIOCA3/(TMRI0)

P21/PO1*/ TIOCB3/TMRI1

P22/PO2*/ TIOCC3/TMCI0

P23/PO3*/ TIOCD3/TMCI1/ TxD4

P24/PO4*/ TIOCA4/TMO0/ RxD4

Flash Memory Programmer Mode

Rev. 2.00, 05/03, page 10 of 820

Pin No. Pin Name

TFP-120 QFP-128 Mode 1 Mode 2 Mode 4

EXPE = 1 EXPE = 0

47 53 P25/PO5*/

TIOCB4/TMO1

48 54 P26/PO6*/

TIOCA5

49 55 P27/PO7*/

TIOCB5 50 56 P85/SCK3 P85/SCK3 P85/SCK3 P85/SCK3 P85/SCK3 NC 51 57 D0 PE0/D0 PE0/D0 PE0/D0 PE0 NC 52 58 D1 PE1/D1 PE1/D1 PE1/D1 PE1 NC 53 59 D2 PE2/D2 PE2/D2 PE2/D2 PE2 NC 54 60 D3 PE3/D3 PE3/D3 PE3/D3 PE3 NC 55 61 D4 PE4/D4 PE4/D4 PE4/D4 PE4 NC 56 62 D5 PE5/D5 PE5/D5 PE5/D5 PE5 NC 57 63 D6 PE6/D6 PE6/D6 PE6/D6 PE6 NC 58 64 Vss Vss Vss Vss Vss Vss 59 65 D7 PE7/D7 PE7/D7 PE7/D7 PE7 NC 60 66 Vcc Vcc Vcc Vcc Vcc Vcc

 67 NC NC NC NC NC NC  68 Vss Vss Vss Vss Vss Vss

61 69 D8 D8 D8 D8 PD0 I/O0 62 70 D9 D9 D9 D9 PD1 I/O1 63 71 D10 D10 D10 D10 PD2 I/O2 64 72 D11 D11 D11 D11 PD3 I/O3 65 73 D12 D12 D12 D12 PD4 I/O4 66 74 D13 D13 D13 D13 PD5 I/O5 67 75 D14 D14 D14 D14 PD6 I/O6 68 76 D15 D15 D15 D15 PD7 I/O7 69 77 PF0/WAIT/OE* PF0/WAIT/OE* PF0/WAIT/OE* PF0/WAIT/OE* PF0 NC 70 78 PF1/CS5/UCAS* PF1/CS5/UCAS* PF1/CS5/UCAS* PF1/CS5/UCAS* PF1 NC 71 79 PF2/CS6/LCAS* PF2/CS6/LCAS* PF2/CS6/LCAS* PF2/CS6/LCAS* PF2 NC 72 80 PF3/LWR PF3/LWR PF3/LWR PF3/LWR PF3 NC 73 81 HWR HWR HWR HWR PF4 NC 74 82 RD RD RD RD PF5 NC

P25/PO5*/ TIOCB4/TMO1

P26/PO6*/ TIOCA5

P27/PO7*/ TIOCB5

P25/PO5*/ TIOCB4/TMO1

P26/PO6*/ TIOCA5

P27/PO7*/ TIOCB5

P25/PO5*/ TIOCB4/TMO1

P26/PO6*/ TIOCA5

P27/PO7*/ TIOCB5

Mode 7

P25/PO5*/ TIOCB4/TMO1

P26/PO6*/ TIOCA5

P27/PO7*/ TIOCB5

Flash Memory Programmer Mode

Vss

Rev. 2.00, 05/03, page 11 of 820

Pin No. Pin Name

TFP-120 QFP-128 Mode 1 Mode 2 Mode 4

EXPE = 1 EXPE = 0

75 83 PF6/AS PF6/AS PF6/AS PF6/AS PF6 NC 76 84 PLLVcc PLLVcc PLLVcc PLLVcc PLLVcc Vcc 77 85 RES RES RES RES RES RES 78 86 PLLVss PLLVss PLLVss PLLVss PLLVss Vss 79 87 PF7/φ PF7/φ PF7/φ PF7/φ PF7/φ NC 80 88 Vss Vss Vss Vss Vss Vss 81 89 XTAL XTAL XTAL XTAL XTAL XTAL 82 90 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL 83 91 Vcc Vcc Vcc Vcc Vcc Vcc 84 92 Vcc Vcc Vcc Vcc Vcc Vcc 85 93 P83/RxD3 P83/RxD3 P83/RxD3 P83/RxD3 P83/RxD3 NC 86 94 P81/TxD3 P81/TxD3 P81/TxD3 P81/TxD3 P81/TxD3 NC 87 95 Vss Vss Vss Vss Vss Vss 88 96 STBY STBY STBY STBY STBY Vcc 89 97 PG0/CS0 PG0/CS0 PG0/CS0 PG0/CS0 PG0 NC 90 98 PG1/CS1 PG1/CS1 PG1/CS1 PG1/CS1 PG1 NC

 99 Vss Vss Vss Vss Vss Vss  100 Vss Vss Vss Vss Vss Vss

91 101 PG2/CS2/RAS2* PG2/CS2/RAS2* PG2/CS2/RAS2* PG2/CS2/RAS2* PG2 NC 92 102 PG3/CS3/RAS3* PG3/CS3/RAS3* PG3/CS3/RAS3* PG3/CS3/RAS3* PG3 NC 93 103 AVcc AVcc AVcc AVcc AVcc Vcc 94 104 Vref Vref Vref Vref Vref NC 95 105 P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0)NC 96 106 P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1)NC 97 107 P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2)NC 98 108 P43/AN3/(IRQ3) P43/AN3/(IRQ3) P43/AN3/(IRQ3) P43/AN3/(IRQ3) P43/AN3/(IRQ3)NC

99 109 P44/AN4/(IRQ4) P44/AN4/(IRQ4) P44/AN4/(IRQ4) P44/AN4/(IRQ4) P44/AN4/(IRQ4)NC 100 110 P45/AN5/(IRQ5) P45/AN5/(IRQ5) P45/AN5/(IRQ5) P45/AN5/(IRQ5) P45/AN5/(IRQ5)NC 101 111 P46/AN6/(IRQ6) P46/AN6/(IRQ6) P46/AN6/(IRQ6) P46/AN6/(IRQ6) P46/AN6/(IRQ6)NC 102 112 P47/AN7/(IRQ7) P47/AN7/(IRQ7) P47/AN7/(IRQ7) P47/AN7/(IRQ7) P47/AN7/(IRQ7)NC 103 113 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 NC 104 114 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 NC

Mode 7

Flash Memory Programmer Mode

Rev. 2.00, 05/03, page 12 of 820

Pin No. Pin Name

TFP-120 QFP-128 Mode 1 Mode 2 Mode 4

EXPE = 1 EXPE = 0

105 115 AVss AVss AVss AVss AVss Vss 106 116 PG4/CS4/

BREQO

107 117 PG5/BACK PG5/BACK PG5/BACK PG5/BACK PG5 NC 108 118 PG6/BREQ PG6/BREQ PG6/BREQ PG6/BREQ PG6 NC 109 119 P50/TxD2/IRQ0 P50/TxD2/IRQ0 P50/TxD2/IRQ0 110 120 P51/RxD2/IRQ1 P51/RxD2/IRQ1 P51/RxD2/IRQ1 111 121 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 Vcc 112 122 P53/ADTRG/

IRQ3

113 123 P35/SCK1/SCL0/

(OE)*

114 124 P34/SCK0/SCK4/

SDA0 115 125 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 NC 116 126 P32/RxD0/IrRxD/

SDA1 117 127 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 NC 118 128 P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD NC 119 1 MD0 MD0 MD0 MD0 MD0 Vss 120 2 MD1 MD1 MD1 MD1 MD1 Vss

 3 Vss Vss Vss Vss Vss Vss  4 Vss Vss Vss Vss Vss Vss

PG4/CS4/ BREQO

P53/ADTRG/ IRQ3

P35/SCK1/SCL0/ (OE)*

P34/SCK0/SCK4/ SDA0

P32/RxD0/IrRxD/ SDA1

PG4/CS4/

BREQO

P53/ADTRG/ IRQ3

P35/SCK1/SCL0/ (OE)*

P34/SCK0/SCK4/ SDA0

P32/RxD0/IrRxD/ SDA1

PG4/CS4/

BREQO

P50/TxD2/IRQ0 P50/TxD2/IRQ0 P51/RxD2/IRQ1 P51/RxD2/IRQ1

P53/ADTRG/

IRQ3

P35/SCK1/SCL0/ (OE)*

P34/SCK0/SCK4/ SDA0

P32/RxD0/IrRxD/ SDA1

Mode 7

PG4 NC

P53/ADTRG/

IRQ3

P35/SCK1/SCL0 NC

P34/SCK0/SCK4/ SDA0

P32/RxD0/IrRxD/ SDA1

Note: * Not supported by the H8S/2366.

Flash Memory Programmer Mode

Vss Vss

Vcc

Rev. 2.00, 05/03, page 13 of 820

1.3.3 Pin Functions

Table 1.2 Pin F unct ions

Type Symbol

Power

Clock

Operating mode control

System control

PLLV

XTAL 81 89 Input For connection to a crystal oscillator.

EXTAL 82 90 Input For connection to a crystal oscillator.

0 79 87 Output Supplies the system clock to external

MD2 MD1 MD0

RES 77 85 Input Reset pin. When this pin is driven

STBY 88 96 Input When this pin is driven low, a

EMLE 30 34 Input Enables emulator. This pin should be

Pin No. TFP-120 QFP-128

2,33,60, 83,84

6,39,66, 91,92

I/O Function

Input Power supply pins. VCC pins should

be connected to the system power supply.

8,17,22, 58,80,87

3,4,12, 21,26,35, 36,64,68

Input Ground pins. V

connected to the system power supply (0 V).

pins should be

88,95,99 100

76 84 Input Power supply pin for the on-chip PLL

oscillator.

78 86 Input Ground pin for the on-chip PLL

oscillator.

See section 21, Clock Pulse Generator for typical connection diagrams for a crystal oscillator and external clock input.

The EXTAL pin can also input an external clock. See section 21, Clock Pulse Generator for typical connection diagrams for a crystal oscillator and external clock input.

devices.

1, 120, 119

5, 2, 1

Input These pins set the operating mode.

These pins should not be changed while the MCU is operating.

low, the chip is reset.

transition is made to hardware standby mode.

connected to the power supply (0 V).

Rev. 2.00, 05/03, page 14 of 820

Pin No.

Type Symbol

Address bus A23 toA029 to 23,

Data bus D15 toD068 to 61,

Bus control CS7 to

CS0

AS 75 83 Output When this pin is low, it indicates that

RD 74 82 Output When this pin is low, it indicates that

HWR 73 81 Output Strobe signal indicating that external

LWR 72 80 Output Strobe signal indicating that external

BREQ 108 118 Input The external bus master requests the

BREQO 106 116 Input External bus request signal when the

BACK 107 117 Output Indicates the bus is released to the

UCAS* 70 78 Output Upper column address strobe signal

TFP-120 QFP-128

21 to 18, 16 to 9, 7 to 3

59, 57 to 51

29,71,70, 106, 92 to 89

33 to 27, 25 to 22, 20 to 13, 11 to 7

76 to 69, 65, 63 to 57

33,79,78, 116,102, 101,98,97

I/O Function

Output Address output pins.

Input/ output

Output Signals that select division areas 7 to

These pins constitute a bidirectional data bus.

0 in the external address space.

address output on the address bus is valid.

the external address space is being read.

address space is to be written, and the upper half (D15 to D8) of the data bus is enabled.

Write enable signal for accessing the DRAM space.

address space is to be written, and the lower half (D7 to D0) of the data bus is enabled.

bus to this LSI.

internal bus master accesses the external space in external bus release state.

external bus master.

for accessing the 16-bit DRAM space.

Column address strobe signal for accessing the 8-bit DRAM space.

Rev. 2.00, 05/03, page 15 of 820

Pin No.

Type Symbol

Bus control LCAS* 71 79 Output Lower column address strobe signal

RAS2* RAS3*9192

WAIT* 69 77 Input Requests insertion of a wait state in

OE*

(OE)*

Interrupt signals

DMA controller (DMAC)*

16-bit timer pulse unit (TPU)

NMI 32 38 Input Nonmaskable interrupt request pin.

IRQ7 to IRQ0

(IRQ7) to (IRQ0)

DREQ1* DREQ0*

TEND1*, TEND0*

DACK1*, DACK0*

TCLKD TCLKC TCLKB TCLKA

TIOCA0 TIOCB0 TIOCC0 TIOCD0

TIOCA1 TIOCB1

TFP-120 QFP-128

101 102

69, 113

29 to 26, 112 to 109, 102 to 95

35, 34

37, 36

39, 38

41, 39, 37, 36

34, 35, 36, 37

38, 39

77, 123

33 to 30, 122 to 119, 112 to 105

41, 40

43, 42

45, 44

47, 45, 43, 42

40, 41, 42, 43

44, 45

I/O Function

for accessing the 16-bit DRAM space.

Output Row address strobe signal for the

DRAM interface.

the bus cycle when accessing external 3-state address space.

Output Output enable signal for accessing

the DRAM space. The output pins of OE and (OE) are

selected by the port function control register 2 (PFCR2) of port 3.

Fix high when not used.

Input These pins request a maskable

interrupt. The input pins of IRQn and (IRQn)

are selected by the IRQ pin select register (ITSR) of the interrupt controller. (n = 0 to 7)

Input These signals request DMAC

activation.

Output These signals indicate the end of

DMAC data transfer.

Output DMAC single address transfer

acknowledge signals.

Input External clock input pins for the timer.

Input/ output

TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins.

TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins.

Rev. 2.00, 05/03, page 16 of 820

Type Symbol

16-bit timer pulse unit (TPU)

Programmable pulse generator (PPG)*

8-bit timer (TMR)

Watchdog Timer(WDT)

Serial communication interface(SCI)/ smart card interface (SCI_0 with IrDA function)

TIOCA2 TIOCB2

TIOCA3 TIOCB3 TIOCC3 TIOCD3

TIOCA4 TIOCB4

TIOCA5 TIOCB5

PO15 to PO0*

TMO0 TMO1

TMCI0 TMCI1

TMRI0 TMRI1

WDTOVF 31 37 Output Counter overflow sig nal output pin in

TxD4 TxD3 TxD2 TxD1 TxD0/ IrTxD

RxD4 RxD3 RxD2 RxD1 RxD0/ IrRxD

SCK4 SCK3 SCK2 SCK1 SCK0

Pin No. TFP-120 QFP-128

40, 41

42, 43, 44, 45

46, 47

48, 49

41 to 34, 49 to42

46, 47

44, 45

42, 43

45, 86, 109, 117, 118

46, 85, 110, 115, 116

114, 50, 111, 113, 114

46, 47

48, 49, 50, 51

52, 53

54, 55

47 to 40, 55 to 48

52, 53

50, 51

48, 49

51, 94, 119, 127, 128

52, 93, 120 125, 126

124, 56, 121, 123, 124

I/O Function

Input/ output

Output Pulse output pins.

Output Waveform output pins with output

Input External event input pins.

Input Counter reset input pins.

Output Data output pins.

Input Data input pins.

Input/ output

TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins.

TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins.

TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins.

TGRA_5 and TGRB_5 input capture input/output compare output/PWM output pins.

compare function.

watchdog timer mode.

Clock input/output pins.

Rev. 2.00, 05/03, page 17 of 820

Type Symbol

IIC bus interface2

SCL1 SCL0

(IIC2) IIC bus

interface (IIC)

SDA1 SDA0

AN13, AN12, AN7 to AN0

ADTRG 112 122 Input Pin for input of an external trigger to

D/A converter DA3,

DA2

A/D converter,

D/A converter

Vref 94 104 Input The reference voltage input pin for

I/O ports P17 to

P10 P27 to

P20 P35 to

P30 P47 to

P40 P53 to

P50

Pin No. TFP-120 QFP-128

115, 113

116, 114

125, 123

126, 124

I/O Function

Input/

IIC clock input/output pins.

output

Input/

IIC data input/output pins.

output

104 to 95 114 to 105 Input Analog input pins.A/D converter

start A/D conversion.

104, 103

114, 113

Output Analog output pins.

93 103 Input The analog power-supply pin for the

A/D converter and D/A converter. When the A/D converter and D/A

converter are not used, this pin should be connected to the system power supply (+3 V).

105 115 Input The ground pin for the A/D

converter and D/A converter. This pin should be connected to the

system power supply (0 V).

the A/D converter and D/A converter.

When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V).

41 to 34 47 to 40 Input/

Eight-bit input/output pins.

output

49 to 42 55 to 48 Input/

Eight-bit input/output pins.

output

113 to 118 123 to 128 Input/

Six-bit input/output pins.

output

102 to 95 112 to 105 Input Eight-bit input pins.

112 to 109 122 to 119 Input/

Four-bit input/output pins.

output

Rev. 2.00, 05/03, page 18 of 820

Pin No.

Type Symbol

I/O ports P85,

P83, P81

P95, P94

PA7 to PA0

PB7 to PB0

PC7 to PC0

PD7 to PD0

PE7 to PE0

PF7 to PF0

PG6 to PG0

Note: * Not supported by the H8S/2366.

TFP-120 QFP-128

50, 85, 86

104, 103

29 to 23,2133 to 27,25Input/

20 to 18, 16 to 12

11 to 9, 7 to 3

68 to 61 76 to 69 Input/

59, 57 to 51

79, 75 to 69

108 to 106, 92 to 89

56, 93, 94

114, 113

24 to 22, 20 to 16

15 to 13, 11 to 7

65, 63 to 57

87, 83 to 77

118 to 116, 102,101, 98,97

I/O Function

Input/ output

Input Two-bit input pins.

output Input/ output Input/ output

output Input/ output Input/ output Input/ output

Three-bit input/output pins.

Eight-bit input/output pins.

Seven-bit input/output pins.

Rev. 2.00, 05/03, page 19 of 820

Rev. 2.00, 05/03, page 20 of 820

Section 2 CPU

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1 Features

• Upward-compatibility with H8/300 and H8/300H CPUs  Can execute H8/300 and H8/300H CPU object programs

• General-register architecture  Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-five basic instructions  8/16/32-bit arithmetic and logic instructions  Multiply and divide instructions  Powerful bit-manipulation instructions

• Eight addressing modes  Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]  Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]  Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]  Immediate [#xx:8, #xx:16, or #xx:3 2]  Program-counter relative [@(d:8,PC) or @(d:16,PC)]  Memory indirect [@@aa:8]

• 16-Mbyte address space  Program: 16 Mbytes  Data: 16 Mbytes

• High-speed operation  All frequently-used instructions are executed in one or two states  8/16/32-bit register-register add/subtract: 1 state  8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)  16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)  16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)  32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)

CPUS211A_000020020100

Rev. 2.00, 05/03, page 21 of 820

• Two CPU operating modes  Normal mode*  Advanced mode

Note: * For this LSI, normal mode is not available.

• Power-down state  Transition to power-down state by SLEEP instruction  Selectable CPU clock speed

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• The number of execution states of the MULXU and MULXS instructions

Execution States

Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs, Rd 3 12

MULXU.W Rs, ERd 4 20

MULXS MULXS.B Rs, Rd 4 13

MULXS.W Rs, ERd 5 21

In addition, there are differences in address space, CCR and EXR register function s, p o wer-do wn modes, etc., depending on the model.

Rev. 2.00, 05/03, page 22 of 820

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.

• More general registers and control registers  Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been

added.

• Expanded address space  Normal mode supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Signed multiply and divide instructions have been add ed.  Two-bit shift and two-bit rotate instructions have been added.  Instructions for saving and restoring multiple r egisters have been added.  A test and set instruction has been added.

• Higher speed  Basic instructions are executed twice as fast.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.

• Additional control register  One 8-bit control register has been added.

• Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Two-bit shift and two-bit rotate instructions have been added.  Instructions for saving and restoring multiple r egisters have been added.  A test and set instruction has been added.

• Higher speed  Basic instructions are executed twice as fast.

Rev. 2.00, 05/03, page 23 of 820

2.2 CPU Operating Modes

The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins.

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode.

• Address spac e Linear access to a maximum address space of 64 kbytes is possible.

• Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers. When extended register En is used as a 16-bit register it can contain any value, even when the

corresponding general register (Rn) is used as an address register. (If general register Rn is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended register (En) will be affected.)

• Instruction set All instructions and addressing modes can be used. Only the lo wer 16 bits of effective

addresses (EA) are valid.

• Exception vector table and memory indirect branch addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One

branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode, the operand is a 16-bit (word) operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table.

• Stack structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,

condition-code register (CCR), and extended control register (EXR) are pushed onto th e stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling.

Note: For this LSI, normal mode is not availab le.

Rev. 2.00, 05/03, page 24 of 820

H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B

Reset exception vector

(Reserved for system use)

Exception vector 1

Exception vector 2

Exception vector table

Figure 2.1 Exception Vector Table (Normal Mode)

Notes:

1 When EXR is not used, it is not stored on the stack.

2 SP when EXR is not used.

3 lgnored when returning.

(16 bits)

(SP

)

(b) Exception Handling(a) Subroutine Branch

EXR*

Reserved*1*

CCR

CCR*

(16 bits)

Figure 2.2 Stack Structure in Normal Mode

2.2.2 Advanced Mode

• Address spac e Linear access to a maximum address space of 16 Mbytes is possible.

• Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the

upper 16-bit segments of 32-bit registers or address registers.

• Instruction set All instructions and addressing modes can be used.

Rev. 2.00, 05/03, page 25 of 820

• Exception vector table and memory indirect br anch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table

in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section 4, Exception Handling.

H'00000000

H'00000003

H'00000004

H'00000007

H'00000008

H'0000000B

H'0000000C

H'00000010

Reserved

Reset exception vector

Reserved

(Reserved for system use)

Exception vector table

(Reserved for system use)

Reserved

Exception vector 1

Figure 2.3 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area th at is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the top area of this range is also used for the exception vector table.

• Stack structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine

call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not pushed onto the stack in interrupt control mode 0. For d e tails, see section 4, Exception Handling.

Rev. 2.00, 05/03, page 26 of 820

Notes: *1 When EXR is not used, it is not stored on the stack.

*2 SP when EXR is not used. *3 Ignored when returning.

Reserved

(24 bits)

(a) Subroutine Branch (b) Exception Handling

(SP

Figure 2.4 Stack Structure in Advanced Mode

EXR*

)

Reserved*1*

CCR

(24 bits)

Rev. 2.00, 05/03, page 27 of 820

2.3 Address Space

Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.

H'0000

64 kbyte 16 Mbyte

H'FFFF

Note: * For this LSI, normal mode is not available.

H'00000000

H'00FFFFFF

H'FFFFFFFF

Figure 2.5 Memory Map

Program area

Data area

Not available in this LSI

(b) Advanced Mode(a) Normal Mode*

Rev. 2.00, 05/03, page 28 of 820

2.4 Register Configuration

The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).

General Registers (Rn) and Extended Registers (En)

15 0 7 0 7 0

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

Control Registers

23 0

Legend

:Stack pointer

:Program counter

:Extended control register

EXR

:Trace bit

:Interrupt mask bits

I2 to I0

:Condition-code register

CCR

:Interrupt mask bit

:User bit or interrupt mask bit*

Note: * For this LSI, the interrupt mask bit is not available.

Figure 2.6 CPU Internal Registers

H U N Z V C

76543210

T I2I1I0

EXR

----

76543210

CCR

IUIHUNZVC

:Half-carry flag :User bit :Negative flag :Zero flag :Overflow flag :Carry flag

Rev. 2.00, 05/03, page 29 of 820

2.4.1 General Registers

The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, prov iding a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers.

When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers.

The usage of each register can be selected independently.

General register ER7 has the function of th e stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack.

• Address registers

• 32-bit registers

ER registers

(ER0 to ER7)

Figure 2.7 Usage of General Registers

Rev. 2.00, 05/03, page 30 of 820

• 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

RH registers

(R0H to R7H)

R registers

(R0 to R7)

RL registers

(R0L to R7L)

Free area

SP (ER7)

Stack area

Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instructio n the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.)

2.4.3 Extended Control Register (EXR)

EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC instructions. When an instruction oth e r than STC is executed, all interrupts including NMI are masked in three states after the instruction is completed.

Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

When this bit is set to 1, trace exception processing starts every when an instruction is executed. When this bit is cleared to 0, instructions are consecutively executed.

6 to3– 1 – Reserved

These bits are always read as 1.

2 to 0 I2

I1 I0

1 R/W Interrupt Mask Bits 2 to 0

Specify interrupt request mask levels (0 to 7). For details, see section 5, Interrupt Controller.

Rev. 2.00, 05/03, page 31 of 820

2.4.4 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as bran ching conditions for conditional branch (Bcc) instructions.

Rev. 2.00, 05/03, page 32 of 820

Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller.

6 UI Undefined R/W User Bit or Interrupt Mask Bit

Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. For this LSI, Interrupt Mask Bit is not available.

5 H Undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.

4 U Undefined R/W User Bit

Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit of data as a sign bit.

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to indicate a carry

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Rev. 2.00, 05/03, page 33 of 820

2.4.5 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.

2.5 Data Formats

The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data formats of general registers.

Data Type Register Number Data Format

65432710

Don't care

1-bit data

RnH

1-bit data

4-bit BCD data

Byte data

RnL

RnH

RnL

RnH

RnL

Figure 2.9 General Register Data Formats (1)

Rev. 2.00, 05/03, page 34 of 820

Don't care

7043

Upper Lower

Don't care

MSB LSB

Don't care

65432710

Don't care

7043

Upper Lower

Don't care

MSB LSB

Data Type Data FormatRegister Number

Word data

15 0

MSB LSB

Longword data

31 16

MSB

ERn

En Rn

Legend

: General register ER

ERn

: General register E

: General register R

: General register RH

RnH

: General register RL

RnL

: Most significant bit

MSB

: Least significant bit

LSB

Figure 2.9 General Register Data Formats (2)

15 0

MSB LSB

15 0

LSB

Rev. 2.00, 05/03, page 35 of 820

2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fe tches.

When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size.

Data Type Address

1-bit data

Byte data

Word data

Longword data Address 2N

Address L

Address 2M

Address 2M+1

Address 2N+1

Address 2N+2

Address 2N+3

76 543210

MSB

Figure 2.10 Memory Data Formats

Data Format

LSB

Rev. 2.00, 05/03, page 36 of 820

2.6 Instruction Set

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1.

Table 2.1 Instruction Classification

Function Instructions Size Types

Data transfer

Arithmetic operations

Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

Branch BCC*2, JMP, BSR, JSR, RTS – 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,

Block data transfer EEPMOV – 1

Notes: B: Byte size; W: Word size; L: Longword size.

*1 POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-

SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP.

*2 BCC is the general name fo r conditional branch instructions. *3 Cannot be used in this LSI. *4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

MOV B/W/L 5 POP*1, PUSH*

W/L LDM, STM L MOVFPE*

, MOVTPE*

B ADD, SUB, CMP, NEG B/W/L 19 ADDX, SUBX, DAA, DAS B INC, DEC B/W/L ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W EXTU, EXTS W/L

TAS*

B/W/L 8 ROTXR

B14 BIAND, BOR, BIOR, BXOR, BIXOR

–9 NOP

Total: 65

Rev. 2.00, 05/03, page 37 of 820

2.6.1 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notation

Symbol Description

Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction

× Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR → Move ∼ NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Rev. 2.00, 05/03, page 38 of 820

Table 2.3 Data Transfer Instructions

Instruction Size* Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register

and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W

@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn → @-SP

Pushes a general register onto the stack. PUSH.W Rn is identical to

MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM L @SP+ → Rn (register list)

Pops two or more general registers from the stack. STM L Rn (register list) → @-SP

Pushes two or more general registers onto the stack. Note: *Size refers to the operand size.

B: Byte W: Word L: Longword

Rev. 2.00, 05/03, page 39 of 820

Table 2.4 Arithmetic Operations Instructions

Instruction Size*

ADD SUB

ADDX SUBX

Function

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.)

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register.

INC DEC

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Adds or subtracts the value 1 or 2 to or from data in a general register.

(Only the value 1 can be added to or subtracted from byte operands.) ADDS SUBS DAA DAS

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

B Rd (decimal adjust) → Rd

Decimal-adjusts an addition or subtraction result in a general register by

referring to CCR to produce 4-bit BCD data. MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers: either

8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general registers: either 8

bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16

bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →

16-bit quotient and 16-bit remainder.

Rev. 2.00, 05/03, page 40 of 820

Instruction Size*

Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of data in a general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.

TAS*

B @ERd – 0, 1 → (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

Notes: *1 Size refers to the operand size.

B: Byte W: Word L: Longword

*2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

Rev. 2.00, 05/03, page 41 of 820

Table 2.5 Logic Operations Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another

general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another

general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and

another general register or immediate data. NOT B/W/L ∼ Rd → Rd

Takes the one's complement (logical complement) of data in a general

B: Byte W: Word L: Longword

Table 2.6 Shift Instructions

Instruction Size* Function

SHAL SHAR

SHLL SHLR

ROTL ROTR ROTXL ROTXR

Note: * Size refers to the operand size.

Rev. 2.00, 05/03, page 42 of 820

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on data in a general register. 1-bit or 2 bit

shift is possible.

B/W/L Rd (shift) → Rd

Performs a logical shift on data in a general register. 1-bit or 2 bit shift is

possible.

B/W/L Rd (rotate) → Rd

Rotates data in a general register. 1-bit or 2 bit rotation is possible.

B/W/L Rd (rotate) → Rd

Rotates data including the carry flag in a general register. 1-bit or 2 bit

rotation is possible.

B: Byte W: Word L: Longword

Table 2.7 Bit Manipulation Instructions

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BTST B ∼ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specif ied by 3-bi t immediate data or the lower three bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

Logically ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

BIAND B C ∧ (<bit-No.> of <EAd>) → C

Logically ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit-No.> of <EAd>) → C

Logically ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

BIOR B C ∨ (∼ <bit-No.> of <EAd>) → C

Logically ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

Rev. 2.00, 05/03, page 43 of 820

Instruction Size* Function

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

BIXOR B C ⊕ ∼ (<bit-No.> of <EAd>) → C

Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to the carry flag.

BILD B ∼ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register or memory operand.

BIST B ∼ C → (<bit-No.>. of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3bit immediate data.

Note:* Size refers to the operand size.

B: Byte

Rev. 2.00, 05/03, page 44 of 820

Table 2.8 Branch Instructions

Instruction Size Function

Bcc – Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 BCC (BHS) Carry clear

(high or same) BCS (BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ⊕ V = 0 BLT Less than N ⊕ V = 1 BGT Greater than Z ∨ (N ⊕ V) = 0 BLE Less or equal Z ∨ (N ⊕ V) = 1

C = 0

JMP – Branches unconditionally to a specified address. BSR – Branches to a subroutine at a specified address. JSR – Branches to a subroutine at a specified address. RTS – Returns from a subroutine.

Rev. 2.00, 05/03, page 45 of 820

Table 2.9 System Control Instructions

Instruction Size* Function

TRAPA – Starts trap-instruction exception handling. RTE – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR

Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory operand. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with immediate data.

NOP – PC + 2 → PC

Only increments the program counter.

Note:* Size refers to the operand size.

B: Byte W: Word

Rev. 2.00, 05/03, page 46 of 820

Table 2.10 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B – if R4L ≠ 0 then

Repeat @ER5+ → @ER6+

R4L–1 → R4L

Until R4L = 0

else next:

EEPMOV.W – i f R4 ≠ 0 then

Repeat @ER5+ → @ER6+

R4–1 → R4

Until R4 = 0

else next: Transfers a data block. Starting from the address set in ER5, transfers

data for the number of bytes set in R4L or R4 to the address location set in ER6.

Execution of the next instruction begins as soon as the transfer is completed.

2.6.2 Basic Instruction Formats

The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc).

Figure 2.11 shows examples of instruction formats.

• Operation field Indicates the function of the instruction, the addressing mode, and the operation to be carried

out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields.

• Register field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3

bits or 4 bits. Some instructions have two register fields, and some have no register field.

• Effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition field Specifies the branching condition of Bcc instructions.

Rev. 2.00, 05/03, page 47 of 820

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16, etc.

rn rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

Figure 2.11 Instruction Formats (Examples)

2.7 Addressing Modes and Effective Address Calculation

The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes.

Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8

Rev. 2.00, 05/03, page 48 of 820

@ERn+ @–ERn

Renesas H8S/2368 Series, H8S Series, H8S/2300 Series Hardware Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Cautions

General Precautions on Handling of Product

Configuration of This Manual

Preface

Main Revisions and Additions in this Edition

Contents

Figures

Tables

Section 1 Overview

1.1 Features

1.2 Block Diagram

1.3 Pin Description

1.3.1 Pin Arrangement

1.3.2 Pin Arrangement in Each Operating Mode

1.3.3 Pin Functions

Section 2 CPU

2.1 Features

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

2.1.2 Differences from H8/300 CPU

2.1.3 Differences from H8/300H CPU

2.2 CPU Operating Modes

2.2.1 Normal Mode

2.2.2 Advanced Mode

2.3 Address Space

2.4 Register Configuration

2.4.1 General Registers

2.4.2 Program Counter (PC)

2.4.3 Extended Control Register (EXR)

2.4.4 Condition-Code Register (CCR)

2.4.5 Initial Register Values

2.5 Data Formats

2.5.1 General Register Data Formats

2.5.2 Memory Data Formats

2.6 Instruction Set

2.6.1 Table of Instructions Classified by Function

2.6.2 Basic Instruction Formats

2.7 Addressing Modes and Effective Address Calculation