RENESAS H8S-2368F-ZTAT User Manual

REJ09B0050-0300O

The revision list can be viewed directly by clicking the title page.

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

H8S/2368 Group, H8S/2368F-ZTAT™

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family/H8S/2300 Series

Rev. 3.00 Revision Date: July 07, 2004

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Rev. 3.00, 07/04, page ii of l

General Precautions on Handling of Product

1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Trea t ment of Unused Input Pins Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.

3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.

Rev. 3.00, 07/04, page iii of l

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descr i ptions given, and usage notes are give n, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for r e vised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see t he actual locations in this manual.

11.Index

Rev. 3.00, 07/04, page iv of l

Preface

The H8S/2368 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas Technology’s original architecture as their cores, and the peripheral functions required to configure a system.

The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a 16-Mbyte linear address space.

This LSI is equipped with direct memory access controller (DMAC) and data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), 8-bit timers (TMR), a watchdog timer ( WDT), serial communication interfaces (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as onchip peripheral modules required for system configuration. I included as an optional interface.

A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM and other ki nds of memor y.

A single-p o wer fla s h me mo r y (F -ZTAT) version is available for this LSI's ROM. This provides flexibility as it can be reprogrammed in no time to cope with all situation s from the early stages of mass production to full-scale mass production. This is particularly app licable to application devices with specifications that will most probably change.

C bus interface 2 (IIC2) can also be

Note: F-ZTAT is a trademark of Renesas Technology Corp.

Target Users: This manual was written for users who will be using the H8S/2368 Group in the

design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2368 Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction se t.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.

Rev. 3.00, 07/04, page v of l

• In order to understand the details o f the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual. For the execution state of each instruction in this LSI, see Appendix D, Bus State during Execution of Instructions.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 23, List of Register s.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel

number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require. http://www.renesas.com/

H8S/2368 Group manuals:

Manual Title ADE No.

H8S/2368 Group, H8S/2368F-ZTAT™ Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

User's manuals for development tools:

Manual Title ADE No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual

H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-282 H8S, H8/300 Series High-Performance Embedded Workshop, HDI Tutorial ADE-702-231 High-Performance Embedded Workshop User's Manual ADE-702-201

Rev. 3.00, 07/04, page vi of l

ADE-702-247

Main Revisions for this Edition

Item Page Revisions (See Manual for Details)

1.1 Features 1 • On-chip memory Lineup added

ROM Type Model ROM RAM Remarks

Flash memory version HD64F2368 512 kbytes 32 kbytes

HD64F2367 384 kbytes 24 kbytes HD64F2366 384 kbytes 30 kbytes

2 • Compact package

Note *2 added

QFP-128 Note: 2. Not supported by the HD64F2368.

1.2 Block Diagram 3 Description amended Figures 1.1, 1.2

diagrams of this LSI.

Figure 1.3 Internal Block

5 Figure 1.3 added

Diagram of H8S/2368

1.3.1 Pin Arrangement 6 Description amended Figures

LSI.

Figure 1.6 Pin Arrangement

8 Figure 1.6 added

of H8S/2368 Figure 1.7 Pin Arrangement

of H8S/2367, H8S/2365, and H8S/2363

Figure 1.8 Pin Arrangement

9 Note added

Note:

of H8S/2366

1.3.2 Pin Arrangement in

Each Operating Mode Table 1.1 Pin Arrangement in

Each Operating Mode

11 to 15 Note *1 added

QFP-128

12 Name of pin 33 amended, note *2 added

(Before) V

Notes: 1. Not supported by the H8S/2368.

, and 1.3 show the internal block

1.4 to 1.8 show the pin arrangements of this

FP-128B is not supported by the HD64F2368.

→ (After) VCC (V

)

2. Used as the VCL pin in the H8S/2368.

Rev. 3.00, 07/04, page vii of l

Item Page Revisions (See Manual for Details)

1.3.3 Pin Functions Table 1.2 Pin Functions

16 to 21 Note *1 added

QFP-128

Note: 1. Not supported by the H8S/2368.

16 VCC Function amended

Pin No.

6,39,66, 91,92

I/O Function

Input Power supply pins. VCC pins

Type Symbol TFP-120 QFP-128

Power V

2,33,60,

83,84

should be connected to the system power supply. The pin 33 of TFP-120, which is used as the VCL pin, should not be connected to the power supply. The pin should be connected to VSS via 0.1-µF (recommended value) capacitor (placed close to the pins).

3.1 Operating Mode Selection

Mode Selection

59 Description amended

This LSI has

six operating modes (modes 1 to 5 and 7). Modes 1 to 5 and 7 are available in the H8S/2368 flash memory version. Modes 1 to 4 and 7 are available in the H8S/2367. Modes 1, 2, 4, and 7 are available in ... at the beginning of a program execution. Modes 3

and 5 are a boot mode/user boot mod e in which the flash memory can be programmed or erased. For details on the boot mode/user boot mode, refer to section 19, Flash Memory ( or section 20, Flash Memory (0.18-µm F-ZTAT Version).

Table 3.1 amended, note * addedTable 3.1 MCU Operating

MCU Operating Mode MD2 MD1 MD0

4 1 0 0 Advanced Expanded

5* 1 0 1 Advanced User boot

7 1 1 1 Advanced

Note: * Supported only by the H8S/2368.

0.35-µm F-ZTAT Version),

CPU Operating Mode Description

mode with onchip ROM enabled

mode Single-chip

mode

External Data Bus

On-Chip

Initial

ROM

Width

Enabled 8 bits

Enabled —

Max. Value

16 bits

Rev. 3.00, 07/04, page viii of l

Item Page Revisions (See Manual for Details)

3.3.5 Mode 5 63 Item added

3.3.7 Pin Functions Table 3.2 Pin Functions in

Each Operating Mode

64 Table 3.2 amended, note *3 added

Port

Port A

PA7 to PA5 P

PA4 to PA0 Port B P Port C P Port D D P Port E P Port F

PF7, PF6 P/C

PF5, PF4 C

PF3 P/C

PF2 to PF0 P Port G

PG6 to PG1 P

PG0 P

Mode 4

/A P

/D P

Mode 5

Note: 3.Mode 5 is available only in the H8S/2368.

3.4 Memory Map in Each

65, 66 Figures 3.1, 3.2 added

Operating Mode Figure 3.1 H8S/2368 Memory

Map (1) Figure 3.2 H8S/2368 Memory

Map (2)

6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)

124 • CSACRL

Description amended

Bit Bit Name Initial Value R/W Description

CSXT7

CSXT6

CSXT5

CSXT4

CSXT3

CSXT2

CSXT1

CSXT0

0 0 0 0 0 0 0 0

R/W

CS and Address Signal

R/W

Assertion Period Control 2

R/W

These bits specify whether or

R/W

not the T

R/W

6.3 is to be inserted. When an

R/W

area for which the CSXTn bit is

R/W

set to 1 is accessed, a one-

R/W

state T CSn and address signals are asserted, is inserted normal access cycle.

2 *3

Mode 7

/A P

/D P

/C P

cycle shown in figure

cycle, in which only the

after th e

Rev. 3.00, 07/04, page ix of l

Item Page Revisions (See Manual for Details)

14.3.9 Bit Rate Register (BRR)

Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode)

Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)

Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)

Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)

Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372)

Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372)

14.3.11 Serial Extension Mode Register (SEMR)

14.8 IrDA Operation Table 14.12 Settings of Bits

IrCKS2 to IrCKS0

14.10.3 Mark State and Break Sending

Section 15 I2C Bus Interface2 (IIC2) (Option)

536 Values when operating frequency φ is 34 MHz added,

note * added Note: * Supported only by the H8S/2368.

537

538

539

540

541

542

545 Bits 2 to 0 description amended

Asynchronous clock source selection (valid when = 1 in asynchronous mode)

585 High Pulse Width Selection

Values when operating frequency φ 34MHz added, note * added

Note: * Supported only by the H8S/2368.

589 Description amended

(Before) (After) PCR → PDR →

595 Description amended

2. For the F-ZTAT version, model names do not depend on optional functions. When using optional functions, conta ct the Renesa s Technology sales office.

DDR DR

ROMless version, product

CKE1

Rev. 3.00, 07/04, page x of l

Item Page Revisions (See Manual for Details)

15.3.1 I2C Bus Control Register A (ICCRA)

599 Bits 5, 4 and bits 3 to 0 description amended

Initial

Bit Bit Name

54MST

TRS00

CKS3

CKS2

CKS1

CKS0

Value

0 0 0 0

R/W Description

R/W

Master/Slave Select

R/W

Transmit/Receive Select When arbitration is lost in master mode, MST

and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. In addition, TRS is set to 1 automatically in slave receive mode when the seventh bit of the start condition matches the slave address set in SAR and the eighth bit is set to 1.

Operating modes are described below according to MST and TRS combination.

00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode

Transfer clock select 3 to 0

R/W R/W

In master mode, these bits should be set

R/W

according to the necessary transfer rate. In

R/W

slave mode, they are used to secure the data setup time in transmit mode. The data setup time is 10 tcyc when CKS3 is cleared to 0; 20 tcyc when CKS3 is set to 1.

Table 15.2 Transfer Rate 600 Table 15.2 amended, notes *1 to *3 added

Bit3 Bit2 Bit1 Bit0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock φ=8MHz φ=10MHz φ=20MHz φ=25MHz φ=33MHz φ=34MHz

0 φ/28 286kHz 357kHz 714kHz

1 φ/40 200kHz 250kHz 500kHz 0 φ/48 167kHz 208kHz 417kHz

1 φ/64 125kHz 156kHz 313kHz 0 φ/168 47.6kHz 59.5kHz 119kHz 149kHz 196kHz 202kHz0

1 φ/100 80.0kHz 100kHz 200kHz 250kHz 330kHz 340kHz 0 φ/112 71.4kHz 89.3kHz 179kHz 223kHz 295kHz 304kHz

1 φ/128 62.5kHz 78.1kHz 156kHz 195kHz 258kHz 266kHz 0 φ/56 143kHz 179kHz 357kHz 446kHz

1 φ/80 100kHz 125kHz 250kHz 313kHz 413kHz

0 φ/96 83.3kHz 104kHz 208kHz 260kHz 344kHz 354kHz 1 φ/128 62.5kHz 78.1kHz 156kHz 195kHz 258kHz 266kHz

0 φ/336 23.8kHz 29.8kHz 59.5kHz 74.4kHz 98.2kHz 101kHz0 1 φ/200 40.0kHz 50.0kHz 100kHz 125kHz 165kHz 170kHz

0 φ/224 35.7kHz 44.6kHz 89.3kHz 112kHz 147kHz 152kHz 1 φ/256 31.3kHz 39.1kHz 78.1kHz 97.7kHz 129kHz 133kHz

Notes: 1. Supported only by the H8S/2368.

2. Does not conform to the I2C bus interface specification (normal mode: max. 100 kHz, highspeed mode: max. 400 kHz).

3. If CKS3 and CKS2 are both cleared to 0 (7.5 tcyc bit synchronization) and the operating frequency is 20 MHz or greater, it may not be possible to maintain the prescribed transfer rate under certain load conditions. Therefore, a bit synchronization setting other than 7.5 tcyc should be used if the operating frequency exceeds 20 MHz.

*2* *2* *2*

2 2 2 2

589kHz

607kHz

425kHz

Rev. 3.00, 07/04, page xi of l

Item Page Revisions (See Manual for Details)

15.3.3 I (ICMR)

C Bus Mode Register

602 Description amended

ICMR performs master mode wait control and selects the transfer bit count.

605 Bit 7, and bit 4 description amended15.3.5 I2C Bus Status

Bit Bit Name

7 TDRE 0 R/W Transmit Data Register Empty

4 NACKF 0 R/W No acknowledge detection flag

Initial Value R/W Description

[Setting conditions]

• When data is transferred from ICDRT to ICDRS and ICDRT becomes empty

• When TRS is set

• When a start condition (including retransmission) is issued

• When a transition from receive mode to transmit mode is made in slave mode

[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When data is written to ICDRT

[Setting condition] When no acknowledge is detected from the

receive device in transmission while the ACKE bit in ICIER is 1

[Clearing condition] When 0 is written in NACKF after reading

NACKF = 1 Note: When NACKF = 1 is detected, NACKF

must be cleared to 0. Subsequent transmission in not made until NACKF is cleared to 0.

15.3.7 I2C Bus Transmit Data Register (ICDRT)

15.3.8 I2C Bus Receive Data Register (ICDRR)

15.4.4 Slave Transmit Operation

Figure 15.10 Slave Transmit Mode Operation Timing 2

Rev. 3.00, 07/04, page xii of l

607 Description added

If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.

The initial value of ICDRT is H'FF.

607 Description added

ICDRR is a receive-only register, therefore the CPU cannot be written to this register. The initial value of ICDRR is H'FF.

615 Figure 15.10.amended

SDA

(master output)

Item Page Revisions (See Manual for Details)

15.4.5 Slave Receive Operation

615 Description amended

3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before

reading ICDRR, to be returned to the master device, is reflected to the next transmit frame.

Figure 15.12 Slave Receive

616 Figure 15.12 amended

Mode Operation Timing 2

SDA

(slave output)

15.4.7 Example of Use Figure 15.15 Sample

Flowchart for Master Receive Mode

619 Note *, additional information added

Note: * Prevent any interrupts while steps [1] to [3] are executed.

Additional information: When receiving one-byte data, execute step [1], and then step [7] omitting steps [2] to [6]. In step [8], dummy read ICDRR.

Figure 15.17 Sample Flowchart for Slave Receive Mode

621 Additional information added

Additional information: When receiving one-byte data, execute step [1], and then step [7] omitting steps [2] to [6]. In step [8], dummy read ICDRR.

15.5 Interrupt Request 622 Description added When interrupt conditions described in table 15.3 are 1

and the CPU is ready to receive interrupts, an interrupt execution handling is executed. Clear each interrupt source during an interrupt execution handling. Note that TDRE and TEND are automatically cleared by writing the transmit data to ICDRT, and RDRF is automatically cleared by reading ICDRR. When the transmit data is written to ICDR, TDRE is set again simultaneously. When TDRE is cleared, extra one byte of data may be transmitted.

15.6 Bit Synchronous Circuit

Table 15.4 Time for monitoring SCL

623 Note * added

Note * If the operating frequency exceeds 20 MHz, it may not be possible to maintain the prescribed transfer rate under certain load conditions. A setting other than

7.5 tcyc should therefore be used.

Section 18 RAM 649 Lineup added

Product Type Name ROM Type

H8S/2368 Group

HD64F2368 Flash memory

HD64F2367 24 kbytes H'FF6000 to

HD64F2366 30 kbytes H'FF4800 to

version

RAM Capacitance RAM Address

32 kbytes H'FF4000 to

H'FFBFFF

Rev. 3.00, 07/04, page xiii of l

Item Page Revisions (See Manual for Details)

Section 19 Flash Memory (0.35-µm F-ZTAT Version)

19.5.5 RAM Emulation Register (RAMER)

19.7 Flash Memory Emulation in RAM

Section 20 Flash Memory (0.18-µm F-ZTAT Version)

22.2.1 Connecting a Crystal Oscillator

Figure 22.2 Connection of Crystal Oscillator (Example)

23.2.3 Software Standby Mode

Table 23.2 Oscillation Stabilization Time Settings

23.2.4 Hardware Standby Mode

651 Section title amended

662 Note amended

Note: This function is not supported by the H8S/2367, or H8S/2366.

668 Note amended

Note: This function is not supported by the H8S/2367, or H8S/2366.

679 to 764 Section added

770 Note * added

Note: * In the H8S/2368, CL1 = CL2 = 10 pF.

784 φ [MHz]34 added, note *2 added

2. Supported only by the H8S/2368.

Note:

786 Hardware Standby Mode Timing when Power Is

Supplied (Only H8S/2368) added

H8S/2368,

Rev. 3.00, 07/04, page xiv of l

Item Page Revisions (See Manual for Details)

24.1 Register Addresses

(Address Order)

800, 801 Table amended, notes *4, *5 added

Flash code control status register

Flash program code select register

Flash erase code select register

Flash memory control register 1

Flash key code register

Flash memory control register 2

Flash MAT select register

Flash transfer destination address register

Erase block register 1 EBR1 8 H'FFCA FLASH 8 2 Erase block register 2 EBR2 8 H'FFCB FLASH 8 2 Flash vector address

control register

Abbreviation Bit No. Address Module

FCCS

FPCS

FECS

8 H'FFC4

8 H'FFC5

8 H'FFC6

FLMCR1 8 H'FFC8 FLASH 8 2

FKEY

8 H'FFC8 FLASH 8 2

FLMCR2 8 H'FFC9 FLASH 8 2

FMATS

FTDAR

FVACR

8 H'FFC9 FLASH 8 2

8 H'FFCA FLASH 8 2

8 H'FFCB FLASH 8 2

Notes: 4. Supported only by the H8S/2368.

5. Cannot be acces sed by other than H8S/2368.

24.2 Register Bits 812, 814 Item FLASH amended, note *8 added

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

FCCS

— — — FLER — — — SCO FLASH

FPCS

— — — PPVD — — — PPVS

FECS

— — — — — — — EPVB

FLMCR1 — SWE ESU PSU EV PV E P

FKEY

K7 K6 K5 K4 K3 K2 K1 K0

FLMCR2 FLER — — — — — — —

FMATS

MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0

FTDAR

TDER TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 EBR2 — — EB13 EB12 EB11 EB10 EB9 EB8

FVACR

FVCHGE — — — FVSEL3 FVSEL2 FVSEL1 FVSEL0

Data

Width

FLASH 8 2

Access States

Note: 8. Supported only by the H8S/2368.

Rev. 3.00, 07/04, page xv of l

Item Page Revisions (See Manual for Details)

24.3 Register States in Each Operating Mode

823, 824 Item FLASH amended, note *2 added

All

FCCS

FPCS

FECS FLMCR1 Initialized — — — — — — Initialized

FKEY FLMCR2 Initialized — — — — — — Initialized

FMATS

FTDAR EBR1 Initialized — — — — — — Initialized EBR2 Initialized — — — — — — Initialized

FVACR

High-

Clock

Speed

Division Sleep

Initialized — — — — — — Initialized FLASH Initialized — — — — — — Initialized Initialized — — — — — — Initialized

Initialized — — — — — — Initialized

Initialized — — — — — — Initialized Initialized — — — — — — Initialized

Initialized — — — — — — Initialized

Module Stop

Module Clock Stop

Software Standby

Note: 2. Supported only by the H8S/2368.

25.2 Electrical Characteristics of

0.35 µm

861 Item title amended

F-ZTAT Version

25.2.2 DC Characteristics Table 25.16 Permissible

Output Currents

25.3 Electrical

864 Table 25.16 amended

Item Symbol Min Typ Max Unit

Permissible output low current (per pin)

SCL0 toSCL1, SDA0to SDA1 — — 10.0 All outputpins

875 to 888 Item added

——2.0

Characteristics for 0.18 µm F-ZTAT Version

Appendix B. Product Lineup 898 Lineup added, note amended, *1 added

Product Type Name

H8S/2368

F-ZTAT

HD64F2368 HD64F2368

version

H8S/2367 F-ZTAT

HD64F2367 HD64F2367

version

H8S/2366

F-ZTAT

HD64F2366 HD64F2366

version

H8S/2365 Masked

HD6432365 HD6432365 ROM version

H8S/2363

ROMless

HD6412363 HD6412363 version

Model Marking Package (Code)

Notes: When using the optional functions for the F-

ZTAT version,

ROMless version, which has the common type name, contact a Renesas Sales office.

1. Supported only by the H8S/2368.

Hardware Standby Module

120-pin TFP (TFP-120, TFP-120V

128-pin

QFP (FP-128B, FP-128BV

)

Rev. 3.00, 07/04, page xvi of l

Section 1 Overview............................................................................................................. 1

1.1 Features............................................................................................................................. 1

1.2 Block Diagram.................................................................................................................. 3

1.3 Pin Description.................................................................................................................. 6

1.3.1 Pin Arrangement.................................................................................................. 6

1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 11

1.3.3 Pin Functions ....................................................................................................... 16

Section 2 CPU...................................................................................................................... 23

2.1 Features............................................................................................................................. 23

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 24

2.1.2 Differences from H8/300 CPU ............................................................................ 25

2.1.3 Differences from H8/300H CPU.......................................................................... 25

2.2 CPU Operating Modes...................................................................................................... 26

2.2.1 Normal Mode....................................................................................................... 26

2.2.2 Advanced Mode................................................................................................... 27

2.3 Address Space................................................................................................................... 30

2.4 Register Configuration...................................................................................................... 31

2.4.1 General Registers................................................................................................. 32

2.4.2 Program Counter (PC) ......................................................................................... 33

2.4.3 Extended Control Register (EXR) ....................................................................... 33

2.4.4 Condition-Code Register (CCR).......................................................................... 34

2.4.5 Initial Register Values.......................................................................................... 36

2.5 Data Formats..................................................................................................................... 36

2.5.1 General Register Data Formats............................................................................ 36

2.5.2 Memory Data Formats......................................................................................... 38

2.6 Instruction Set................................................................................................................... 39

2.6.1 Table of Instructions Classified by Function....................................................... 40

2.6.2 Basic Instruction Formats .................................................................................... 49

2.7 Addressing Modes and Effective Address Calculation..................................................... 50

2.7.1 Register Direct—Rn............................................................................................. 51

2.7.2 Register Indirect—@ERn.................................................................................... 51

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 51

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.. 51

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 51

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 52

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC).................................... 52

2.7.8 Memory Indirect—@@aa:8 ................................................................................ 52

2.7.9 Effective Address Calculation.............................................................................. 53

Rev. 3.00, 07/04, page xvii of l

2.8 Processing States............................................................................................................... 56

2.9 Usage Note........................................................................................................................ 57

2.9.1 Note on Bit Manipulation Instructions................................................................. 57

Section 3 MCU Operating Modes.................................................................................. 59

3.1 Operating Mode Selection ................................................................................................ 59

3.2 Register Descriptions........................................................................................................60

3.2.1 Mode Control Register (MDCR)......................................................................... 60

3.2.2 System Control Register (SYSCR)...................................................................... 60

3.3 Operating Mode Descriptions........................................................................................... 62

3.3.1 Mode 1................................................................................................................. 62

3.3.2 Mode 2................................................................................................................. 62

3.3.3 Mode 3................................................................................................................. 62

3.3.4 Mode 4................................................................................................................. 62

3.3.5 Mode 5................................................................................................................. 63

3.3.6 Mode 7................................................................................................................. 63

3.3.7 Pin Functions ....................................................................................................... 64

3.4 Memory Map in Each Operating Mode............................................................................ 65

Section 4 Exception Handling......................................................................................... 75

4.1 Exception Handling Types and Priority ............................................................................ 75

4.2 Exception Sources and Exception Vector Table............................................................... 75

4.3 Reset.................................................................................................................................. 77

4.3.1 Reset Exception Handling.................................................................................... 77

4.3.2 Interrupts after Reset............................................................................................ 79

4.3.3 On-Chip Peripheral Functions after Reset Release.............................................. 79

4.4 Traces................................................................................................................................ 80

4.5 Interrupts........................................................................................................................... 80

4.6 Trap Instruction................................................................................................................. 81

4.7 Stack Status after Exception Handling.............................................................................. 82

4.8 Usage Notes...................................................................................................................... 83

Section 5 Interrupt Controller.......................................................................................... 85

5.1 Features............................................................................................................................. 85

5.2 Input/Output Pins.............................................................................................................. 87

5.3 Register Descriptions........................................................................................................87

5.3.1 Interrupt Control Register (INTCR) .................................................................... 88

5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 88

5.3.3 IRQ Enable Register (IER).................................................................................. 90

5.3.4 IRQ Sense Control Register L (ISCRL)............................................................... 91

5.3.5 IRQ Status Register (ISR).................................................................................... 94

5.3.6 IRQ Pin Select Register (ITSR)........................................................................... 95

5.3.7 Software Standby Release IRQ Enable Register (SSIER)................................... 96

Rev. 3.00, 07/04, page xviii of l

5.4 Interrupt Sources............................................................................................................... 96

5.4.1 External Interrupts ............................................................................................... 96

5.4.2 Internal Interrupts................................................................................................. 97

5.5 Interrupt Exception Handling Vector Table...................................................................... 98

5.6 Interrupt Control Modes and Interrupt Operation............................................................. 103

5.6.1 Interrupt Control Mode 0..................................................................................... 103

5.6.2 Interrupt Control Mode 2..................................................................................... 105

5.6.3 Interrupt Exception Handling Sequence .............................................................. 106

5.6.4 Interrupt Response Times.................................................................................... 108

5.6.5 DTC and DMAC* Activation by Interrupt.......................................................... 109

5.7 Usage Notes...................................................................................................................... 109

5.7.1 Contention between Interrupt Generation and Disabling..................................... 109

5.7.2 Instructions that Disable Interrupts...................................................................... 110

5.7.3 Times when Interrupts are Disabled .................................................................... 110

5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 110

5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ............................................. 111

5.7.6 Note on IRQ Status Register (ISR)...................................................................... 111

Section 6 Bus Controller (BSC)...................................................................................... 113

6.1 Features............................................................................................................................. 113

6.2 Input/Output Pins.............................................................................................................. 115

6.3 Register Descriptions........................................................................................................ 116

6.3.1 Bus Width Control Register (ABWCR)............................................................... 117

6.3.2 Access State Control Register (ASTCR) ............................................................. 117

6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL,

WTCRBH, and WTCRBL).................................................................................. 118

6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................ 123

6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 124

6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)

Area 1 Burst ROM Interface Control Register (BROMCRL).............................. 126

6.3.7 Bus Control Register (BCR)................................................................................ 127

6.3.8 DRAM Control Register (DRAMCR)................................................................. 129

6.3.9 DRAM Access Control Register (DRACCR)...................................................... 134

6.3.10 Refresh Control Register (REFCR) ..................................................................... 135

6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 138

6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... 138

6.4 Operation........................................................................................................................... 138

6.4.1 Area Division....................................................................................................... 138

6.4.2 Bus Specifications................................................................................................ 140

6.4.3 Memory Interfaces............................................................................................... 142

6.4.4 Chip Select Signals .............................................................................................. 143

6.5 Basic Bus Interface ........................................................................................................... 144

6.5.1 Data Size and Data Alignment............................................................................. 144

Rev. 3.00, 07/04, page xix of l

6.5.2 Valid Strobes ....................................................................................................... 145

6.5.3 Basic Timing........................................................................................................ 146

6.5.4 Wait Control ........................................................................................................ 154

6.5.5 Read Strobe (RD) Timing.................................................................................... 155

6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. 156

6.6 DRAM Interface ............................................................................................................... 158

6.6.1 Setting DRAM Space........................................................................................... 158

6.6.2 Address Multiplexing........................................................................................... 158

6.6.3 Data Bus............................................................................................................... 159

6.6.4 Pins Used for DRAM Interface............................................................................ 160

6.6.5 Basic Timing........................................................................................................ 161

6.6.6 Column Address Output Cycle Control............................................................... 162

6.6.7 Row Address Output State Control...................................................................... 162

6.6.8 Precharge State Control ....................................................................................... 165

6.6.9 Wait Control ........................................................................................................ 166

6.6.10 Byte Access Control ............................................................................................ 169

6.6.11 Burst Operation .................................................................................................... 170

6.6.12 Refresh Control.................................................................................................... 174

6.6.13 DMAC Single Address Transfer Mode and DRAM Interface............................. 179

6.7 Burst ROM Interface......................................................................................................... 182

6.7.1 Basic Timing........................................................................................................ 182

6.7.2 Wait Control ........................................................................................................ 184

6.7.3 Write Access........................................................................................................ 184

6.8 Idle Cycle.......................................................................................................................... 185

6.8.1 Operation ............................................................................................................. 185

6.8.2 Pin States in Idle Cycle........................................................................................ 195

6.9 Write Data Buffer Function .............................................................................................. 195

6.10 Bus Release....................................................................................................................... 196

6.10.1 Operation ............................................................................................................. 196

6.10.2 Pin States in External Bus Released State............................................................ 198

6.10.3 Transition Timing ................................................................................................ 199

6.11 Bus Arbitration.................................................................................................................. 200

6.11.1 Operation ............................................................................................................. 200

6.11.2 Bus Transfer Timing............................................................................................ 201

6.12 Bus Controller Operation in Reset.................................................................................... 202

6.13 Usage Notes...................................................................................................................... 202

6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 202

6.13.2 External Bus Release Function and Software Standby........................................ 202

6.13.3 External Bus Release Function and CBR Refreshing.......................................... 202

6.13.4 BREQO Output Timing....................................................................................... 203

Section 7 DMA Controller (DMAC)............................................................................. 205

7.1 Features............................................................................................................................. 205

Rev. 3.00, 07/04, page xx of l

7.2 Input/Output Pins.............................................................................................................. 207

7.3 Register Descriptions........................................................................................................ 207

7.3.1 Memory Address Registers (MARA and MARB)............................................... 208

7.3.2 I/O Address Registers (IOARA and IOARB)...................................................... 209

7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) .................................. 209

7.3.4 DMA Control Registers (DMACRA and DMACRB)......................................... 210

7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)............. 217

7.3.6 DMA Write Enable Register (DMAWER).......................................................... 229

7.3.7 DMA Terminal Control Register (DMATCR)..................................................... 231

7.4 Activation Sources............................................................................................................ 232

7.4.1 Activation by Internal Interrupt Request.............................................................. 232

7.4.2 Activation by External Request ........................................................................... 233

7.4.3 Activation by Auto-Request................................................................................. 233

7.5 Operation........................................................................................................................... 234

7.5.1 Transfer Modes.................................................................................................... 234

7.5.2 Sequential Mode .................................................................................................. 236

7.5.3 Idle Mode............................................................................................................. 238

7.5.4 Repeat Mode........................................................................................................ 240

7.5.5 Single Address Mode........................................................................................... 243

7.5.6 Normal Mode....................................................................................................... 246

7.5.7 Block Transfer Mode........................................................................................... 249

7.5.8 Basic Bus Cycles.................................................................................................. 255

7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles............................................... 255

7.5.10 DMA Transfer (Single Address Mode) Bus Cycles............................................. 263

7.5.11 Write Data Buffer Function ................................................................................. 269

7.5.12 Multi-Channel Operation..................................................................................... 270

7.5.13 Relation between DMAC and External Bus Requests and Refresh Cycles......... 271

7.5.14 DMAC and NMI Interrupts.................................................................................. 272

7.5.15 Forced Termination of DMAC Operation............................................................ 272

7.5.16 Clearing Full Address Mode................................................................................ 273

7.6 Interrupt Sources............................................................................................................... 274

7.7 Usage Notes...................................................................................................................... 275

7.7.1 DMAC Register Access during Operation........................................................... 275

7.7.2 Module Stop......................................................................................................... 277

7.7.3 Write Data Buffer Function ................................................................................. 277

7.7.4 TEND Output....................................................................................................... 277

7.7.5 Activation by Falling Edge on DREQ Pin........................................................... 278

7.7.6 Activation Source Acceptance............................................................................. 279

7.7.7 Internal Interrupt after End of Transfer................................................................ 279

7.7.8 Channel Re-Setting.............................................................................................. 279

Section 8 Data Transfer Controller (DTC)................................................................... 281

8.1 Features............................................................................................................................. 281

Rev. 3.00, 07/04, page xxi of l

8.2 Register Descriptions........................................................................................................ 282

8.2.1 DTC Mode Register A (MRA)............................................................................ 283

8.2.2 DTC Mode Register B (MRB)............................................................................. 284

8.2.3 DTC Source Address Register (SAR).................................................................. 284

8.2.4 DTC Destination Address Register (DAR).......................................................... 284

8.2.5 DTC Transfer Count Register A (CRA).............................................................. 284

8.2.6 DTC Transfer Count Register B (CRB)............................................................... 285

8.2.7 DTC Enable Registers A to G (DTCERA to DTCERG)..................................... 285

8.2.8 DTC Vector Register (DTVECR)........................................................................ 285

8.3 Activation Sources............................................................................................................ 286

8.4 Location of Register Information and DTC Vector Table................................................ 287

8.5 Operation .......................................................................................................................... 290

8.5.1 Normal Mode....................................................................................................... 292

8.5.2 Repeat Mode........................................................................................................ 293

8.5.3 Block Transfer Mode........................................................................................... 294

8.5.4 Chain Transfer ..................................................................................................... 295

8.5.5 Interrupts.............................................................................................................. 296

8.5.6 Operation Timing................................................................................................. 297

8.5.7 Number of DTC Execution States ....................................................................... 298

8.6 Procedures for Using DTC................................................................................................ 299

8.6.1 Activation by Interrupt......................................................................................... 299

8.6.2 Activation by Software........................................................................................ 299

8.7 Examples of Use of the DTC............................................................................................ 299

8.7.1 Normal Mode....................................................................................................... 299

8.7.2 Chain Transfer ..................................................................................................... 300

8.7.3 Chain Transfer when Counter = 0........................................................................ 301

8.7.4 Software Activation............................................................................................. 302

8.8 Usage Notes...................................................................................................................... 303

8.8.1 Module Stop Mode Setting.................................................................................. 303

8.8.2 On-Chip RAM ..................................................................................................... 303

8.8.3 DTCE Bit Setting................................................................................................. 303

8.8.4 DMAC Transfer End Interrupt............................................................................. 303

8.8.5 Chain Transfer ..................................................................................................... 303

Section 9 I/O Ports.............................................................................................................. 305

9.1 Port 1................................................................................................................................. 309

9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 309

9.1.2 Port 1 Data Register (P1DR)................................................................................ 310

9.1.3 Port 1 Register (PORT1)...................................................................................... 310

9.1.4 Pin Functions ....................................................................................................... 311

9.2 Port 2................................................................................................................................. 319

9.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 319

9.2.2 Port 2 Data Register (P2DR)................................................................................ 319

Rev. 3.00, 07/04, page xxii of l

9.2.3 Port 2 Register (PORT2)...................................................................................... 320

9.2.4 Pin Functions ....................................................................................................... 321

9.3 Port 3................................................................................................................................. 329

9.3.1 Port 3 Data Direction Register (P3DDR) ............................................................. 329

9.3.2 Port 3 Data Register (P3DR)................................................................................ 330

9.3.3 Port 3 Register (PORT3)...................................................................................... 330

9.3.4 Port 3 Open Drain Control Register (P3ODR)..................................................... 331

9.3.5 Port Function Control Register 2 (PFCR2).......................................................... 332

9.3.6 Pin Functions ....................................................................................................... 333

9.4 Port 4................................................................................................................................. 336

9.4.1 Port 4 Register (PORT4)...................................................................................... 336

9.4.2 Pin Functions ....................................................................................................... 337

9.5 Port 5................................................................................................................................. 339

9.5.1 Port 5 Data Direction Register (P5DDR) ............................................................. 339

9.5.2 Port 5 Data Register (P5DR)................................................................................ 339

9.5.3 Port 5 Register (PORT5)...................................................................................... 340

9.5.4 Pin Functions ....................................................................................................... 340

9.6 Port 8................................................................................................................................. 342

9.6.1 Port 8 Data Direction Register (P8DDR) ............................................................. 342

9.6.2 Port 8 Data Register (P8DR)................................................................................ 343

9.6.3 Port 8 Register (PORT8)...................................................................................... 343

9.6.4 Pin Functions ....................................................................................................... 344

9.7 Port 9................................................................................................................................. 345

9.7.1 Port 9 Register (PORT9)...................................................................................... 345

9.7.2 Pin Functions ....................................................................................................... 345

9.8 Port A................................................................................................................................ 346

9.8.1 Port A Data Direction Register (PADDR)........................................................... 347

9.8.2 Port A Data Register (PADR).............................................................................. 348

9.8.3 Port A Register (PORTA).................................................................................... 348

9.8.4 Port A MOS Pull-Up Control Register (PAPCR)................................................ 349

9.8.5 Port A Open Drain Control Register (PAODR)................................................... 349

9.8.6 Port Function Control Register 0 (PFCR0).......................................................... 350

9.8.7 Port Function Control Register 1 (PFCR1).......................................................... 350

9.8.8 Pin Functions ....................................................................................................... 351

9.8.9 Port A MOS Input Pull-Up States........................................................................ 353

9.9 Port B................................................................................................................................ 354

9.9.1 Port B Data Direction Register (PBDDR) ........................................................... 354

9.9.2 Port B Data Register (PBDR) .............................................................................. 355

9.9.3 Port B Register (PORTB) .................................................................................... 355

9.9.4 Port B MOS Pull-Up Control Register (PBPCR)................................................. 356

9.9.5 Pin Functions ....................................................................................................... 356

9.9.6 Port B MOS Input Pull-Up States........................................................................ 357

9.10 Port C................................................................................................................................ 358

Rev. 3.00, 07/04, page xxiii of l

9.10.1 Port C Data Direction Register (PCDDR) ........................................................... 358

9.10.2 Port C Data Register (PCDR).............................................................................. 359

9.10.3 Port C Register (PORTC) .................................................................................... 359

9.10.4 Port C MOS Pull-Up Control Register (PCPCR) ................................................ 360

9.10.5 Pin Functions ....................................................................................................... 360

9.10.6 Port C MOS Input Pull-Up States........................................................................ 361

9.11 Port D................................................................................................................................ 362

9.11.1 Port D Data Direction Register (PDDDR)........................................................... 362

9.11.2 Port D Data Register (PDDR).............................................................................. 362

9.11.3 Port D Register (PORTD).................................................................................... 363

9.11.4 Port D Pull-up Control Register (PDPCR) .......................................................... 363

9.11.5 Pin Functions ....................................................................................................... 364

9.11.6 Port D MOS Input Pull-Up States........................................................................ 364

9.12 Port E ................................................................................................................................ 365

9.12.1 Port E Data Direction Register (PEDDR)............................................................ 365

9.12.2 Port E Data Register (PEDR)............................................................................... 366

9.12.3 Port E Register (PORTE)..................................................................................... 366

9.12.4 Port E Pull-up Control Register (PEPCR) ........................................................... 367

9.12.5 Pin Functions ....................................................................................................... 367

9.12.6 Port E MOS Input Pull-Up States........................................................................ 368

9.13 Port F ................................................................................................................................ 368

9.13.1 Port F Data Direction Register (PFDDR) ............................................................ 369

9.13.2 Port F Data Register (PFDR)............................................................................... 370

9.13.3 Port F Register (PORTF)..................................................................................... 370

9.13.4 Pin Functions ....................................................................................................... 371

9.14 Port G................................................................................................................................ 374

9.14.1 Port G Data Direction Register (PGDDR)........................................................... 374

9.14.2 Port G Data Register (PGDR).............................................................................. 376

9.14.3 Port G Register (PORTG).................................................................................... 376

9.14.4 Pin Functions ....................................................................................................... 377

Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 379

10.1 Features............................................................................................................................. 379

10.2 Input/Output Pins.............................................................................................................. 383

10.3 Register Descriptions........................................................................................................ 384

10.3.1 Timer Control Register (TCR)............................................................................. 386

10.3.2 Timer Mode Register (TMDR)............................................................................ 391

10.3.3 Timer I/O Control Register (TIOR)..................................................................... 392

10.3.4 Timer Interrupt Enable Register (TIER).............................................................. 410

10.3.5 Timer Status Register (TSR)................................................................................ 412

10.3.6 Timer Counter (TCNT)........................................................................................ 415

10.3.7 Timer General Register (TGR)............................................................................ 415

10.3.8 Timer Start Register (TSTR) ............................................................................... 415

Rev. 3.00, 07/04, page xxiv of l

10.3.9 Timer Synchronous Register (TSYR).................................................................. 416

10.4 Operation........................................................................................................................... 417

10.4.1 Basic Functions.................................................................................................... 417

10.4.2 Synchronous Operation........................................................................................ 422

10.4.3 Buffer Operation.................................................................................................. 424

10.4.4 Cascaded Operation ............................................................................................. 428

10.4.5 PWM Modes........................................................................................................ 430

10.4.6 Phase Counting Mode.......................................................................................... 435

10.5 Interrupts........................................................................................................................... 441

10.6 DTC Activation................................................................................................................. 443

10.7 DMAC Activation ............................................................................................................. 443

10.8 A/D Converter Activation................................................................................................. 443

10.9 Operation Timing.............................................................................................................. 444

10.9.1 Input/Output Timing............................................................................................ 444

10.9.2 Interrupt Signal Timing........................................................................................ 447

10.10 Usage Notes...................................................................................................................... 450

10.10.1 Module Stop Mode Setting.................................................................................. 450

10.10.2 Input Clock Restrictions....................................................................................... 450

10.10.3 Caution on Cycle Setting..................................................................................... 451

10.10.4 Contention between TCNT Write and Clear Operations..................................... 451

10.10.5 Contention between TCNT Write and Increment Operations.............................. 452

10.10.6 Contention between TGR Write and Compare Match......................................... 453

10.10.7 Contention between Buffer Register Write and Compare Match ........................ 453

10.10.8 Contention between TGR Read and Input Capture.............................................. 454

10.10.9 Contention between TGR Write and Input Capture............................................. 455

10.10.10 Contention between Buffer Register Write and Input Capture ........................ 455

10.10.11 Contention between Overflow/Underflow and Counter Clearing.................... 456

10.10.12 Contention between TCNT Write and Overflow/Underflow........................... 457

10.10.13 Multiplexing of I/O Pins.................................................................................. 457

10.10.14 Interrupts and Module Stop Mode................................................................... 457

Section 11 Programmable Pulse Generator (PPG) .................................................... 459

11.1 Features............................................................................................................................. 459

11.2 Input/Output Pins.............................................................................................................. 461

11.3 Register Descriptions........................................................................................................ 461

11.3.1 Next Data Enable Registers H, L (NDERH, NDERL)......................................... 462

11.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 463

11.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 464

11.3.4 PPG Output Control Register (PCR).................................................................... 466

11.3.5 PPG Output Mode Register (PMR)...................................................................... 467

11.4 Operation........................................................................................................................... 469

11.4.1 Output Timing...................................................................................................... 470

11.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 471

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11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 472

11.4.4 Non-Overlapping Pulse Output............................................................................ 473

11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output.............................. 474

11.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase

Complementary Non-Overlapping Output)......................................................... 475

11.4.7 Inverted Pulse Output .......................................................................................... 477

11.4.8 Pulse Output Triggered by Input Capture............................................................ 478

11.5 Usage Notes...................................................................................................................... 478

11.5.1 Module Stop Mode Setting.................................................................................. 478

11.5.2 Operation of Pulse Output Pins............................................................................ 478

Section 12 8-Bit Timers (TMR)...................................................................................... 479

12.1 Features............................................................................................................................. 479

12.2 Input/Output Pins.............................................................................................................. 481

12.3 Register Descriptions........................................................................................................ 481

12.3.1 Timer Counter (TCNT)........................................................................................ 481

12.3.2 Time Constant Register A (TCORA)................................................................... 482

12.3.3 Time Constant Register B (TCORB)................................................................... 482

12.3.4 Timer Control Register (TCR)............................................................................. 482

12.3.5 Timer Control/Status Register (TCSR)................................................................ 484

12.4 Operation .......................................................................................................................... 487

12.4.1 Pulse Output......................................................................................................... 487

12.5 Operation Timing........................................................................................................... ... 488

12.5.1 TCNT Incrementation Timing............................................................................. 488

12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs................. 489

12.5.3 Timing of Timer Output when Compare-Match Occurs...................................... 489

12.5.4 Timing of Compare Match Clear......................................................................... 490

12.5.5 Timing of TCNT External Reset.......................................................................... 490

12.5.6 Timing of Overflow Flag (OVF) Setting............................................................. 491

12.6 Operation with Cascaded Connection............................................................................... 491

12.6.1 16-Bit Counter Mode........................................................................................... 491

12.6.2 Compare Match Count Mode............................................................................... 492

12.7 Interrupts........................................................................................................................... 492

12.7.1 Interrupt Sources and DTC Activation ................................................................ 492

12.7.2 A/D Converter Activation.................................................................................... 493

12.8 Usage Notes...................................................................................................................... 494

12.8.1 Contention between TCNT Write and Clear........................................................ 494

12.8.2 Contention between TCNT Write and Increment................................................ 494

12.8.3 Contention between TCOR Write and Compare Match ...................................... 495

12.8.4 Contention between Compare Matches A and B................................................. 496

12.8.5 Switching of Internal Clocks and TCNT Operation ............................................ 497

12.8.6 Mode Setting with Cascaded Connection............................................................ 499

12.8.7 Interrupts in Module Stop Mode.......................................................................... 499

Rev. 3.00, 07/04, page xxvi of l

Section 13 Watchdog Timer............................................................................................. 501

13.1 Features............................................................................................................................. 501

13.2 Input/Output Pin................................................................................................................ 502

13.3 Register Descriptions........................................................................................................ 503

13.3.1 Timer Counter (TCNT)........................................................................................ 503

13.3.2 Timer Control/Status Register (TCSR)................................................................ 503

13.3.3 Reset Control/Status Register (RSTCSR)............................................................ 505

13.4 Operation........................................................................................................................... 506

13.4.1 Watchdog Timer Mode........................................................................................ 506

13.4.2 Interval Timer Mode............................................................................................ 507

13.5 Interrupts........................................................................................................................... 508

13.6 Usage Notes ...................................................................................................................... 508

13.6.1 Notes on Register Access..................................................................................... 508

13.6.2 Contention between Timer Counter (TCNT) Write and Increment..................... 509

13.6.3 Changing Value of CKS2 to CKS0...................................................................... 510

13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 510

13.6.5 Internal Reset in Watchdog Timer Mode............................................................. 510

13.6.6 System Reset by WDTOVF Signal...................................................................... 511

Section 14 Serial Communication Interface (SCI, IrDA)........................................ 513

14.1 Features............................................................................................................................. 513

14.2 Input/Output Pins.............................................................................................................. 515

14.3 Register Descriptions........................................................................................................ 516

14.3.1 Receive Shift Register (RSR) .............................................................................. 517

14.3.2 Receive Data Register (RDR).............................................................................. 517

14.3.3 Transmit Data Register (TDR)............................................................................. 517

14.3.4 Transmit Shift Register (TSR)............................................................................. 518

14.3.5 Serial Mode Register (SMR)................................................................................ 518

14.3.6 Serial Control Register (SCR).............................................................................. 522

14.3.7 Serial Status Register (SSR) ................................................................................ 526

14.3.8 Smart Card Mode Register (SCMR).................................................................... 533

14.3.9 Bit Rate Register (BRR) ...................................................................................... 534

14.3.10 IrDA Control Register (IrCR).............................................................................. 543

14.3.11 Serial Extension Mode Register (SEMR)............................................................ 544

14.4 Operation in Asynchronous Mode.................................................................................... 546

14.4.1 Data Transfer Format........................................................................................... 546

14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 548

14.4.3 Clock.................................................................................................................... 549

14.4.4 SCI Initialization (Asynchronous Mode)............................................................. 550

14.4.5 Data Transmission (Asynchronous Mode)........................................................... 551

14.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 553

14.5 Multiprocessor Communication Function......................................................................... 557

14.5.1 Multiprocessor Serial Data Transmission ............................................................ 558

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14.5.2 Multiprocessor Serial Data Reception ................................................................. 560

14.6 Operation in Clocked Synchronous Mode........................................................................ 564

14.6.1 Clock.................................................................................................................... 564

14.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 565

14.6.3 Serial Data Transmission (Clocked Synchronous Mode).................................... 566

14.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 569

14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous

Mode)................................................................................................................... 571

14.7 Operation in Smart Card Interface Mode.......................................................................... 573

14.7.1 Pin Connection Example...................................................................................... 573

14.7.2 Data Format (Except for Block Transfer Mode).................................................. 573

14.7.3 Block Transfer Mode........................................................................................... 575

14.7.4 Receive Data Sampling Timing and Reception Margin....................................... 575

14.7.5 Initialization......................................................................................................... 576

14.7.6 Data Transmission (Except for Block Transfer Mode)........................................ 577

14.7.7 Serial Data Reception (Except for Block Transfer Mode)................................... 580

14.7.8 Clock Output Control........................................................................................... 581

14.8 IrDA Operation................................................................................................................. 583

14.9 SCI Interrupts.................................................................................................................... 586

14.9.1 Interrupts in Normal Serial Communication Interface Mode .............................. 586

14.9.2 Interrupts in Smart Card Interface Mode............................................................. 587

14.10 Usage Notes...................................................................................................................... 589

14.10.1 Module Stop Mode Setting.................................................................................. 589

14.10.2 Break Detection and Processing .......................................................................... 589

14.10.3 Mark State and Break Sending............................................................................. 589

14.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode

Only).................................................................................................................... 589

14.10.5 Relation between Writes to TDR and the TDRE Flag......................................... 590

14.10.6 Restrictions on Use of DMAC* or DTC.............................................................. 590

14.10.7 Operation in Case of Mode Transition................................................................. 590

Section 15 I2C Bus Interface2 (IIC2) (Option)........................................................... 595

15.1 Features............................................................................................................................. 595

15.2 Input/Output Pins.............................................................................................................. 597

15.3 Register Descriptions........................................................................................................ 598

15.3.1 I

15.3.2 I

15.3.3 I

15.3.4 I

15.3.5 I

15.3.6 Slave Address Register (SAR)............................................................................. 607

15.3.7 I

15.3.8 I

Rev. 3.00, 07/04, page xxviii of l

C Bus Control Register A (ICCRA).................................................................. 599

C Bus Control Register B (ICCRB).................................................................. 601

C Bus Mode Register (ICMR)........................................................................... 602

C Bus Interrupt Enable Register (ICIER).......................................................... 603

C Bus Status Register (ICSR)........................................................................... 605

C Bus Transmit Data Register (ICDRT)........................................................... 607

C Bus Receive Data Register (ICDRR)............................................................. 607

15.3.9 I2C Bus Shift Register (ICDRS)........................................................................... 607

15.4 Operation........................................................................................................................... 608

15.4.1 I

C Bus Format .................................................................................................... 608

15.4.2 Master Transmit Operation.................................................................................. 609

15.4.3 Master Receive Operation.................................................................................... 611

15.4.4 Slave Transmit Operation .................................................................................... 613

15.4.5 Slave Receive Operation ...................................................................................... 615

15.4.6 Noise Canceler..................................................................................................... 617

15.4.7 Example of Use.................................................................................................... 617

15.5 Interrupt Request............................................................................................................... 622

15.6 Bit Synchronous Circuit .................................................................................................... 622

Section 16 A/D Converter................................................................................................. 625

16.1 Features............................................................................................................................. 625

16.2 Input/Output Pins.............................................................................................................. 627

16.3 Register Descriptions........................................................................................................ 628

16.3.1 A/D Data Registers A to H (ADDRA to ADDRH).............................................. 628

16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 629

16.3.3 A/D Control Register (ADCR) ............................................................................ 631

16.4 Operation........................................................................................................................... 632

16.4.1 Single Mode......................................................................................................... 632

16.4.2 Scan Mode ........................................................................................................... 632

16.4.3 Input Sampling and A/D Conversion Time.......................................................... 633

16.4.4 External Trigger Input Timing............................................................................. 635

16.5 Interrupts........................................................................................................................... 635

16.6 A/D Conversion Precision Definitions.............................................................................. 636

16.7 Usage Notes ...................................................................................................................... 638

16.7.1 Module Stop Mode Setting .................................................................................. 638

16.7.2 Permissible Signal Source Impedance................................................................. 638

16.7.3 Influences on Absolute Precision......................................................................... 639

16.7.4 Setting Range of Analog Power Supply and Other Pins...................................... 639

16.7.5 Notes on Board Design........................................................................................ 639

16.7.6 Notes on Noise Countermeasures ........................................................................ 640

Section 17 D/A Converter................................................................................................. 643

17.1 Features............................................................................................................................. 643

17.2 Input/Output Pins.............................................................................................................. 645

17.3 Register Descriptions........................................................................................................ 645

17.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)............................................ 645

17.3.2 D/A Control Register 23 (DACR23).................................................................... 645

17.4 Operation........................................................................................................................... 647

17.5 Usage Notes ...................................................................................................................... 648

17.5.1 Setting for Module Stop Mode............................................................................. 648

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17.5.2 D/A Output Hold Function in Software Standby Mode....................................... 648

Section 18 RAM.................................................................................................................. 649

Section 19 Flash Memory (0.35-µm F-ZTAT Version)........................................... 651

19.1 Features............................................................................................................................. 651

19.2 Mode Transitions .............................................................................................................. 652

19.3 Block Configuration.......................................................................................................... 656

19.4 Input/Output Pins.............................................................................................................. 658

19.5 Register Descriptions........................................................................................................ 658

19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 658

19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 660

19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 660

19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 661

19.5.5 RAM Emulation Register (RAMER)................................................................... 662

19.6 On-Board Programming Modes........................................................................................ 663

19.6.1 Boot Mode ........................................................................................................... 664

19.6.2 User Program Mode............................................................................................. 667

19.7 Flash Memory Emulation in RAM ................................................................................... 668

19.8 Flash Memory Programming/Erasing............................................................................... 670

19.8.1 Program/Program-Verify..................................................................................... 670

19.8.2 Erase/Erase-Verify............................................................................................... 672

19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 672

19.9 Program/Erase Protection ................................................................................................. 674

19.9.1 Hardware Protection ............................................................................................ 674

19.9.2 Software Protection.............................................................................................. 674

19.9.3 Error Protection.................................................................................................... 674

19.10 Programmer Mode............................................................................................................ 675

19.11 Power-Down States for Flash Memory ............................................................................. 675

19.12 Usage Notes...................................................................................................................... 675

Section 20 Flash Memory (0.18-µm F-ZTAT Version)........................................... 679

20.1 Features............................................................................................................................. 679

20.1.1 Operating Mode................................................................................................... 682

20.1.2 Mode Comparison................................................................................................ 683

20.1.3 Flash MAT Configuration.................................................................................... 684

20.1.4 Block Division..................................................................................................... 685

20.1.5 Programming/Erasing Interface........................................................................... 686

20.2 Input/Output Pins.............................................................................................................. 688

20.3 Register Descriptions........................................................................................................ 688

20.3.1 Programming/Erasing Interface Register............................................................. 689

20.3.2 Programming/Erasing Interface Parameter.......................................................... 696

20.3.3 Flash Vector Address Control Register (FVACR)............................................... 706

Rev. 3.00, 07/04, page xxx of l

+ 951 hidden pages

RENESAS H8S-2368F-ZTAT User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Precautions on Handling of Product

Configuration of This Manual

Preface

Main Revisions for this Edition

Contents