RENESAS H8S-2368F-ZTAT User Manual

REJ09B0050-0300O

The revision list can be viewed directly by clicking the title page.

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

H8S/2368 Group, H8S/2368F-ZTAT™

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family/H8S/2300 Series

Rev. 3.00 Revision Date: July 07, 2004

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Rev. 3.00, 07/04, page ii of l

General Precautions on Handling of Product

1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Trea t ment of Unused Input Pins Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.

3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.

Rev. 3.00, 07/04, page iii of l

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descr i ptions given, and usage notes are give n, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for r e vised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see t he actual locations in this manual.

11.Index

Rev. 3.00, 07/04, page iv of l

Preface

The H8S/2368 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas Technology’s original architecture as their cores, and the peripheral functions required to configure a system.

The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a 16-Mbyte linear address space.

This LSI is equipped with direct memory access controller (DMAC) and data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), 8-bit timers (TMR), a watchdog timer ( WDT), serial communication interfaces (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as onchip peripheral modules required for system configuration. I included as an optional interface.

A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM and other ki nds of memor y.

A single-p o wer fla s h me mo r y (F -ZTAT) version is available for this LSI's ROM. This provides flexibility as it can be reprogrammed in no time to cope with all situation s from the early stages of mass production to full-scale mass production. This is particularly app licable to application devices with specifications that will most probably change.

C bus interface 2 (IIC2) can also be

Note: F-ZTAT is a trademark of Renesas Technology Corp.

Target Users: This manual was written for users who will be using the H8S/2368 Group in the

design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2368 Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction se t.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.

Rev. 3.00, 07/04, page v of l

• In order to understand the details o f the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual. For the execution state of each instruction in this LSI, see Appendix D, Bus State during Execution of Instructions.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 23, List of Register s.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel

number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require. http://www.renesas.com/

H8S/2368 Group manuals:

Manual Title ADE No.

H8S/2368 Group, H8S/2368F-ZTAT™ Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

User's manuals for development tools:

Manual Title ADE No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual

H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-282 H8S, H8/300 Series High-Performance Embedded Workshop, HDI Tutorial ADE-702-231 High-Performance Embedded Workshop User's Manual ADE-702-201

Rev. 3.00, 07/04, page vi of l

ADE-702-247

Main Revisions for this Edition

Item Page Revisions (See Manual for Details)

1.1 Features 1 • On-chip memory Lineup added

ROM Type Model ROM RAM Remarks

Flash memory version HD64F2368 512 kbytes 32 kbytes

HD64F2367 384 kbytes 24 kbytes HD64F2366 384 kbytes 30 kbytes

2 • Compact package

Note *2 added

QFP-128 Note: 2. Not supported by the HD64F2368.

1.2 Block Diagram 3 Description amended Figures 1.1, 1.2

diagrams of this LSI.

Figure 1.3 Internal Block

5 Figure 1.3 added

Diagram of H8S/2368

1.3.1 Pin Arrangement 6 Description amended Figures

LSI.

Figure 1.6 Pin Arrangement

8 Figure 1.6 added

of H8S/2368 Figure 1.7 Pin Arrangement

of H8S/2367, H8S/2365, and H8S/2363

Figure 1.8 Pin Arrangement

9 Note added

Note:

of H8S/2366

1.3.2 Pin Arrangement in

Each Operating Mode Table 1.1 Pin Arrangement in

Each Operating Mode

11 to 15 Note *1 added

QFP-128

12 Name of pin 33 amended, note *2 added

(Before) V

Notes: 1. Not supported by the H8S/2368.

, and 1.3 show the internal block

1.4 to 1.8 show the pin arrangements of this

FP-128B is not supported by the HD64F2368.

→ (After) VCC (V

)

2. Used as the VCL pin in the H8S/2368.

Rev. 3.00, 07/04, page vii of l

Item Page Revisions (See Manual for Details)

1.3.3 Pin Functions Table 1.2 Pin Functions

16 to 21 Note *1 added

QFP-128

Note: 1. Not supported by the H8S/2368.

16 VCC Function amended

Pin No.

6,39,66, 91,92

I/O Function

Input Power supply pins. VCC pins

Type Symbol TFP-120 QFP-128

Power V

2,33,60,

83,84

should be connected to the system power supply. The pin 33 of TFP-120, which is used as the VCL pin, should not be connected to the power supply. The pin should be connected to VSS via 0.1-µF (recommended value) capacitor (placed close to the pins).

3.1 Operating Mode Selection

Mode Selection

59 Description amended

This LSI has

six operating modes (modes 1 to 5 and 7). Modes 1 to 5 and 7 are available in the H8S/2368 flash memory version. Modes 1 to 4 and 7 are available in the H8S/2367. Modes 1, 2, 4, and 7 are available in ... at the beginning of a program execution. Modes 3

and 5 are a boot mode/user boot mod e in which the flash memory can be programmed or erased. For details on the boot mode/user boot mode, refer to section 19, Flash Memory ( or section 20, Flash Memory (0.18-µm F-ZTAT Version).

Table 3.1 amended, note * addedTable 3.1 MCU Operating

MCU Operating Mode MD2 MD1 MD0

4 1 0 0 Advanced Expanded

5* 1 0 1 Advanced User boot

7 1 1 1 Advanced

Note: * Supported only by the H8S/2368.

0.35-µm F-ZTAT Version),

CPU Operating Mode Description

mode with onchip ROM enabled

mode Single-chip

mode

External Data Bus

On-Chip

Initial

ROM

Width

Enabled 8 bits

Enabled —

Max. Value

16 bits

Rev. 3.00, 07/04, page viii of l

Item Page Revisions (See Manual for Details)

3.3.5 Mode 5 63 Item added

3.3.7 Pin Functions Table 3.2 Pin Functions in

Each Operating Mode

64 Table 3.2 amended, note *3 added

Port

Port A

PA7 to PA5 P

PA4 to PA0 Port B P Port C P Port D D P Port E P Port F

PF7, PF6 P/C

PF5, PF4 C

PF3 P/C

PF2 to PF0 P Port G

PG6 to PG1 P

PG0 P

Mode 4

/A P

/D P

Mode 5

Note: 3.Mode 5 is available only in the H8S/2368.

3.4 Memory Map in Each

65, 66 Figures 3.1, 3.2 added

Operating Mode Figure 3.1 H8S/2368 Memory

Map (1) Figure 3.2 H8S/2368 Memory

Map (2)

6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)

124 • CSACRL

Description amended

Bit Bit Name Initial Value R/W Description

CSXT7

CSXT6

CSXT5

CSXT4

CSXT3

CSXT2

CSXT1

CSXT0

0 0 0 0 0 0 0 0

R/W

CS and Address Signal

R/W

Assertion Period Control 2

R/W

These bits specify whether or

R/W

not the T

R/W

6.3 is to be inserted. When an

R/W

area for which the CSXTn bit is

R/W

set to 1 is accessed, a one-

R/W

state T CSn and address signals are asserted, is inserted normal access cycle.

2 *3

Mode 7

/A P

/D P

/C P

cycle shown in figure

cycle, in which only the

after th e

Rev. 3.00, 07/04, page ix of l

Item Page Revisions (See Manual for Details)

14.3.9 Bit Rate Register (BRR)

Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode)

Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)

Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)

Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)

Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372)

Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372)

14.3.11 Serial Extension Mode Register (SEMR)

14.8 IrDA Operation Table 14.12 Settings of Bits

IrCKS2 to IrCKS0

14.10.3 Mark State and Break Sending

Section 15 I2C Bus Interface2 (IIC2) (Option)

536 Values when operating frequency φ is 34 MHz added,

note * added Note: * Supported only by the H8S/2368.

537

538

539

540

541

542

545 Bits 2 to 0 description amended

Asynchronous clock source selection (valid when = 1 in asynchronous mode)

585 High Pulse Width Selection

Values when operating frequency φ 34MHz added, note * added

Note: * Supported only by the H8S/2368.

589 Description amended

(Before) (After) PCR → PDR →

595 Description amended

2. For the F-ZTAT version, model names do not depend on optional functions. When using optional functions, conta ct the Renesa s Technology sales office.

DDR DR

ROMless version, product

CKE1

Rev. 3.00, 07/04, page x of l

Item Page Revisions (See Manual for Details)

15.3.1 I2C Bus Control Register A (ICCRA)

599 Bits 5, 4 and bits 3 to 0 description amended

Initial

Bit Bit Name

54MST

TRS00

CKS3

CKS2

CKS1

CKS0

Value

0 0 0 0

R/W Description

R/W

Master/Slave Select

R/W

Transmit/Receive Select When arbitration is lost in master mode, MST

and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. In addition, TRS is set to 1 automatically in slave receive mode when the seventh bit of the start condition matches the slave address set in SAR and the eighth bit is set to 1.

Operating modes are described below according to MST and TRS combination.

00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode

Transfer clock select 3 to 0

R/W R/W

In master mode, these bits should be set

R/W

according to the necessary transfer rate. In

R/W

slave mode, they are used to secure the data setup time in transmit mode. The data setup time is 10 tcyc when CKS3 is cleared to 0; 20 tcyc when CKS3 is set to 1.

Table 15.2 Transfer Rate 600 Table 15.2 amended, notes *1 to *3 added

Bit3 Bit2 Bit1 Bit0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock φ=8MHz φ=10MHz φ=20MHz φ=25MHz φ=33MHz φ=34MHz

0 φ/28 286kHz 357kHz 714kHz

1 φ/40 200kHz 250kHz 500kHz 0 φ/48 167kHz 208kHz 417kHz

1 φ/64 125kHz 156kHz 313kHz 0 φ/168 47.6kHz 59.5kHz 119kHz 149kHz 196kHz 202kHz0

1 φ/100 80.0kHz 100kHz 200kHz 250kHz 330kHz 340kHz 0 φ/112 71.4kHz 89.3kHz 179kHz 223kHz 295kHz 304kHz

1 φ/128 62.5kHz 78.1kHz 156kHz 195kHz 258kHz 266kHz 0 φ/56 143kHz 179kHz 357kHz 446kHz

1 φ/80 100kHz 125kHz 250kHz 313kHz 413kHz

0 φ/96 83.3kHz 104kHz 208kHz 260kHz 344kHz 354kHz 1 φ/128 62.5kHz 78.1kHz 156kHz 195kHz 258kHz 266kHz

0 φ/336 23.8kHz 29.8kHz 59.5kHz 74.4kHz 98.2kHz 101kHz0 1 φ/200 40.0kHz 50.0kHz 100kHz 125kHz 165kHz 170kHz

0 φ/224 35.7kHz 44.6kHz 89.3kHz 112kHz 147kHz 152kHz 1 φ/256 31.3kHz 39.1kHz 78.1kHz 97.7kHz 129kHz 133kHz

Notes: 1. Supported only by the H8S/2368.

2. Does not conform to the I2C bus interface specification (normal mode: max. 100 kHz, highspeed mode: max. 400 kHz).

3. If CKS3 and CKS2 are both cleared to 0 (7.5 tcyc bit synchronization) and the operating frequency is 20 MHz or greater, it may not be possible to maintain the prescribed transfer rate under certain load conditions. Therefore, a bit synchronization setting other than 7.5 tcyc should be used if the operating frequency exceeds 20 MHz.

*2* *2* *2*

2 2 2 2

589kHz

607kHz

425kHz

Rev. 3.00, 07/04, page xi of l

Item Page Revisions (See Manual for Details)

15.3.3 I (ICMR)

C Bus Mode Register

602 Description amended

ICMR performs master mode wait control and selects the transfer bit count.

605 Bit 7, and bit 4 description amended15.3.5 I2C Bus Status

Bit Bit Name

7 TDRE 0 R/W Transmit Data Register Empty

4 NACKF 0 R/W No acknowledge detection flag

Initial Value R/W Description

[Setting conditions]

• When data is transferred from ICDRT to ICDRS and ICDRT becomes empty

• When TRS is set

• When a start condition (including retransmission) is issued

• When a transition from receive mode to transmit mode is made in slave mode

[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When data is written to ICDRT

[Setting condition] When no acknowledge is detected from the

receive device in transmission while the ACKE bit in ICIER is 1

[Clearing condition] When 0 is written in NACKF after reading

NACKF = 1 Note: When NACKF = 1 is detected, NACKF

must be cleared to 0. Subsequent transmission in not made until NACKF is cleared to 0.

15.3.7 I2C Bus Transmit Data Register (ICDRT)

15.3.8 I2C Bus Receive Data Register (ICDRR)

15.4.4 Slave Transmit Operation

Figure 15.10 Slave Transmit Mode Operation Timing 2

Rev. 3.00, 07/04, page xii of l

607 Description added

If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.

The initial value of ICDRT is H'FF.

607 Description added

ICDRR is a receive-only register, therefore the CPU cannot be written to this register. The initial value of ICDRR is H'FF.

615 Figure 15.10.amended

SDA

(master output)

Item Page Revisions (See Manual for Details)

15.4.5 Slave Receive Operation

615 Description amended

3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before

reading ICDRR, to be returned to the master device, is reflected to the next transmit frame.

Figure 15.12 Slave Receive

616 Figure 15.12 amended

Mode Operation Timing 2

SDA

(slave output)

15.4.7 Example of Use Figure 15.15 Sample

Flowchart for Master Receive Mode

619 Note *, additional information added

Note: * Prevent any interrupts while steps [1] to [3] are executed.

Additional information: When receiving one-byte data, execute step [1], and then step [7] omitting steps [2] to [6]. In step [8], dummy read ICDRR.

Figure 15.17 Sample Flowchart for Slave Receive Mode

621 Additional information added

Additional information: When receiving one-byte data, execute step [1], and then step [7] omitting steps [2] to [6]. In step [8], dummy read ICDRR.

15.5 Interrupt Request 622 Description added When interrupt conditions described in table 15.3 are 1

and the CPU is ready to receive interrupts, an interrupt execution handling is executed. Clear each interrupt source during an interrupt execution handling. Note that TDRE and TEND are automatically cleared by writing the transmit data to ICDRT, and RDRF is automatically cleared by reading ICDRR. When the transmit data is written to ICDR, TDRE is set again simultaneously. When TDRE is cleared, extra one byte of data may be transmitted.

15.6 Bit Synchronous Circuit

Table 15.4 Time for monitoring SCL

623 Note * added

Note * If the operating frequency exceeds 20 MHz, it may not be possible to maintain the prescribed transfer rate under certain load conditions. A setting other than

7.5 tcyc should therefore be used.

Section 18 RAM 649 Lineup added

Product Type Name ROM Type

H8S/2368 Group

HD64F2368 Flash memory

HD64F2367 24 kbytes H'FF6000 to

HD64F2366 30 kbytes H'FF4800 to

version

RAM Capacitance RAM Address

32 kbytes H'FF4000 to

H'FFBFFF

Rev. 3.00, 07/04, page xiii of l

Item Page Revisions (See Manual for Details)

Section 19 Flash Memory (0.35-µm F-ZTAT Version)

19.5.5 RAM Emulation Register (RAMER)

19.7 Flash Memory Emulation in RAM

Section 20 Flash Memory (0.18-µm F-ZTAT Version)

22.2.1 Connecting a Crystal Oscillator

Figure 22.2 Connection of Crystal Oscillator (Example)

23.2.3 Software Standby Mode

Table 23.2 Oscillation Stabilization Time Settings

23.2.4 Hardware Standby Mode

651 Section title amended

662 Note amended

Note: This function is not supported by the H8S/2367, or H8S/2366.

668 Note amended

Note: This function is not supported by the H8S/2367, or H8S/2366.

679 to 764 Section added

770 Note * added

Note: * In the H8S/2368, CL1 = CL2 = 10 pF.

784 φ [MHz]34 added, note *2 added

2. Supported only by the H8S/2368.

Note:

786 Hardware Standby Mode Timing when Power Is

Supplied (Only H8S/2368) added

H8S/2368,

Rev. 3.00, 07/04, page xiv of l

Item Page Revisions (See Manual for Details)

24.1 Register Addresses

(Address Order)

800, 801 Table amended, notes *4, *5 added

Flash code control status register

Flash program code select register

Flash erase code select register

Flash memory control register 1

Flash key code register

Flash memory control register 2

Flash MAT select register

Flash transfer destination address register

Erase block register 1 EBR1 8 H'FFCA FLASH 8 2 Erase block register 2 EBR2 8 H'FFCB FLASH 8 2 Flash vector address

control register

Abbreviation Bit No. Address Module

FCCS

FPCS

FECS

8 H'FFC4

8 H'FFC5

8 H'FFC6

FLMCR1 8 H'FFC8 FLASH 8 2

FKEY

8 H'FFC8 FLASH 8 2

FLMCR2 8 H'FFC9 FLASH 8 2

FMATS

FTDAR

FVACR

8 H'FFC9 FLASH 8 2

8 H'FFCA FLASH 8 2

8 H'FFCB FLASH 8 2

Notes: 4. Supported only by the H8S/2368.

5. Cannot be acces sed by other than H8S/2368.

24.2 Register Bits 812, 814 Item FLASH amended, note *8 added

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

FCCS

— — — FLER — — — SCO FLASH

FPCS

— — — PPVD — — — PPVS

FECS

— — — — — — — EPVB

FLMCR1 — SWE ESU PSU EV PV E P

FKEY

K7 K6 K5 K4 K3 K2 K1 K0

FLMCR2 FLER — — — — — — —

FMATS

MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0

FTDAR

TDER TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 EBR2 — — EB13 EB12 EB11 EB10 EB9 EB8

FVACR

FVCHGE — — — FVSEL3 FVSEL2 FVSEL1 FVSEL0

Data

Width

FLASH 8 2

Access States

Note: 8. Supported only by the H8S/2368.

Rev. 3.00, 07/04, page xv of l

Item Page Revisions (See Manual for Details)

24.3 Register States in Each Operating Mode

823, 824 Item FLASH amended, note *2 added

All

FCCS

FPCS

FECS FLMCR1 Initialized — — — — — — Initialized

FKEY FLMCR2 Initialized — — — — — — Initialized

FMATS

FTDAR EBR1 Initialized — — — — — — Initialized EBR2 Initialized — — — — — — Initialized

FVACR

High-

Clock

Speed

Division Sleep

Initialized — — — — — — Initialized FLASH Initialized — — — — — — Initialized Initialized — — — — — — Initialized

Initialized — — — — — — Initialized

Initialized — — — — — — Initialized Initialized — — — — — — Initialized

Initialized — — — — — — Initialized

Module Stop

Module Clock Stop

Software Standby

Note: 2. Supported only by the H8S/2368.

25.2 Electrical Characteristics of

0.35 µm

861 Item title amended

F-ZTAT Version

25.2.2 DC Characteristics Table 25.16 Permissible

Output Currents

25.3 Electrical

864 Table 25.16 amended

Item Symbol Min Typ Max Unit

Permissible output low current (per pin)

SCL0 toSCL1, SDA0to SDA1 — — 10.0 All outputpins

875 to 888 Item added

——2.0

Characteristics for 0.18 µm F-ZTAT Version

Appendix B. Product Lineup 898 Lineup added, note amended, *1 added

Product Type Name

H8S/2368

F-ZTAT

HD64F2368 HD64F2368

version

H8S/2367 F-ZTAT

HD64F2367 HD64F2367

version

H8S/2366

F-ZTAT

HD64F2366 HD64F2366

version

H8S/2365 Masked

HD6432365 HD6432365 ROM version

H8S/2363

ROMless

HD6412363 HD6412363 version

Model Marking Package (Code)

Notes: When using the optional functions for the F-

ZTAT version,

ROMless version, which has the common type name, contact a Renesas Sales office.

1. Supported only by the H8S/2368.

Hardware Standby Module

120-pin TFP (TFP-120, TFP-120V

128-pin

QFP (FP-128B, FP-128BV

)

Rev. 3.00, 07/04, page xvi of l

Section 1 Overview............................................................................................................. 1

1.1 Features............................................................................................................................. 1

1.2 Block Diagram.................................................................................................................. 3

1.3 Pin Description.................................................................................................................. 6

1.3.1 Pin Arrangement.................................................................................................. 6

1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 11

1.3.3 Pin Functions ....................................................................................................... 16

Section 2 CPU...................................................................................................................... 23

2.1 Features............................................................................................................................. 23

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 24

2.1.2 Differences from H8/300 CPU ............................................................................ 25

2.1.3 Differences from H8/300H CPU.......................................................................... 25

2.2 CPU Operating Modes...................................................................................................... 26

2.2.1 Normal Mode....................................................................................................... 26

2.2.2 Advanced Mode................................................................................................... 27

2.3 Address Space................................................................................................................... 30

2.4 Register Configuration...................................................................................................... 31

2.4.1 General Registers................................................................................................. 32

2.4.2 Program Counter (PC) ......................................................................................... 33

2.4.3 Extended Control Register (EXR) ....................................................................... 33

2.4.4 Condition-Code Register (CCR).......................................................................... 34

2.4.5 Initial Register Values.......................................................................................... 36

2.5 Data Formats..................................................................................................................... 36

2.5.1 General Register Data Formats............................................................................ 36

2.5.2 Memory Data Formats......................................................................................... 38

2.6 Instruction Set................................................................................................................... 39

2.6.1 Table of Instructions Classified by Function....................................................... 40

2.6.2 Basic Instruction Formats .................................................................................... 49

2.7 Addressing Modes and Effective Address Calculation..................................................... 50

2.7.1 Register Direct—Rn............................................................................................. 51

2.7.2 Register Indirect—@ERn.................................................................................... 51

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 51

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.. 51

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 51

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 52

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC).................................... 52

2.7.8 Memory Indirect—@@aa:8 ................................................................................ 52

2.7.9 Effective Address Calculation.............................................................................. 53

Rev. 3.00, 07/04, page xvii of l

2.8 Processing States............................................................................................................... 56

2.9 Usage Note........................................................................................................................ 57

2.9.1 Note on Bit Manipulation Instructions................................................................. 57

Section 3 MCU Operating Modes.................................................................................. 59

3.1 Operating Mode Selection ................................................................................................ 59

3.2 Register Descriptions........................................................................................................60

3.2.1 Mode Control Register (MDCR)......................................................................... 60

3.2.2 System Control Register (SYSCR)...................................................................... 60

3.3 Operating Mode Descriptions........................................................................................... 62

3.3.1 Mode 1................................................................................................................. 62

3.3.2 Mode 2................................................................................................................. 62

3.3.3 Mode 3................................................................................................................. 62

3.3.4 Mode 4................................................................................................................. 62

3.3.5 Mode 5................................................................................................................. 63

3.3.6 Mode 7................................................................................................................. 63

3.3.7 Pin Functions ....................................................................................................... 64

3.4 Memory Map in Each Operating Mode............................................................................ 65

Section 4 Exception Handling......................................................................................... 75

4.1 Exception Handling Types and Priority ............................................................................ 75

4.2 Exception Sources and Exception Vector Table............................................................... 75

4.3 Reset.................................................................................................................................. 77

4.3.1 Reset Exception Handling.................................................................................... 77

4.3.2 Interrupts after Reset............................................................................................ 79

4.3.3 On-Chip Peripheral Functions after Reset Release.............................................. 79

4.4 Traces................................................................................................................................ 80

4.5 Interrupts........................................................................................................................... 80

4.6 Trap Instruction................................................................................................................. 81

4.7 Stack Status after Exception Handling.............................................................................. 82

4.8 Usage Notes...................................................................................................................... 83

Section 5 Interrupt Controller.......................................................................................... 85

5.1 Features............................................................................................................................. 85

5.2 Input/Output Pins.............................................................................................................. 87

5.3 Register Descriptions........................................................................................................87

5.3.1 Interrupt Control Register (INTCR) .................................................................... 88

5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 88

5.3.3 IRQ Enable Register (IER).................................................................................. 90

5.3.4 IRQ Sense Control Register L (ISCRL)............................................................... 91

5.3.5 IRQ Status Register (ISR).................................................................................... 94

5.3.6 IRQ Pin Select Register (ITSR)........................................................................... 95

5.3.7 Software Standby Release IRQ Enable Register (SSIER)................................... 96

Rev. 3.00, 07/04, page xviii of l

5.4 Interrupt Sources............................................................................................................... 96

5.4.1 External Interrupts ............................................................................................... 96

5.4.2 Internal Interrupts................................................................................................. 97

5.5 Interrupt Exception Handling Vector Table...................................................................... 98

5.6 Interrupt Control Modes and Interrupt Operation............................................................. 103

5.6.1 Interrupt Control Mode 0..................................................................................... 103

5.6.2 Interrupt Control Mode 2..................................................................................... 105

5.6.3 Interrupt Exception Handling Sequence .............................................................. 106

5.6.4 Interrupt Response Times.................................................................................... 108

5.6.5 DTC and DMAC* Activation by Interrupt.......................................................... 109

5.7 Usage Notes...................................................................................................................... 109

5.7.1 Contention between Interrupt Generation and Disabling..................................... 109

5.7.2 Instructions that Disable Interrupts...................................................................... 110

5.7.3 Times when Interrupts are Disabled .................................................................... 110

5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 110

5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ............................................. 111

5.7.6 Note on IRQ Status Register (ISR)...................................................................... 111

Section 6 Bus Controller (BSC)...................................................................................... 113

6.1 Features............................................................................................................................. 113

6.2 Input/Output Pins.............................................................................................................. 115

6.3 Register Descriptions........................................................................................................ 116

6.3.1 Bus Width Control Register (ABWCR)............................................................... 117

6.3.2 Access State Control Register (ASTCR) ............................................................. 117

6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL,

WTCRBH, and WTCRBL).................................................................................. 118

6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................ 123

6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 124

6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)

Area 1 Burst ROM Interface Control Register (BROMCRL).............................. 126

6.3.7 Bus Control Register (BCR)................................................................................ 127

6.3.8 DRAM Control Register (DRAMCR)................................................................. 129

6.3.9 DRAM Access Control Register (DRACCR)...................................................... 134

6.3.10 Refresh Control Register (REFCR) ..................................................................... 135

6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 138

6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... 138

6.4 Operation........................................................................................................................... 138

6.4.1 Area Division....................................................................................................... 138

6.4.2 Bus Specifications................................................................................................ 140

6.4.3 Memory Interfaces............................................................................................... 142

6.4.4 Chip Select Signals .............................................................................................. 143

6.5 Basic Bus Interface ........................................................................................................... 144

6.5.1 Data Size and Data Alignment............................................................................. 144

Rev. 3.00, 07/04, page xix of l

6.5.2 Valid Strobes ....................................................................................................... 145

6.5.3 Basic Timing........................................................................................................ 146

6.5.4 Wait Control ........................................................................................................ 154

6.5.5 Read Strobe (RD) Timing.................................................................................... 155

6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. 156

6.6 DRAM Interface ............................................................................................................... 158

6.6.1 Setting DRAM Space........................................................................................... 158

6.6.2 Address Multiplexing........................................................................................... 158

6.6.3 Data Bus............................................................................................................... 159

6.6.4 Pins Used for DRAM Interface............................................................................ 160

6.6.5 Basic Timing........................................................................................................ 161

6.6.6 Column Address Output Cycle Control............................................................... 162

6.6.7 Row Address Output State Control...................................................................... 162

6.6.8 Precharge State Control ....................................................................................... 165

6.6.9 Wait Control ........................................................................................................ 166

6.6.10 Byte Access Control ............................................................................................ 169

6.6.11 Burst Operation .................................................................................................... 170

6.6.12 Refresh Control.................................................................................................... 174

6.6.13 DMAC Single Address Transfer Mode and DRAM Interface............................. 179

6.7 Burst ROM Interface......................................................................................................... 182

6.7.1 Basic Timing........................................................................................................ 182

6.7.2 Wait Control ........................................................................................................ 184

6.7.3 Write Access........................................................................................................ 184

6.8 Idle Cycle.......................................................................................................................... 185

6.8.1 Operation ............................................................................................................. 185

6.8.2 Pin States in Idle Cycle........................................................................................ 195

6.9 Write Data Buffer Function .............................................................................................. 195

6.10 Bus Release....................................................................................................................... 196

6.10.1 Operation ............................................................................................................. 196

6.10.2 Pin States in External Bus Released State............................................................ 198

6.10.3 Transition Timing ................................................................................................ 199

6.11 Bus Arbitration.................................................................................................................. 200

6.11.1 Operation ............................................................................................................. 200

6.11.2 Bus Transfer Timing............................................................................................ 201

6.12 Bus Controller Operation in Reset.................................................................................... 202

6.13 Usage Notes...................................................................................................................... 202

6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 202

6.13.2 External Bus Release Function and Software Standby........................................ 202

6.13.3 External Bus Release Function and CBR Refreshing.......................................... 202

6.13.4 BREQO Output Timing....................................................................................... 203

Section 7 DMA Controller (DMAC)............................................................................. 205

7.1 Features............................................................................................................................. 205

Rev. 3.00, 07/04, page xx of l

7.2 Input/Output Pins.............................................................................................................. 207

7.3 Register Descriptions........................................................................................................ 207

7.3.1 Memory Address Registers (MARA and MARB)............................................... 208

7.3.2 I/O Address Registers (IOARA and IOARB)...................................................... 209

7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) .................................. 209

7.3.4 DMA Control Registers (DMACRA and DMACRB)......................................... 210

7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)............. 217

7.3.6 DMA Write Enable Register (DMAWER).......................................................... 229

7.3.7 DMA Terminal Control Register (DMATCR)..................................................... 231

7.4 Activation Sources............................................................................................................ 232

7.4.1 Activation by Internal Interrupt Request.............................................................. 232

7.4.2 Activation by External Request ........................................................................... 233

7.4.3 Activation by Auto-Request................................................................................. 233

7.5 Operation........................................................................................................................... 234

7.5.1 Transfer Modes.................................................................................................... 234

7.5.2 Sequential Mode .................................................................................................. 236

7.5.3 Idle Mode............................................................................................................. 238

7.5.4 Repeat Mode........................................................................................................ 240

7.5.5 Single Address Mode........................................................................................... 243

7.5.6 Normal Mode....................................................................................................... 246

7.5.7 Block Transfer Mode........................................................................................... 249

7.5.8 Basic Bus Cycles.................................................................................................. 255

7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles............................................... 255

7.5.10 DMA Transfer (Single Address Mode) Bus Cycles............................................. 263

7.5.11 Write Data Buffer Function ................................................................................. 269

7.5.12 Multi-Channel Operation..................................................................................... 270

7.5.13 Relation between DMAC and External Bus Requests and Refresh Cycles......... 271

7.5.14 DMAC and NMI Interrupts.................................................................................. 272

7.5.15 Forced Termination of DMAC Operation............................................................ 272

7.5.16 Clearing Full Address Mode................................................................................ 273

7.6 Interrupt Sources............................................................................................................... 274

7.7 Usage Notes...................................................................................................................... 275

7.7.1 DMAC Register Access during Operation........................................................... 275

7.7.2 Module Stop......................................................................................................... 277

7.7.3 Write Data Buffer Function ................................................................................. 277

7.7.4 TEND Output....................................................................................................... 277

7.7.5 Activation by Falling Edge on DREQ Pin........................................................... 278

7.7.6 Activation Source Acceptance............................................................................. 279

7.7.7 Internal Interrupt after End of Transfer................................................................ 279

7.7.8 Channel Re-Setting.............................................................................................. 279

Section 8 Data Transfer Controller (DTC)................................................................... 281

8.1 Features............................................................................................................................. 281

Rev. 3.00, 07/04, page xxi of l

8.2 Register Descriptions........................................................................................................ 282

8.2.1 DTC Mode Register A (MRA)............................................................................ 283

8.2.2 DTC Mode Register B (MRB)............................................................................. 284

8.2.3 DTC Source Address Register (SAR).................................................................. 284

8.2.4 DTC Destination Address Register (DAR).......................................................... 284

8.2.5 DTC Transfer Count Register A (CRA).............................................................. 284

8.2.6 DTC Transfer Count Register B (CRB)............................................................... 285

8.2.7 DTC Enable Registers A to G (DTCERA to DTCERG)..................................... 285

8.2.8 DTC Vector Register (DTVECR)........................................................................ 285

8.3 Activation Sources............................................................................................................ 286

8.4 Location of Register Information and DTC Vector Table................................................ 287

8.5 Operation .......................................................................................................................... 290

8.5.1 Normal Mode....................................................................................................... 292

8.5.2 Repeat Mode........................................................................................................ 293

8.5.3 Block Transfer Mode........................................................................................... 294

8.5.4 Chain Transfer ..................................................................................................... 295

8.5.5 Interrupts.............................................................................................................. 296

8.5.6 Operation Timing................................................................................................. 297

8.5.7 Number of DTC Execution States ....................................................................... 298

8.6 Procedures for Using DTC................................................................................................ 299

8.6.1 Activation by Interrupt......................................................................................... 299

8.6.2 Activation by Software........................................................................................ 299

8.7 Examples of Use of the DTC............................................................................................ 299

8.7.1 Normal Mode....................................................................................................... 299

8.7.2 Chain Transfer ..................................................................................................... 300

8.7.3 Chain Transfer when Counter = 0........................................................................ 301

8.7.4 Software Activation............................................................................................. 302

8.8 Usage Notes...................................................................................................................... 303

8.8.1 Module Stop Mode Setting.................................................................................. 303

8.8.2 On-Chip RAM ..................................................................................................... 303

8.8.3 DTCE Bit Setting................................................................................................. 303

8.8.4 DMAC Transfer End Interrupt............................................................................. 303

8.8.5 Chain Transfer ..................................................................................................... 303

Section 9 I/O Ports.............................................................................................................. 305

9.1 Port 1................................................................................................................................. 309

9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 309

9.1.2 Port 1 Data Register (P1DR)................................................................................ 310

9.1.3 Port 1 Register (PORT1)...................................................................................... 310

9.1.4 Pin Functions ....................................................................................................... 311

9.2 Port 2................................................................................................................................. 319

9.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 319

9.2.2 Port 2 Data Register (P2DR)................................................................................ 319

Rev. 3.00, 07/04, page xxii of l

9.2.3 Port 2 Register (PORT2)...................................................................................... 320

9.2.4 Pin Functions ....................................................................................................... 321

9.3 Port 3................................................................................................................................. 329

9.3.1 Port 3 Data Direction Register (P3DDR) ............................................................. 329

9.3.2 Port 3 Data Register (P3DR)................................................................................ 330

9.3.3 Port 3 Register (PORT3)...................................................................................... 330

9.3.4 Port 3 Open Drain Control Register (P3ODR)..................................................... 331

9.3.5 Port Function Control Register 2 (PFCR2).......................................................... 332

9.3.6 Pin Functions ....................................................................................................... 333

9.4 Port 4................................................................................................................................. 336

9.4.1 Port 4 Register (PORT4)...................................................................................... 336

9.4.2 Pin Functions ....................................................................................................... 337

9.5 Port 5................................................................................................................................. 339

9.5.1 Port 5 Data Direction Register (P5DDR) ............................................................. 339

9.5.2 Port 5 Data Register (P5DR)................................................................................ 339

9.5.3 Port 5 Register (PORT5)...................................................................................... 340

9.5.4 Pin Functions ....................................................................................................... 340

9.6 Port 8................................................................................................................................. 342

9.6.1 Port 8 Data Direction Register (P8DDR) ............................................................. 342

9.6.2 Port 8 Data Register (P8DR)................................................................................ 343

9.6.3 Port 8 Register (PORT8)...................................................................................... 343

9.6.4 Pin Functions ....................................................................................................... 344

9.7 Port 9................................................................................................................................. 345

9.7.1 Port 9 Register (PORT9)...................................................................................... 345

9.7.2 Pin Functions ....................................................................................................... 345

9.8 Port A................................................................................................................................ 346

9.8.1 Port A Data Direction Register (PADDR)........................................................... 347

9.8.2 Port A Data Register (PADR).............................................................................. 348

9.8.3 Port A Register (PORTA).................................................................................... 348

9.8.4 Port A MOS Pull-Up Control Register (PAPCR)................................................ 349

9.8.5 Port A Open Drain Control Register (PAODR)................................................... 349

9.8.6 Port Function Control Register 0 (PFCR0).......................................................... 350

9.8.7 Port Function Control Register 1 (PFCR1).......................................................... 350

9.8.8 Pin Functions ....................................................................................................... 351

9.8.9 Port A MOS Input Pull-Up States........................................................................ 353

9.9 Port B................................................................................................................................ 354

9.9.1 Port B Data Direction Register (PBDDR) ........................................................... 354

9.9.2 Port B Data Register (PBDR) .............................................................................. 355

9.9.3 Port B Register (PORTB) .................................................................................... 355

9.9.4 Port B MOS Pull-Up Control Register (PBPCR)................................................. 356

9.9.5 Pin Functions ....................................................................................................... 356

9.9.6 Port B MOS Input Pull-Up States........................................................................ 357

9.10 Port C................................................................................................................................ 358

Rev. 3.00, 07/04, page xxiii of l

9.10.1 Port C Data Direction Register (PCDDR) ........................................................... 358

9.10.2 Port C Data Register (PCDR).............................................................................. 359

9.10.3 Port C Register (PORTC) .................................................................................... 359

9.10.4 Port C MOS Pull-Up Control Register (PCPCR) ................................................ 360

9.10.5 Pin Functions ....................................................................................................... 360

9.10.6 Port C MOS Input Pull-Up States........................................................................ 361

9.11 Port D................................................................................................................................ 362

9.11.1 Port D Data Direction Register (PDDDR)........................................................... 362

9.11.2 Port D Data Register (PDDR).............................................................................. 362

9.11.3 Port D Register (PORTD).................................................................................... 363

9.11.4 Port D Pull-up Control Register (PDPCR) .......................................................... 363

9.11.5 Pin Functions ....................................................................................................... 364

9.11.6 Port D MOS Input Pull-Up States........................................................................ 364

9.12 Port E ................................................................................................................................ 365

9.12.1 Port E Data Direction Register (PEDDR)............................................................ 365

9.12.2 Port E Data Register (PEDR)............................................................................... 366

9.12.3 Port E Register (PORTE)..................................................................................... 366

9.12.4 Port E Pull-up Control Register (PEPCR) ........................................................... 367

9.12.5 Pin Functions ....................................................................................................... 367

9.12.6 Port E MOS Input Pull-Up States........................................................................ 368

9.13 Port F ................................................................................................................................ 368

9.13.1 Port F Data Direction Register (PFDDR) ............................................................ 369

9.13.2 Port F Data Register (PFDR)............................................................................... 370

9.13.3 Port F Register (PORTF)..................................................................................... 370

9.13.4 Pin Functions ....................................................................................................... 371

9.14 Port G................................................................................................................................ 374

9.14.1 Port G Data Direction Register (PGDDR)........................................................... 374

9.14.2 Port G Data Register (PGDR).............................................................................. 376

9.14.3 Port G Register (PORTG).................................................................................... 376

9.14.4 Pin Functions ....................................................................................................... 377

Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 379

10.1 Features............................................................................................................................. 379

10.2 Input/Output Pins.............................................................................................................. 383

10.3 Register Descriptions........................................................................................................ 384

10.3.1 Timer Control Register (TCR)............................................................................. 386

10.3.2 Timer Mode Register (TMDR)............................................................................ 391

10.3.3 Timer I/O Control Register (TIOR)..................................................................... 392

10.3.4 Timer Interrupt Enable Register (TIER).............................................................. 410

10.3.5 Timer Status Register (TSR)................................................................................ 412

10.3.6 Timer Counter (TCNT)........................................................................................ 415

10.3.7 Timer General Register (TGR)............................................................................ 415

10.3.8 Timer Start Register (TSTR) ............................................................................... 415

Rev. 3.00, 07/04, page xxiv of l

10.3.9 Timer Synchronous Register (TSYR).................................................................. 416

10.4 Operation........................................................................................................................... 417

10.4.1 Basic Functions.................................................................................................... 417

10.4.2 Synchronous Operation........................................................................................ 422

10.4.3 Buffer Operation.................................................................................................. 424

10.4.4 Cascaded Operation ............................................................................................. 428

10.4.5 PWM Modes........................................................................................................ 430

10.4.6 Phase Counting Mode.......................................................................................... 435

10.5 Interrupts........................................................................................................................... 441

10.6 DTC Activation................................................................................................................. 443

10.7 DMAC Activation ............................................................................................................. 443

10.8 A/D Converter Activation................................................................................................. 443

10.9 Operation Timing.............................................................................................................. 444

10.9.1 Input/Output Timing............................................................................................ 444

10.9.2 Interrupt Signal Timing........................................................................................ 447

10.10 Usage Notes...................................................................................................................... 450

10.10.1 Module Stop Mode Setting.................................................................................. 450

10.10.2 Input Clock Restrictions....................................................................................... 450

10.10.3 Caution on Cycle Setting..................................................................................... 451

10.10.4 Contention between TCNT Write and Clear Operations..................................... 451

10.10.5 Contention between TCNT Write and Increment Operations.............................. 452

10.10.6 Contention between TGR Write and Compare Match......................................... 453

10.10.7 Contention between Buffer Register Write and Compare Match ........................ 453

10.10.8 Contention between TGR Read and Input Capture.............................................. 454

10.10.9 Contention between TGR Write and Input Capture............................................. 455

10.10.10 Contention between Buffer Register Write and Input Capture ........................ 455

10.10.11 Contention between Overflow/Underflow and Counter Clearing.................... 456

10.10.12 Contention between TCNT Write and Overflow/Underflow........................... 457

10.10.13 Multiplexing of I/O Pins.................................................................................. 457

10.10.14 Interrupts and Module Stop Mode................................................................... 457

Section 11 Programmable Pulse Generator (PPG) .................................................... 459

11.1 Features............................................................................................................................. 459

11.2 Input/Output Pins.............................................................................................................. 461

11.3 Register Descriptions........................................................................................................ 461

11.3.1 Next Data Enable Registers H, L (NDERH, NDERL)......................................... 462

11.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 463

11.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 464

11.3.4 PPG Output Control Register (PCR).................................................................... 466

11.3.5 PPG Output Mode Register (PMR)...................................................................... 467

11.4 Operation........................................................................................................................... 469

11.4.1 Output Timing...................................................................................................... 470

11.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 471

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11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 472

11.4.4 Non-Overlapping Pulse Output............................................................................ 473

11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output.............................. 474

11.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase

Complementary Non-Overlapping Output)......................................................... 475

11.4.7 Inverted Pulse Output .......................................................................................... 477

11.4.8 Pulse Output Triggered by Input Capture............................................................ 478

11.5 Usage Notes...................................................................................................................... 478

11.5.1 Module Stop Mode Setting.................................................................................. 478

11.5.2 Operation of Pulse Output Pins............................................................................ 478

Section 12 8-Bit Timers (TMR)...................................................................................... 479

12.1 Features............................................................................................................................. 479

12.2 Input/Output Pins.............................................................................................................. 481

12.3 Register Descriptions........................................................................................................ 481

12.3.1 Timer Counter (TCNT)........................................................................................ 481

12.3.2 Time Constant Register A (TCORA)................................................................... 482

12.3.3 Time Constant Register B (TCORB)................................................................... 482

12.3.4 Timer Control Register (TCR)............................................................................. 482

12.3.5 Timer Control/Status Register (TCSR)................................................................ 484

12.4 Operation .......................................................................................................................... 487

12.4.1 Pulse Output......................................................................................................... 487

12.5 Operation Timing........................................................................................................... ... 488

12.5.1 TCNT Incrementation Timing............................................................................. 488

12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs................. 489

12.5.3 Timing of Timer Output when Compare-Match Occurs...................................... 489

12.5.4 Timing of Compare Match Clear......................................................................... 490

12.5.5 Timing of TCNT External Reset.......................................................................... 490

12.5.6 Timing of Overflow Flag (OVF) Setting............................................................. 491

12.6 Operation with Cascaded Connection............................................................................... 491

12.6.1 16-Bit Counter Mode........................................................................................... 491

12.6.2 Compare Match Count Mode............................................................................... 492

12.7 Interrupts........................................................................................................................... 492

12.7.1 Interrupt Sources and DTC Activation ................................................................ 492

12.7.2 A/D Converter Activation.................................................................................... 493

12.8 Usage Notes...................................................................................................................... 494

12.8.1 Contention between TCNT Write and Clear........................................................ 494

12.8.2 Contention between TCNT Write and Increment................................................ 494

12.8.3 Contention between TCOR Write and Compare Match ...................................... 495

12.8.4 Contention between Compare Matches A and B................................................. 496

12.8.5 Switching of Internal Clocks and TCNT Operation ............................................ 497

12.8.6 Mode Setting with Cascaded Connection............................................................ 499

12.8.7 Interrupts in Module Stop Mode.......................................................................... 499

Rev. 3.00, 07/04, page xxvi of l

Section 13 Watchdog Timer............................................................................................. 501

13.1 Features............................................................................................................................. 501

13.2 Input/Output Pin................................................................................................................ 502

13.3 Register Descriptions........................................................................................................ 503

13.3.1 Timer Counter (TCNT)........................................................................................ 503

13.3.2 Timer Control/Status Register (TCSR)................................................................ 503

13.3.3 Reset Control/Status Register (RSTCSR)............................................................ 505

13.4 Operation........................................................................................................................... 506

13.4.1 Watchdog Timer Mode........................................................................................ 506

13.4.2 Interval Timer Mode............................................................................................ 507

13.5 Interrupts........................................................................................................................... 508

13.6 Usage Notes ...................................................................................................................... 508

13.6.1 Notes on Register Access..................................................................................... 508

13.6.2 Contention between Timer Counter (TCNT) Write and Increment..................... 509

13.6.3 Changing Value of CKS2 to CKS0...................................................................... 510

13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 510

13.6.5 Internal Reset in Watchdog Timer Mode............................................................. 510

13.6.6 System Reset by WDTOVF Signal...................................................................... 511

Section 14 Serial Communication Interface (SCI, IrDA)........................................ 513

14.1 Features............................................................................................................................. 513

14.2 Input/Output Pins.............................................................................................................. 515

14.3 Register Descriptions........................................................................................................ 516

14.3.1 Receive Shift Register (RSR) .............................................................................. 517

14.3.2 Receive Data Register (RDR).............................................................................. 517

14.3.3 Transmit Data Register (TDR)............................................................................. 517

14.3.4 Transmit Shift Register (TSR)............................................................................. 518

14.3.5 Serial Mode Register (SMR)................................................................................ 518

14.3.6 Serial Control Register (SCR).............................................................................. 522

14.3.7 Serial Status Register (SSR) ................................................................................ 526

14.3.8 Smart Card Mode Register (SCMR).................................................................... 533

14.3.9 Bit Rate Register (BRR) ...................................................................................... 534

14.3.10 IrDA Control Register (IrCR).............................................................................. 543

14.3.11 Serial Extension Mode Register (SEMR)............................................................ 544

14.4 Operation in Asynchronous Mode.................................................................................... 546

14.4.1 Data Transfer Format........................................................................................... 546

14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 548

14.4.3 Clock.................................................................................................................... 549

14.4.4 SCI Initialization (Asynchronous Mode)............................................................. 550

14.4.5 Data Transmission (Asynchronous Mode)........................................................... 551

14.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 553

14.5 Multiprocessor Communication Function......................................................................... 557

14.5.1 Multiprocessor Serial Data Transmission ............................................................ 558

Rev. 3.00, 07/04, page xxvii of l

14.5.2 Multiprocessor Serial Data Reception ................................................................. 560

14.6 Operation in Clocked Synchronous Mode........................................................................ 564

14.6.1 Clock.................................................................................................................... 564

14.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 565

14.6.3 Serial Data Transmission (Clocked Synchronous Mode).................................... 566

14.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 569

14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous

Mode)................................................................................................................... 571

14.7 Operation in Smart Card Interface Mode.......................................................................... 573

14.7.1 Pin Connection Example...................................................................................... 573

14.7.2 Data Format (Except for Block Transfer Mode).................................................. 573

14.7.3 Block Transfer Mode........................................................................................... 575

14.7.4 Receive Data Sampling Timing and Reception Margin....................................... 575

14.7.5 Initialization......................................................................................................... 576

14.7.6 Data Transmission (Except for Block Transfer Mode)........................................ 577

14.7.7 Serial Data Reception (Except for Block Transfer Mode)................................... 580

14.7.8 Clock Output Control........................................................................................... 581

14.8 IrDA Operation................................................................................................................. 583

14.9 SCI Interrupts.................................................................................................................... 586

14.9.1 Interrupts in Normal Serial Communication Interface Mode .............................. 586

14.9.2 Interrupts in Smart Card Interface Mode............................................................. 587

14.10 Usage Notes...................................................................................................................... 589

14.10.1 Module Stop Mode Setting.................................................................................. 589

14.10.2 Break Detection and Processing .......................................................................... 589

14.10.3 Mark State and Break Sending............................................................................. 589

14.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode

Only).................................................................................................................... 589

14.10.5 Relation between Writes to TDR and the TDRE Flag......................................... 590

14.10.6 Restrictions on Use of DMAC* or DTC.............................................................. 590

14.10.7 Operation in Case of Mode Transition................................................................. 590

Section 15 I2C Bus Interface2 (IIC2) (Option)........................................................... 595

15.1 Features............................................................................................................................. 595

15.2 Input/Output Pins.............................................................................................................. 597

15.3 Register Descriptions........................................................................................................ 598

15.3.1 I

15.3.2 I

15.3.3 I

15.3.4 I

15.3.5 I

15.3.6 Slave Address Register (SAR)............................................................................. 607

15.3.7 I

15.3.8 I

Rev. 3.00, 07/04, page xxviii of l

C Bus Control Register A (ICCRA).................................................................. 599

C Bus Control Register B (ICCRB).................................................................. 601

C Bus Mode Register (ICMR)........................................................................... 602

C Bus Interrupt Enable Register (ICIER).......................................................... 603

C Bus Status Register (ICSR)........................................................................... 605

C Bus Transmit Data Register (ICDRT)........................................................... 607

C Bus Receive Data Register (ICDRR)............................................................. 607

15.3.9 I2C Bus Shift Register (ICDRS)........................................................................... 607

15.4 Operation........................................................................................................................... 608

15.4.1 I

C Bus Format .................................................................................................... 608

15.4.2 Master Transmit Operation.................................................................................. 609

15.4.3 Master Receive Operation.................................................................................... 611

15.4.4 Slave Transmit Operation .................................................................................... 613

15.4.5 Slave Receive Operation ...................................................................................... 615

15.4.6 Noise Canceler..................................................................................................... 617

15.4.7 Example of Use.................................................................................................... 617

15.5 Interrupt Request............................................................................................................... 622

15.6 Bit Synchronous Circuit .................................................................................................... 622

Section 16 A/D Converter................................................................................................. 625

16.1 Features............................................................................................................................. 625

16.2 Input/Output Pins.............................................................................................................. 627

16.3 Register Descriptions........................................................................................................ 628

16.3.1 A/D Data Registers A to H (ADDRA to ADDRH).............................................. 628

16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 629

16.3.3 A/D Control Register (ADCR) ............................................................................ 631

16.4 Operation........................................................................................................................... 632

16.4.1 Single Mode......................................................................................................... 632

16.4.2 Scan Mode ........................................................................................................... 632

16.4.3 Input Sampling and A/D Conversion Time.......................................................... 633

16.4.4 External Trigger Input Timing............................................................................. 635

16.5 Interrupts........................................................................................................................... 635

16.6 A/D Conversion Precision Definitions.............................................................................. 636

16.7 Usage Notes ...................................................................................................................... 638

16.7.1 Module Stop Mode Setting .................................................................................. 638

16.7.2 Permissible Signal Source Impedance................................................................. 638

16.7.3 Influences on Absolute Precision......................................................................... 639

16.7.4 Setting Range of Analog Power Supply and Other Pins...................................... 639

16.7.5 Notes on Board Design........................................................................................ 639

16.7.6 Notes on Noise Countermeasures ........................................................................ 640

Section 17 D/A Converter................................................................................................. 643

17.1 Features............................................................................................................................. 643

17.2 Input/Output Pins.............................................................................................................. 645

17.3 Register Descriptions........................................................................................................ 645

17.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)............................................ 645

17.3.2 D/A Control Register 23 (DACR23).................................................................... 645

17.4 Operation........................................................................................................................... 647

17.5 Usage Notes ...................................................................................................................... 648

17.5.1 Setting for Module Stop Mode............................................................................. 648

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17.5.2 D/A Output Hold Function in Software Standby Mode....................................... 648

Section 18 RAM.................................................................................................................. 649

Section 19 Flash Memory (0.35-µm F-ZTAT Version)........................................... 651

19.1 Features............................................................................................................................. 651

19.2 Mode Transitions .............................................................................................................. 652

19.3 Block Configuration.......................................................................................................... 656

19.4 Input/Output Pins.............................................................................................................. 658

19.5 Register Descriptions........................................................................................................ 658

19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 658

19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 660

19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 660

19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 661

19.5.5 RAM Emulation Register (RAMER)................................................................... 662

19.6 On-Board Programming Modes........................................................................................ 663

19.6.1 Boot Mode ........................................................................................................... 664

19.6.2 User Program Mode............................................................................................. 667

19.7 Flash Memory Emulation in RAM ................................................................................... 668

19.8 Flash Memory Programming/Erasing............................................................................... 670

19.8.1 Program/Program-Verify..................................................................................... 670

19.8.2 Erase/Erase-Verify............................................................................................... 672

19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 672

19.9 Program/Erase Protection ................................................................................................. 674

19.9.1 Hardware Protection ............................................................................................ 674

19.9.2 Software Protection.............................................................................................. 674

19.9.3 Error Protection.................................................................................................... 674

19.10 Programmer Mode............................................................................................................ 675

19.11 Power-Down States for Flash Memory ............................................................................. 675

19.12 Usage Notes...................................................................................................................... 675

Section 20 Flash Memory (0.18-µm F-ZTAT Version)........................................... 679

20.1 Features............................................................................................................................. 679

20.1.1 Operating Mode................................................................................................... 682

20.1.2 Mode Comparison................................................................................................ 683

20.1.3 Flash MAT Configuration.................................................................................... 684

20.1.4 Block Division..................................................................................................... 685

20.1.5 Programming/Erasing Interface........................................................................... 686

20.2 Input/Output Pins.............................................................................................................. 688

20.3 Register Descriptions........................................................................................................ 688

20.3.1 Programming/Erasing Interface Register............................................................. 689

20.3.2 Programming/Erasing Interface Parameter.......................................................... 696

20.3.3 Flash Vector Address Control Register (FVACR)............................................... 706

Rev. 3.00, 07/04, page xxx of l

20.4 On-Board Programming Mode ......................................................................................... 707

20.4.1 Boot Mode ........................................................................................................... 707

20.4.2 User Program Mode............................................................................................. 711

20.4.3 User Boot Mode................................................................................................... 721

20.4.4 Procedure Program and Storable Area for Programming Data............................ 725

20.5 Protection.......................................................................................................................... 735

20.5.1 Hardware Protection ............................................................................................ 735

20.5.2 Software Protection.............................................................................................. 736

20.5.3 Error Protection.................................................................................................... 736

20.6 Switching between User MAT and User Boot MAT........................................................ 737

20.7 Programmer Mode ............................................................................................................ 739

20.8 Serial Communication Interface Specification for Boot Mode......................................... 739

20.9 Usage Notes ...................................................................................................................... 764

Section 21 Mask ROM....................................................................................................... 765

Section 22 Clock Pulse Generator.................................................................................. 767

22.1 Register Descriptions........................................................................................................ 767

22.1.1 System Clock Control Register (SCKCR)........................................................... 767

22.1.2 PLL Control Register (PLLCR)........................................................................... 769

22.2 Oscillator........................................................................................................................... 770

22.2.1 Connecting a Crystal Oscillator........................................................................... 770

22.2.2 External Clock Input............................................................................................ 771

22.3 PLL Circuit ....................................................................................................................... 772

22.4 Frequency Divider............................................................................................................. 773

22.5 Usage Notes ...................................................................................................................... 773

22.5.1 Notes on Clock Pulse Generator.......................................................................... 773

22.5.2 Notes on Oscillator .............................................................................................. 773

22.5.3 Notes on Board Design........................................................................................ 774

Section 23 Power-Down Modes...................................................................................... 775

23.1 Register Descriptions........................................................................................................ 778

23.1.1 Standby Control Register (SBYCR) .................................................................... 778

23.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 780

23.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH,

EXMSTPCRL)..................................................................................................... 781

23.2 Operation........................................................................................................................... 782

23.2.1 Clock Division Mode........................................................................................... 782

23.2.2 Sleep Mode .......................................................................................................... 782

23.2.3 Software Standby Mode....................................................................................... 783

23.2.4 Hardware Standby Mode ..................................................................................... 785

23.2.5 Module Stop Mode .............................................................................................. 787

23.2.6 All-Module-Clocks-Stop Mode........................................................................... 788

Rev. 3.00, 07/04, page xxxi of l

23.3 φ Clock Output Control..................................................................................................... 788

23.4 Usage Notes...................................................................................................................... 789

23.4.1 I/O Port Status...................................................................................................... 789

23.4.2 Current Dissipation during Oscillation Stabilization Standby Period.................. 789

23.4.3 DMAC/DTC Module Stop................................................................................... 789

23.4.4 On-Chip Peripheral Module Interrupts................................................................ 789

23.4.5 Writing to MSTPCR, EXMSTPCR ..................................................................... 789

23.4.6 Notes on Clock Division Mode............................................................................ 790

Section 24 List of Registers.............................................................................................. 791

24.1 Register Addresses (Address Order)................................................................................. 792

24.2 Register Bits...................................................................................................................... 802

24.3 Register States in Each Operating Mode .......................................................................... 815

Section 25 Electrical Characteristics ............................................................................. 825

25.1 Electrical Characteristics of Masked ROM and ROMless Versions................................. 825

25.1.1 Absolute Maximum Ratings................................................................................ 825

25.1.2 DC Characteristics............................................................................................... 826

25.1.3 AC Characteristics............................................................................................... 829

25.1.4 A/D Conversion Characteristics........................................................................... 860

25.1.5 D/A Conversion Characteristics........................................................................... 860

25.2 Electrical Characteristics of 0.35 µm F-ZTAT Version.................................................... 861

25.2.1 Absolute Maximum Ratings................................................................................ 861

25.2.2 DC Characteristics............................................................................................... 862

25.2.3 A/D Conversion Characteristics........................................................................... 872

25.2.4 D/A Conversion Characteristics........................................................................... 872

25.2.5 Flash Memory Characteristics ............................................................................. 873

25.3 Electrical Characteristics for 0.18 µm F-ZTAT Version.................................................. 875

25.3.1 Absolute Maximum Ratings................................................................................ 875

25.3.2 DC Characteristics............................................................................................... 876

25.3.3 AC Characteristics............................................................................................... 879

25.3.4 A/D Conversion Characteristics........................................................................... 887

25.3.5 D/A Conversion Characteristics........................................................................... 887

25.3.6 Flash Memory Characteristics ............................................................................. 888

25.4 Usage Note........................................................................................................................ 889

Appendix.................................................................................................................................. 891

A. I/O Port States in Each Pin State....................................................................................... 891

B. Product Lineup.................................................................................................................. 898

C. Package Dimensions ......................................................................................................... 899

D. Bus State during Execution of Instructions....................................................................... 901

Index .......................................................................................................................................... 923

Rev. 3.00, 07/04, page xxxii of l

Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram of H8S/2367, H8S/2365, and H8S/2363....................... 3

Figure 1.2 Internal Block Diagram of H8S/2366.................................................................. 4

Figure 1.3 Internal Block Diagram of H8S/2368.................................................................. 5

Figure 1.4 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363.................................. 6

Figure 1.5 Pin Arrangement of H8S/2366............................................................................. 7

Figure 1.6 Pin Arrangement of H8S/2368............................................................................. 8

Figure 1.7 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363.................................. 9

Figure 1.8 Pin Arrangement of H8S/2366............................................................................. 10

Section 2 CPU

Figure 2.1 Exception Vector Table (Normal Mode) ............................................................. 27

Figure 2.2 Stack Structure in Normal Mode ......................................................................... 27

Figure 2.3 Exception Vector Table (Advanced Mode) ......................................................... 28

Figure 2.4 Stack Structure in Advanced Mode...................................................................... 29

Figure 2.5 Memory Map ....................................................................................................... 30

Figure 2.6 CPU Internal Registers......................................................................................... 31

Figure 2.7 Usage of General Registers.................................................................................. 32

Figure 2.8 Stack..................................................................................................................... 33

Figure 2.9 General Register Data Formats (1) ...................................................................... 36

Figure 2.9 General Register Data Formats (2) ...................................................................... 37

Figure 2.10 Memory Data Formats......................................................................................... 38

Figure 2.11 Instruction Formats (Examples) ........................................................................... 50

Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode................. 53

Figure 2.13 State Transitions................................................................................................... 57

Section 3 MCU Operating Modes

Figure 3.1 H8S/2368 Memory Map (1)................................................................................. 65

Figure 3.2 H8S/2368 Memory Map (2)................................................................................. 66

Figure 3.3 H8S/2367 Memory Map (1)................................................................................. 67

Figure 3.4 H8S/2367 Memory Map (2)................................................................................. 68

Figure 3.5 H8S/2366 Memory Map (1)................................................................................. 69

Figure 3.6 H8S/2366 Memory Map (2)................................................................................. 70

Figure 3.7 H8S/2365 Memory Map (1)................................................................................. 71

Figure 3.8 H8S/2365 Memory Map (2)................................................................................. 72

Figure 3.9 H8S/2363 Memory Map...................................................................................... 73

Section 4 Exception Handling

Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)....................... 78

Rev. 3.00, 07/04, page xxxiii of l

Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled)...................... 79

Figure 4.3 Stack Status after Exception Handling................................................................. 82

Figure 4.4 Operation when SP Value Is Odd........................................................................ 83

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller ................................................................ 86

Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ...................................................... 97

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control

Mode 0................................................................................................................. 104

Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control

Mode 2................................................................................................................. 106

Figure 5.5 Interrupt Exception Handling............................................................................... 107

Figure 5.6 Contention between Interrupt Generation and Disabling..................................... 110

Section 6 Bus Controller (BSC)

Figure 6.1 Block Diagram of Bus Controller........................................................................ 114

Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)..................... 123

Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space

and RDNn = 0)..................................................................................................... 125

Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle,

Full Access)......................................................................................................... 133

Figure 6.5 Area Divisions ..................................................................................................... 139

Figure 6.6 CSn Signal Output Timing (n = 0 to 7)................................................................ 143

Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space)........................ 144

Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space) ...................... 145

Figure 6.9 Bus Timing for 8-Bit, 2-State Access Space........................................................ 146

Figure 6.10 Bus Timing for 8-Bit, 3-State Access Space........................................................ 147

Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)....... 148

Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)......... 149

Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................. 150

Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)....... 151

Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)......... 152

Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................. 153

Figure 6.17 Example of Wait State Insertion Timing ............................................................. 155

Figure 6.18 Example of Read Strobe Timing.......................................................................... 156

Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended.................. 157

Figure 6.20 DRAM Basic Access Timing (RAST = 0, CAST = 0)........................................ 161

Figure 6.21 Example of Access Timing with 3-State Column Address Output Cycle

(RAST = 0).......................................................................................................... 162

Figure 6.22 Example of Access Timing when RAS Signal Goes Low from Beginning

State (CAST = 0)......................................................................................... 163

of T

Figure 6.23 Example of Timing with One Row Address Output Maintenance State

(RAST = 0, CAST = 0)........................................................................................ 164

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Figure 6.24 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0)... 165

Figure 6.25 Example of Wait State Insertion Timing (2-State Column Address Output)....... 167

Figure 6.26 Example of Wait State Insertion Timing (3-State Column Address Output)....... 168

Figure 6.27 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) ....... 169

Figure 6.28 Example of 2-CAS DRAM Connection............................................................... 170

Figure 6.29 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0)............................ 171

Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1)............................ 172

Figure 6.31 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0)..... 173

Figure 6.32 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0).......... 174

Figure 6.33 RTCNT Operation ............................................................................................... 175

Figure 6.34 Compare Match Timing....................................................................................... 175

Figure 6.35 CBR Refresh Timing ........................................................................................... 176

Figure 6.36 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)............. 176

Figure 6.37 Example of CBR Refresh Timing (CBRM = 1)................................................... 177

Figure 6.38 Self-Refresh Timing............................................................................................. 178

Figure 6.39 Example of Timing when Precharge Time after Self-Refreshing Is Extended

by 2 States............................................................................................................ 179

Figure 6.40 Example of DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0)....... 180

Figure 6.41 Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1)....... 181

Figure 6.42 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle).......... 183

Figure 6.43 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle).......... 184

Figure 6.44 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)......... 185

Figure 6.45 Example of Idle Cycle Operation (Write after Read)........................................... 186

Figure 6.46 Example of Idle Cycle Operation (Read after Write)........................................... 187

Figure 6.47 Relationship between Chip Select (CS) and Read (RD)...................................... 188

Figure 6.48 Example of DRAM Full Access after External Read (CAST = 0) ...................... 188

Figure 6.49 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads

in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)....................................... 189

Figure 6.50 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)

(IDLC = 0, RAST = 0, CAST = 0) ...................................................................... 189

Figure 6.51 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads

in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)....................................... 190

Figure 6.52 Example of Idle Cycle Operation after DRAM Access (Write after Read)

(IDLC = 0, RAST = 0, CAST = 0) ...................................................................... 191

Figure 6.53 Example of Idle Cycle Operation after DRAM Write Access

(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)..................................................... 192

Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read

and Write Accesses to DRAM Space in RAS Down Mode................................. 194

Figure 6.55 Example of Timing when Write Data Buffer Function is Used........................... 196

Figure 6.56 Bus Released State Transition Timing................................................................. 199

Section 7 DMA Controller (DMAC)

Figure 7.1 Block Diagram of DMAC.................................................................................... 206

Rev. 3.00, 07/04, page xxxv of l

Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A).......................................... 230

Figure 7.3 Operation in Sequential Mode............................................................................. 237

Figure 7.4 Example of Sequential Mode Setting Procedure ................................................. 238

Figure 7.5 Operation in Idle Mode........................................................................................ 239

Figure 7.6 Example of Idle Mode Setting Procedure............................................................ 240

Figure 7.7 Operation in Repeat mode ................................................................................... 242

Figure 7.8 Example of Repeat Mode Setting Procedure....................................................... 243

Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified)......... 245

Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential Mode is

Specified)............................................................................................................. 246

Figure 7.11 Operation in Normal Mode.................................................................................. 248

Figure 7.12 Example of Normal Mode Setting Procedure...................................................... 249

Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) ............................................. 251

Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ............................................. 252

Figure 7.15 Operation Flow in Block Transfer Mode............................................................. 253

Figure 7.16 Example of Block Transfer Mode Setting Procedure.......................................... 254

Figure 7.17 Example of DMA Transfer Bus Timing.............................................................. 255

Figure 7.18 Example of Short Address Mode Transfer........................................................... 256

Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)....................................... 257

Figure 7.20 Example of Full Address Mode Transfer (Burst Mode)...................................... 258

Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)....................... 259

Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer............. 260

Figure 7.23 Example of DREQ Pin Falling Edge Activa t ed Block Transfer Mode Transfer . 26 1

Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer................ 262

Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer.... 263

Figure 7.26 Example of Single Address Mode Transfer (Byte Read)..................................... 264

Figure 7.27 Example of Single Address Mode (Word Read) Transfer................................... 264

Figure 7.28 Example of Single Address Mode Transfer (Byte Write).................................... 265

Figure 7.29 Example of Single Address Mode Transfer (Word Write).................................. 266

Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer. 267

Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer.... 268

Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function.............. 269

Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function............ 270

Figure 7.34 Example of Multi-Channel Transfer.................................................................... 271

Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI

Interrupt ............................................................................................................... 272

Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation................... 273

Figure 7.37 Example of Procedure for Clearing Full Address Mode...................................... 274

Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt................................... 275

Figure 7.39 DMAC Register Update Timing.......................................................................... 276

Figure 7.40 Contention between DMAC Register Update and CPU Read............................. 276

Figure 7.41 Example in which Low Level is Not Output at TEND Pin.................................. 278

Rev. 3.00, 07/04, page xxxvi of l

Section 8 Data Transfer Controller (DTC)

Figure 8.1 Block Diagram of DTC........................................................................................ 282

Figure 8.2 Block Diagram of DTC Activation Source Control............................................. 287

Figure 8.3 Correspondence between DTC Vector Address and Register Information.......... 288

Figure 8.4 Correspondence between DTC Vector Address and Register Information.......... 288

Figure 8.5 Flowchart of DTC Operation............................................................................... 291

Figure 8.6 Memory Mapping in Normal Mode..................................................................... 293

Figure 8.7 Memory Mapping in Repeat Mode...................................................................... 294

Figure 8.8 Memory Mapping in Block Transfer Mode......................................................... 295

Figure 8.9 Operation of Chain Transfer................................................................................ 296

Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)................ 297

Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode,

with Block Size of 2) ........................................................................................... 297

Figure 8.12 DTC Operation Timing (Example of Chain Transfer)......................................... 297

Figure 8.13 Chain Transfer when Counter = 0........................................................................ 302

Section 10 16-Bit Timer Pulse Unit (TPU)

Figure 10.1 Block Diagram of TPU........................................................................................ 382

Figure 10.2 Example of Counter Operation Setting Procedure............................................... 417

Figure 10.3 Free-Running Counter Operation......................................................................... 418

Figure 10.4 Periodic Counter Operation ................................................................................. 419

Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match.......... 419

Figure 10.6 Example of 0 Output/1 Output Operation............................................................ 420

Figure 10.7 Example of Toggle Output Operation.................................................................. 420

Figure 10.8 Example of Setting Procedure for Input Capture Operation................................ 421

Figure 10.9 Example of Input Capture Operation................................................................... 422

Figure 10.10 Example of Synchronous Operation Setting Procedure....................................... 423

Figure 10.11 Example of Synchronous Operation .................................................................... 424

Figure 10.12 Compare Match Buffer Operation ....................................................................... 425

Figure 10.13 Input Capture Buffer Operation........................................................................... 425

Figure 10.14 Example of Buffer Operation Setting Procedure ................................................. 426

Figure 10.15 Example of Buffer Operation (1)......................................................................... 427

Figure 10.16 Example of Buffer Operation (2)......................................................................... 428

Figure 10.17 Cascaded Operation Setting Procedure................................................................ 429

Figure 10.18 Example of Cascaded Operation (1).................................................................... 429

Figure 10.19 Example of Cascaded Operation (2).................................................................... 430

Figure 10.20 Example of PWM Mode Setting Procedure......................................................... 432

Figure 10.21 Example of PWM Mode Operation (1)................................................................ 433

Figure 10.22 Example of PWM Mode Operation (2)................................................................ 433

Figure 10.23 Example of PWM Mode Operation (3)................................................................ 434

Figure 10.24 Example of Phase Counting Mode Setting Procedure......................................... 435

Figure 10.25 Example of Phase Counting Mode 1 Operation................................................... 436

Figure 10.26 Example of Phase Counting Mode 2 Operation................................................... 437

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Figure 10.27 Example of Phase Counting Mode 3 Operation................................................... 438

Figure 10.28 Example of Phase Counting Mode 4 Operation................................................... 439

Figure 10.29 Phase Counting Mode Application Example....................................................... 440

Figure 10.30 Count Timing in Internal Clock Operation.......................................................... 444

Figure 10.31 Count Timing in External Clock Operation......................................................... 444

Figure 10.32 Output Compare Output Timing.......................................................................... 445

Figure 10.33 Input Capture Input Signal Timing...................................................................... 445

Figure 10.34 Counter Clear Timing (Compare Match)............................................................. 446

Figure 10.35 Counter Clear Timing (Input Capture)................................................................. 446

Figure 10.36 Buffer Operation Timing (Compare Match)........................................................ 446

Figure 10.37 Buffer Operation Timing (Input Capture)............................................................ 447

Figure 10.38 TGI Interrupt Timing (Compare Match).............................................................. 447

Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................. 448

Figure 10.40 TCIV Interrupt Setting Timing............................................................................ 448

Figure 10.41 TCIU Interrupt Setting Timing............................................................................ 449

Figure 10.42 Timing for Status Flag Clearing by CPU............................................................. 449

Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC* Activation............................ 450

Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... 451

Figure 10.45 Contention between TCNT Write and Clear Operations..................................... 452

Figure 10.46 Contention between TCNT Write and Increment Operations.............................. 452

Figure 10.47 Contention between TGR Write and Compare Match......................................... 453

Figure 10.48 Contention between Buffer Register Write and Compare Match........................ 454

Figure 10.49 Contention between TGR Read and Input Capture.............................................. 454

Figure 10.50 Contention between TGR Write and Input Capture............................................. 455

Figure 10.51 Contention between Buffer Register Write and Input Capture............................ 456

Figure 10.52 Contention between Overflow and Counter Clearing.......................................... 456

Figure 10.53 Contention between TCNT Write and Overflow................................................. 457

Section 11 Programmable Pulse Generator (PPG)

Figure 11.1 Block Diagram of PPG ........................................................................................ 460

Figure 11.2 Overview Diagram of PPG.................................................................................. 469

Figure 11.3 Timing of Transfer and Output of NDR Contents (Example).............................. 470

Figure 11.4 Setup Procedure for Normal Pulse Output (Example)......................................... 471

Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output).................................. 472

Figure 11.6 Non-Overlapping Pulse Output............................................................................ 473

Figure 11.7 Non-Overlapping Operation and NDR Write Timing.......................................... 474

Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)......................... 475

Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)............ 476

Figure 11.10 Inverted Pulse Output (Example)......................................................................... 477

Figure 11.11 Pulse Output Triggered by Input Capture (Example) .......................................... 478

Section 12 8-Bit Timers (TMR)

Figure 12.1 Block Diagram of 8-Bit Timer Module ............................................................... 480

Rev. 3.00, 07/04, page xxxviii of l

Figure 12.2 Example of Pulse Output ..................................................................................... 488

Figure 12.3 Count Timing for Internal Clock Input................................................................ 488

Figure 12.4 Count Timing for External Clock Input............................................................... 489

Figure 12.5 Timing of CMF Setting........................................................................................ 489

Figure 12.6 Timing of Timer Output....................................................................................... 490

Figure 12.7 Timing of Compare Match Clear......................................................................... 490

Figure 12.8 Timing of Clearance by External Reset............................................................... 491

Figure 12.9 Timing of OVF Setting ........................................................................................ 491

Figure 12.10 Contention between TCNT Write and Clear........................................................ 494

Figure 12.11 Contention between TCNT Write and Increment................................................ 495

Figure 12.12 Contention between TCOR Write and Compare Match ...................................... 496

Section 13 Watchdog Timer

Figure 13.1 Block Diagram of WDT....................................................................................... 502

Figure 13.2 Operation in Watchdog Timer Mode................................................................... 507

Figure 13.3 Operation in Interval Timer Mode....................................................................... 508

Figure 13.4 Writing to TCNT, TCSR, and RSTCSR.............................................................. 509

Figure 13.5 Contention between TCNT Write and Increment................................................ 510

Figure 13.6 Circuit for System Reset by WDTOVF Signal (Example) .................................. 511

Section 14 Serial Communication Interface (SCI, IrDA)

Figure 14.1 Block Diagram of SCI ......................................................................................... 514

Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data,

Parity, Two Stop Bits).......................................................................................... 546

Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode..................................... 548

Figure 14.4 Relation between Output Clock and Transfer Data Phase

(Asynchronous Mode) ......................................................................................... 549

Figure 14.5 Sample SCI Initialization Flowchart.................................................................... 550

Figure 14.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 551

Figure 14.7 Sample Serial Transmission Flowchart................................................................ 552

Figure 14.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,

One Stop Bit)....................................................................................................... 553

Figure 14.9 Sample Serial Reception Data Flowchart (1)....................................................... 555

Figure 14.9 Sample Serial Reception Data Flowchart (2)....................................................... 556

Figure 14.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)......................................... 558

Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart....................................... 559

Figure 14.12 Example of SCI Operation in Reception (Example with 8-Bit Data,

Multiprocessor Bit, One Stop Bit) ....................................................................... 561

Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1) ...................................... 562

Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2) ...................................... 563

Figure 14.14 Data Format in Clocked Synchronous Communication (For LSB-First)............. 564

Rev. 3.00, 07/04, page xxxix of l

Figure 14.15 Sample SCI Initialization Flowchart.................................................................... 565

Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode................. 567

Figure 14.17 Sample Serial Transmission Flowchart................................................................ 568

Figure 14.18 Example of SCI Operation in Reception.............................................................. 569

Figure 14.19 Sample Serial Reception Flowchart..................................................................... 570

Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations..... 572

Figure 14.21 Schematic Diagram of Smart Card Interface Pin Connections............................ 573

Figure 14.22 Normal Smart Card Interface Data Format.......................................................... 574

Figure 14.23 Direct Convention (SDIR = SINV = O/E = 0)..................................................... 574

Figure 14.24 Inverse Convention (SDIR = SINV = O/E = 1)................................................... 574

Figure 14.25 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Bit Rate)............................................................. 576

Figure 14.26 Retransfer Operation in SCI Transmit Mode....................................................... 578

Figure 14.27 TEND Flag Generation Timing in Transmission Operation................................ 578

Figure 14.28 Example of Transmission Processing Flow......................................................... 579

Figure 14.29 Retransfer Operation in SCI Receive Mode......................................................... 580

Figure 14.30 Example of Reception Processing Flow .............................................................. 581

Figure 14.31 Timing for Fixing Clock Output Level................................................................ 581

Figure 14.32 Clock Halt and Restart Procedure........................................................................ 582

Figure 14.33 Block Diagram of IrDA....................................................................................... 583

Figure 14.34 IrDA Transmit/Receive Operations ..................................................................... 584

Figure 14.35 Example of Synchronous Transmission Using DTC........................................... 590

Figure 14.36 Sample Flowchart for Mode Transition during Transmission ............................. 592

Figure 14.37 Port Pin States during Mode Transition (Internal Clock, As ync hro nous

Transmission)....................................................................................................... 593

Figure 14.38 Port Pin States during Mode Transition (Internal Clock, Synchronous

Transmission)....................................................................................................... 593

Figure 14.39 Sample Flowchart for Mode Transition during Reception................................... 594

Section 15 I

Figure 15.1 Block Diagram of I

C Bus Interface2 (IIC2) (Option)

C Bus Interface2.................................................................. 596

Figure 15.2 External Circuit Connections of I/O Pins............................................................. 597

Figure 15.3 I Figure 15.4 I

C Bus Formats................................................................................................... 608

C Bus Timing.................................................................................................... 608

Figure 15.5 Master Transmit Mode Operation Timing 1........................................................ 610

Figure 15.6 Master Transmit Mode Operation Timing 2........................................................ 610

Figure 15.7 Master Receive Mode Operation Timing 1.......................................................... 612

Figure 15.8 Master Receive Mode Operation Timing 2.......................................................... 612

Figure 15.9 Slave Transmit Mode Operation Timing 1 .......................................................... 614

Figure 15.10 Slave Transmit Mode Operation Timing 2 .......................................................... 615

Figure 15.11 Slave Receive Mode Operation Timing 1............................................................ 616

Figure 15.12 Slave Receive Mode Operation Timing 2............................................................ 616

Figure 15.13 Block Diagram of Noise Canceler ....................................................................... 617

Rev. 3.00, 07/04, page xl of l

Figure 15.14 Sample Flowchart for Master Transmit Mode..................................................... 618

Figure 15.15 Sample Flowchart for Master Receive Mode....................................................... 619

Figure 15.16 Sample Flowchart for Slave Transmit Mode ....................................................... 620

Figure 15.17 Sample Flowchart for Slave Receive Mode......................................................... 621

Figure 15.18 Timing of the Bit Synchronous Circuit................................................................ 623

Section 16 A/D Converter

Figure 16.1 Block Diagram of A/D Converter........................................................................ 626

Figure 16.2 A/D Conversion Timing....................................................................................... 633

Figure 16.3 External Trigger Input Timing............................................................................. 635

Figure 16.4 A/D Conversion Precision Definitions................................................................. 637

Figure 16.5 A/D Conversion Precision Definitions................................................................. 637

Figure 16.6 Example of Analog Input Circuit......................................................................... 638

Figure 16.7 Example of Analog Input Protection Circuit........................................................ 640

Section 17 D/A Converter

Figure 17.1 Block Diagram of D/A Converter........................................................................ 644

Figure 17.2 Example of D/A Converter Operation ................................................................. 648

Section 19 Flash Memory (0.35-µµµµm F-ZTAT Version)

Figure 19.1 Block Diagram of Flash Memory ........................................................................ 652

Figure 19.2 Flash Memory State Transitions .......................................................................... 653

Figure 19.3 Boot Mode ........................................................................................................... 654

Figure 19.4 User Program Mode............................................................................................. 655

Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)................... 657

Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode..................... 667

Figure 19.7 Flowchart for Flash Memory Emulation in RAM................................................ 668

Figure 19.8 Example of RAM Overlap Operation.................................................................. 669

Figure 19.9 Program/Program-Verify Flowchart.................................................................... 671

Figure 19.10 Erase/Erase-Verify Flowchart.............................................................................. 673

Figure 19.11 Power-On/Off Timing.......................................................................................... 677

Figure 19.12 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program

Mode)................................................................................................................... 678

Section 20 Flash Memory (0.18-µµµµm F-ZTAT Version)

Figure 20.1 Block Diagram of Flash Memory ........................................................................ 681

Figure 20.2 Mode Transition of Flash Memory...................................................................... 682

Figure 20.3 Flash Memory Configuration............................................................................... 684

Figure 20.4 Block Division of User MAT............................................................................... 685

Figure 20.5 Overview of User Procedure Program................................................................. 686

Figure 20.6 System Configuration in Boot Mode ................................................................... 708

Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI.............................................. 708

Figure 20.8 Overview of Boot Mode State Transition Diagram ............................................. 710

Rev. 3.00, 07/04, page xli of l

Figure 20.9 Programming/Erasing Overview Flow ................................................................ 711

Figure 20.10 RAM Map when Programming/Erasing Is Executed........................................... 712

Figure 20.11 Programming Procedure ...................................................................................... 713

Figure 20.12 Erasing Procedure................................................................................................ 719

Figure 20.13 Procedure for Programming User MAT in User Boot Mode............................... 722

Figure 20.14 Procedure for Erasing User MAT in User Boot Mode ........................................ 724

Figure 20.15 Transitions to Error-Protection State ................................................................... 737

Figure 20.16 Switching between the User MAT and User Boot MAT..................................... 738

Figure 20.17 Boot Program States ............................................................................................ 740

Figure 20.18 Bit-Rate-Adjustment Sequence............................................................................ 741

Figure 20.19 Communication Protocol Format......................................................................... 742

Figure 20.20 New Bit-Rate Selection Sequence ....................................................................... 752

Figure 20.21 Programming Sequence....................................................................................... 755

Figure 20.22 Erasure Sequence................................................................................................. 758

Section 21 Mask ROM

Figure 21.1 Block Diagram of 256-kbyte Mask ROM (HD6432365).................................... 765

Section 22 Clock Pulse Generator

Figure 22.1 Block Diagram of Clock Pulse Generator............................................................ 767

Figure 22.2 Connection of Crystal Oscillator (Example)........................................................ 770

Figure 22.3 Crystal Oscillator Equivalent Circuit................................................................... 770

Figure 22.4 External Clock Input (Examples)......................................................................... 771

Figure 22.5 External Clock Input Timing............................................................................... 772

Figure 22.6 Note on Oscillator Board Design......................................................................... 774

Figure 22.7 Recommended External Circuitry for PLL Circuit.............................................. 774

Section 23 Power-Down Modes

Figure 23.1 Mode Transitions................................................................................................. 777

Figure 23.2 Software Standby Mode Application Example.................................................... 785

Figure 23.3 Hardware Standby Mode Timing......................................................................... 786

Figure 23.4 Hardware Standby Mode Timing when Power Is Supplied................................. 787

Section 25 Electrical Characteristics

Figure 25.1 Output Load Circuit............................................................................................. 829

Figure 25.2 System Clock Timing .......................................................................................... 830

Figure 25.3 Oscillation Stabilization Timing (1) .................................................................... 831

Figure 25.3 Oscillation Stabilization Timing (2) .................................................................... 831

Figure 25.4 Reset Input Timing .............................................................................................. 832

Figure 25.5 Interrupt Input Timing......................................................................................... 833

Figure 25.6 Basic Bus Timing: Two-State Access.................................................................. 837

Figure 25.7 Basic Bus Timing: Three-State Access................................................................ 838

Figure 25.8 Basic Bus Timing: Three-State Access, One Wait .............................................. 839

Rev. 3.00, 07/04, page xlii of l

Figure 25.9 Basic Bus Timing: Two-State Access (CS Assertion Period Extended).............. 840

Figure 25.10 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)............ 841

Figure 25.11 Burst ROM Access Timing: One-State Burst Access.......................................... 842

Figure 25.12 Burst ROM Access Timing: Two-State Burst Access ......................................... 843

Figure 25.13 DRAM Access Timing: Two-State Access.......................................................... 844

Figure 25.14 DRAM Access Timing: Two-State Access, One Wait ........................................ 845

Figure 25.15 DRAM Access Timing: Two-State Burst Access................................................ 846

Figure 25.16 DRAM Access Timing: Three-State Access (RAST = 1).................................... 847

Figure 25.17 DRAM Access Timing: Three-State Burst Access.............................................. 848

Figure 25.18 CAS-Before-RAS Refresh Timing ...................................................................... 849

Figure 25.19 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion).......................... 849

Figure 25.20 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) ........... 849

Figure 25.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ........... 850

Figure 25.22 External Bus Release Timing............................................................................... 850

Figure 25.23 External Bus Request Output Timing.................................................................. 851

Figure 25.24 DMAC Single Address Transfer Timing: Two-State Access .............................. 852

Figure 25.25 DMAC Single Address Transfer Timing: Three-State Access ............................ 853

Figure 25.26 DMAC TEND Output Timing............................................................................. 853

Figure 25.27 DMAC DREQ Input Timing................................................................................ 854

Figure 25.28 I/O Port Input/Output Timing .............................................................................. 856

Figure 25.29 PPG Output Timing ............................................................................................. 856

Figure 25.30 TPU Input/Output Timing.................................................................................... 856

Figure 25.31 TPU Clock Input Timing ..................................................................................... 857

Figure 25.32 8-Bit Timer Output Timing.................................................................................. 857

Figure 25.33 8-Bit Timer Clock Input Timing.......................................................................... 857

Figure 25.34 8-Bit Timer Reset Input Timing........................................................................... 857

Figure 25.35 WDT Output Timing............................................................................................ 858

Figure 25.36 SCK Clock Input Timing..................................................................................... 858

Figure 25.37 SCI Input/Output Timing: Synchronous Mode.................................................... 858

Figure 25.38 A/D Converter External Trigger Input Timing.................................................... 858

Figure 25.39 I

C Bus Interface Input/Output Timing (Option)................................................. 859

Appendix

Figure C.1 Package Dimensions (TFP-120).......................................................................... 899

Figure C.2 Package Dimensions (FP-128B).......................................................................... 900

Figure D.1 Timing of Address Bus, RD, HWR, and LWR

(8-bit bus, 3-state access, no wait)....................................................................... 902

Rev. 3.00, 07/04, page xliii of l

Tables

Section 1 Overview

Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ 11

Table 1.2 Pin Functions..........................................................................................................16

Section 2 CPU

Table 2.1 Instruction Classification........................................................................................ 39

Table 2.2 Operation Notation................................................................................................. 40

Table 2.3 Data Transfer Instructions...................................................................................... 41

Table 2.4 Arithmetic Operations Instructions ........................................................................ 42

Table 2.5 Logic Operations Instructions ................................................................................ 44

Table 2.6 Shift Instructions .................................................................................................... 44

Table 2.7 Bit Manipulation Instructions................................................................................. 45

Table 2.8 Branch Instructions ................................................................................................ 47

Table 2.9 System Control Instructions................................................................................... 48

Table 2.10 Block Data Transfer Instructions............................................................................ 49

Table 2.11 Addressing Modes.................................................................................................. 50

Table 2.12 Absolute Address Access Ranges .......................................................................... 52

Table 2.13 Effective Address Calculation................................................................................ 54

Section 3 MCU Operating Modes

Table 3.1 MCU Operating Mode Selection............................................................................ 59

Table 3.2 Pin Functions in Each Operating Mode.................................................................. 64

Section 4 Exception Handling

Table 4.1 Exception Types and Priority................................................................................. 75

Table 4.2 Exception Handling Vector Table.......................................................................... 76

Table 4.3 Status of CCR and EXR after Trace Exception Handling...................................... 80

Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling..................... 81

Section 5 Interrupt Controller

Table 5.1 Pin Configuration................................................................................................... 87

Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................ 99

Table 5.3 Interrupt Control Modes......................................................................................... 103

Table 5.4 Interrupt Response Times....................................................................................... 108

Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses .................... 108

Section 6 Bus Controller (BSC)

Table 6.1 Pin Configuration................................................................................................... 115

Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)........................................ 141

Rev. 3.00, 07/04, page xliv of l

Table 6.3 Data Buses Used and Valid Strobes....................................................................... 145

Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space............. 158

Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing.... 159

Table 6.6 DRAM Interface Pins............................................................................................. 160

Table 6.7 Idle Cycles in Mixed Accesses to Normal Space and DRAM ............................... 193

Table 6.8 Pin States in Idle Cycle .......................................................................................... 195

Table 6.9 Pin States in Bus Released State ............................................................................ 198

Section 7 DMA Controller (DMAC)

Table 7.1 Pin Configuration................................................................................................... 207

Table 7.3 DMAC Activation Sources..................................................................................... 232

Table 7.4 DMAC Transfer Modes.......................................................................................... 234

Table 7.5 Register Functions in Sequential Mode .................................................................. 236

Table 7.6 Register Functions in Idle Mode ............................................................................ 239

Table 7.7 Register Functions in Repeat Mode ....................................................................... 241

Table 7.8 Register Functions in Single Address Mode .......................................................... 244

Table 7.9 Register Functions in Normal Mode ...................................................................... 247

Table 7.10 Register Functions in Block Transfer Mode........................................................... 250

Table 7.11 DMAC Channel Priority Order.............................................................................. 270

Table 7.12 Interrupt Sources and Priority Order...................................................................... 274

Section 8 Data Transfer Controller (DTC)

Table 8.1 Relationship between Activation Sources and DTCER Clearing........................... 287

Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................ 289

Table 8.3 Chain Transfer Conditions ..................................................................................... 292

Table 8.4 Register Function in Normal Mode........................................................................ 292

Table 8.5 Register Function in Repeat Mode......................................................................... 293

Table 8.6 Register Function in Block Transfer Mode............................................................ 294

Table 8.7 DTC Execution Status............................................................................................ 298

Table 8.8 Number of States Required for Each Execution Status.......................................... 298

Section 9 I/O Ports

Table 9.1 Port Functions ........................................................................................................ 306

Table 9.2 MOS Input Pull-Up States (Port A)........................................................................ 353

Table 9.3 MOS Input Pull-Up States (Port B)........................................................................ 357

Table 9.4 MOS Input Pull-Up States (Port C)........................................................................ 361

Table 9.5 MOS Input Pull-Up States (Port D)........................................................................ 364

Table 9.6 MOS Input Pull-Up States (Port E)........................................................................ 368

Section 10 16-Bit Timer Pulse Unit (TPU)

Table 10.1 TPU Functions........................................................................................................ 380

Table 10.2 Pin Configuration................................................................................................... 383

Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3)................................................................... 387

Rev. 3.00, 07/04, page xlv of l

Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).......................................................... 387

Table 10.5 TPSC2 to TPSC0 (Channel 0)................................................................................ 388

Table 10.6 TPSC2 to TPSC0 (Channel 1)................................................................................ 388

Table 10.7 TPSC2 to TPSC0 (Channel 2)................................................................................ 389

Table 10.8 TPSC2 to TPSC0 (Channel 3)................................................................................ 389

Table 10.9 TPSC2 to TPSC0 (Channel 4)................................................................................ 390

Table 10.10 TPSC2 to TPSC0 (Channel 5) ................................................................................ 390

Table 10.11 MD3 to MD0.......................................................................................................... 392

Table 10.12 TIORH_0 ............................................................................................................... 394

Table 10.13 TIORL_0................................................................................................................ 395

Table 10.14 TIOR_1 .................................................................................................................. 396

Table 10.15 TIOR_2 .................................................................................................................. 397

Table 10.16 TIORH_3 ............................................................................................................... 398

Table 10.17 TIORL_3................................................................................................................ 399

Table 10.18 TIOR_4 .................................................................................................................. 400

Table 10.19 TIOR_5 .................................................................................................................. 401

Table 10.20 TIORH_0 ............................................................................................................... 402

Table 10.21 TIORL_0................................................................................................................ 403

Table 10.22 TIOR_1 .................................................................................................................. 404

Table 10.23 TIOR_2 .................................................................................................................. 405

Table 10.24 TIORH_3 ............................................................................................................... 406

Table 10.25 TIORL_3................................................................................................................ 407

Table 10.26 TIOR_4 .................................................................................................................. 408

Table 10.27 TIOR_5 .................................................................................................................. 409

Table 10.28 Register Combinations in Buffer Operation........................................................... 424

Table 10.29 Cascaded Combinations ......................................................................................... 428

Table 10.30 PWM Output Registers and Output Pins................................................................ 431

Table 10.31 Clock Input Pins in Phase Counting Mode............................................................. 435

Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1....................................... 436

Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2....................................... 437

Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3...................................... 438

Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4....................................... 439

Table 10.36 TPU Interrupts........................................................................................................ 442

Section 11 Programmable Pulse Generator (PPG)

Table 11.1 Pin Configuration................................................................................................... 461

Section 12 8-Bit Timers (TMR)

Table 12.1 Pin Configuration................................................................................................... 481

Table 12.2 Clock Input to TCNT and Count Condition........................................................... 484

Table 12.3 8-Bit Timer Interrupt Sources ................................................................................ 493

Table 12.4 Timer Output Priorities .......................................................................................... 496

Table 12.5 Switching of Internal Clock and TCNT Operation ................................................ 498

Rev. 3.00, 07/04, page xlvi of l

Section 13 Watchdog Timer

Table 13.1 Pin Configuration................................................................................................... 502

Table 13.2 WDT Interrupt Source............................................................................................ 508

Section 14 Serial Communication Interface (SCI, IrDA)

Table 14.1 Pin Configuration................................................................................................... 515

Table 14.2 Relationships between N Setting in BRR and Bit Rate B ...................................... 534

Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode).................................. 535

Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 537

Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 538

Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)...................... 539

Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 540

Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)

(when n = 0 and S = 372)....................................................................................... 541

Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)

(when S = 372)....................................................................................................... 542

Table 14.10 Serial Transfer Formats (Asynchronous Mode)..................................................... 547

Table 14.11 SSR Status Flags and Receive Data Handling........................................................ 554

Table 14.12 Settings of Bits IrCKS2 to IrCKS0 ........................................................................ 585

Table 14.13 SCI Interrupt Sources............................................................................................. 587

Table 14.14 Interrupt Sources .................................................................................................... 588

Section 15 I

C Bus Interface2 (IIC2) (Option)

Table 15.1 Pin Configuration................................................................................................... 597

Table 15.2 Transfer Rate.......................................................................................................... 600

Table 15.3 Interrupt Requests................................................................................................... 622

Table 15.4 Time for monitoring SCL....................................................................................... 623

Section 16 A/D Converter

Table 16.1 Pin Configuration................................................................................................... 627

Table 16.2 Analog Input Channels and Corresponding ADDR Registers................................ 628

Table 16.3 A/D Conversion Time (Single Mode).................................................................... 634

Table 16.4 A/D Conversion Time (Scan Mode)....................................................................... 634

Table 16.5 A/D Converter Interrupt Source............................................................................. 635

Table 16.6 Analog Pin Specifications ...................................................................................... 641

Section 17 D/A Converter

Table 17.1 Pin Configuration................................................................................................... 645

Table 17.2 Control of D/A Conversion.................................................................................... 646

Section 19 Flash Memory (0.35-µµµµm F-ZTAT Version)

Table 19.1 Differences between Boot Mode and User Program Mode.................................... 653

Table 19.2 Pin Configuration................................................................................................... 658

Rev. 3.00, 07/04, page xlvii of l

Table 19.3 Erase Blocks........................................................................................................... 662

Table 19.4 Setting On-Board Programming Mode .................................................................. 663

Table 19.5 Boot Mode Operation............................................................................................. 666

Table 19.6 System Clock Frequencies for which Automatic Adjust ment of LSI Bit Rate is

Possible ..................................................................................................................667

Table 19.7 Flash Memory Operating States............................................................................. 675

Section 20 Flash Memory (0.18-µµµµm F-ZTAT Version)

Table 20.1 Comparison of Programming Modes..................................................................... 683

Table 20.2 Pin Configuration................................................................................................... 688

Table 20.3 Register/Parameter and Target Mode..................................................................... 689

Table 20.4 Parameters and Target Modes................................................................................ 696

Table 20.5 Setting On-Board Programming Mode .................................................................. 707

Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI.......... 709

Table 20.7 Executable MAT .................................................................................................... 726

Table 20.8 (1) Useable Area for Programming in User Program Mode...................................... 727

Table 20.8 (2) Useable Area for Erasure in User Program Mode................................................ 729

Table 20.8 (3) Useable Area for Programming in User Boot Mode............................................ 731

Table 20.8 (4) Useable Area for Erasure in User Boot Mode..................................................... 733

Table 20.9 Hardware Protection............................................................................................... 735

Table 20.10 Software Protection................................................................................................ 736

Table 20.11 Inquiry and Selection Commands .......................................................................... 743

Table 20.12 Programming/Erasing Command........................................................................... 754

Table 20.13 Status Code............................................................................................................. 762

Table 20.14 Error Code.............................................................................................................. 763

Section 22 Clock Pulse Generator

Table 22.1 Damping Resistance Value .................................................................................... 770

Table 22.2 Crystal Oscillator Characteristics........................................................................... 771

Table 22.3 External Clock Input Conditions............................................................................ 772

Section 23 Power-Down Modes

Table 23.1 Operating Modes and Internal States of the LSI.................................................... 776

Table 23.2 Oscillation Stabilization Time Settings.................................................................. 784

Table 23.3 φ Pin State in Each Processing State...................................................................... 788

Section 25 Electrical Characteristics

Table 25.1 Absolute Maximum Ratings................................................................................... 825

Table 25.2 DC Characteristics (1)............................................................................................ 826

Table 25.3 DC Characteristics (2)............................................................................................ 827

Table 25.4 Permissible Output Currents .................................................................................. 828

Table 25.5 Clock Timing ......................................................................................................... 830

Table 25.6 Control Signal Timing............................................................................................ 832

Rev. 3.00, 07/04, page xlviii of l

Table 25.7 Bus Timing (1)....................................................................................................... 834

Table 25.8 Bus Timing (2)....................................................................................................... 835

Table 25.9 DMAC Timing....................................................................................................... 851

Table 25.10 Timing of On-Chip Peripheral Modules................................................................. 854

Table 25.11 A/D Conversion Characteristics............................................................................. 860

Table 25.12 D/A Conversion Characteristics............................................................................. 860

Table 25.13 Absolute Maximum Ratings ................................................................................... 861

Table 25.14 DC Characteristics (1)............................................................................................ 862

Table 25.15 DC Characteristics (2)............................................................................................ 863

Table 25.16 Permissible Output Currents................................................................................... 864

Table 25.17 Clock Timing.......................................................................................................... 865

Table 25.18 Control Signal Timing............................................................................................ 866

Table 25.19 Bus Timing (1) ....................................................................................................... 867

Table 25.20 Bus Timing (2) ....................................................................................................... 868

Table 25.21 DMAC Timing....................................................................................................... 869

Table 25.22 Timing of On-Chip Peripheral Modules................................................................. 870

Table 25.23 A/D Conversion Characteristics............................................................................. 872

Table 25.24 D/A Conversion Characteristics............................................................................. 872

Table 25.25 Flash Memory Characteristics................................................................................ 873

Table 25.26 Absolute Maximum Ratings ................................................................................... 875

Table 25.27 DC Characteristics.................................................................................................. 876

Table 25.28 DC Characteristics.................................................................................................. 877

Table 25.29 Permissible Output Currents................................................................................... 878

Table 25.30 Clock Timing.......................................................................................................... 879

Table 25.31 Control Signal Timing............................................................................................ 880

Table 25.32 Bus Timing (1) ....................................................................................................... 881

Table 25.33 Bus Timing (2) ....................................................................................................... 883

Table 25.34 DMAC Timing....................................................................................................... 884

Table 25.35 Timing of On-Chip Peripheral Modules................................................................. 885

Table 25.36 A/D Conversion Characteristics............................................................................. 887

Table 25.37 D/A Conversion Characteristics............................................................................. 887

Table 25.38 Flash Memory Characteristics (0.18-µm F-ZTAT Version) .................................. 888

Appendix

Table D.1 Execution State of Instructions................................................................................. 903

Rev. 3.00, 07/04, page xlix of l

Rev. 3.00, 07/04, page l of l

Section 1 Overview

1.1 Features

• High-speed H8S/2000 central processing unit with an internal 16-bit architecture

Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bi t general registers 65 basic instructions

• Various peripheral functions

DMA controller (DMAC)* Data transfer controller (DTC) 16-bit timer-pulse unit (TPU ) Programmable pulse generator (PPG)* 8-bit timer (TMR) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI)

C bus interface 2 (IIC2) 10-bit A/D converter 8-bit D/A converter Clock pulse generator

Note: * Not supported by the H8S/2366.

• On-chip memory

ROM Type Model ROM RAM Remarks

Flash memory version HD64F2368 512 kbytes 32 kbytes

HD64F2367 384 kbytes 24 kbytes

HD64F2366 384 kbytes 30 kbytes Masked ROM version HD6432365 256 kbytes 16 kbytes ROMless version HD6412363  16 kbytes

• General I/O ports

I/O pins: 84 Input-only pins: 10

• Supports various power-down states

Rev. 3.00, 07/04, page 1 of 928

• Compact package

Package Code Body Size Pin Pitch

TFP-120 TFP-120 (TFP-120V

QFP-128

FP-128B (FP-128BV

Notes: 1. Pb free version

2. Not supported by the HD64F2368.

) 14.0 × 14.0 mm 0.4 mm

) 14.0 × 20.0 mm 0.5 mm

Rev. 3.00, 07/04, page 2 of 928

1.2 Block Diagram

Figures 1.1, 1.2, and 1.3 show the internal block diagrams of this LSI.

PF2/ /

PF1//

PF0/ /

PG4/ /

PG3/ / PG2/ /

PF6/ PF5/

PF4/

PF3/

PG6/

PG5/

PG1/ PG0/

P85/SCK3

P83/RxD3 P81/TxD3

MD2 MD1 MD0

EXTAL

XTAL

EMLE

NMI

PF7/

VCCVCCVCCVCCVCCPLLVCCPLLVSSVSSVSSVSSVSSVSSV

Port FPort GPort 8

PLL

Clock pulse

generator

Interrupt controller

ROM

(Flash memory

Mask ROM)

RAM

TPU × 6 channels

PPG

TMR × 2 channels

PD7/D15

PD6/D14

PD5/D13

Port D Port E

H8S/2000 CPU

PE7/D7

PE6/D6

PD1/D9

PD0/D8

WDT

PE5/D5

Internal data bus

Internal address bus

PD4/D12

PD3/D11

DTC

DMAC

SCI

PD2/D10

× 5 channels

I2C bus interface 2 (option)

8-bit D/A converter

10-bit A/D converter

PE4/D4

PE3/D3

PE2/D2

PE1/D1

Bus controller

Peripheral data bus

PE0/D0

PA7/A23/ / PA6/A22/ PA5/A21/ PA4/A20/ PA3/A19

Port APort BPort CPort 5 Port 3

PA2/A18 PA1/A17 PA0/A16

PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8

PC7/A7 PC6/A6

Peripheral address bus

PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0

P35/SCK1/SCL0/( ) P34/SCK0/SCK4/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD

P53/ P52/SCK2/ P51/RxD2/ P50/TxD2/

Port 1

P10/PO8/TIOCA0/

P11/PO9/TIOCB0/

P14/PO12/TIOCA1/

P12/PO10/TIOCC0/TCLKA/

P13/PO11/TIOCD0/TCLKB/

P15/PO13/TIOCB1/TCLKC/

Port 2 Port 4 Port 9

Vref

AVCCAV

P47/AN7/( )

P16/PO14/TIOCA2

P20/PO0/TIOCA3/TMRI0

P21/PO1/TIOCB3/TMRI1

P22/PO2/TIOCC3/TMCI0

P17/PO15/TIOCB2/TCLKD

P24/PO4/TIOCA4/RxD4/TMO0

P23/PO3/TIOCD3/TxD4/TMCI1

P26/PO6/TIOCA5

P27/PO7/TIOCB5

P25/PO5/TIOCB4/TMO1

P46/AN6/()P45/AN5/()P44/AN4/()P43/AN3/()P42/AN2/()P41/AN1/()P40/AN0/(

)

P95/AN13/DA3

P94/AN12/DA2

Note: * The ROMless version has no on-chip ROM.

Figure 1.1 Internal Block Diagram of H8S/2367, H8S/2365, and H8S/2363

Rev. 3.00, 07/04, page 3 of 928

PG4/ /

EXTAL

PF7/ PF6/ PF5/

PF4/ PF3/

PF2/ PF1

PF0/

PG6/ PG5/

PG3/ PG2/ PG1/ PG0/

P85/SCK3 P83/RxD3

P81/TxD3

MD2 MD1 MD0

XTAL

EMLE

NMI

VCC

PLLVCC

PLLVSS

VSS

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

Port D Port E

PA7/A23/ / PA6/A22/ PA5/A21/ PA4/A20/ PA3/A19

PLL

Clock pulse

generator

Interrupt controller

H8S/2000 CPU

DTC

Internal data bus

Internal address bus

Bus controller

Port FPort GPort 8

ROM

(Flash memory)

RAM

WDT

SCI

× 5 channels

I2C bus interface 2 (option)

TPU × 6 channels

8-bit D/A converter

10-bit A/D converter

Port APort BPort CPort 5 Port 3

Peripheral address bus

Peripheral data bus

PA2/A18 PA1/A17 PA0/A16

PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8

PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0

P35/SCK1/SCL0 P34/SCK0/SCK4/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD

P53/ P52/SCK2/ P51/RxD2/ P50/TxD2/

TMR × 2 channels

P10/TIOCA0

P11/TIOCB0

Figure 1.2 Internal Block Diagram of H8S/2366

Rev. 3.00, 07/04, page 4 of 928

Port 1 Port 2 Port 4 Port 9

)

Vref

AVCCAVSS

P14/TIOCA1

P16/TIOCA2

P12/TIOCC0/TCLKA

P13/TIOCD0/TCLKB

P15/TIOCB1/TCLKC

P17/TIOCB2/TCLKD

P20/TIOCA3/TMRI0

P21/TIOCB3/TMRI1

P26/TIOCA5

P27/TIOCB5

P25/TIOCB4/TMO1

P22/TIOCC3/TMCI0

P24/TIOCA4/RxD4/TMO0

P23/TIOCD3/TxD4/TMCI1

P46/AN6/()P45/AN5/()P44/AN4/()P43/AN3/()P42/AN2/()P41/AN1/()P40/AN0/(

P47/AN7/( )

P95/AN13/DA3

P94/AN12/DA2

MD2 MD1 MD0

EXTAL

XTAL

EMLE

STBY

RES

WDTOVF

PF7/

PF6/AS

PF5/RD PF4/HWR PF3/LWR

PF2/CS6/LCAS PF1

CS5/UCAS

PF0/WAIT/OE

PG6/BREQ

PG5/BACK

PG4/CS4/BREQO

PG3/CS3/RAS3 PG2/CS2/RAS2

PG1/CS1 PG0/CS0

P85/SCK3 P83/RxD3

P81/TxD3

NMI

VCCVCCVCCVCCPLLVCCPLLVSSVSSVSSVSSVSSVSSV

Port FPort GPort 8

PLL

Clock pulse

generator

Interrupt controller

ROM

(Flash memory)

RAM

TPU × 6 channels

PPG

TMR × 2 channels

PD7/D15

PD6/D14

PD5/D13

PD4/D12

Port D Port E

H8S/2000 CPU

I2C bus interface 2 (option)

PE7/D7

PD2/D10

PD1/D9

PD0/D8

PE6/D6

Internal data bus

PD3/D11

DTC

DMAC

WDT

SCI

× 5 channels

8-bit D/A converter

10-bit A/D converter

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

Internal address bus

Bus controller

Peripheral data bus

PE0/D0

PA7/A23/CS7/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 PA4/A20/IRQ4 PA3/A19

Port APort BPort CPort 5 Port 3

PA2/A18 PA1/A17 PA0/A16

PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8

PC7/A7 PC6/A6

Peripheral address bus

PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0

P35/SCK1/SCL0/(OE) P34/SCK0/SCK4/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD

P53/ADTRG//IRQ3 P52/SCK2/IRQ2 P51/RxD2/IRQ1 P50/TxD2/IRQ0

Port 1 Port 2 Port 4 Port 9

Vref

AVCCAV

P47/AN7/(IRQ7)

P46/AN6/(IRQ6)

P45/AN5/(IRQ5)

P44/AN4/(IRQ4)

P43/AN3/(IRQ3)

P42/AN2/(IRQ2)

P41/AN1/(IRQ1)

P40/AN0/(IRQ0)

P10/PO8/TIOCA0/DREQ0

P11/PO9/TIOCB0/DREQ1

P12/PO10/TIOCC0/TCLKA/TEND0

P13/PO11/TIOCD0/TCLKB/TEND1

P16/PO14/TIOCA2

P20/PO0/TIOCA3/TMRI0

P17/PO15/TIOCB2/TCLKD

P14/PO12/TIOCA1/DACK0

P15/PO13/TIOCB1/TCLKC/DACK1

P26/PO6/TIOCA5

P27/PO7/TIOCB5

P25/PO5/TIOCB4/TMO1

P21/PO1/TIOCB3/TMRI1

P22/PO2/TIOCC3/TMCI0

P24/PO4/TIOCA4/RxD4/TMO0

P23/PO3/TIOCD3/TxD4/TMCI1

Figure 1.3 Internal Block Diagram of H8S/2368

Rev. 3.00, 07/04, page 5 of 928

P95/AN13/DA3

P94/AN12/DA2

1.3 Pin Description

1.3.1 Pin Arrangement

Figures 1.4 to 1.8 show the pin arrangements of this LSI.

PG0/

VSSP81/TxD3

P83/RxD3

VCCVCCEXTAL

XTAL

PC4/A4

PC5/A5

PC6/A6

VSSPF7/φ

PC7/A7

PG1/

9089888786858483828180797877767574737271706968676665646362

MD0 MD1

Vref

91 92 93

94 95

)

100

)

101

)

102

)

103 104 105

106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

1234567891011121314151617181920212223242526272829

MD2

PC0/A0

PC1/A1

PC2/A2

PC3/A3

PG2/ /

PG3/ /

P40/AN0/( P41/AN1/( P42/AN2/( P43/AN3/( P44/AN4/( P45/AN5/( P46/AN6/( P47/AN7/(

P94/AN12/DA2 P95/AN13/DA3

PG4/ /

PG5/ PG6/

P50/TxD2/ P51/RxD2/ P52/SCK2/

P53/ /

P35/SCK1/SCL0/( )

P34/SCK0/SCK4/SDA0

P33/RxD1/SCL1

P32/RxD0/IrRxD/SDA1

Note: * This is an emulator enable pin. Normally, this pin should be set to low. If this pin goes high in the flash memory version,

P31/TxD1

P30/TxD0/IrTxD

the on-chip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and

PLLVSSPLLV

TFP-120

(Top view)

PB0/A8

PB1/A9

PB2/A10

PB3/A11

PF6/

PF5/

PF4/

PB4/A12

PB5/A13

PF3/

PF2/ /

PF1/ /

PB6/A14

PB7/A15

PA0/A16

PF0/ /

PD7/D15

PA1/A17

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

PA2/A18

PA3/A19

EMLE*

PA5/A21/

PA6/A22/

PA4/A20/

PA7/A23/ /

function only for the on-chip emulator.

V PE7/D7

V PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 P85/SCK3 P27/PO7/TIOCB5 P26/PO6/TIOCA5 P25/PO5/TIOCB4/TMO1 P24/PO4/TIOCA4/TMO0/RxD4 P23/PO3/TIOCD3/TMCI1/TxD4 P22/PO2/TIOCC3/TMCI0 P21/PO1/TIOCB3/TMRI1 P20/PO0/TIOCA3/TMRI0 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC/ P14/PO12/TIOCA1/ P13/PO11/TIOCD0/TCLKB/ P12/PO10/TIOCC0/TCLKA/ P11/PO9/TIOCB0/ P10/PO8/TIOCA0/ V

NMI

Figure 1.4 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363

Rev. 3.00, 07/04, page 6 of 928

PG1/

PG0/

VSSP81/TxD3

P83/RxD3

VCCVCCEXTAL

XTAL

VSSPF7/φ

PLLVSSPLLV

PF5/

PF6/

9089888786858483828180797877767574737271706968676665646362

MD0 MD1

Vref

91 92 93

94 95

)

100

)

101

)

102

)

103 104 105

106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

TFP-120

(Top view)

PG2/

PG3/

P40/AN0/( P41/AN1/( P42/AN2/( P43/AN3/( P44/AN4/( P45/AN5/( P46/AN6/( P47/AN7/(

P94/AN12/DA2 P95/AN13/DA3

PG4/ /

PG5/

PG6/ P50/TxD2/ P51/RxD2/

P52/SCK2/

P53/ /

P35/SCK1/SCL0

P34/SCK0/SCK4/SDA0

P33/RxD1/SCL1

P32/RxD0/IrRxD/SDA1

P31/TxD1

P30/TxD0/IrTxD

1234567891011121314151617181920212223242526272829

MD2

PC0/A0

PC1/A1

PC2/A2

PC3/A3

PC4/A4

PC5/A5

PC6/A6

PB0/A8

PC7/A7

PB1/A9

PB2/A10

PB3/A11

PB4/A12

Note: * This pin should be set to low and should not be changed during operation.

PF4/

PF3/

PB5/A13

PB6/A14

PF2/

PF1/

PB7/A15

PA0/A16

PF0/

PD7/D15

PA1/A17

PD6/D14

PD5/D13

PD4/D12

PA2/A18

PA3/A19

PA4/A20/

PD3/D11

PD2/D10

PD1/D9

PA5/A21/

PA6/A22/

PA7/A23/ /

PD0/D8

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

P85/SCK3

P27/TIOCB5

P26/TIOCA5

P25/TIOCB4/TMO1

P24/TIOCA4/TMO0/RxD4

P23/TIOCD3/TMCI1/TxD4

P22/TIOCC3/TMCI0

P21/TIOCB3/TMRI1

P20/TIOCA3/TMRI0

P17/TIOCB2/TCLKD

P16/TIOCA2

P15/TIOCB1/TCLKC

P14/TIOCA1

P13/TIOCD0/TCLKB

P12/TIOCC0/TCLKA

P11/TIOCB0

P10/TIOCA0

NMI

32 31

EMLE*

Figure 1.5 Pin Arrangement of H8S/2366

Rev. 3.00, 07/04, page 7 of 928

1 0

VSSPF7/φ

PLLVSSRES

TFP-120

(Top view)

PB0/A8

PB1/A9

PC7/A7

pin.

PLLV

PF6/AS

PB2/A10

PB3/A11

PB4/A12

PF5/RD

PF3/LWR

PF2/CS6/LCAS

PF4/HWR

PB5/A13

PB6/A14

PF1/CS5/UCA

PF0/WAIT/OE

PB7/A15

PA0/A16

PD7/D15

PD6/D14

PD5/D13

PA1/A17

PA2/A18

PA3/A19

PD4/D12

PD3/D11

PD2/D10

PA4/A20/IRQ4

PA5/A21/IRQ5

PA6/A22/IRQ6

PD1/D9

PD0/D8

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

P85/SCK3

P27/PO7/TIOCB5

P26/PO6/TIOCA5

P25/PO5/TIOCB4/TMO1

P24/PO4/TIOCA4/TMO0/RxD4

P23/PO3/TIOCD3/TMCI1/TxD4

P22/PO2/TIOCC3/TMCI0

P21/PO1/TIOCB3/TMRI1

P20/PO0/TIOCA3/TMRI0

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2

P15/PO13/TIOCB1/TCLKC/DACK

P14/PO12/TIOCA1/DACK0

P13/PO11/TIOCD0/TCLKB/TEND

P12/PO10/TIOCC0/TCLKA/TEND

P11/PO9/TIOCB0/DREQ1

P10/PO8/TIOCA0/DREQ0

NMI

WDTOVF

EMLE

PA7/A23/CS7/IRQ7

VSSP81/TxD3

P83/RxD3

PC1/A1

PC2/A2

PC3/A3

PC4/A4

EXTAL

XTAL

PC5/A5

PC6/A6

PG1/CS1

PG0/CS0

STBY

MD0

MD1

Vref

91 92 93

94 95 96 97 98 99 100 101 102 103 104 105

106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

PG2/CS2/RAS2

PG3/CS3/RAS3

P40/AN0/(IRQ0) P41/AN1/(IRQ1) P42/AN2/(IRQ2) P43/AN3/(IRQ3) P44/AN4/(IRQ4) P45/AN5/(IRQ5) P46/AN6/(IRQ6) P47/AN7/(IRQ7)

P94/AN12/DA2 P95/AN13/DA3

PG4/CS4/BREQO

PG5/BACK

PG6/BREQ P50/TxD2/IRQ0 P51/RxD2/IRQ1

P52/SCK2/IRQ2

P53/ADTRG/IRQ3

P35/SCK1/SCL0/(OE)

P34/SCK0/SCK4/SDA0

P33/RxD1/SCL1

P32/RxD0/IrRxD/SDA1

P31/TxD1

P30/TxD0/IrTxD

1 2 3 4 5 6 7 8 9

MD2

PC0/A0

Notes: 1. This is an emulator enable pin. Normally, this pin should be set to low. If this pin goes high in the flash memory version, the on-chip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and WDTOVF function only for the on-chip emulator.

2. A capacitor should be externally connected to the V

0.1 µF (Recommended value)

Figure 1.6 Pin Arrangement of H8S/2368

Rev. 3.00, 07/04, page 8 of 928

1 0

AVCC

Vref P40/AN0/(IRQ0) P41/AN1/(IRQ1) P42/AN2/(IRQ2) P43/AN3/(IRQ3) P44/AN4/(IRQ4) P45/AN5/(IRQ5) P46/AN6/(IRQ6) P47/AN7/(IRQ7)

P94/AN12/DA2 P95/AN13/DA3

PG4/CS4/BREQO

PG5/BACK

PG6/BREQ

P50/TxD2/IRQ0

P51/RxD2/IRQ1

P52/SCK2/IRQ2

P53/ADTRG/IRQ3

P35/SCK1/SCL0/(OE)

P34/SCK0/SCK4/SDA0

P33/RxD1/SCL1

P32/RxD0/IrRxD/SDA1

P31/TxD1

P30/TxD0/IrTxD

SS VSS

100

SS VSS

PG1/CS1

PG0/CS0

STBY

P81/TxD3

P83/RxD3

VCCVCCEXTAL

XTAL

PC0/A0

PC1/A1

PC2/A2

PC3/A3

919092939495969798

898887868584838281

PC5/A5

PC6/A6

PC4/A4

MD2

PG3/CS3/RAS

PG2/CS2/RAS

101

102

103 104 105 106 107 108 109 110 111 112 113 114

115 116 117 118 119 120 121 122 123 124 125 126 127 128

1234567891011121314151617181920212223242526272829

MD0

MD1

PF7/φPLLV

FP-128B

(Top view)

PB0/A8

PB1/A9

PC7/A7

RES

PLLV

PB2/A10

PB3/A11

PB4/A12

PF6/AS

PF5/RD

PB5/A13

PF4/HWR

PF3/LWR

PB6/A14

PF1/CS5/UCA

PF2/CS6/LCAS

PB7/A15

PA0/A16

PF0/WAIT/OE

PD7/D15

PD6/D14

PD5/D13

PD4/D12

75747677787980

737271706968676665

PA1/A17

PA2/A18

PA3/A19

PA4/A20/IRQ4

PD3/D11

PD2/D10

PA5/A21/IRQ5

PA6/A22/IRQ6

PD1/D9

PD0/D8

EMLE*

NC*1VCCPE7/D7

SS VSS

WDTOVF

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

P85/SCK3

P27/PO7/TIOCB5

P26/PO6/TIOCA5

P25/PO5/TIOCB4/TMO1

P24/PO4/TIOCA4/TMO0/RxD4

P23/PO3/TIOCD3/TMCI1/TxD4

P22/PO2/TIOCC3/TMCI0

P21/PO1/TIOCB3/TMRI1

P20/PO0/TIOCA3/TMRI0

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2

P15/PO13/TIOCB1/TCLKC/DACK

P14/PO12/TIOCA1/DACK0

P13/PO11/TIOCD0/TCLKB/TEND

P12/PO10/TIOCC0/TCLKA/TEND

P11/PO9/TIOCB0/DREQ1 P10/PO8/TIOCA0/DREQ0

NMI

PA7/A23/CS7/IRQ7

Notes: FP-128B is not supported by the HD64F2368.

1. The NC pin should be fixed to Vss or should be open.

2. This is an emulator enable pin. Normally, this pin should be set to low. If this pin goes high in the flash memory version, the on-chip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and WDTOVF function only for the on-chip emulator.

Figure 1.7 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363

Rev. 3.00, 07/04, page 9 of 928

SS VSS

100

SS VSS

PG1/CS1

PG0/CS0

STBY

P81/TxD3

P83/RxD3

VCCVCCEXTAL

PC0/A0

PC1/A1

PC2/A2

PC3/A3

919092939495969798

PC4/A4

MD2

PG3/CS3

PG2/CS2

101

AVCC

Vref P40/AN0/(IRQ0) P41/AN1/(IRQ1) P42/AN2/(IRQ2) P43/AN3/(IRQ3) P44/AN4/(IRQ4) P45/AN5/(IRQ5) P46/AN6/(IRQ6) P47/AN7/(IRQ7)

P94/AN12/DA2 P95/AN13/DA3

PG4/CS4/BREQO

P53/ADTRG/IRQ3

P34/SCK0/SCK4/SDA0

P32/RxD0/IrRxD/SDA1

Notes: 1. The NC pin should be fixed to Vss or should be open.

2. This pin should be set to low and should not be changed during operation.

PG5/BACK

PG6/BREQ P50/TxD2/IRQ0 P51/RxD2/IRQ1

P52/SCK2/IRQ2

P35/SCK1/SCL0

P33/RxD1/SCL1

P31/TxD1

P30/TxD0/IrTxD

102

103 104 105 106 107 108 109 110 111 112 113 114

115 116 117 118 119 120 121 122 123 124 125 126 127 128

1234567891011121314151617181920212223242526272829

MD0

MD1

XTAL

PF7/φPLLV

898887868584838281

FP-128B

(Top view)

PB0/A8

PB1/A9

PC5/A5

PC6/A6

PC7/A7

RES

PB2/A10

Figure 1.8 Pin Arrangement of H8S/2366

PF6/AS

PLLV

PB3/A11

PB4/A12

PF5/RD

PF4/HWR

PB5/A13

PF3/LWR

PF2/CS6

PB6/A14

PB7/A15

PA0/A16

PF1/CS5

PF0/WAI

PD7/D15

PA1/A17

75747677787980

PA2/A18

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

737271706968676665

EMLE*

PA3/A19

PA4/A20/IRQ4

PA5/A21/IRQ5

PA6/A22/IRQ6

PA7/A23/CS7/IRQ7

PD0/D8

SS VSS

NC*1VCCPE7/D7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

NMI

WDTOVF

PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0

P85/SCK3

P27/TIOCB5 P26/TIOCA5 P25/TIOCB4/TMO1 P24/TIOCA4/TMO0/RxD4 P23/TIOCD3/TMCI1/TxD4 P22/TIOCC3/TMCI0 P21/TIOCB3/TMRI1 P20/TIOCA3/TMRI0 P17/TIOCB2/TCLKD P16/TIOCA2 P15/TIOCB1/TCLKC P14/TIOCA1 P13/TIOCD0/TCLKB P12/TIOCC0/TCLKA P11/TIOCB0 P10/TIOCA0

Rev. 3.00, 07/04, page 10 of 928

1.3.2 Pin Arrangement in Each Operating Mode

Table 1.1 Pin Arrangement in Each Operating Mode

Pin No. Pin Name

Mode 7

TFP-120 QFP-128

1 5 MD2 MD2 MD2 MD2 MD2 Vss 2 6 Vcc Vcc Vcc Vcc Vcc Vcc 3 7 A0 A0 PC0/A0 PC0/A0 PC0 A0 4 8 A1 A1 PC1/A1 PC1/A1 PC1 A1 5 9 A2 A2 PC2/A2 PC2/A2 PC2 A2 6 10 A3 A3 PC3/A3 PC3/A3 PC3 A3 7 11 A4 A4 PC4/A4 PC4/A4 PC4 A4 8 12 Vss Vss Vss Vss Vss Vss 9 13 A5 A5 PC5/A5 PC5/A5 PC5 A5 10 14 A6 A6 PC6/A6 PC6/A6 PC6 A6 11 15 A7 A7 PC7/A7 PC7/A7 PC7 A7 12 16 A8 A8 PB0/A8 PB0/A8 PB0 A8 13 17 A9 A9 PB1/A9 PB1/A9 PB1 A9 14 18 A10 A10 PB2/A10 PB2/A10 PB2 A10 15 19 A11 A11 PB3/A11 PB3/A11 PB3 A11 16 20 A12 A12 PB4/A12 PB4/A12 PB4 A12 17 21 Vss Vss Vss Vss Vss Vss 18 22 A13 A13 PB5/A13 PB5/A13 PB5 A13 19 23 A14 A14 PB6/A14 PB6/A14 PB6 A14 20 24 A15 A15 PB7/A15 PB7/A15 PB7 A15 21 25 A16 A16 PA0/A16 PA0/A16 PA0 A16 22 26 Vss Vss Vss Vss Vss Vss 23 27 A17 A17 PA1/A17 PA1/A17 PA1 A17 24 28 A18 A18 PA2/A18 PA2/A18 PA2 A18 25 29 A19 A19 PA3/A19 PA3/A19 PA3 NC 26 30 A20/IRQ4 A20/IRQ4 PA4/A20/IRQ4 PA4/A20/IRQ4 PA4/IRQ4 NC 27 31 PA5/A21/IRQ5 PA5/A21/IRQ5 PA5/A21/IRQ5 PA5/IRQ5 PA5/IRQ5 NC 28 32 PA6/A22/IRQ6 PA6/A22/IRQ6 PA6/A22/IRQ6 PA6/IRQ6 PA6/IRQ6 NC 29 33 PA7/A23/CS7/

Mode 1 Mode 2 Mode 4

IRQ7

PA7/A23/CS7/ IRQ7

EXPE = 1 EXPE = 0

PA7/CS7/ IRQ7

PA7/IRQ7 NC

Flash Memory Programmer Mode

Rev. 3.00, 07/04, page 11 of 928

Pin No. Pin Name

Flash Memory Programmer Mode

TFP-120 QFP-128

Mode 1 Mode 2 Mode 4

Mode 7

EXPE = 1 EXPE = 0

30 34 EMLE EMLE EMLE EMLE EMLE EMLE

 35 Vss Vss Vss Vss Vss Vss  36 Vss Vss Vss Vss Vss Vss

31 37 WDTOVF WDTOV F WDTOVF WDTOVF WDTOVF NC 32 38 NMI NMI NMI NMI NMI Vcc 33 39 VCC (V

34 40 P10/PO8

TIOCA0/

DREQ0

35 41 P11/PO9

TIOCB0/

DREQ1

36 42 P12/PO10

TIOCC0/TCLKA/

TEND0

37 43 P13/PO11

TIOCD0/TCLKB/

TEND1

38 44 P14/PO12

TIOCA1/

DACK0

39 45 P15/PO13

TIOCB1/TCLKC/

DACK1

40 46 P16/PO14

TIOCA2

41 47 P17/PO15

TIOCB2/TCLKD

42 48 P20/PO0

TIOCA3/TMRI0

43 49 P21/PO1

TIOCB3/TMRI1

44 50 P22/PO2

TIOCC3/TMCI0

45 51 P23/PO3

TIOCD3/TMCI1/ TxD4

)VCC (V

P10/PO8 TIOCA0/

DREQ0

P11/PO9 TIOCB0/

DREQ1

P12/PO10 TIOCC0/TCLKA/

TEND0

P13/PO11 TIOCD0/TCLKB/

TEND1

P14/PO12 TIOCA1/

DACK0

P15/PO13 TIOCB1/TCLKC/

DACK1

P16/PO14 TIOCA2

P17/PO15 TIOCB2/TCLKD

P20/PO0 TIOCA3/(TMRI0)

P21/PO1 TIOCB3/TMRI1

P22/PO2 TIOCC3/TMCI0

P23/PO3 TIOCD3/TMCI1/ TxD4

)VCC (V

P10/PO8 TIOCA0/

DREQ0

P11/PO9 TIOCB0/

DREQ1

P12/PO10 TIOCC0/TCLKA/

TEND0

P13/PO11 TIOCD0/TCLKB/

TEND1

P14/PO12 TIOCA1/

DACK0

P15/PO13 TIOCB1/TCLKC/

DACK1

P16/PO14

TIOCA2

P17/PO15

TIOCB2/TCLKD P20/PO0

TIOCA3/(TMRI0) P21/PO1

TIOCB3/TMRI1 P22/PO2

TIOCC3/TMCI0 P23/PO3

TIOCD3/TMCI1/ TxD4

)VCC (V

P10/PO8 TIOCA0/

DREQ0

P11/PO9 TIOCB0/

DREQ1

P12/PO10 TIOCC0/TCLKA/

TEND0

P13/PO11 TIOCD0/TCLKB/

TEND1

P14/PO12 TIOCA1/

DACK0

P15/PO13 TIOCB1/TCLKC/

DACK1

P16/PO14

TIOCA2

P17/PO15

TIOCB2/TCLKD P20/PO0

TIOCA3/(TMRI0) P21/PO1

TIOCB3/TMRI1 P22/PO2

TIOCC3/TMCI0 P23/PO3

TIOCD3/TMCI1/ TxD4

)VCC (V

P10/PO8 TIOCA0/

DREQ0

P11/PO9 TIOCB0/

DREQ1

P12/PO10 TIOCC0/TCLKA/

TEND0

P13/PO11 TIOCD0/TCLKB/

TEND1

P14/PO12 TIOCA1/

DACK0

P15/PO13 TIOCB1/TCLKC/

DACK1

P16/PO14

TIOCA2

P17/PO15

TIOCB2/TCLKD P20/PO0

TIOCA3/(TMRI0) P21/PO1

TIOCB3/TMRI1 P22/PO2

TIOCC3/TMCI0 P23/PO3

TIOCD3/TMCI1/ TxD4

)

Rev. 3.00, 07/04, page 12 of 928

Pin No. Pin Name

Flash Memory Programmer Mode

Vss

TFP-120 QFP-128

Mode 1 Mode 2 Mode 4

46 52 P24/PO4

TIOCA4/TMO0/ RxD4

47 53 P25/PO5

TIOCB4/TMO1

48 54 P26/PO6

TIOCA5

49 55 P27/PO7

TIOCB5

P24/PO4

TIOCA4/TMO0/ RxD4

P25/PO5

TIOCB4/TMO1 P26/PO6

TIOCA5 P27/PO7

TIOCB5

P24/PO4

TIOCA4/TMO0/ RxD4

P25/PO5

TIOCB4/TMO1 P26/PO6

TIOCA5 P27/PO7

TIOCB5

Mode 7

EXPE = 1 EXPE = 0

P24/PO4 TIOCA4/TMO0/ RxD4

P25/PO5 TIOCB4/TMO1

P26/PO6 TIOCA5

P27/PO7 TIOCB5

P24/PO4 TIOCA4/TMO0/ RxD4

P25/PO5 TIOCB4/TMO1

P26/PO6 TIOCA5

P27/PO7

TIOCB5 50 56 P85/SCK3 P85/SCK3 P85/SCK3 P85/SCK3 P85/SCK3 NC 51 57 D0 PE0/D0 PE0/D0 PE0/D0 PE0 NC 52 58 D1 PE1/D1 PE1/D1 PE1/D1 PE1 NC 53 59 D2 PE2/D2 PE2/D2 PE2/D2 PE2 NC 54 60 D3 PE3/D3 PE3/D3 PE3/D3 PE3 NC 55 61 D4 PE4/D4 PE4/D4 PE4/D4 PE4 NC 56 62 D5 PE5/D5 PE5/D5 PE5/D5 PE5 NC 57 63 D6 PE6/D6 PE6/D6 PE6/D6 PE6 NC 58 64 Vss Vss Vss Vss Vss Vss 59 65 D7 PE7/D7 PE7/D7 PE7/D7 PE7 NC 60 66 Vcc Vcc Vcc Vcc Vcc Vcc

 67 NC NC NC NC NC NC  68 Vss Vss Vss Vss Vss Vss

61 69 D8 D8 D8 D8 PD0 I/O0 62 70 D9 D9 D9 D9 PD1 I/O1 63 71 D10 D10 D10 D10 PD2 I/O2 64 72 D11 D11 D11 D11 PD3 I/O3 65 73 D12 D12 D12 D12 PD4 I/O4 66 74 D13 D13 D13 D13 PD5 I/O5 67 75 D14 D14 D14 D14 PD6 I/O6 68 76 D15 D15 D15 D15 PD7 I/O7 69 77 PF0/WAIT/OE 70 78 PF1/CS5/

UCAS

PF0/WAIT/OE PF1/CS5/

UCAS

PF0/WAIT/OE

PF1/CS5/ UCAS

PF0/WAIT/OE

PF1/CS5/ UCAS

PF0 NC

PF1 NC

Rev. 3.00, 07/04, page 13 of 928

Pin No. Pin Name

Flash Memory Programmer Mode

TFP-120 QFP-128

71 79 PF2/CS6/

Mode 1 Mode 2 Mode 4

LCAS

PF2/CS6/

LCAS

PF2/CS6/

LCAS

Mode 7

EXPE = 1 EXPE = 0

PF2/CS6/

LCAS

PF2 NC

72 80 PF3/LWR PF3/LWR PF3/LWR PF3/LWR PF3 NC 73 81 HWR HWR HWR HWR PF4 NC 74 82 RD RD RD RD PF5 NC 75 83 PF6/AS PF6/AS PF6/AS PF6/AS PF6 NC 76 84 PLLVcc PLLVcc PLLVcc PLLVcc PLLVcc Vcc 77 85 RES RES RES RES RES RES 78 86 PLLVss PLLVss PLLVss PLLVss PLLVss Vss 79 87 PF7/φ PF7/φ PF7/φ PF7/φ PF7/φ NC 80 88 Vss Vss Vss Vss Vss Vss 81 89 XTAL XTAL XTAL XTAL XTAL XTAL 82 90 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL 83 91 Vcc Vcc Vcc Vcc Vcc Vcc 84 92 Vcc Vcc Vcc Vcc Vcc Vcc 85 93 P83/RxD3 P83/RxD3 P83/RxD3 P83/RxD3 P83/RxD3 NC 86 94 P81/TxD3 P81/TxD3 P81/TxD3 P81/TxD3 P81/TxD3 NC 87 95 Vss Vss Vss Vss Vss Vss 88 96 STBY STBY STBY STBY STBY Vcc 89 97 PG0/CS0 PG0/CS0 PG0/CS0 PG0/CS0 PG0 NC 90 98 PG1/CS1 PG1/CS1 PG1/CS1 PG1/CS1 PG1 NC

 99 Vss Vss Vss Vss Vss Vss  100 Vss Vss Vss Vss Vss Vss

91 101 PG2/CS2/

92 102 PG3/CS3/

RAS2

RAS3

PG2/CS2/

RAS2

PG3/CS3/

RAS3

PG2/CS2/

RAS2

PG3/CS3/

RAS3

PG2/CS2/

RAS2

PG3/CS3/

RAS3

PG2 NC

PG3 NC

93 103 AVcc AVcc AVcc AVcc AVcc Vcc 94 104 Vref Vref Vref Vref Vref NC 95 105 P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0)NC 96 106 P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1)NC 97 107 P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2)NC 98 108 P43/AN3/(IRQ3) P43/AN3/(IRQ3) P43/AN3/(IRQ3) P43/AN3/(IRQ3) P43/AN3/(IRQ3)NC

Rev. 3.00, 07/04, page 14 of 928

Pin No. Pin Name

Flash Memory Programmer Mode

TFP-120 QFP-128

Mode 1 Mode 2 Mode 4

Mode 7

EXPE = 1 EXPE = 0

99 109 P44/AN4/(IRQ4) P44/AN4/(IRQ4) P44/AN4/(IRQ4) P44/AN4/(IRQ4) P44/AN4/(IRQ4)NC 100 110 P45/AN5/(IRQ5) P45/AN5/(IRQ5) P45/AN5/(IRQ5) P45/AN5/(IRQ5) P45/AN5/(IRQ5)NC 101 111 P46/AN6/(IRQ6) P46/AN6/(IRQ6) P46/AN6/(IRQ6) P46/AN6/(IRQ6) P46/AN6/(IRQ6)NC 102 112 P47/AN7/(IRQ7) P47/AN7/(IRQ7) P47/AN7/(IRQ7) P47/AN7/(IRQ7) P47/AN7/(IRQ7)NC 103 113 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 NC 104 114 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 NC 105 115 AVss AVss AVss AVss AVss Vss 106 116 PG4/CS4/

BREQO

PG4/CS4/ BREQO

PG4 NC

107 117 PG5/BACK PG5/BACK PG5/BACK PG5/BACK PG5 NC 108 118 PG6/BREQ PG6/BREQ PG6/BREQ PG6/BREQ PG6 NC 109 119 P50/TxD2/IRQ0 P50/TxD2/IRQ0 P50/TxD2/IRQ0 P50/TxD2/IRQ0 P50/TxD2/IRQ0 Vss 110 120 P51/RxD2/IRQ1 P51/RxD2/IRQ1 P51/RxD2/IRQ1 P51/RxD2/IRQ1 P51/RxD2/IRQ1 Vss 111 121 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 Vcc 112 122 P53/ADTRG/

IRQ3

113 123 P35/SCK1/

SCL0/(OE)

114 124 P34/SCK0/

SCK4/SDA0

P53/ADTRG/ IRQ3

P35/SCK1/ SCL0/(OE)

P34/SCK0/ SCK4/SDA0

P53/ADTRG/ IRQ3

P35/SCK1/ SCL0/(OE)

P34/SCK0/ SCK4/SDA0

P53/ADTRG/ IRQ3

P35/SCK1/ SCL0/(OE)

P34/SCK0/ SCK4/SDA0

P53/ADTRG/

IRQ3

P35/SCK1/SCL0 NC

P34/SCK0/

SCK4/SDA0

115 125 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 NC 116 126 P32/RxD0/

IrRxD/SDA1

P32/RxD0/ IrRxD/SDA1

P32/RxD0/

IrRxD/SDA1

Vcc

117 127 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 NC 118 128 P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD NC 119 1 MD0 MD0 MD0 MD0 MD0 Vss 120 2 MD1 MD1 MD1 MD1 MD1 Vss

 3 Vss Vss Vss Vss Vss Vss  4 Vss Vss Vss Vss Vss Vss

Notes: 1. Not supported by the H8S/2368.

2. Used as the V

pin in the H8S/2368.

3. Not supported by the H8S/2366.

Rev. 3.00, 07/04, page 15 of 928

1.3.3 Pin Functions

Table 1.2 Pin Functions

Type Symbol

Power

Clock

Operating mode control

System control

PLLV

XTAL 81 89 Input

EXTAL 82 90 Input For connection to a crystal oscillator.

0 79 87 Output Supplies the system clock to external

MD2 MD1 MD0

RES 77 85 Input Reset pin. When this pin is driven

STBY 88 96 Input

EMLE 30 34 Input

Pin No.

TFP-120 QFP-128

2,33,60, 83,84

6,39,66, 91,92

I/O Function

Input

Power supply pins. V

pins should

be connected to the system power supply. The pin 33 of TFP-120, which is used as the V

pin, should

not be connected to the power supply. The pin should be connected

via 0.1-µF (recommended

to V

value) capacitor (placed close to the pins).

8,17,22, 58,80,87

3,4,12,21, 26,35,36, 64,68,88,

Input Ground pins. VSS pins should be

connected to the system power supply (0 V).

95,99,100

76 84 Input

Power supply pin for the on-chip PLL oscillator.

78 86 Input Ground pin for the on-chip PLL

oscillator. For connection to a crystal oscillator.

See section 22, Clock Pulse Generator for typical connection diagrams for a crystal oscillator and external clock input.

The EXTAL pin can also input an external clock. See section 22, Clock Pulse Generator for typical connection diagrams for a crystal oscillator and external clock input.

devices.

1, 120, 119

5, 2, 1

Input These pins set the operating mode.

These pins should not be changed while the MCU is operating.

low, the chip is reset. When this pin is driven low, a

transition is made to hardware standby mode.

Enables emulator. This pin should be connected to the power supply (0 V).

Rev. 3.00, 07/04, page 16 of 928

Pin No.

Type Symbol

TFP-120 QFP-128

Address bus A23 toA029 to 23,

21 to 18, 16 to 9, 7 to 3

Data bus D15 toD068 to 61,

59, 57 to 51

Bus control CS7 to

CS0

29,71,70, 106, 92 to 89

AS 75 83 Output When this pin is low, it indicates that

RD 74 82 Output When this pin is low, it indicates that

HWR 73 81 Output Strobe signal indicating that external

LWR 72 80 Output Strobe signal indicating that external

BREQ 108 118 Input The external bus master requests the

BREQO 106 116 Input External bus request signal when the

BACK 107 117 Output Indicates the bus is released to the

UCAS

70 78 Output Upper column address strobe signal

33 to 27, 25 to 22, 20 to 13, 11 to 7

76 to 69, 65, 63 to 57

33,79,78, 116,102, 101,98,97

I/O Function

Output Address output pins.

Input/ output

These pins constitute a bidirectiona l data bus.

Output Signals that select division areas 7 to

0 in the external address space.

address output on the address bus is valid.

the external address space is being read.

address space is to be written, and the upper half (D15 to D8) of the data bus is enabled.

Write enable signal for accessing the DRAM space.

address space is to be written, and the lower half (D7 to D0) of the data bus is enabled.

bus to this LSI.

internal bus master accesses the external space in external bus release state.

external bus master.

for accessing the 16-bit DRAM space.

Column address strobe signal for accessing the 8-bit DRAM space.

Rev. 3.00, 07/04, page 17 of 928

Type Symbol

Bus control LCAS

Interrupt

RAS2

RAS3

WAIT

(OE)

NMI 32 38 Input Nonmaskable interrupt request pin.

signals

IRQ7 to IRQ0

) to

(IRQ (IRQ0)

DMA controller (DMAC)

DREQ1

DREQ0 TEND1

TEND0 DACK1

DACK0

16-bit timer pulse unit (TPU)

TCLKD TCLKC TCLKB TCLKA

TIOCA0 TIOCB0 TIOCC0 TIOCD0

TIOCA1 TIOCB1

Pin No.

TFP-120 QFP-128

71 79 Output Lower column address strobe signal

I/O Function

for accessing the 16-bit DRAM space.

69 77 Input Requests insertion of a wait state in

101 102

Output Row address strobe signal for the

DRAM interface.

the bus cycle when accessing external 3-state address space.

69, 113

77, 123

Output Output enable signal for accessing

the DRAM space. The output pins of OE and (OE) are

selected by the port function control register 2 (PFCR2) of port 3.

Fix high when not used.

29 to 26, 112 to 109, 102 to 95

33 to 30, 122 to 119, 112 to 105

Input These pins request a maskable

interrupt. The input pins of IRQn and (IRQn)

are selected by the IRQ pin select register (ITSR) of the interrupt controller. (n = 0 to 7)

35,

37,

39,

38 41,

39, 37, 36

34, 35, 36, 37

38, 39

41, 40

43, 42

45, 44

47, 45, 43, 42

40, 41, 42, 43

44, 45

Input These signals request DMAC

activation.

Output These signals indicate the end of

DMAC data transfer.

Output DMAC single address transfer

acknowledge signals.

Input External clock input pins for the timer.

Input/ output

TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins.

Input/ output

TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins.

Rev. 3.00, 07/04, page 18 of 928

Type Symbol

16-bit timer pulse unit

TIOCA2 TIOCB2

(TPU)

TIOCA3 TIOCB3 TIOCC3 TIOCD3

TIOCA4 TIOCB4

TIOCA5 TIOCB5

Programmable pulse generator

(PPG) 8-bit timer

(TMR)

PO15 to

PO0

TMO0 TMO1

TMCI0 TMCI1

TMRI0 TMRI1

Watchdog

WDTOVF 31 37 Output Counter overflow signal output pin in

Timer(WDT) Serial

communication interface(SCI)/ smart card interface (SCI_0 with IrDA function)

TxD4 TxD3 TxD2 TxD1 TxD0/ IrTxD

RxD4 RxD3 RxD2 RxD1 RxD0/ IrRxD

SCK4 SCK3 SCK2 SCK1 SCK0

Pin No. TFP-120 QFP-128

40, 41

42, 43, 44, 45

46, 47

48, 49

41 to 34, 49 to42

46, 47

44, 45

42, 43

45, 86, 109, 117, 118

46, 85, 110, 115, 116

114, 50, 111, 113, 114

46, 47

48, 49, 50, 51

52, 53

54, 55

47 to 40, 55 to 48

52, 53

50, 51

48, 49

51, 94, 119, 127, 128

52, 93, 120 125, 126

124, 56, 121, 123, 124

I/O Function

Input/ output

TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins.

Input/ output

TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins.

Input/ output

TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins.

Input/ output

TGRA_5 and TGRB_5 input capture input/output compare output/PWM output pins.

Output Pulse output pins.

Output W aveform output pins with output

compare function.

Input External event input pins.

Input Counter reset input pins.

watchdog timer mode.

Output Data output pins.

Input Data input pins.

Input/

Clock input/output pins.

output

Rev. 3.00, 07/04, page 19 of 928

Type Symbol

IIC bus interface2

SCL1 SCL0

(IIC2) IIC bus

interface (IIC)

SDA1 SDA0

AN13, AN12, AN7 to AN0

ADTRG 112 122 Input Pin for input of an external trigger to

D/A converter DA3,

DA2

A/D converter,

D/A converter

Vref 94 104 Input The reference voltage input pin for

I/O ports P17 to

P10 P27 to

P20 P35 to

P30 P47 to

P40 P53 to

P50

Pin No.

TFP-120 QFP-128

115, 113

116, 114

125, 123

126, 124

I/O Function

Input/ output

IIC clock input/output pins.

IIC data input/output pins.

104 to 95 114 to 105 Input Analog input pins.A/D converter

start A/D conversion.

104, 103

114, 113

Output Analog output pins.

93 103 Input The analog power-supply pin for the

A/D converter and D/A converter. When the A/D converter and D/A

converter are not used, this pin should be connected to the system power supply (+3 V).

105 115 Input The ground pin for the A/D

converter and D/A converter. This pin should be connected to the

system power supply (0 V).

the A/D converter and D/A converter.

When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V).

41 to 34 47 to 40 Input/

Eight-bit input/output pins.

output

49 to 42 55 to 48 Input/

Eight-bit input/output pins.

output

113 to 118 123 to 128 Input/

Six-bit input/output pins.

output

102 to 95 112 to 105 Input Eight-bit input pins.

112 to 109 122 to 119 Input/

Four-bit input/output pins.

output

Rev. 3.00, 07/04, page 20 of 928

Pin No.

Type Symbol

I/O ports P85,

P83, P81

P95, P94

PA7 to

TFP-120 QFP-128

50, 85, 86

104, 103

56, 93, 94

114, 113

29 to 23,2133 to 27,25Input/

PA0 PB7 to

PB0 PC7 to

PC0 PD7 to

20 to 18, 16 to 12

11 to 9, 7 to 3

24 to 22, 20 to 16

15 to 13, 11 to 7

68 to 61 76 to 69 Input/

PD0 PE7 to

PE0 PF7 to

PF0 PG6 to

PG0

59, 57 to 51

79, 75 to 69

108 to 106, 92 to 89

65, 63 to 57

87, 83 to 77

118 to 116, 102,101, 98,97

Notes: 1. Not supported by the H8S/2368.

2. Not supported by the H8S/2366.

I/O Function

Input/

Three-bit input/output pins.

output

Input Two-bit input pins.

Eight-bit input/output pins. output Input/

Eight-bit input/output pins. output

Eight-bit input/output pins. output Input/

Seven-bit input/output pins. output

Rev. 3.00, 07/04, page 21 of 928

Rev. 3.00, 07/04, page 22 of 928

Section 2 CPU

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1 Features

• Upward-compatibility with H8/300 and H8/300H CPUs  Can execute H8/300 and H8/300H CPU object programs

• General-register architecture  Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-five basic instructions  8/16/32-bit arithmetic and logic instructions  Multiply and divide instructions  Powerful bit-manipulation instructions

• Eight addressing modes  Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]  Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]  Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]  Immediate [#xx:8, #xx:16, or #xx:32]  Program-counter relative [@(d:8,PC) or @(d :16,P C) ]  Memory indirect [@@aa:8]

• 16-Mbyte address space  Program: 16 Mbytes  Data: 16 Mbytes

• High-speed operation  All frequently-used instructions are executed in one or two states  8/16/32-bit register-register add/subtract: 1 state  8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)  16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)  16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)  32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)

CPUS211A_000020020100

Rev. 3.00, 07/04, page 23 of 928

• Two CPU operating modes  Normal mode*  Advanced mode

Note: * For this LSI, normal mode is not available.

• Power-down state  Transition to power-down state by SLEEP instruction  Selectable CPU clock speed

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration The MAC register is supported only by the H8S/2600 CPU.

• Basic instructio ns The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• The number of execution states of the MULXU and MULXS instructions

Execution States

Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs, Rd 3 12

MULXU.W Rs, ERd 4 20

MULXS MULXS.B Rs, Rd 4 13

MULXS.W Rs, ERd 5 21

In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model.

Rev. 3.00, 07/04, page 24 of 928

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.

• More general registers and control registers  Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been

added.

• Expanded address space  Normal mode supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Signed multiply and divide instructions have been added.  Two-bit shift and two-bit rotate instructions have been added.  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added.

• Higher speed  Basic instructions are executed twice as fast.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.

• Additional control register  One 8-bit control register has been added.

• Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Two-bit shift and two-bit rotate instructions have been added.  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added.

• Higher speed  Basic instructions are executed twice as fast.

Rev. 3.00, 07/04, page 25 of 928

2.2 CPU Operating Modes

The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins.

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode.

• Address spac e

Linear access to a maximum address space of 64 kbytes is possible.

• Extended registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers.

When extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an ad dress register. (If general register Rn is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended register (En) will be affected.)

• Instruction set

All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid.

• Exception vector table and memory indirect branch addresses

In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode, the operand is a 16-bit (word) operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table.

• Stack structure

When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling.

Note: For this LSI, normal mode is not available.

Rev. 3.00, 07/04, page 26 of 928

H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B

Reset exception vector

(Reserved for system use)

Exception vector 1

Exception vector 2

Exception vector table

Figure 2.1 Exception Vector Table (Normal Mode)

1. When EXR is not used, it is not stored on the stack.

Notes:

2. SP when EXR is not used.

3. lgnored when returning.

(16 bits)

(SP

)

(b) Exception Handling(a) Subroutine Branch

EXR* Reserved*1* CCR

CCR*

(16 bits)

Figure 2.2 Stack Structure in Normal Mode

2.2.2 Advanced Mode

• Address spac e Linear access to a maximum address space of 16 Mbytes is possible.

• Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the

upper 16-bit segments of 32-bit registers or address registers.

• Instruction set All instructions and addressing modes can be used.

Rev. 3.00, 07/04, page 27 of 928

• Exception vector table and memory indirect branch addresses

In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section 4, Exception Handling.

H'00000000

H'00000003 H'00000004

H'00000007 H'00000008

H'0000000B H'0000000C

H'00000010

Reserved

Reset exception vector

Reserved

(Reserved for system use)

Exception vector table

(Reserved for system use)

Reserved

Exception vector 1

Figure 2.3 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the top area of this range is also used for the exception vector table.

• Stack structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not pushed onto the stack in interrupt control mode 0. For d etails, see section 4, Exception Handling.

Rev. 3.00, 07/04, page 28 of 928

Notes: 1. When EXR is not used, it is not stored on the stack.

2. SP when EXR is not used.

3. Ignored when returning.

Reserved

(24 bits)

(a) Subroutine Branch (b) Exception Handling

(SP

Figure 2.4 Stack Structure in Advanced Mode

EXR*

)

Reserved*1* CCR

(24 bits)

Rev. 3.00, 07/04, page 29 of 928

2.3 Address Space

Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.

H'0000

64 kbyte 16 Mbyte

H'FFFF

Note: * For this LSI, normal mode is not available.

H'00000000

H'00FFFFFF

H'FFFFFFFF

Figure 2.5 Memory Map

Program area

Data area

Not available in this LSI

(b) Advanced Mode(a) Normal Mode*

Rev. 3.00, 07/04, page 30 of 928

2.4 Register Configuration

The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).

General Registers (Rn) and Extended Registers (En)

15 0 7 0 7 0 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP)

E0 E1 E2 E3 E4 E5 E6 E7

R0H R1H R2H R3H R4H R5H R6H R7H

R0L R1L R2L R3L R4L R5L R6L R7L

Control Registers

23 0

[Legend]

SP:

Stack pointer

PC:

Program counter

EXR:

Extended control register

Trace bit

I2 to I0:

Interrupt mask bits

CCR:

Condition-code register

Interrupt mask bit

UI:

User bit or interrupt mask bit*

Note: * For this LSI, the interrupt mask bit is not available.

Half-carry flag

User bit

Negative flag

Zero flag

Overflow flag

Carry flag

Figure 2.6 CPU Internal Registers

76543210 TI2I1I0

EXR

----

76543210

CCR

IUIHUNZVC

Rev. 3.00, 07/04, page 31 of 928

2.4.1 General Registers

The H8S/20 00 CPU has eight 3 2-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, provid ing a maximu m sixteen 16-bit registers. The E regi st ers (E0 to E 7) are also referred to as extended registers.

When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivale nt, providing a maximum sixteen 8-bit registers.

The usage of each register can be selected independently.

General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack.

• Address registers

• 32-bit registers

ER registers

(ER0 to ER7)

Figure 2.7 Usage of General Registers

Rev. 3.00, 07/04, page 32 of 928

• 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

RH registers

(R0H to R7H)

R registers

(R0 to R7)

RL registers

(R0L to R7L)

Free area

SP (ER7)

Stack area

Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. ( When an instruction is fetched for read, the least significant PC bit is regard ed as 0.)

2.4.3 Extended Control Register (EXR)

EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC instructions. When an instruction other than STC is executed, all interrupts including NMI are masked in three states after the instruction is completed.

Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

When this bit is set to 1, trace exception processing starts every when an instruction is executed. When this bit is cleare d to 0, inst ructions are consecutively executed.

6 to3– 1 – Reserved

These bits are always read as 1.

2 to 0 I2

I1 I0

1 R/W Interrupt Mask Bits 2 to 0

Specify interrupt request mask levels (0 to 7). For details, see section 5, Interrupt Controller.

Rev. 3.00, 07/04, page 33 of 928

2.4.4 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.

Rev. 3.00, 07/04, page 34 of 928

Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller.

6 UI Undefined R/W User Bit or Interrupt Mask Bit

Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. For this LSI, Interrupt Mask Bit is not available.

5 H Undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.

4 U Undefined R/W User Bit

Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit of data as a sign bit.

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to indicate a carry

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Rev. 3.00, 07/04, page 35 of 928

2.4.5 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.

2.5 Data Formats

The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data formats of general registers.

Data Type Register Number Data Format

65432710

Don't care

1-bit data

RnH

1-bit data

4-bit BCD data

Byte data

RnL

RnH

RnL

RnH

RnL

Figure 2.9 General Register Data Formats (1)

Rev. 3.00, 07/04, page 36 of 928

Don't care

7043

Upper Lower

Don't care

MSB LSB

Don't care

65432710

Don't care

7043

Upper Lower

Don't care

MSB LSB

Data Type Data FormatRegister Number

Word data

15 0

MSB LSB

Longword data

31 16

MSB

ERn

En Rn

[Legend]

General register ER

ERn:

General register E

En:

General register R

Rn:

General register RH

RnH:

General register RL

RnL:

Most significant bit

MSB:

Least significant bit

LSB:

Figure 2.9 General Register Data Formats (2)

15 0

MSB LSB

15 0

LSB

Rev. 3.00, 07/04, page 37 of 928

2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.

When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size.

Data T ype Address

1-bit data

Byte data

Word data

Longword data Address 2N

Address L

Address 2M Address 2M+1

Address 2N+1 Address 2N+2 Address 2N+3

76 543210

MSB

Figure 2.10 Memory Data Formats

Data Format

LSB

Rev. 3.00, 07/04, page 38 of 928

2.6 Instruction Set

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1.

Table 2.1 Instruction Classification

Function Instructions Size Types

Data transfer

Arithmetic operations

Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

Branch BCC*2, JMP, BSR, JSR, RTS – 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,

Block data transfer EEPMOV – 1

Notes: B: Byte size; W: Word size; L: Longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP.

2. BCC is the general name for conditional branch instructions.

3. Cannot be used in this LSI.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

MOV B/W/L 5 POP*1, PUSH*

W/L LDM, STM L MOVFPE*

, MOVTPE*

B ADD, SUB, CMP, NEG B/W/L 19 ADDX, SUBX, DAA, DAS B INC, DEC B/W/L ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W EXTU, EXTS W/L

TAS*

B/W/L 8 ROTXR

B14 BIAND, BOR, BIOR, BXOR, BIXOR

–9 NOP

Total: 65

Rev. 3.00, 07/04, page 39 of 928

2.6.1 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notation

Symbol Description

Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended contr ol r egi ster CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction

× Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical ex clusiv e OR → Move ∼ NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Rev. 3.00, 07/04, page 40 of 928

Table 2.3 Data Transfer Instructions

Instruction Size* Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register

and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W

@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn → @-SP

Pushes a general register onto the stack. PUSH.W Rn is identical to

MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM L @SP+ → Rn (register list )

Pops two or more general registers from the stack. STM L Rn (register list) → @-SP

Pushes two or more general registers onto the stack. Note: *Size refers to the operand size.

B: Byte W: Word L: Longword

Rev. 3.00, 07/04, page 41 of 928

Table 2.4 Arithmetic Operations Instructions

Instruction Size*

ADD SUB

ADDX SUBX

Function

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.)

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register.

INC DEC

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Adds or subtracts the value 1 or 2 to or from data in a general register.

(Only the value 1 can be added to or subtracted from byte operands.) ADDS SUBS DAA DAS

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

B Rd (decimal adjust) → Rd

Decimal-adjusts an addition or subtraction result in a general register by

referring to CCR to produce 4-bit BCD data. MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers: either

8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general registers: either 8

bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16

bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →

16-bit quotient and 16-bit remainder.

Rev. 3.00, 07/04, page 42 of 928

Instruction Size*

Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of data in a general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.

TAS*

B @ERd – 0, 1 → (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

Notes: 1. Size refers to the operand size.

B: Byte W: Word L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

Rev. 3.00, 07/04, page 43 of 928

Table 2.5 Logic Operations Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another

general register or immediate data. OR B/W/L Rd ∨ Rs → Rd , Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another

general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and

another general register or immediate data. NOT B/W/L ∼ Rd → Rd

Takes the one's complement (logical complement) of data in a general

B: Byte W: Word L: Longword

Table 2.6 Shift Instructions

Instruction Size* Function

SHAL SHAR

SHLL SHLR

ROTL ROTR ROTXL ROTXR

Note: *Size refers to the operand size.

Rev. 3.00, 07/04, page 44 of 928

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on data in a general register. 1-bit or 2 bit

shift is possible.

B/W/L Rd (shift) → Rd

Performs a logical shift on data in a general register. 1-bit or 2 bit shift is

possible.

B/W/L Rd (rotate) → Rd

Rotates data in a general register. 1-bit or 2 bit rotation is possible.

B/W/L Rd (rotate) → Rd

Rotates data including the carry flag in a general register. 1-bit or 2 bit

rotation is possible.

B: Byte W: Word L: Longword

Table 2.7 Bit Manipulation Instructions

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BTST B ∼ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

Logically ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

BIAND B C ∧ (<bit-No.> of <EAd>) → C

Logically ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit-No.> of <EAd>) → C

Logically ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

BIOR B C ∨ (∼ <bit-No.> of <EAd>) → C

Logically ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

Rev. 3.00, 07/04, page 45 of 928

Instruction Size* Function

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

BIXOR B C ⊕ ∼ (<bit-No.> of <EAd>) → C

Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to the carry flag.

BILD B ∼ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register or memory operand.

BIST B ∼ C → (<bit-No.>. of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3bit immediate data.

Note:* Size refers to the operand size.

B: Byte

Rev. 3.00, 07/04, page 46 of 928

Table 2.8 Branch Instructions

Instruction Size Function

Bcc – Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 BCC (BHS) Carry clear

(high or same) BCS (BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ⊕ V = 0 BLT Less than N ⊕ V = 1 BGT Greater than Z ∨ (N ⊕ V) = 0 BLE Less or equal Z ∨ (N ⊕ V) = 1

C = 0

JMP – Branches unconditionally to a specified address. BSR – Branches to a subroutine at a specified address. JSR – Branches to a subroutine at a specified address. RTS – Returns from a subroutine.

Rev. 3.00, 07/04, page 47 of 928

Table 2.9 System Control Instructions

Instruction Size* Function

TRAPA – Starts trap-instruction ex ception handling. RTE – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR

Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory operand. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with immediate data.

NOP – PC + 2 → PC

Only increments the program counter.

Note:* Size refers to the operand size.

B: Byte W: Word

Rev. 3.00, 07/04, page 48 of 928

Table 2.10 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B – if R4L ≠ 0 then

Repeat @ER5+ → @ER6+

R4L–1 → R4L

Until R4L = 0

else next:

EEPMOV.W – if R4 ≠ 0 then

Repeat @ER5+ → @ER6+

R4–1 → R4

Until R4 = 0

else next: Transfers a data block. Starting from the address set in ER5, transfers

data for the number of bytes set in R4L or R4 to the address location set in ER6.

Execution of the next instruction begins as soon as the transfer is completed.

2.6.2 Basic Instruction Formats

The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc).

Figure 2.11 shows examples of instruction formats.

• Operation field

Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields.

• Register field

Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bi ts. Some instruct i ons have two register fields, and some have no regist er field.

• Effective address extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition field

Specifies the branching condition of Bcc instructions.

Rev. 3.00, 07/04, page 49 of 928

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16, etc.

rn rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

Figure 2.11 Instruction Formats (Examples)

2.7 Addressing Modes and Effective Address Calculation

The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes.

Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment

Register indirect with pre-decrement 5 Absolute address @aa:8/@aa:16/@ aa:2 4/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8

Rev. 3.00, 07/04, page 50 of 928

@ERn+ @–ERn

RENESAS H8S-2368F-ZTAT User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Precautions on Handling of Product

Configuration of This Manual

Preface

Main Revisions for this Edition

Contents

Figures

Tables

Section 1 Overview

1.1 Features

1.2 Block Diagram

1.3 Pin Description

1.3.1 Pin Arrangement

1.3.2 Pin Arrangement in Each Operating Mode

1.3.3 Pin Functions

Section 2 CPU

2.1 Features

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

2.1.2 Differences from H8/300 CPU

2.1.3 Differences from H8/300H CPU

2.2 CPU Operating Modes

2.2.1 Normal Mode

2.2.2 Advanced Mode

2.3 Address Space

2.4 Register Configuration

2.4.1 General Registers

2.4.2 Program Counter (PC)

2.4.3 Extended Control Register (EXR)

2.4.4 Condition-Code Register (CCR)

2.4.5 Initial Register Values

2.5 Data Formats

2.5.1 General Register Data Formats

2.5.2 Memory Data Formats

2.6 Instruction Set

2.6.1 Table of Instructions Classified by Function

2.6.2 Basic Instruction Formats

2.7 Addressing Modes and Effective Address Calculation