Page 1
To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas
companies.
Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry
Electronics Corporation took over all the business of both
Renesas Electronics website: http://www.renesas.com
st
, 2010
April 1
Renesas Electronics Corporation
.
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Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
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Page 3
User’s Manual
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2158 Group,
TM
H8S/2158 F-ZTAT
Hardware Manual
Renesas 16-Bit Single-Chip
Microcomputer
H8S Family/H8S/2100 Series
H8S/2158 HD64F2158
Rev.3.00 2006.01
Page 4
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
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Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
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6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
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8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 3.00 Jan 25, 2006 page ii of lii
Page 5
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 3.00 Jan 25, 2006 page iii of lii
Page 6
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Main Revisions in This Edition
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
5. Contents
6Overview
7. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
8. List of Registers
9. Electrical Characteristics
10. Appendix
11. Index
Rev. 3.00 Jan 25, 2006 page iv of lii
Page 7
Preface
The H8S/2158 is a microcomputer made up of the H8S/2000 CPU employing Renesas
Technology’s original architecture as its core, and the peripheral functions required to configure a
system, such as a notebook PC and portable information appliance products.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a
16-Mbyte linear address space. The instruction set of the H8S/2600 CPU maintains upward
compatibility at the object level with the H8/300 CPU and H8/300H CPU. This allows the H8/300,
H8/300L, or H8/300H user to easily utilize the H8S/2600 CPU.
This LSI is equipped with ROM, RAM, two PWM timers (PWM and PWMX), a 16-bit freerunning timer (FRT), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication
interface (SCI), an I
chip peripheral modules required for system configuration.
2
C bus interface (IIC), a D/A converter, an A/D converter, and I/O ports as on-
In particular, this LSI incorporates a universal serial bus interface (USB) and a multimedia card
1
*
(MultiMediaCard™
) interface (MCIF) for system configuration using a flash memory card as
the recording media. In addition, the serial communication interface (SCI) has a smart card
interface function. Auxiliary hardware for encryption operation (DES, GF) conforming to the
2
*
“Keitaide-Music
to the secure multimedia card (Secure-MultiMediaCard™
” standard is necessary to protect music copyright. Thus, it is easy to interface
1
*
).
Further, a data transfer controller (DTC), and a RAM-FIFO unit (RFU) that can operate FIFOs
such as the USB and MCIF together are incorporated as a bus master.
3
*
The on-chip ROM is flash memory (F-ZTAT™
) with a capacity of 256 kbytes. ROM is
connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in
one state. Instruction fetching has been speeded up, and processing speed increased.
Two operating modes, modes 2 and 3, are provided, and there is a choice of address spaces and
modes, single-chip mode and external extended mode. Other unique operating modes, such as
writing the boot program to the flash memory, on-chip emulation, and boundary scan, are also
available.
Notes: 1. MultiMediaCard™ is a trademark of Infineon Technologies AG.
Secure-MultiMediaCard™ is a multimedia card with a content protection function.
2. Technology standards for systems that deliver digital contents, such as music over
mobile phones. These standards were put together by five companies: SANYO Electric
Co., Ltd., Fujitsu Limited, Nippon Columbia Co., Ltd., PFU Limited, and Hitachi, Ltd.
These standards consist of a security guideline, a protocol standard, a secure
Rev. 3.00 Jan 25, 2006 page v of lii
Page 8
multimedia card standard, and a download and playback system standard.
URL: http://www.keitaide-music.org/
3. F-ZTAT™ is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using the H8S/2158 in the design of
application systems. Target users are expected to understand the fundamentals of
electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2158 to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 28,
List of Registers.
Rules: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication, is implemented
on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev. 3.00 Jan 25, 2006 page vi of lii
Page 9
H8S/2158 manuals:
Document Title Document No.
H8S/2158 Hardware Manual This manual
H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139
User’s manuals for development tools:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User’s Manual
H8S, H8/300 Series Simulator/Debugger User’s Manual ADE-702-037
H8S, H8/300 Series High-performance Embedded Workshop,
High-performance Debugging Interface Tutorial
High-performance Embedded Workshop User’s Manual ADE-702-201
REJ10B0058
ADE-702-231
Rev. 3.00 Jan 25, 2006 page vii of lii
Page 10
Rev. 3.00 Jan 25, 2006 page viii of lii
Page 11
Main Revisions in This Edition
Item Page Revision (See Manual for Details)
All — All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors,
and other Hitachi brand names changed to Renesas
Technology Corp. Designation for categories changed from
“series” to “group”
Package
TQFP (TFP-100B) deleted
A)
Switching
5.3.4 IRQ Sense
Control Registers
(ISCR16H, ISCR16L,
ISCRH, ISCRL)
6.3.1 Bus Control
Register (BCR)
(Before) TFBGA (TBP-112) → (After) TFBGA (TBP-112
79 Description added
The ISCR registers
between pins IRQ15 to IRQ2 and pins ExIRQ15 to ExIRQ2 is
performed by means of IRQ sense port select register 16
(ISSR16) and the IRQ sense port select register (ISSR).
107 Bit table amended
Bit Bit Name Initial Value R/W Description
10IOS1
IOS0
1
1
...
or pins ExIRQ15 to ExIRQ2.
R/W
IOS Select 1, 0
R/W
Select the address range where the IOS signal is
output. For details, refer to table 6.8.
8.2.15 Data Transfer
ID Read/Write Select
Register B (DTIDSRB)
9.9.2 Port 9 Data
Register (P9DR)
179 Bit table amended
RAM → Peripheral modules (write)
0:
Peripheral modules (read) → RAM
1:
251 Table amended
(Before) R
/W → (After) R
13.1 Features 315 Description amended
• Cascading of two channels
— Cascading of TMR_0 and TMR_1
...
TMR_1 can be used to count TMR_0 compare-match
occurrences (compare-match count
• Multiple interrupt sources for each channel
mode).
...
Rev. 3.00 Jan 25, 2006 page ix of lii
Page 12
Item Page Revision (See Manual for Details)
13.3.4 Time Control
Register (TCR)
Table 13.2 Clock
Input to TCNT and
Count Condition
322 Table 13.2 amended
TMR_Y when (CKS2, CKS1, CKS0) = (1, 0, 0) (Before)
Increments at overflow signal from TCNT_X
prohibited
TMR_X when (CKS2, CKS1, CKS0) = (1, 0, 0) (Before)
*
→ (After) Setting
Increments at compare-match A from TCNT_Y → (After)
Setting prohibited
Note * amended
Note: * If the TMR_0 clock input is
generated. Simultaneous setting of this condition should
be
...
, a count-up clock cannot
therefore be avoided.
— — Description of “TMR_Y and TMR_X Cascaded Connection”
deleted
13.7 Input Capture
Operation
13.9.6 Mode Setting
with Cascaded
Connection
15.3 Register
Descriptions
16.3.7 Serial Status
Register (SSR)
336 Section number amended
344 Description amended
If the 16-bit count mode
and TCNT_
1 are not generated,
378 • TCSR_1
Notes amended
1
*
R/(W)
[Setting conditions] ...
• When TCSR is read when OVF = 1
OVF ...
402 Description amended
Bit Functions in Smart card Interface Mode (when SMIF in
SCMR = 1)
Bit 6 [Clearing conditions] ...
• When RFU is activated by RDR
from RDR (only for SCI_0 and SCI_2)
...
, the input clock pulses for TCNT_0
2
*
, then 0 is written to
F = 1 allowing data to be read
Rev. 3.00 Jan 25, 2006 page x of lii
Page 13
Item Page Revision (See Manual for Details)
16.3.9 Bit Rate
Register (BRR)
Table 16.2
Relationship between
405 Table 16.2 amended
Mode Bit Rate Error
Smart card
interface mode
B =
S × 2
φ × 10
2n+1
6
× (N + 1)
Error (%) =
N Setting in BRR and
Bit Rate B
16.3.10 Serial
Interface Control
Register (SCICR)
412 Table amended
Bit Bit Name Initial Value R/W Description
3, 2 — All 0 R/W
1, 0 — All 0 R Reserved
Reserved
The initial value should not be changed.
These bits are always read as 0 and cannot be
modified.
B × S ×2
φ × 10
2n+1
6
× (N + 1)
– 1 × 100
16.7.8 Clock Output
Control
16.8 IrDA Operation
Figure 16.36 IrDA
Block Diagram
455 Description amended
At Transition from Smart Card Interface Mode
Standby Mode:
1. Set the port data register (DR) ...
At Transition from
Software Standby Mode to Smart Card
Interface Mode:
1. Cancel software standby mode. ...
456 Figure 16.36 amended
TxD1/IrTxD
RxD1/IrRxD
Description amended
Transmission: ... The high-level pulse can be selected using
the IrCKS2 to IrCKS0 bits in
457 Description amended
Reception: ... IR frames are converted to UART frames using
the IrDA interface before inputting to
IrDA
Pulse encoder
Pulse decoder
SCICR
SCICR.
to Software
SCI_1
TxD1
RxD1
SCI_1. Data of level 0 is ...
Rev. 3.00 Jan 25, 2006 page xi of lii
Page 14
Item Page Revision (See Manual for Details)
17.3.8 IIC Operation
Reservation Adapter
Status Register A
(ICSRA)
17.3.10 IIC
Operation Reservation
Adapter Status
Register C (ICSRC)
Figure 17.3 State
Transitions of TDRE,
SDRF, and RDRF Bits
17.5.3 Master
Receive Operation
498 Bit table amended
ACKXE
(Before) R
/W → (After) R
506 Description amended
Bit 0 [Clearing conditions]
• When ICDRX is read from with no receive data in the shift
register (SDRF =
0) in receive mode ...
507 Figure 17.3 amended
(b) Receive mode
(Before)
(Before)
TDRE → (After) SDRE
SDRF → (After) RDRF
520 Description amended
9. Clear the IRIC flag in ICCR to cancel wait state.
The master device outputs the 9th clock and drives SDA
9th receive clock pulse ...
17.7 Usage Notes
Table 17.12
Permissible SCL Rise
Time (t
) Values
sr
542 Table 17.12 amended
IICX1,
t
cyc
Indication
IICX0
1 17.5 t
Standard mode 1000 1000 1000 1000 1000 875 700
cyc
2
I
C Bus
Specification
(Max.)
φ =
5 MHz
Time Indication[ns]
φ =
φ =
8 MHz
10 MHz
φ =
16 MHz
φ =
20 MHz
low at
φ =
25 MHz
Rev. 3.00 Jan 25, 2006 page xii of lii
Page 15
Item Page Revision (See Manual for Details)
17.7 Usage Notes 549,
550
Description added
15. Notes on WAIT function
(a) Conditions to cause this phenomenon
When both of the following conditions are satisfied, the clock
pulse of the 9th clock could be outputted continuously in master
mode using the WAIT function due to the failure of the WAIT
insertion after the 8th clock fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating
WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between
the fall of the 7th clock and the fall of the 8th clock.
(b) Error phenomenon
Normally, WAIT State will be cancelled by clearing the IRIC flag
bit from 1 to 0 after the fall of the 8th clock in WAIT State. In this
case, if the IRIC flag bit is cleared between the 7th clock fall and
the 8th clock fall, the IRIC flag clear- data will be retained
internally. Therefore, the WAIT State will be cancelled right after
WAIT insertion on 8th clock fall.
(c) Restrictions
Please clear the IRIC flag before the rise of the 7th clock (the
counter value of BC2 through BC0 should be 2 or greater), after
the IRIC flag is set to 1 on the rise of the 9th clock.
If the IRIC flag-clear is delayed due to the interrupt or other
processes and the value of BC counter is turned to 1 or 0,
please confirm the SCL pins are in L’ state after the counter
value of BC2 through BC0 is turned to 0, and clear the IRIC
flag. (See figure 17.28.)
ASD
SCL
BC2 to BC0
IRIC
(operation
example)
A
9
0
Transmit/receive data
1 2 3 4 5 6 7 8 9 1 2 3
7 6 5 4 3 2 1 0 7 6 5
IRIC flag clear available
IRIC flag clear unavailable
SCL =
‘L’ confirm
IRIC flag clear available
A
IRIC clear
Transmit/receive
data
When BC2-0 ≥ 2
IRIC clear
Figure 17.28 IRIC Flag Clear Timing on WAIT Operation
Rev. 3.00 Jan 25, 2006 page xiii of lii
Page 16
Item Page Revision (See Manual for Details)
17.7 Usage Notes 550,
551
16. Notes on Arbitration Lost
The I2C bus interface recognizes the data in transmit/receive
frame as an address when arbitration is lost in master mode
and a transition to slave receive mode is automatically carried
out.
When arbitration is lost not in the first frame but in the second
frame or subsequent frame, transmit/receive data that is not an
address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the
address in the SAR or SARX register, the I2C bus interface
erroneously recognizes that the address call has occurred. (See
figure 17.29.)
In multi-master mode, a bus conflict could happen. When The
I2C bus interface is operated in master mode, check the state of
the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or
subsequent frame, take avoidance measures.
• Arbitration is lost
2
C bus interface
I
(Master transmit mode)
Other device
(Master transmit mode)
2
C bus interface
I
(Slave receive mode)
S SLA
S SLA
S SLA
R/W
Transmit data match
Transmit timing match
R/W ADATA2
R/W ASLA R/W
• Receive address is ignored • Automatically transferred to slave
• The AL flag in ICSR is set to 1
A
A
A
receive mode
• Receive data is recognized as
an address
• When the receive data matches to
the address set in the SAR or SARX
register, the I
as a slave device
DATA1
Transmit data does not match
2
C bus interface operates
DATA3
DATA4
A
Data contention
A
Figure 17.29 Diagram of Erroneous Operation when
Arbitration is Lost
Though it is prohibited in the normal I2C protocol, the same
problem may occur when the MST bit is erroneously set to 1
and a transition to master mode is occurred during data
transmission or reception in slave mode. In multi-master mode,
pay attention to the setting of the MST bit when a bus conflict
may occur. In this case, the MST bit in the ICCR register should
be set to 1 according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and
the bus is free before setting the MST bit.
Rev. 3.00 Jan 25, 2006 page xiv of lii
Page 17
Item Page Revision (See Manual for Details)
17.7 Usage Notes 551
(b) Set the MST bit to 1.
(c) To confirm that the bus was not entered to the busy state
while the MST bit is being set, check that the BBSY flag in the
ICCR register is 0 immediately after the MST bit has been set.
Note: Above restriction can be cleared by setting bits FNC1 and
FNC0 in the ICXR register.
18.3.1 USB Data
FIFO
Table 18.2 FIFO
Configuration
557 Table 18.2 amended
Endpoint Transfer Direction FIFO Size Configuration Description
Endpoint 4 EP4 IN Max. 2048 bytes Max. 64 bytes
Endpoint 5 EP5 OUT Max. 2048 bytes Max. 64 bytes
× 32
× 32
RAM-FIFO
(RFU)
25.4.1 TAP
Controller State
Transitions
Figure 25.2 TAP
Controller State
Transitions
28.1 Register
Addresses (Address
Order)
28.1 Register Bits
755 Figure 25.2 replaced
792 Table amended
Register Name Abbreviation
Command register 5 CMDR5 8 H'FBC5 MCIF 8 3
Com
mand start register CMDSTRT 8 H'FBC6 MCIF 8 3
Operation control register OPCR 8 H'FBCA MCIF 8 3
793 Table amended
Register Name Abbreviation
Response register 16 RSPR16 8 H'FBF0 MCIF 8 3
Response register D RSPRD 8 H'FBF1 MCIF 8 3
Data timeout register H DTOUTRH 8 H'FBF2 MCIF 8 3
804 Table amended
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
CMDR5 CRC CRC CRC CRC CRC CRC CRC En
CMDSTRT ———————START
OPCR CMDOFF — RD_CONTI DATAEN ————
Number
of Bits
Number
of Bits
Address Module
Address Module
Data
Bus
Width
Data
Bus
Width
d
Number
of
Access
States
Number
of
Access
States
MCIF
805 Table amended
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
RSPR16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCIF
PSPRD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DTOUTRH DTOUT15 DTOUT14 DTOUT13 DTOUT12 DTOUT11 DTOUT10 DTOUT9 DTOUT8
Rev. 3.00 Jan 25, 2006 page xv of lii
Page 18
Item Page Revision (See Manual for Details)
28.1 Register Bits 808 Table amended
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
KBCOMP ———SCANE KBADE KBCH2 KBCH1 KBCH0 A/D
SCICR IrE IrCKS2 IrCKS1 IrCKS0 ————SCI_1
28.2 Register Bits 808 Bits 2 and 3 in SCICR description amended
IrTxINV → (After) —
IrRxINV → (After) —
High-Speed/
Medium-
Reset
Speed Watch Sleep Sub-Active Sub-Sleep
Module
Stop
28.3 Register States
in Each Operating
Mode
(Before)
(Before)
815 Table amended
Register
Abbreviation
CMDR5 Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized
CMDSTRT Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized
OPCR Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized
816 Table amended
High-Speed/
Medium-
Reset
Speed Watch Sleep Sub-Active Sub-Sleep
10
*
WEC
t
DRP
Module
Stop
8
*
100
10,000
10 — — Years
8. Minimum number of times for which all characteristics
29.6 Flash Memory
Characteristics
Table 29.18 Flash
Memory
Characteristics
Register
Abbreviation
RSPR16 Initialized — Initialized — Initialized Initialized Initialized Initialized Initializ
PSPRD Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized
DTOUTRH Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized
859 Table 29.18 amended
Item Symbol Min Typ Max Unit
Reprogramming count N
Data retention time
860 Notes *8*9*10 added
Notes:
are guaranteed after rewriting. (Guarantee range is 1 to
minimum value.)
9. Reference value for 25°C (as a guide line, rewriting should
normally function up to this value).
10. Data retention characteristics when rewriting is performed
within the specification range, including the minimum value.
B. Product Lineup
863 Product type amended
(Before) F2158VBP25 → (After) F2158VBQ25
C. Package
Figure of TFP-100B deleted
Dimensions
Figure C.1 Package
864 Figure C.1 replaced
Dimensions (TBP112A)
Software
Standby
Software
Standby
9
*
— Times
Hardware
Standby
Hardware
Standby
Test
Conditions
converter
Module
MCIF
Module
MCIF
ed
Rev. 3.00 Jan 25, 2006 page xvi of lii
Page 19
Contents
Section 1 Overview............................................................................................................. 1
1.1 Features ............................................................................................................................. 1
1.2 Internal Block Diagram..................................................................................................... 2
1.3 Pin Description.................................................................................................................. 3
1.3.1 Pin Arrangement.................................................................................................. 3
1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 4
1.3.3 Pin Functions ....................................................................................................... 8
Section 2 CPU ...................................................................................................................... 17
2.1 Features ............................................................................................................................. 17
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 18
2.1.2 Differences from H8/300 CPU ............................................................................ 19
2.1.3 Differences from H8/300H CPU.......................................................................... 19
2.2 CPU Operating Modes ...................................................................................................... 20
2.2.1 Normal Mode....................................................................................................... 20
2.2.2 Advanced Mode................................................................................................... 22
2.3 Address Space ................................................................................................................... 24
2.4 Register Configuration ...................................................................................................... 25
2.4.1 General Registers................................................................................................. 26
2.4.2 Program Counter (PC) ......................................................................................... 27
2.4.3 Extended Control Register (EXR) ....................................................................... 27
2.4.4 Condition-Code Register (CCR).......................................................................... 28
2.4.5 Initial Register Values.......................................................................................... 29
2.5 Data Formats ..................................................................................................................... 30
2.5.1 General Register Data Formats............................................................................ 30
2.5.2 Memory Data Formats ......................................................................................... 32
2.6 Instruction Set ................................................................................................................... 33
2.6.1 Table of Instructions Classified by Function ....................................................... 34
2.6.2 Basic Instruction Formats .................................................................................... 43
2.7 Addressing Modes and Effective Address Calculation..................................................... 44
2.7.1 Register Direct—Rn............................................................................................. 45
2.7.2 Register Indirect—@ERn.................................................................................... 45
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 45
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.. 45
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 46
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 46
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC).................................... 47
2.7.8 Memory Indirect—@@aa:8 ................................................................................ 47
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2.7.9 Effective Address Calculation.............................................................................. 48
2.8 Processing States............................................................................................................... 50
2.9 Usage Notes ...................................................................................................................... 52
2.9.1 Note on TAS Instruction Usage........................................................................... 52
2.9.2 Note on Bit Manipulation Instructions................................................................. 52
2.9.3 EEPMOV Instruction........................................................................................... 54
Section 3 MCU Operating Modes .................................................................................. 55
3.1 Operating Mode Selection................................................................................................. 55
3.2 Register Descriptions ........................................................................................................55
3.2.1 Mode Control Register (MDCR) ......................................................................... 56
3.2.2 System Control Register (SYSCR)...................................................................... 57
3.2.3 Serial Timer Control Register (STCR) ................................................................ 59
3.3 Operating Mode Descriptions ........................................................................................... 60
3.3.1 Mode 2................................................................................................................. 60
3.3.2 Mode 3................................................................................................................. 61
3.3.3 Pin Functions ....................................................................................................... 61
3.4 Address Map in Each Operating Mode ............................................................................. 62
Section 4 Exception Handling ......................................................................................... 65
4.1 Exception Handling Types and Priority ............................................................................ 65
4.2 Exception Sources and Exception Vector Table ............................................................... 66
4.3 Reset.................................................................................................................................. 67
4.3.1 Reset Exception Handling.................................................................................... 68
4.3.2 Interrupts after Reset............................................................................................ 69
4.3.3 On-Chip Peripheral Modules after Reset Is Cancelled ........................................ 69
4.4 Interrupt Exception Handling............................................................................................ 69
4.5 Trap Instruction Exception Handling................................................................................ 69
4.6 Stack Status after Exception Handling.............................................................................. 70
4.7 Usage Note........................................................................................................................ 71
Section 5 Interrupt Controller .......................................................................................... 73
5.1 Features ............................................................................................................................. 73
5.2 Input/Output Pins .............................................................................................................. 75
5.3 Register Descriptions ........................................................................................................75
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD)........................................... 76
5.3.2 Address Break Control Register (ABRKCR)....................................................... 77
5.3.3 Break Address Registers A to C (BARA to BARC)............................................ 78
5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................ 79
5.3.5 IRQ Enable Registers (IER16, IER) .................................................................... 81
5.3.6 IRQ Status Registers (ISR16, ISR)...................................................................... 82
Rev. 3.00 Jan 25, 2006 page xviii of lii
Page 21
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6)
Wake-Up Event Interrupt Mask Register (WUEMR3)........................................ 83
5.4 Interrupt Sources ............................................................................................................... 84
5.4.1 External Interrupts ............................................................................................... 84
5.4.2 Internal Interrupts................................................................................................. 86
5.5 Interrupt Exception Handling Vector Table...................................................................... 86
5.6 Interrupt Control Modes and Interrupt Operation ............................................................. 90
5.6.1 Interrupt Control Mode 0..................................................................................... 92
5.6.2 Interrupt Control Mode 1..................................................................................... 94
5.6.3 Interrupt Exception Handling Sequence .............................................................. 96
5.6.4 Interrupt Response Times .................................................................................... 98
5.6.5 DTC Activation by Interrupt................................................................................ 99
5.7 Usage Notes ...................................................................................................................... 101
5.7.1 Conflict between Interrupt Generation and Disabling ......................................... 101
5.7.2 Instructions that Disable Interrupts...................................................................... 102
5.7.3 Interrupts during Execution of EEPMOV Instruction.......................................... 102
Section 6 Bus Controller.................................................................................................... 103
6.1 Features ............................................................................................................................. 103
6.2 Input/Output Pins .............................................................................................................. 105
6.3 Register Descriptions ........................................................................................................ 106
6.3.1 Bus Control Register (BCR) ................................................................................ 106
6.3.2 Bus Control Register 2 (BCR2) ........................................................................... 108
6.3.3 Wait State Control Register (WSCR) .................................................................. 110
6.3.4 Wait State Control Register 2 (WSCR2) ............................................................. 112
6.4 Bus Control ....................................................................................................................... 113
6.4.1 Bus Specifications................................................................................................ 113
6.4.2 Advanced Mode................................................................................................... 121
6.4.3 Normal Mode....................................................................................................... 122
6.4.4 I/O Select Signals................................................................................................. 122
6.5 Basic Bus Interface ........................................................................................................... 123
6.5.1 Data Size and Data Alignment............................................................................. 123
6.5.2 Valid Strobes........................................................................................................ 124
6.5.3 Basic Operation Timing....................................................................................... 125
6.5.4 Wait Control ........................................................................................................ 133
6.6 Burst ROM Interface......................................................................................................... 134
6.6.1 Basic Operation Timing....................................................................................... 135
6.6.2 Wait Control ........................................................................................................ 136
6.7 Memory Card Interface ..................................................................................................... 137
6.7.1 Data Size and Data Alignment............................................................................. 137
6.7.2 Valid Strobes........................................................................................................ 138
Rev. 3.00 Jan 25, 2006 page xix of lii
Page 22
6.7.3 Basic Operation Timing....................................................................................... 138
6.7.4 Wait Control ........................................................................................................ 140
6.8 Idle Cycle .......................................................................................................................... 141
6.9 Bus Arbitration.................................................................................................................. 142
6.9.1 Bus Master Priority.............................................................................................. 142
6.9.2 Bus Transfer Timing............................................................................................ 143
Section 7 Data Transfer Controller (DTC)................................................................... 145
7.1 Features ............................................................................................................................. 145
7.2 Register Descriptions ........................................................................................................ 146
7.2.1 DTC Mode Register A (MRA) ............................................................................ 147
7.2.2 DTC Mode Register B (MRB)............................................................................. 148
7.2.3 DTC Source Address Register (SAR).................................................................. 149
7.2.4 DTC Destination Address Register (DAR).......................................................... 149
7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 149
7.2.6 DTC Transfer Count Register B (CRB)............................................................... 149
7.2.7 DTC Enable Registers (DTCER)......................................................................... 150
7.2.8 DTC Vector Register (DTVECR)........................................................................ 151
7.3 Activation Sources ............................................................................................................ 152
7.4 Location of Register Information and DTC Vector Table ................................................ 153
7.5 Operation........................................................................................................................... 156
7.5.1 Normal Mode....................................................................................................... 157
7.5.2 Repeat Mode........................................................................................................ 158
7.5.3 Block Transfer Mode........................................................................................... 159
7.5.4 Chain Transfer ..................................................................................................... 160
7.5.5 Interrupts.............................................................................................................. 161
7.5.6 Operation Timing................................................................................................. 161
7.5.7 Number of DTC Execution States........................................................................ 163
7.6 Procedures for Using DTC................................................................................................ 164
7.6.1 Activation by Interrupt......................................................................................... 164
7.6.2 Activation by Software ........................................................................................ 164
7.7 Examples of Use of the DTC ............................................................................................ 164
7.7.1 Normal Mode....................................................................................................... 164
7.7.2 Software Activation ............................................................................................. 165
7.8 Usage Notes ...................................................................................................................... 166
7.8.1 Module Stop Mode Setting .................................................................................. 166
7.8.2 On-Chip RAM ..................................................................................................... 166
7.8.3 DTCE Bit Setting................................................................................................. 166
7.8.4 Setting Required on Entering Subactive Mode or Watch Mode .......................... 166
7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter.................. 166
7.8.6 DTC Activation by Interrupt Sources of USB or MCIF ...................................... 166
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Page 23
Section 8 RAM-FIFO Unit (RFU).................................................................................. 167
8.1 Features ............................................................................................................................. 167
8.2 Register Descriptions ........................................................................................................ 169
8.2.1 FIFO Status/Register/Pointer (FSTR).................................................................. 169
8.2.2 Base Address Register (BAR).............................................................................. 170
8.2.3 Read Address Pointer (RAR)............................................................................... 170
8.2.4 Write Address Pointer (WAR)............................................................................. 171
8.2.5 Temporary Pointer (TMP) ................................................................................... 171
8.2.6 Valid Data Byte Number (DATAN).................................................................... 172
8.2.7 Free Area Byte Number (FREEN)....................................................................... 172
8.2.8 Read Start Address (NRA)................................................................................... 172
8.2.9 Write Start Address (NWA)................................................................................. 173
8.2.10 Data Transfer Control Register A (DTCRA) ....................................................... 173
8.2.11 Data Transfer Control Register B (DTCRB) ....................................................... 175
8.2.12 Data Transfer Status Register C (DTSTRC)........................................................ 176
8.2.13 Data Transfer ID Register (DTIDR) .................................................................... 178
8.2.14 Data Transfer ID Read/Write Select Register A (DTIDSRA) ............................. 178
8.2.15 Data Transfer ID Read/Write Select Register B (DTIDSRB).............................. 179
8.2.16 Data Transfer Status Register A (DTSTRA)........................................................ 179
8.2.17 Data Transfer Status Register B (DTSTRB)........................................................ 180
8.2.18 Data Transfer Control Register C (DTCRC)........................................................ 180
8.2.19 Data Transfer Control Register D (DTCRD)....................................................... 181
8.2.20 Data Transfer Interrupt Enable Register (DTIER)............................................... 181
8.2.21 Data Transfer Register Select Register (DTRSR)................................................ 181
8.3 Activation Source and Priority.......................................................................................... 183
8.4 RAM-FIFO Location ........................................................................................................ 184
8.5 RAM-FIFO Pointer ........................................................................................................... 184
8.6 RAM-FIFO Manipulation and RFU Bus Cycles............................................................... 184
8.7 RFU Bus Cycle ................................................................................................................. 188
8.7.1 Clock Division ..................................................................................................... 188
8.7.2 RFU Bus Cycle Insertion..................................................................................... 189
8.7.3 RFU Response Time ............................................................................................ 189
8.8 Operation........................................................................................................................... 191
8.8.1 Transmission/Reception of Single Data Block .................................................... 191
8.8.2 Transmission/Reception of Consecutive Data Blocks ......................................... 192
8.8.3 RFU Manipulation by USB.................................................................................. 193
8.8.4 RFU Manipulation by SCI................................................................................... 197
8.8.5 RFU Manipulation by MCIF................................................................................ 200
8.9 Interrupt Sources ............................................................................................................... 202
8.10 RFU Initialization ............................................................................................................. 203
8.11 Usage Notes ...................................................................................................................... 204
Rev. 3.00 Jan 25, 2006 page xxi of lii
Page 24
Section 9 I/O Ports .............................................................................................................. 205
9.1 Port 1 ................................................................................................................................. 209
9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 209
9.1.2 Port 1 Data Register (P1DR)................................................................................ 210
9.1.3 Port 1 Pull-Up MOS Control Register (P1PCR).................................................. 210
9.1.4 Pin Functions ....................................................................................................... 211
9.1.5 Port 1 Input Pull-Up MOS ................................................................................... 211
9.2 Port 2 ................................................................................................................................. 212
9.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 212
9.2.2 Port 2 Data Register (P2DR)................................................................................ 213
9.2.3 Port 2 Pull-Up MOS Control Register (P2PCR).................................................. 213
9.2.4 Pin Functions ....................................................................................................... 214
9.2.5 Port 2 Input Pull-Up MOS ................................................................................... 215
9.3 Port 3 ................................................................................................................................. 215
9.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 216
9.3.2 Port 3 Data Register (P3DR)................................................................................ 216
9.3.3 Port 3 Pull-Up MOS Control Register (P3PCR).................................................. 217
9.3.4 Pin Functions ....................................................................................................... 217
9.3.5 Port 3 Input Pull-Up MOS ................................................................................... 222
9.4 Port 4 ................................................................................................................................. 222
9.4.1 Port 4 Data Direction Register (P4DDR)............................................................. 223
9.4.2 Port 4 Data Register (P4DR)................................................................................ 223
9.4.3 Pin Functions ....................................................................................................... 224
9.5 Port 5 ................................................................................................................................. 228
9.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 228
9.5.2 Port 5 Data Register (P5DR)................................................................................ 229
9.5.3 Pin Functions ....................................................................................................... 229
9.6 Port 6 ................................................................................................................................. 232
9.6.1 Port 6 Data Direction Register (P6DDR)............................................................. 233
9.6.2 Port 6 Data Register (P6DR)................................................................................ 233
9.6.3 Port 6 Pull-Up MOS Control Register (KMPCR6).............................................. 234
9.6.4 System Control Register 2 (SYSCR2)................................................................. 235
9.6.5 Pin Functions ....................................................................................................... 236
9.6.6 Port 6 Input Pull-Up MOS ................................................................................... 244
9.7 Port 7 ................................................................................................................................. 244
9.7.1 Port 7 Input Data Register (P7PIN) ..................................................................... 244
9.8 Port 8 ................................................................................................................................. 245
9.8.1 Port 8 Data Direction Register (P8DDR)............................................................. 245
9.8.2 Port 8 Data Register (P8DR)................................................................................ 246
9.8.3 Pin Functions ....................................................................................................... 246
9.9 Port 9 ................................................................................................................................. 250
Rev. 3.00 Jan 25, 2006 page xxii of lii
Page 25
9.9.1 Port 9 Data Direction Register (P9DDR)............................................................. 250
9.9.2 Port 9 Data Register (P9DR)................................................................................ 251
9.9.3 Pin Functions ....................................................................................................... 251
9.10 Port A................................................................................................................................ 254
9.10.1 Port A Data Direction Register (PADDR)........................................................... 254
9.10.2 Port A Output Data Register (PAODR)............................................................... 254
9.10.3 Port A Input Data Register (PAPIN).................................................................... 255
9.10.4 Pin Functions ....................................................................................................... 255
9.10.5 Input Pull-Up MOS.............................................................................................. 257
9.11 Change of Peripheral Function Pins.................................................................................. 258
9.11.1 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select
Register (ISSR) .................................................................................................... 258
9.11.2 Port Control Register 0 (PTCNT0) ...................................................................... 260
Section 10 8-Bit PWM Timer (PWM) .......................................................................... 261
10.1 Features............................................................................................................................. 261
10.2 Input/Output Pins.............................................................................................................. 263
10.3 Register Descriptions........................................................................................................ 263
10.3.1 PWM Register Select (PWSL)............................................................................. 264
10.3.2 PWM Data Registers (PWDR0 to PWDR15)...................................................... 266
10.3.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 266
10.3.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 267
10.3.5 Peripheral Clock Select Register (PCSR) ............................................................ 269
10.4 Operation........................................................................................................................... 270
Section 11 14-Bit PWM Timer (PWMX)..................................................................... 273
11.1 Features............................................................................................................................. 273
11.2 Input/Output Pins.............................................................................................................. 274
11.3 Register Descriptions........................................................................................................ 274
11.3.1 PWM D/A Counter H, L (DACNTH, DACNTL)................................................ 275
11.3.2 PWM (D/A) Data Registers A and B (DADRA and DADRB)............................ 276
11.3.3 PWM (D/A) Control Register (DACR) ............................................................... 277
11.3.4 Peripheral Clock Select Register (PCSR) ............................................................ 279
11.4 Bus Master Interface......................................................................................................... 280
11.5 Operation........................................................................................................................... 281
Section 12 16-Bit Free-Running Timer (FRT)............................................................ 287
12.1 Features............................................................................................................................. 287
12.2 Input/Output Pins.............................................................................................................. 289
12.3 Register Descriptions........................................................................................................ 289
12.3.1 Free-Running Counter (FRC) .............................................................................. 290
Rev. 3.00 Jan 25, 2006 page xxiii of lii
Page 26
12.3.2 Output Compare Registers A and B (OCRA and OCRB).................................... 290
12.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 290
12.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) ......................... 291
12.3.5 Output Compare Register DM (OCRDM) ........................................................... 291
12.3.6 Timer Interrupt Enable Register (TIER).............................................................. 292
12.3.7 Timer Control/Status Register (TCSR)................................................................ 293
12.3.8 Timer Control Register (TCR)............................................................................. 296
12.3.9 Timer Output Compare Control Register (TOCR) .............................................. 297
12.4 Operation........................................................................................................................... 299
12.4.1 Pulse Output......................................................................................................... 299
12.5 Operation Timing.............................................................................................................. 300
12.5.1 FRC Increment Timing ........................................................................................ 300
12.5.2 Output Compare Output Timing .......................................................................... 301
12.5.3 FRC Clear Timing................................................................................................ 301
12.5.4 Input Capture Input Timing ................................................................................. 302
12.5.5 Buffered Input Capture Input Timing .................................................................. 303
12.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 304
12.5.7 Timing of Output Compare Flag (OCF) setting................................................... 305
12.5.8 Timing of FRC Overflow Flag Setting ................................................................ 305
12.5.9 Automatic Addition Timing................................................................................. 306
12.5.10 Mask Signal Generation Timing .......................................................................... 307
12.6 Interrupt Sources............................................................................................................... 308
12.7 Usage Notes ...................................................................................................................... 309
12.7.1 Conflict between FRC Write and Clear ............................................................... 309
12.7.2 Conflict between FRC Write and Increment........................................................ 310
12.7.3 Conflict between OCR Write and Compare-Match ............................................. 311
12.7.4 Switching of Internal Clock and FRC Operation................................................. 312
Section 13 8-Bit Timer (TMR)........................................................................................ 315
13.1 Features............................................................................................................................. 315
13.2 Input/Output Pins.............................................................................................................. 318
13.3 Register Descriptions........................................................................................................ 318
13.3.1 Timer Counter (TCNT)........................................................................................ 320
13.3.2 Time Constant Register A (TCORA)................................................................... 320
13.3.3 Time Constant Register B (TCORB)................................................................... 320
13.3.4 Timer Control Register (TCR)............................................................................. 321
13.3.5 Timer Control/Status Register (TCSR)................................................................ 323
13.3.6 Input Capture Register (TICR) ............................................................................ 328
13.3.7 Time Constant Register (TCORC)....................................................................... 328
13.3.8 Input Capture Registers R and F (TICRR and TICRF)........................................ 329
13.3.9 Timer Input Select Register (TISR) ..................................................................... 329
Rev. 3.00 Jan 25, 2006 page xxiv of lii
Page 27
13.4 Operation........................................................................................................................... 330
13.4.1 Pulse Output......................................................................................................... 330
13.5 Operation Timing.............................................................................................................. 331
13.5.1 TCNT Count Timing............................................................................................ 331
13.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 332
13.5.3 Timing of Timer Output at Compare-Match........................................................ 332
13.5.4 Timing of Counter Clear at Compare-Match....................................................... 333
13.5.5 TCNT External Reset Timing.............................................................................. 333
13.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 334
13.6 TMR_0 and TMR_1 Cascaded Connection ...................................................................... 335
13.6.1 16-Bit Count Mode .............................................................................................. 335
13.6.2 Compare-Match Count Mode .............................................................................. 335
13.7 Input Capture Operation.................................................................................................... 336
13.8 Interrupt Sources............................................................................................................... 338
13.9 Usage Notes ...................................................................................................................... 339
13.9.1 Conflict between TCNT Write and Clear ............................................................ 339
13.9.2 Conflict between TCNT Write and Increment ..................................................... 340
13.9.3 Conflict between TCOR Write and Compare-Match........................................... 341
13.9.4 Conflict between Compare-Matches A and B...................................................... 342
13.9.5 Switching of Internal Clocks and TCNT Operation............................................. 342
13.9.6 Mode Setting with Cascaded Connection ............................................................ 344
Section 14 Timer Connection........................................................................................... 345
14.1 Features............................................................................................................................. 345
14.2 Input/Output Pins.............................................................................................................. 347
14.3 Register Descriptions........................................................................................................ 347
14.3.1 Timer Connection Register I (TCONRI) ............................................................. 348
14.3.2 Timer Connection Register O (TCONRO) .......................................................... 352
14.3.3 Timer Connection Register S (TCONRS)............................................................ 354
14.3.4 Edge Sense Register (SEDGR) ............................................................................ 356
14.4 Operation........................................................................................................................... 358
14.4.1 PWM Decoding (PDC Signal Generation) .......................................................... 358
14.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 359
14.4.3 8-Bit Timer Divided Waveform Period Measurement......................................... 361
14.4.4 IHI Signal and 2fH Modification ......................................................................... 363
14.4.5 IVI Signal Fall Modification and IHI Synchronization........................................ 365
14.4.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) 367
14.4.7 HSYNCO Output ................................................................................................. 370
14.4.8 VSYNCO Output ................................................................................................. 371
14.4.9 CBLANK Output ................................................................................................. 372
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Section 15 Watchdog Timer (WDT).............................................................................. 373
15.1 Features............................................................................................................................. 373
15.2 Input/Output Pins.............................................................................................................. 375
15.3 Register Descriptions........................................................................................................ 375
15.3.1 Timer Counter (TCNT)........................................................................................ 375
15.3.2 Timer Control/Status Register (TCSR)................................................................ 376
15.4 Operation........................................................................................................................... 379
15.4.1 Watchdog Timer Mode........................................................................................ 379
15.4.2 Interval Timer Mode ............................................................................................ 381
15.4.3 RESO Signal Output Timing ............................................................................... 382
15.5 Interrupt Sources............................................................................................................... 382
15.6 Usage Notes ...................................................................................................................... 383
15.6.1 Notes on Register Access..................................................................................... 383
15.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 384
15.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 384
15.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 384
15.6.5 System Reset by RESO Signal............................................................................. 385
15.6.6 Counter Values during Transitions between High-Speed, Sub-Active,
and Watch Modes ................................................................................................ 385
Section 16 Serial Communication Interface (SCI, IrDA, and CRC).................... 387
16.1 Features............................................................................................................................. 387
16.2 Input/Output Pins.............................................................................................................. 391
16.3 Register Descriptions........................................................................................................ 391
16.3.1 Receive Shift Register (RSR) .............................................................................. 392
16.3.2 Receive Data Register (RDR) .............................................................................. 392
16.3.3 Transmit Data Register (TDR)............................................................................. 392
16.3.4 Transmit Shift Register (TSR) ............................................................................. 392
16.3.5 Serial Mode Register (SMR)................................................................................ 393
16.3.6 Serial Control Register (SCR).............................................................................. 396
16.3.7 Serial Status Register (SSR) ................................................................................ 398
16.3.8 Smart Card Mode Register (SCMR).................................................................... 404
16.3.9 Bit Rate Register (BRR) ...................................................................................... 405
16.3.10 Serial Interface Control Register (SCICR)........................................................... 412
16.3.11 Serial Enhanced Mode Register_0 and 2 (SEMR_0 and SEMR_2) .................... 412
16.3.12 Serial RFU Enable Register_0 and 2 (SCIDTER_0 and SCIDTER_2)............... 416
16.4 Operation in Asynchronous Mode .................................................................................... 417
16.4.1 Data Transfer Format........................................................................................... 418
16.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 419
16.4.3 Clock .................................................................................................................... 420
16.4.4 Serial Enhanced Mode Clock............................................................................... 421
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16.4.5 SCI Initialization (Asynchronous Mode) ............................................................. 424
16.4.6 Serial Data Transmission (Asynchronous Mode) ................................................425
16.4.7 Serial Data Reception (Asynchronous Mode)...................................................... 427
16.5 Multiprocessor Communication Function......................................................................... 431
16.5.1 Multiprocessor Serial Data Transmission ............................................................ 432
16.5.2 Multiprocessor Serial Data Reception ................................................................. 433
16.6 Operation in Clocked Synchronous Mode ........................................................................ 437
16.6.1 Clock .................................................................................................................... 437
16.6.2 SCI Initialization (Synchronous).......................................................................... 437
16.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 438
16.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 441
16.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) ............................................................................. 443
16.6.6 SCI Selection in Serial Enhanced Mode .............................................................. 443
16.7 Smart Card Interface Description...................................................................................... 445
16.7.1 Sample Connection .............................................................................................. 445
16.7.2 Data Format (Except in Block Transfer Mode) ................................................... 446
16.7.3 Block Transfer Mode ........................................................................................... 447
16.7.4 Receive Data Sampling Timing and Reception Margin....................................... 447
16.7.5 Initialization ......................................................................................................... 449
16.7.6 Serial Data Transmission (Except in Block Transfer Mode) ............................... 450
16.7.7 Serial Data Reception (Except in Block Transfer Mode)..................................... 453
16.7.8 Clock Output Control........................................................................................... 454
16.8 IrDA Operation ................................................................................................................. 456
16.9 Interrupt Sources............................................................................................................... 459
16.9.1 Interrupts in Normal Serial Communication Interface Mode............................... 459
16.9.2 Interrupts in Smart Card Interface Mode ............................................................. 460
16.10 Usage Notes ...................................................................................................................... 461
16.10.1 Module Stop Mode Setting .................................................................................. 461
16.10.2 Break Detection and Processing........................................................................... 461
16.10.3 Mark State and Break Detection .......................................................................... 462
16.10.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only)..................................................................... 462
16.10.5 Relation between Writing to TDR and TDRE Flag ............................................. 462
16.10.6 Restrictions on Using DTC or RFU..................................................................... 462
16.10.7 SCI Operations during Mode Transitions ............................................................ 463
16.10.8 Notes on Switching from SCK Pins to Port Pins ................................................. 466
16.11 CRC Operation Circuit...................................................................................................... 467
16.11.1 Features................................................................................................................ 467
16.11.2 Register Descriptions ........................................................................................... 467
16.11.3 CRC Operation Circuit Operation........................................................................ 469
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16.11.4 Note on CRC Operation Circuit........................................................................... 472
Section 17 I2C Bus Interface (IIC).................................................................................. 473
17.1 Features............................................................................................................................. 473
17.2 Input/Output Pins.............................................................................................................. 476
17.3 Register Descriptions........................................................................................................ 476
17.3.1 I
17.3.2 Slave Address Register (SAR)............................................................................. 480
17.3.3 Second Slave Address Register (SARX) ............................................................. 481
17.3.4 I
17.3.5 I
17.3.6 I
17.3.7 IIC Operation Reservation Adapter Control Register (ICCRX) .......................... 496
17.3.8 IIC Operation Reservation Adapter Status Register A (ICSRA) ......................... 497
17.3.9 IIC Operation Reservation Adapter Status Register B (ICSRB).......................... 499
17.3.10 IIC Operation Reservation Adapter Status Register C (ICSRC).......................... 502
17.3.11 IIC Operation Reservation Adapter Data Register (ICDRX)............................... 507
17.3.12 IIC Data Shift Register (ICDRS) ......................................................................... 508
17.3.13 IIC Operation Reservation Adapter Count Register (ICCNT)............................. 508
17.3.14 IIC Operation Reservation Adapter Command Register (ICCMD)..................... 510
17.4 IIC Operation Reservation Adapter................................................................................... 510
17.4.1 Restrictions on Accessing IIC Registers .............................................................. 510
17.4.2 Operation Reservation Commands ...................................................................... 512
17.5 Operation........................................................................................................................... 516
17.5.1 I
17.5.2 Master Transmit Operation .................................................................................. 517
17.5.3 Master Receive Operation.................................................................................... 519
17.5.4 Slave Receive Operation...................................................................................... 522
17.5.5 Slave Transmit Operation .................................................................................... 525
17.5.6 IRIC Setting Timing and SCL Control ................................................................ 527
17.5.7 Operation Using DTC .......................................................................................... 531
17.5.8 Noise Canceler ..................................................................................................... 533
17.5.9 Initialization of Internal State .............................................................................. 534
17.5.10 Sample Flowcharts............................................................................................... 535
17.6 Interrupt Sources............................................................................................................... 539
17.7 Usage Notes ...................................................................................................................... 541
2
C Bus Data Register (ICDR)............................................................................. 477
2
C Bus Mode Register (ICMR)........................................................................... 482
2
C Bus Control Register (ICCR)......................................................................... 485
2
C Bus Status Register (ICSR)............................................................................ 492
2
C Bus Data Format............................................................................................ 516
Section 18 Universal Serial Bus Interface (USB) ...................................................... 553
18.1 Features............................................................................................................................. 553
18.2 Input/Output Pins.............................................................................................................. 555
18.3 Register Descriptions........................................................................................................ 555
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18.3.1 USB Data FIFO.................................................................................................... 557
18.3.2 Endpoint Size Register 1 (EPSZR1) .................................................................... 558
18.3.3 Endpoint Data Registers 0S, 0O, 0I, 1, 2, and 3
(EPDR0S, EPDR0O, EPDR0I, EPDR1, EPDR2, and EPDR3)........................... 559
18.3.4 Endpoint Valid Size Registers 0S, 0O, 0I, 1, 2, and 3
(FVSR0S, FVSR0O, FVSR0I, FVSR1, FVSR 2, and FVSR3) ........................... 560
18.3.5 Endpoint Direction Register 0 (EPDIR0) ............................................................ 563
18.3.6 Packet Transfer Enable Register 0 (PTTER0) ..................................................... 564
18.3.7 USB Interrupt Enable Registers 0 and 1 (USBIER0, USBIER1) ........................ 565
18.3.8 USB Interrupt Flag Registers 0 and 1 (USBIFR0, USBIFR1)............................. 567
18.3.9 Transfer Normal Completion Interrupt Flag Register 0 (TSFR0)........................ 571
18.3.10 Transfer Abnormal Completion Interrupt Flag Register 0 (TFFR0).................... 576
18.3.11 USB Control /Status Register 0 (USBCSR0)....................................................... 581
18.3.12 Endpoint Stall Register 0 (EPSTLR0) ................................................................. 584
18.3.13 Endpoint Reset Register 0 (EPRSTR0)................................................................ 587
18.3.14 Device Resume Register (DEVRSMR) ............................................................... 589
18.3.15 Interrupt Source Select Register 0 (INTSELR0).................................................. 590
18.3.16 USB Control Registers 0 and 1 (USBCR0, USBCR1) ........................................ 592
18.3.17 USB PLL Control Register (UPLLCR) ............................................................... 595
18.3.18 Configuration Value Register (CONFV) ............................................................. 597
18.3.19 Endpoint 4 Packet Size Register (EP4PKTSZR)................................................. 598
18.3.20 RFU/FIFO Read Request Flag Register (UDTRFR) ........................................... 599
18.3.21 USB Mode Control Register (USBMDCR)......................................................... 600
18.3.22 USB Port Control Register (UPRTCR), and USB Test Registers 0 and 1
(UTESTR0 and UTESTR1)................................................................................. 601
18.4 Operation........................................................................................................................... 602
18.4.1 USB Function Core Functions ............................................................................. 602
18.4.2 Operation on Receiving a SETUP Token (Endpoint 0) ....................................... 604
18.4.3 Operation on Receiving an OUT Token (Endpoints 0, 2, and 5)......................... 610
18.4.4 Operation on Receiving an IN Token (Endpoints 0, 1, 2, 3 and 4)...................... 614
18.4.5 Suspend/Resume Operation ................................................................................. 618
18.4.6 USB Module Reset and Operation Stop Modes................................................... 618
18.4.7 USB Module Startup Sequence............................................................................ 621
18.5 Interrupt Sources............................................................................................................... 625
18.6 Usage Notes ...................................................................................................................... 626
Section 19 Multimedia Card Interface (MCIF)........................................................... 627
19.1 Features............................................................................................................................. 627
19.2 Input/Output Pins.............................................................................................................. 629
19.3 Register Descriptions........................................................................................................ 630
19.3.1 Mode Register (MODER) .................................................................................... 631
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19.3.2 Command Type Register (CMDTYR)................................................................. 632
19.3.3 Response Type Register (RSPTYR) .................................................................... 633
19.3.4 Transfer Byte Number Count Register (TBCR) .................................................. 636
19.3.5 Transfer Block Number Counter (TBNCR)......................................................... 636
19.3.6 Command Registers 0 to 5 (CMDR0 to CMDR5)............................................... 637
19.3.7 Response Registers 0 to 16, and D (RSPR0 to RSPR16, and RSPRD) ............... 638
19.3.8 Command Start Register (CMDSTRT)................................................................ 640
19.3.9 Operation Control Register (OPCR) .................................................................... 641
19.3.10 Command Timeout Control Register (CTOCR) .................................................. 643
19.3.11 Data Timeout Register (DTOUTR) ..................................................................... 644
19.3.12 Card Status Register (CSTR) ............................................................................... 645
19.3.13 Interrupt Control Registers 0, 1 (INTCR0, INTCR1).......................................... 647
19.3.14 Interrupt Status Registers 0, 1 (INTSTR0, INTSTR1)......................................... 649
19.3.15 Pin Mode Control Register (IOMCR).................................................................. 653
19.3.16 Transfer Clock Control Register (CLKON)......................................................... 654
19.4 MCIF Activation............................................................................................................... 655
19.4.1 Initial Status ......................................................................................................... 655
19.4.2 Activation Procedure ........................................................................................... 655
19.5 Operations in MMC Mode................................................................................................ 656
19.5.1 Operation of Broadcast Commands ..................................................................... 656
19.5.2 Operation of Relative Address Commands.......................................................... 657
19.5.3 Operation of Commands Not Requiring Command Response............................. 657
19.5.4 Operation of Commands without Data Transfer .................................................. 659
19.5.5 Commands with Read Data.................................................................................. 663
19.5.6 Commands with Write Data................................................................................. 669
19.6 Operations in SPI Mode.................................................................................................... 675
19.6.1 Operation of Commands without Data Transfer .................................................. 675
19.6.2 Commands with Read Data.................................................................................. 679
19.6.3 Commands with Write Data................................................................................. 683
19.7 Interrupt Sources............................................................................................................... 687
19.8 Usage Notes ...................................................................................................................... 687
Section 20 Encryption Operation Circuit (DES and GF)......................................... 689
Section 21 D/A Converter................................................................................................. 691
21.1 Features............................................................................................................................. 691
21.2 Input/Output Pins.............................................................................................................. 692
21.3 Register Descriptions........................................................................................................ 692
21.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 692
21.3.2 D/A Control Register (DACR) ............................................................................ 692
21.4 Operation........................................................................................................................... 694
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21.5 Usage Notes ...................................................................................................................... 695
Section 22 A/D Converter................................................................................................. 697
22.1 Features............................................................................................................................. 697
22.2 Input/Output Pins.............................................................................................................. 699
22.3 Register Descriptions........................................................................................................ 700
22.3.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 700
22.3.2 A/D Control/Status Register (ADCSR) ............................................................... 701
22.3.3 A/D Control Register (ADCR) ............................................................................ 702
22.3.4 Keyboard Comparator Control Register (KBCOMP).......................................... 703
22.4 DTC Comparator Scan...................................................................................................... 704
22.5 Operation........................................................................................................................... 705
22.5.1 Single Mode ......................................................................................................... 705
22.5.2 Scan Mode ........................................................................................................... 706
22.5.3 Input Sampling and A/D Conversion Time.......................................................... 706
22.5.4 External Trigger Input Timing ............................................................................. 708
22.6 Interrupt Source................................................................................................................. 708
22.7 A/D Conversion Accuracy Definitions ............................................................................. 709
22.8 Usage Notes ...................................................................................................................... 711
22.8.1 Permissible Signal Source Impedance ................................................................. 711
22.8.2 Influences on Absolute Accuracy ........................................................................ 711
22.8.3 Setting Range of Analog Power Supply and Other Pins...................................... 712
22.8.4 Notes on Board Design ........................................................................................ 712
22.8.5 Notes on Noise Countermeasures ........................................................................ 712
Section 23 RAM .................................................................................................................. 715
Section 24 ROM .................................................................................................................. 717
24.1 Features............................................................................................................................. 717
24.2 Mode Transition Diagrams ............................................................................................... 718
24.3 Block Configuration.......................................................................................................... 722
24.4 Input/Output Pins.............................................................................................................. 723
24.5 Register Descriptions........................................................................................................ 723
24.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 723
24.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 725
24.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) .................................................... 725
24.6 Operating Modes............................................................................................................... 727
24.7 On-Board Programming Modes........................................................................................ 727
24.7.1 Boot Mode ........................................................................................................... 728
24.7.2 User Program Mode ............................................................................................. 732
24.8 Flash Memory Programming/Erasing ............................................................................... 732
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24.8.1 Program/Program-Verify ..................................................................................... 733
24.8.2 Erase/Erase-Verify ............................................................................................... 735
24.9 Program/Erase Protection.................................................................................................. 737
24.9.1 Hardware Protection ............................................................................................ 737
24.9.2 Software Protection.............................................................................................. 737
24.9.3 Error Protection.................................................................................................... 737
24.10 Interrupts during Flash Memory Programming/Erasing ................................................... 738
24.11 Programmer Mode ............................................................................................................ 738
24.12 Usage Notes ...................................................................................................................... 739
Section 25 User Debug Interface (H-UDI)................................................................... 741
25.1 Features............................................................................................................................. 741
25.2 Input/Output Pins.............................................................................................................. 743
25.3 Register Descriptions........................................................................................................ 744
25.3.1 Instruction Register (SDIR) ................................................................................. 744
25.3.2 Bypass Register (SDBPR) ................................................................................... 746
25.3.3 Boundary Scan Register (SDBSR)....................................................................... 746
25.3.4 ID Code Register (SDIDR) .................................................................................. 754
25.4 Operation........................................................................................................................... 755
25.4.1 TAP Controller State Transitions......................................................................... 755
25.4.2 H-UDI Reset ........................................................................................................ 755
25.5 Boundary Scan.................................................................................................................. 756
25.5.1 Supported Instructions ......................................................................................... 756
25.5.2 Notes .................................................................................................................... 757
25.6 Usage Notes ...................................................................................................................... 758
Section 26 Clock Pulse Generator .................................................................................. 761
26.1 Oscillator........................................................................................................................... 762
26.1.1 Connecting a Crystal Oscillator ........................................................................... 762
26.1.2 External Clock Input Method............................................................................... 763
26.2 Duty Correction Circuit..................................................................................................... 765
26.3 Medium-Speed Clock Divider .......................................................................................... 766
26.4 Bus Master Clock Select Circuit....................................................................................... 766
26.5 Subclock Input Circuit ...................................................................................................... 766
26.6 Waveform Forming Circuit............................................................................................... 767
26.7 Clock Select Circuit .......................................................................................................... 767
26.8 PLL Circuit ....................................................................................................................... 767
26.9 Usage Notes ...................................................................................................................... 768
26.9.1 Note on Resonator................................................................................................ 768
26.9.2 Notes on Board Design ........................................................................................ 768
26.9.3 Processing for X1 and X2 Pins ............................................................................ 769
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Section 27 Power-Down Modes...................................................................................... 771
27.1 Register Descriptions........................................................................................................ 772
27.1.1 Standby Control Register (SBYCR) .................................................................... 772
27.1.2 Low-Power Control Register (LPWRCR) ........................................................... 774
27.1.3 System Control Register 2 (SYSCR2)................................................................. 775
27.1.4 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) Sub-Chip
Module Stop Control Registers BH and BL (SUBMSTPBH, SUBMSTPBL).... 777
27.2 Mode Transitions and LSI States ...................................................................................... 778
27.3 Medium-Speed Mode........................................................................................................ 781
27.4 Sleep Mode ....................................................................................................................... 782
27.5 Software Standby Mode.................................................................................................... 782
27.6 Hardware Standby Mode .................................................................................................. 784
27.7 Watch Mode...................................................................................................................... 785
27.8 Subsleep Mode.................................................................................................................. 786
27.9 Subactive Mode ................................................................................................................ 787
27.10 Module Stop Mode ........................................................................................................... 787
27.11 Direct Transitions.............................................................................................................. 788
27.12 Usage Notes ...................................................................................................................... 789
27.12.1 I/O Port Status...................................................................................................... 789
27.12.2 Current Consumption when Waiting for Oscillation Stabilization ...................... 789
27.12.3 DTC Module Stop Mode ..................................................................................... 789
Section 28 List of Registers.............................................................................................. 791
28.1 Register Addresses (Address Order)................................................................................. 791
28.2 Register Bits...................................................................................................................... 804
28.3 Register States in Each Operating Mode........................................................................... 815
Section 29 Electrical Characteristics.............................................................................. 825
29.1 Absolute Maximum Ratings ............................................................................................. 825
29.2 DC Characteristics ............................................................................................................ 826
29.3 AC Characteristics ............................................................................................................ 834
29.3.1 Clock Timing ....................................................................................................... 835
29.3.2 Control Signal Timing ......................................................................................... 837
29.3.3 Bus Timing .......................................................................................................... 839
29.3.4 Timing of On-Chip Peripheral Modules .............................................................. 845
29.4 A/D Conversion Characteristics........................................................................................ 856
29.5 D/A Conversion Characteristics........................................................................................ 858
29.6 Flash Memory Characteristics........................................................................................... 859
Appendix .................................................................................................................................. 861
A. I/O Port States in Each Pin State....................................................................................... 861
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B. Product Lineup.................................................................................................................. 863
C. Package Dimensions ......................................................................................................... 864
Index .......................................................................................................................................... 865
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Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ........................................................................................ 2
Figure 1.2 Pin Arrangement (TBP-112A: Top View)............................................................ 3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode).............................................................. 21
Figure 2.2 Stack Structure in Normal Mode .......................................................................... 21
Figure 2.3 Exception Vector Table (Advanced Mode).......................................................... 22
Figure 2.4 Stack Structure in Advanced Mode ...................................................................... 23
Figure 2.5 Memory Map ........................................................................................................ 24
Figure 2.6 CPU Internal Registers ......................................................................................... 25
Figure 2.7 Usage of General Registers................................................................................... 26
Figure 2.8 Stack ..................................................................................................................... 27
Figure 2.9 General Register Data Formats (1) ....................................................................... 30
Figure 2.9 General Register Data Formats (2) ....................................................................... 31
Figure 2.10 Memory Data Formats.......................................................................................... 32
Figure 2.11 Instruction Formats (Examples)............................................................................ 44
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ................. 47
Figure 2.13 State Transitions ................................................................................................... 51
Section 3 MCU Operating Modes
Figure 3.1 Address Map (Mode 2)......................................................................................... 62
Figure 3.2 Address Map (Mode 3)......................................................................................... 63
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Mode 3) ..................................................................................... 68
Figure 4.2 Stack Status after Exception Handling.................................................................. 70
Figure 4.3 Operation when SP Value Is Odd......................................................................... 71
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller ................................................................. 74
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ....................................................... 85
Figure 5.3 Block Diagram of Interrupts KIN9 to KIN0 and WUE15 to WUE8
(Example of KIN9 to KIN0)................................................................................. 86
Figure 5.4 Block Diagram of Interrupt Control Operation..................................................... 90
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control
Mode 0.................................................................................................................. 93
Figure 5.6 State Transition in Interrupt Control Mode 1........................................................ 94
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Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control
Mode 1.................................................................................................................. 96
Figure 5.8 Interrupt Exception Handling ............................................................................... 97
Figure 5.9 Interrupt Control for DTC..................................................................................... 99
Figure 5.10 Conflict between Interrupt Generation and Disabling .......................................... 101
Section 6 Bus Controller
Figure 6.1 Block Diagram of Bus Controller......................................................................... 104
Figure 6.2 IOS Signal Output Timing.................................................................................... 122
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)......................... 123
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ....................... 124
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space......................................................... 125
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space......................................................... 126
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) ...................... 127
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) ....................... 128
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access).............................. 129
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)...................... 130
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) ....................... 131
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access).............................. 132
Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode) .................................. 134
Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) ................. 135
Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) ................. 136
Figure 6.16 Access Sizes and Data Alignment Control ........................................................... 137
Figure 6.17 Access Timing in Memory Card Mode (Basic Cycle).......................................... 139
Figure 6.18 Access Timing in Memory Card Mode
(OWEAC = OWENC = 1 with Wait State Insertion) ........................................... 139
Figure 6.19 Access Timing Example in Memory Card Mode
(Wait State Insertion by Program Wait and CPWAIT Pin) .................................. 140
Figure 6.20 Examples of Idle Cycle Operation........................................................................ 141
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC......................................................................................... 146
Figure 7.2 Block Diagram of DTC Activation Source Control.............................................. 152
Figure 7.3 DTC Register Information Location in Address Space ........................................ 153
Figure 7.4 DTC Operation Flowchart .................................................................................... 156
Figure 7.5 Memory Mapping in Normal Mode...................................................................... 157
Figure 7.6 Memory Mapping in Repeat Mode....................................................................... 158
Figure 7.7 Memory Mapping in Block Transfer Mode.......................................................... 159
Figure 7.8 Chain Transfer Operation ..................................................................................... 160
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)................. 161
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Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2) ............................................................................................ 162
Figure 7.11 DTC Operation Timing (Example of Chain Transfer).......................................... 162
Section 8 RAM-FIFO Unit (RFU)
Figure 8.1 Block Diagram of RFU......................................................................................... 168
Figure 8.2 Examples of Temporary Cancellation of Medium-Speed Mode .......................... 188
Figure 8.3 Example of RFU Response Time ........................................................................ 190
Figure 8.4 RFU Interface of USB .......................................................................................... 194
Figure 8.5 Operation Flow of USB IN Transfer .................................................................... 195
Figure 8.6 Operation Flow of USB OUT Transfer................................................................. 196
Figure 8.7 RFU Interface of SCI............................................................................................ 197
Figure 8.8 Operation Flow of SCI Transmission ................................................................... 198
Figure 8.9 Operation Flow of SCI Reception......................................................................... 199
Figure 8.10 RFU Interface of MCIF ........................................................................................ 200
Figure 8.11 Operation Flow of MCIF Transmission................................................................ 201
Figure 8.12 Operation Flow of MCIF Reception..................................................................... 202
Figure 8.13 RFU Initialization Flow........................................................................................ 203
Section 10 8-Bit PWM Timer (PWM)
Figure 10.1 Block Diagram of PWM Timer ............................................................................ 262
Figure 10.2 Example of Additional Pulse Timing
(When Upper 4 Bits of PWDR = B'1000) ............................................................ 271
Section 11 14-Bit PWM Timer (PWMX)
Figure 11.1 PWM (D/A) Block Diagram................................................................................. 273
Figure 11.2 PWM (D/A) Operation ......................................................................................... 281
Figure 11.3 Output Waveform (OS = 0, DADR corresponds to T
Figure 11.4 Output Waveform (OS = 1, DADR corresponds to T
)........................................ 283
L
) ....................................... 284
H
Figure 11.5 D/A Data Register Configuration when CFS = 1 ................................................. 284
Figure 11.6 Output Waveform when DADR = H'0207 (OS = 1)............................................. 285
Section 12 16-Bit Free-Running Timer (FRT)
Figure 12.1 Block Diagram of 16-Bit Free-Running Timer..................................................... 288
Figure 12.2 Example of Pulse Output ...................................................................................... 299
Figure 12.3 Increment Timing with Internal Clock Source...................................................... 300
Figure 12.4 Increment Timing with External Clock Source .................................................... 300
Figure 12.5 Timing of Output Compare A Output................................................................... 301
Figure 12.6 Clearing of FRC by Compare-Match A Signal..................................................... 301
Figure 12.7 Input Capture Input Signal Timing (Usual Case) ................................................. 302
Figure 12.8 Input Capture Input Signal Timing (When ICRA to ICRD Is Read).................... 302
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Figure 12.9 Buffered Input Capture Timing ............................................................................ 303
Figure 12.10 Buffered Input Capture Timing (BUFEA = 1)...................................................... 304
Figure 12.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ................. 304
Figure 12.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................ 305
Figure 12.13 Timing of Overflow Flag (OVF) Setting .............................................................. 306
Figure 12.14 OCRA Automatic Addition Timing...................................................................... 306
Figure 12.15 Timing of Input Capture Mask Signal Setting ...................................................... 307
Figure 12.16 Timing of Input Capture Mask Signal Clearing.................................................... 307
Figure 12.17 FRC Write-Clear Conflict..................................................................................... 309
Figure 12.18 FRC Write-Increment Conflict ............................................................................. 310
Figure 12.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function Is Not Used) .............................................. 311
Figure 12.20 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function Is Used) ..................................................... 312
Section 13 8-Bit Timer (TMR)
Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)......................................... 316
Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ....................................... 317
Figure 13.3 Pulse Output Example .......................................................................................... 330
Figure 13.4 Count Timing for Internal Clock Input................................................................. 331
Figure 13.5 Count Timing for External Clock Input................................................................ 331
Figure 13.6 Timing of CMF Setting at Compare-Match.......................................................... 332
Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal .......................... 332
Figure 13.8 Timing of Counter Clear by Compare-Match....................................................... 333
Figure 13.9 Timing of Counter Clear by External Reset Input ................................................ 333
Figure 13.10 Timing of OVF Flag Setting................................................................................. 334
Figure 13.11 Timing of Input Capture Operation ...................................................................... 336
Figure 13.12 Timing of Input Capture Signal
(Input Capture Signal Is Input during TICRR and TICRF Read)......................... 337
Figure 13.13 Input Capture Signal Selection ............................................................................. 337
Figure 13.14 Conflict between TCNT Write and Clear ............................................................. 340
Figure 13.15 Conflict between TCNT Write and Increment...................................................... 340
Figure 13.16 Conflict between TCOR Write and Compare-Match............................................ 341
Section 14 Timer Connection
Figure 14.1 Block Diagram of Timer Connection.................................................................... 346
Figure 14.2 Timing Chart for PWM Decoding........................................................................ 359
Figure 14.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)............. 360
Figure 14.4 Timing Chart for Clamp Waveform Generation (CL3 Signal)............................. 360
Figure 14.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided
Waveform Periods ................................................................................................ 363
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Figure 14.6 2fH Modification Timing Chart............................................................................ 364
Figure 14.7 Fall Modification and IHI Synchronization Timing Chart.................................... 366
Figure 14.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart............................................... 369
Figure 14.9 CBLANK Output Waveform Generation ............................................................. 372
Section 15 Watchdog Timer (WDT)
Figure 15.1 Block Diagram of WDT ....................................................................................... 374
Figure 15.2 Watchdog Timer Mode (RST/NMI = 1) Operation.............................................. 380
Figure 15.3 Interval Timer Mode Operation............................................................................ 381
Figure 15.4 OVF Flag Set Timing ........................................................................................... 381
Figure 15.5 Output Timing of RESO Signal............................................................................ 382
Figure 15.6 Writing to TCNT and TCSR (WDT_0)................................................................ 383
Figure 15.7 Conflict between TCNT Write and Increment...................................................... 384
Figure 15.8 Sample Circuit for Resetting the System by the RESO Signal ............................. 385
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Figure 16.1 Block Diagram of SCI_1 ...................................................................................... 389
Figure 16.2 Block Diagram of SCI_0 and SCI_2 .................................................................... 390
Figure 16.3 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) ............................................... 417
Figure 16.4 Receive Data Sampling Timing in Asynchronous Mode...................................... 419
Figure 16.5 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode) .......................................................................................... 420
Figure 16.6 Basic Clock Examples When Average Transfer Rate Is Selected (1)................... 422
Figure 16.7 Basic Clock Examples When Average Transfer Rate Is Selected (2)................... 423
Figure 16.8 Sample SCI Initialization Flowchart..................................................................... 424
Figure 16.9 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................. 425
Figure 16.10 Sample Serial Transmission Flowchart................................................................. 426
Figure 16.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,
One Stop Bit) ........................................................................................................ 427
Figure 16.12 Sample Serial Reception Flowchart (1) ................................................................ 429
Figure 16.12 Sample Serial Reception Flowchart (2) ................................................................ 430
Figure 16.13 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A).......................................... 432
Figure 16.14 Sample Multiprocessor Serial Transmission Flowchart........................................ 433
Figure 16.15 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit) ........................................................................ 434
Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (1) ....................................... 435
Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (2) ....................................... 436
Figure 16.17 Data Format in Synchronous Communication (LSB-First) .................................. 437
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Figure 16.18 Sample SCI Initialization Flowchart..................................................................... 438
Figure 16.19 Sample SCI Transmission Operation in Clocked Synchronous Mode.................. 439
Figure 16.20 Sample Serial Transmission Flowchart................................................................. 440
Figure 16.21 Example of SCI Receive Operation in Clocked Synchronous Mode.................... 441
Figure 16.22 Sample Serial Reception Flowchart...................................................................... 442
Figure 16.23 Sample Flowchart of Simultaneous Serial Transmission and Reception.............. 444
Figure 16.24 Pin Connection for Smart Card Interface.............................................................. 445
Figure 16.25 Data Formats in Normal Smart Card Interface Mode........................................... 446
Figure 16.26 Direct Convention (SDIR = SINV = O/E = 0)...................................................... 446
Figure 16.27 Inverse Convention (SDIR = SINV = O/E = 1).................................................... 447
Figure 16.28 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency Is 372 Times the Bit Rate)............................................ 448
Figure 16.29 Data Re-transfer Operation in SCI Transmission Mode....................................... 451
Figure 16.30 TEND Flag Set Timings during Transmission ..................................................... 451
Figure 16.31 Sample Transmission Flowchart........................................................................... 452
Figure 16.32 Data Re-transfer Operation in SCI Reception Mode ............................................ 453
Figure 16.33 Sample Reception Flowchart ................................................................................ 454
Figure 16.34 Clock Output Fixing Timing................................................................................. 455
Figure 16.35 Clock Stop and Restart Procedure ........................................................................ 456
Figure 16.36 IrDA Block Diagram ............................................................................................ 456
Figure 16.37 IrDA Transmission and Reception........................................................................ 457
Figure 16.38 Sample Transmission using DTC in Clocked Synchronous Mode....................... 463
Figure 16.39 Sample Flowchart for Mode Transition during Transmission .............................. 464
Figure 16.40 Pin States during Transmission in Asynchronous Mode (Internal Clock)............ 464
Figure 16.41 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock)..................................................................................................... 465
Figure 16.42 Sample Flowchart for Mode Transition during Reception.................................... 465
Figure 16.43 Switching from SCK Pins to Port Pins ................................................................. 466
Figure 16.44 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins......... 466
Figure 16.45 Block Diagram of CRC Operation Circuit............................................................ 467
Figure 16.46 LSB-First Data Transmission ............................................................................... 469
Figure 16.47 MSB-First Data Transmission .............................................................................. 469
Figure 16.48 LSB-First Data Reception..................................................................................... 470
Figure 16.49 MSB-First Data Reception.................................................................................... 471
Figure 16.50 LSB-First and MSB-First Transmit Data.............................................................. 472
2
Section 17 I
Figure 17.1 Block Diagram of I
Figure 17.2 I
C Bus Interface (IIC)
2
2
C Bus Interface Connections (Example: This LSI as Master)............................ 476
C Bus Interface..................................................................... 475
Figure 17.3 State Transitions of TDRE, SDRF, and RDRF Bits ............................................. 507
2
Figure 17.4 I
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C Bus Data Formats (I2C Bus Formats) ............................................................. 516
Page 43
Figure 17.5 I2C Bus Formats (Serial Formats)......................................................................... 516
2
Figure 17.6 I
C Bus Timing..................................................................................................... 517
Figure 17.7 Master Transmit Mode Operation Timing Example (MLS = WAIT = 0) ............ 519
Figure 17.8 Master Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 521
Figure 17.9 Master Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 522
Figure 17.10 Slave Receive Mode Operation Timing Example (1) (MLS = ACKB = 0).......... 523
Figure 17.11 Slave Receive Mode Operation Timing Example (2) (MLS = ACKB = 0)......... 524
Figure 17.12 Slave Transmit Mode Operation Timing Example (MLS = 0) ............................. 526
Figure 17.13 IRIC Flag Timing and SCL Control (1)................................................................ 527
Figure 17.14 IRIC Flag Timing and SCL Control (2)................................................................ 528
Figure 17.15 IRIC Flag Timing and SCL Control (3)................................................................ 529
Figure 17.16 Example of Interrupt Flag Timing of Operation Reservation Adapter ................. 530
Figure 17.17 Block Diagram of Noise Canceler ........................................................................ 534
Figure 17.18 Sample Flowchart for Master Transmit Mode...................................................... 536
Figure 17.19 Sample Flowchart for Master Receive Mode ....................................................... 537
Figure 17.20 Sample Flowchart for Slave Receive Mode.......................................................... 538
Figure 17.21 Sample Flowchart for Slave Transmit Mode ........................................................ 539
Figure 17.22 Notes on Reading Master Receive Data ............................................................... 544
Figure 17.23 Flowchart and Timing of Start Condition Issuance for Retransmission ............... 545
Figure 17.24 Stop Condition Issuance Timing........................................................................... 546
Figure 17.25 IRIC Flag Clearing Timing When WAIT = 1....................................................... 546
Figure 17.26 ICDR Read and ICCR Access Timing in Slave Transmit Mode .......................... 547
Figure 17.27 TRS Bit Set Timing in Slave Mode ...................................................................... 548
Figure 17.28 IRIC Flag Clear Timing on WAIT Operation....................................................... 550
Figure 17.29 Diagram of Erroneous Operation when Arbitration Is Lost.................................. 551
Section 18 Universal Serial Bus Interface (USB)
Figure 18.1 Block Diagram of USB......................................................................................... 554
Figure 18.2 Operation on Receiving a SETUP Token
(When Decode by the Slave CPU Is not Required and When SETICNT = 0) ..... 606
Figure 18.3 Operation on Receiving a SETUP Token
(When Decode by the Slave CPU Is Required and When SETICNT = 0) ........... 607
Figure 18.4 Operation on Receiving a SETUP Token
(When Decode by the Slave CPU Is Not Required and When SETICNT = 1) .... 608
Figure 18.5 Operation on Receiving a SETUP Token
(When Decode by the Slave CPU Is Required and When SETICNT = 1) ........... 609
Figure 18.6 Operation on Receiving an OUT Token (EP2-OUT: Initial FIFO Is Empty)....... 610
Figure 18.7 Operation on Receiving an OUT Token (EP2-OUT: Initial FIFO Is Full) ........... 611
Figure 18.8 Operation on Receiving an OUT Token (EP5-OUT: Initial FIFO Is Empty)....... 612
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Figure 18.9 Operation on Receiving an OUT Token (EP5-OUT: Initial FIFO Is Full) ........... 613
Figure 18.10 Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Full)................... 614
Figure 18.11 Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Empty)............... 615
Figure 18.12 Operation on Receiving an IN Token (EP4-IN: Initial FIFO Is Full)................... 616
Figure 18.13 Operation on Receiving an IN Token (EP4-IN: Initial FIFO Is Empty)............... 617
Figure 18.14 Operation Procedure for Initializing USB Module ............................................... 624
Section 19 Multimedia Card Interface (MCIF)
Figure 19.1 Block Diagram of MCIF....................................................................................... 628
Figure 19.2 Example of Command Sequence for Commands that Do Not Require
Command Response ............................................................................................. 658
Figure 19.3 Operational Flow for Commands that Do Not Require Command Response....... 658
Figure 19.4 Example of Command Sequence for Commands without Data Transfer
(No Data Busy State) ............................................................................................ 660
Figure 19.5 Example of Command Sequence for Commands without Data Transfer
(with Data Busy State).......................................................................................... 661
Figure 19.6 Operational Flow for Commands without Data Transfer...................................... 662
Figure 19.7 Example of Command Sequence for Commands with Read Data (1).................. 664
Figure 19.8 Example of Command Sequence for Commands with Read Data (2).................. 665
Figure 19.9 Example of Command Sequence for Commands with Read Data (3).................. 666
Figure 19.10 Example of Command Sequence for Commands with Read Data (4).................. 667
Figure 19.11 Operational Flow for Commands with Read Data................................................ 668
Figure 19.12 Example of Command Sequence for Commands with Write Data (1)................. 670
Figure 19.13 Example of Command Sequence for Commands with Write Data (2)................. 671
Figure 19.14 Example of Command Sequence for Commands with Write Data (3)................. 672
Figure 19.15 Example of Command Sequence for Commands with Write Data (4)................. 673
Figure 19.16 Operational Flow for Commands with Write Data............................................... 674
Figure 19.17 Example of Command Sequence for Commands without Data Transfer
(No Data Busy State) ............................................................................................ 676
Figure 19.18 Example of Command Sequence for Commands without Data Transfer
(with Data Busy State).......................................................................................... 677
Figure 19.19 Operational Flow for Commands without Data Transfer...................................... 678
Figure 19.20 Example of Command Sequence for Commands with Read Data (1).................. 680
Figure 19.21 Example of Command Sequence for Commands with Read Data (2).................. 681
Figure 19.22 Operational Flow for Commands with Read Data................................................ 682
Figure 19.23 Example of Command Sequence for Commands with Write Data (1)................. 684
Figure 19.24 Example of Command Sequence for Commands with Write Data (2)................. 685
Figure 19.25 Operational Flow for Commands with Write Data............................................... 686
Section 21 D/A Converter
Figure 21.1 Block Diagram of D/A Converter......................................................................... 691
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Figure 21.2 D/A Converter Operation Example ...................................................................... 694
Section 22 A/D Converter
Figure 22.1 Block Diagram of A/D Converter......................................................................... 698
Figure 22.2 A/D Conversion Timing ....................................................................................... 707
Figure 22.3 External Trigger Input Timing.............................................................................. 708
Figure 22.4 A/D Conversion Accuracy Definitions................................................................. 710
Figure 22.5 A/D Conversion Accuracy Definitions................................................................. 710
Figure 22.6 Example of Analog Input Circuit.......................................................................... 711
Figure 22.7 Example of Analog Input Protection Circuit ........................................................ 713
Figure 22.8 Analog Input Pin Equivalent Circuit..................................................................... 713
Section 24 ROM
Figure 24.1 Block Diagram of Flash Memory......................................................................... 718
Figure 24.2 Flash Memory State Transitions........................................................................... 719
Figure 24.3 Boot Mode............................................................................................................ 720
Figure 24.4 User Program Mode (Example)............................................................................ 721
Figure 24.5 Flash Memory Block Configuration .................................................................... 722
Figure 24.6 On-Chip RAM Area in Boot Mode ...................................................................... 731
Figure 24.7 ID Code Area........................................................................................................ 731
Figure 24.8 Programming/Erasing Flowchart Example in User Program Mode ..................... 732
Figure 24.9 Program/Program-Verify Flowchart..................................................................... 734
Figure 24.10 Erase/Erase-Verify Flowchart............................................................................... 736
Figure 24.11 Memory Map in Programmer Mode..................................................................... 739
Section 25 User Debug Interface (H-UDI)
Figure 25.1 Block Diagram of H-UDI ..................................................................................... 742
Figure 25.2 TAP Controller State Transitions.......................................................................... 755
Figure 25.3 Reset Signal Circuit Without Reset Signal Interference....................................... 758
Figure 25.4 Serial Data Input/Output (1) ................................................................................. 759
Figure 25.4 Serial Data Input/Output (2) ................................................................................. 760
Section 26 Clock Pulse Generator
Figure 26.1 Block Diagram of Clock Pulse Generator............................................................. 761
Figure 26.2 Typical Connection to Crystal Resonator ............................................................. 762
Figure 26.3 Equivalent Circuit of Crystal Resonator ............................................................... 762
Figure 26.4 Example of External Clock Input ......................................................................... 763
Figure 26.5 External Clock Input Timing ................................................................................ 764
Figure 26.6 Timing of External Clock Output Stabilization Delay Time ................................ 765
Figure 26.7 Subclock Input Timing ......................................................................................... 767
Figure 26.8 Note on Board Design of Oscillation Circuit Section........................................... 768
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Figure 26.9 Processing for X1 and X2 Pins............................................................................. 769
Section 27 Power-Down Modes
Figure 27.1 Mode Transition Diagram..................................................................................... 779
Figure 27.2 Medium-Speed Mode Timing............................................................................... 782
Figure 27.3 Software Standby Mode Application Example..................................................... 784
Figure 27.4 Hardware Standby Mode Timing.......................................................................... 785
Section 29 Electrical Characteristics
Figure 29.1 Darlington Transistor Drive Circuit (Example).................................................... 833
Figure 29.2 LED Drive Circuit (Example)............................................................................... 833
Figure 29.3 Output Load Circuit.............................................................................................. 834
Figure 29.4 System Clock Timing ........................................................................................... 835
Figure 29.5 Oscillation Stabilization Timing........................................................................... 836
Figure 29.6 Oscillation Stabilization Timing (Exiting Software Standby Mode).................... 836
Figure 29.7 Reset Input Timing ............................................................................................... 838
Figure 29.8 Interrupt Input Timing .......................................................................................... 838
Figure 29.9 Basic Bus Timing/2-State Access......................................................................... 840
Figure 29.10 Basic Bus Timing/3-State Access......................................................................... 841
Figure 29.11 Basic Bus Timing/3-State Access with One Wait State........................................ 842
Figure 29.12 CF Interface Basic Timing/3-State Access ........................................................... 843
Figure 29.13 Burst ROM Access Timing/2-State Access .......................................................... 844
Figure 29.14 Burst ROM Access Timing/1-State Access .......................................................... 845
Figure 29.15 I/O Port Input/Output Timing ............................................................................... 847
Figure 29.16 FRT Input/Output Timing..................................................................................... 847
Figure 29.17 FRT Clock Input Timing ...................................................................................... 847
Figure 29.18 8-Bit Timer Output Timing................................................................................... 848
Figure 29.19 8-Bit Timer Clock Input Timing........................................................................... 848
Figure 29.20 8-Bit Timer Reset Input Timing ........................................................................... 848
Figure 29.21 PWM, PWMX Output Timing.............................................................................. 848
Figure 29.22 SCK Clock Input Timing...................................................................................... 849
Figure 29.23 SCI Input/Output Timing (Clock Synchronous Mode)......................................... 849
Figure 29.24 A/D Converter External Trigger Input Timing..................................................... 849
Figure 29.25 WDT Output Timing (RESO)............................................................................... 849
2
Figure 29.26 I
C Bus Interface Input/Output Timing ................................................................ 851
Figure 29.27 USB Driver/Receiver Output Timing ................................................................... 852
Figure 29.28 Multimedia Card Interface Timing ....................................................................... 853
Figure 29.29 H-UDI ETCK Timing........................................................................................... 854
Figure 29.30 Reset Hold Timing................................................................................................ 855
Figure 29.31 H-UDI Input/Output Timing................................................................................. 855
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Appendix
Figure C.1 Package Dimensions (TBP-112A) ......................................................................... 864
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Tables
Section 1 Overview
Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ 4
Table 1.2 Pin Functions..........................................................................................................8
Section 2 CPU
Table 2.1 Instruction Classification........................................................................................ 33
Table 2.2 Operation Notation ................................................................................................. 34
Table 2.3 Data Transfer Instructions ...................................................................................... 35
Table 2.4 Arithmetic Operations Instructions (1)................................................................... 36
Table 2.4 Arithmetic Operations Instructions (2)................................................................... 37
Table 2.5 Logic Operations Instructions ................................................................................ 38
Table 2.6 Shift Instructions .................................................................................................... 38
Table 2.7 Bit Manipulation Instructions (1) ........................................................................... 39
Table 2.7 Bit Manipulation Instructions (2) ........................................................................... 40
Table 2.8 Branch Instructions................................................................................................. 41
Table 2.9 System Control Instructions ................................................................................... 42
Table 2.10 Block Data Transfer Instructions............................................................................ 43
Table 2.11 Addressing Modes.................................................................................................. 45
Table 2.12 Absolute Address Access Ranges .......................................................................... 46
Table 2.13 Effective Address Calculation (1) .......................................................................... 48
Table 2.13 Effective Address Calculation (2) .......................................................................... 49
Section 3 MCU Operating Modes
Table 3.1 MCU Operating Mode Selection............................................................................ 55
Table 3.2 Pin Functions in Each Operating Mode.................................................................. 61
Section 4 Exception Handling
Table 4.1 Exception Types and Priority ................................................................................. 65
Table 4.2 Exception Handling Vector Table .......................................................................... 66
Table 4.3 Status of CCR after Trap Instruction Exception Handling..................................... 70
Section 5 Interrupt Controller
Table 5.1 Pin Configuration ................................................................................................... 75
Table 5.2 Correspondence between Interrupt Source and ICR .............................................. 76
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................ 87
Table 5.4 Interrupt Control Modes......................................................................................... 90
Table 5.5 Interrupts Acceptable in Each Interrupt Control Mode .......................................... 91
Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode ........... 92
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Table 5.7 Interrupt Response Times....................................................................................... 98
Table 5.8 Number of States in Interrupt Handling Routine Execution Status........................ 98
Table 5.9 Interrupt Source Selection and Clearing Control.................................................... 100
Section 6 Bus Controller
Table 6.1 Pin Configuration ................................................................................................... 105
Table 6.2 Address Ranges and External Address Spaces....................................................... 115
Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface ................................... 117
Table 6.4 Bus Specifications for Basic Expansion Area/Basic Bus Interface ........................ 118
Table 6.5 Bus Specifications for 256-kbyte Expansion Area/Basic Bus Interface................. 119
Table 6.6 Bus Specifications for CP Expansion Area (Basic Mode)/Basic Bus Interface ..... 120
Table 6.7 Bus Specifications for CF Expansion Area (Memory Card Mode)/
Basic Bus Interface................................................................................................. 121
Table 6.8 Address Range for IOS Signal Output ................................................................... 122
Table 6.9 Data Buses Used and Valid Strobes ....................................................................... 124
Table 6.10 Data Buses Used and Valid Strobes ....................................................................... 138
Table 6.11 Pin States in Idle Cycle .......................................................................................... 142
Section 7 Data Transfer Controller (DTC)
Table 7.1 Correspondence between Interrupt Sources and DTCER....................................... 150
Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................ 154
Table 7.3 Register Functions in Normal Mode ...................................................................... 157
Table 7.4 Register Functions in Repeat Mode ....................................................................... 158
Table 7.5 Register Functions in Block Transfer Mode........................................................... 159
Table 7.6 DTC Execution Status ............................................................................................ 163
Table 7.7 Number of States Required for Each Execution Status.......................................... 163
Section 8 RAM-FIFO Unit (RFU)
Table 8.1 Valid Bits in BAR, RAR, WAR, and TMP............................................................ 174
Table 8.2 Correspondence between Activation Sources and ID Numbers............................. 183
Table 8.3 RFU Bus Cycle Types............................................................................................ 185
Table 8.4 Requests from Peripheral Modules and RFU Bus Cycle........................................ 186
Table 8.5 Bus Cycle Insertion ................................................................................................ 189
Table 8.6 Settings when Using Boundary Overflow
(Transmission/Reception of Single Data Block).................................................... 192
Table 8.7 DATAN/FREEN Read Value................................................................................. 204
Section 9 I/O Ports
Table 9.1 Port Functions ........................................................................................................ 205
Table 9.2 Port 1 Input Pull-Up MOS States ........................................................................... 211
Table 9.3 Port 2 Input Pull-Up MOS States ........................................................................... 215
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Table 9.4 Port 3 Input Pull-Up MOS States ........................................................................... 222
Table 9.5 Port 6 Input Pull-Up MOS States ........................................................................... 244
Table 9.6 Port A Input Pull-Up MOS States .......................................................................... 257
Section 10 8-Bit PWM Timer (PWM)
Table 10.1 Pin Configuration ................................................................................................... 263
Table 10.2 Internal Clock Selection ......................................................................................... 265
Table 10.3 Resolution, PWM Conversion Period, and Carrier Frequency
when φ = 20 MHz................................................................................................... 266
Table 10.4 Duty Cycle of Basic Pulse...................................................................................... 270
Table 10.5 Position of Pulses Added to Basic Pulses............................................................... 271
Section 11 14-Bit PWM Timer (PWMX)
Table 11.1 Pin Configuration ...................................................................................................274
Table 11.2 Read and Write Access Methods for 16-Bit Registers........................................... 280
Table 11.3 Settings and Operation (Examples when φ = 25 MHz) .......................................... 282
Table 11.4 Locations of Additional Pulses Added to Base Pulse (When CFS = 1) .................286
Section 12 16-Bit Free-Running Timer (FRT)
Table 12.1 Pin Configuration ................................................................................................... 289
Table 12.2 FRT Interrupt Sources............................................................................................ 308
Table 12.3 Switching of Internal Clock and FRC Operation ................................................... 313
Section 13 8-Bit Timer (TMR)
Table 13.1 Pin Configuration ................................................................................................... 318
Table 13.2 Clock Input to TCNT and Count Condition ........................................................... 322
Table 13.3 Input Capture Signal Selection............................................................................... 338
Table 13.4 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X......... 339
Table 13.5 Timer Output Priorities .......................................................................................... 342
Table 13.6 Switching of Internal Clocks and TCNT Operation............................................... 343
Section 14 Timer Connection
Table 14.1 Pin Configuration ................................................................................................... 347
Table 14.2 Synchronization Signal Connection Enable ........................................................... 351
Table 14.3 Registers Accessible by TMR_X/TMR_Y............................................................. 355
Table 14.4 Examples of TCR Settings ..................................................................................... 358
Table 14.5 Examples of TCORB (Pulse Width Threshold) Settings........................................ 358
Table 14.6 Examples of TCR and TCSR Settings.................................................................... 362
Table 14.7 Examples of TCR, TCSR, TOCR, and OCRDM Settings...................................... 364
Table 14.8 Examples of TCR, TCSR, and TCORB Settings ................................................... 366
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Table 14.9 Examples of TCR, TCSR, TCORA, TCORB, OCRAR, OCRAF,
and TOCR Settings................................................................................................. 368
Table 14.10 HSYNCO Output Modes........................................................................................ 370
Table 14.11 VSYNCO Output Modes........................................................................................ 371
Section 15 Watchdog Timer (WDT)
Table 15.1 Pin Configuration ................................................................................................... 375
Table 15.2 WDT Interrupt Source............................................................................................ 382
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Table 16.1 Pin Configuration ................................................................................................... 391
Table 16.2 Relationships between N Setting in BRR and Bit Rate B ...................................... 405
Table 16.3 BRR Settings for Various Bit Rates (Asynchronous Mode) .................................. 406
Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 409
Table 16.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 409
Table 16.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... 410
Table 16.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 410
Table 16.8 BRR Settings for Various Bit Rates
(Smart Card Interface Mode, n = 0, s = 372).......................................................... 411
Table 16.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372) ... 411
Table 16.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 418
Table 16.11 SSR Status Flags and Receive Data Handling........................................................ 428
Table 16.12 IrCKS2 to IrCKS0 Bit Settings .............................................................................. 458
Table 16.13 SCI Interrupt Sources ............................................................................................. 460
Table 16.14 SCI Interrupt Sources ............................................................................................. 460
2
Section 17 I
C Bus Interface (IIC)
Table 17.1 Pin Configuration ................................................................................................... 476
Table 17.2 Communication Format.......................................................................................... 481
2
Table 17.3 I
C Transfer Rate.................................................................................................... 484
Table 17.4 Flags and Transfer States ....................................................................................... 490
Table 17.5 Restrictions on Accessing IIC Registers ................................................................ 511
Table 17.6 Operation Reservation Commands......................................................................... 513
Table 17.7 Operation When the Operation Reservation Command Is Completed................... 514
Table 17.8 Examples of Operation Using DTC ....................................................................... 532
Table 17.9 Examples of Operation Reservation Adapter Operation Using DTC..................... 533
Table 17.10 IIC Interrupt Sources .............................................................................................. 540
2
Table 17.11 I
Table 17.12 Permissible SCL Rise Time (t
Table 17.13 I
C Bus Timing (SCL and SDA Outputs) .............................................................. 541
) Values................................................................. 542
2
C Bus Timing (with Maximum Influence of tSr/tSf) ............................................. 543
sr
Rev. 3.00 Jan 25, 2006 page xlix of lii
Page 52
Section 18 Universal Serial Bus Interface (USB)
Table 18.1 Pin Configuration ................................................................................................... 555
Table 18.2 FIFO Configuration................................................................................................ 557
Table 18.3 Port 6 Functions ..................................................................................................... 595
Table 18.4 USB Function Core and Slave CPU Functions ...................................................... 603
Table 18.5 Packets Included in Each Transaction.................................................................... 605
Table 18.6 Registers Initialized by Bit UIFRST or FSRST ..................................................... 619
Table 18.7 Endpoint Information ............................................................................................. 622
Table 18.8 USB Interrupt Sources (When SETICNT of USBMDCR Is 0).............................. 625
Table 18.9 USB Interrupt Sources (When SETICNT of USBMDCR Is 1).............................. 625
Section 19 Multimedia Card Interface (MCIF)
Table 19.1 Pin Configuration ................................................................................................... 629
Table 19.2 Correspondence between Commands and Settings of CMDTYR and RSPTYR ... 634
Table 19.3 CMDR Configuration............................................................................................. 637
Table 19.4 Correspondence between Number of Command Response Bytes
and RSPR Register................................................................................................. 639
Table 19.5 Card States in which Command Sequence Is Halted.............................................. 642
Table 19.6 MCIF Interrupt Sources.......................................................................................... 687
Section 21 D/A Converter
Table 21.1 Pin Configuration ................................................................................................... 692
Table 21.2 D/A Channel Enable............................................................................................... 693
Section 22 A/D Converter
Table 22.1 Pin Configuration ................................................................................................... 699
Table 22.2 Analog Input Channels and Corresponding ADDR Registers................................ 700
Table 22.3 CIN7 to CIN0 Scan by DTC Comparator Scan Function....................................... 704
Table 22.4 A/D Conversion Time (Single Mode) .................................................................... 707
Table 22.5 A/D Converter Interrupt Source ............................................................................. 708
Section 24 ROM
Table 24.1 Differences between Boot Mode and User Program Mode.................................... 719
Table 24.2 Pin Configuration ................................................................................................... 723
Table 24.3 Operating Modes and ROM ................................................................................... 727
Table 24.4 On-Board Programming Mode Settings ................................................................. 727
Table 24.5 Boot Mode Operation............................................................................................. 730
Table 24.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate
Is Possible............................................................................................................... 731
Rev. 3.00 Jan 25, 2006 page l of lii
Page 53
Section 25 User Debug Interface (H-UDI)
Table 25.1 Pin Configuration ................................................................................................... 743
Table 25.2 H-UDI Register Serial Transfer.............................................................................. 744
Table 25.3 Correspondence between Pins and Boundary Scan Register.................................. 747
Section 26 Clock Pulse Generator
Table 26.1 Damping Resistance Values ................................................................................... 762
Table 26.2 Crystal Resonator Parameters................................................................................. 763
Table 26.3 External Clock Input Conditions............................................................................ 764
Table 26.4 External Clock Output Stabilization Delay Time................................................... 765
Table 26.5 Subclock Input Conditions ..................................................................................... 766
Section 27 Power-Down Modes
Table 27.1 Operating Frequency and Wait Time ..................................................................... 774
Table 27.2 LSI Internal States in Each Operating Mode.......................................................... 780
Section 29 Electrical Characteristics
Table 29.1 Absolute Maximum Ratings................................................................................... 825
Table 29.2 DC Characteristics (1)............................................................................................ 826
Table 29.2 DC Characteristics (2)............................................................................................ 828
Table 29.2 DC Characteristics (3)............................................................................................ 829
Table 29.3 Permissible Output Currents................................................................................... 830
2
Table 29.4 I
C Bus Drive Characteristics................................................................................. 831
Table 29.5 USB Pin Characteristics ......................................................................................... 832
Table 29.6 Multimedia Card Interface Pin Characteristics....................................................... 833
Table 29.7 Clock Timing.......................................................................................................... 835
Table 29.8 Control Signal Timing............................................................................................ 837
Table 29.9 Bus Timing (1) (Normal Mode and Advanced Mode)........................................... 839
Table 29.10 Timing of On-Chip Peripheral Modules (1)........................................................... 846
2
Table 29.11 I
C Bus Timing....................................................................................................... 850
Table 29.12 USB Timing ........................................................................................................... 851
Table 29.13 Multimedia Card Interface ..................................................................................... 852
Table 29.14 H-UDI Timing........................................................................................................ 854
Table 29.15 A/D Conversion Characteristics
(AN7 to AN2 Input: 134/266-State Conversion).................................................... 856
Table 29.16 A/D Conversion Characteristics
(CIN7 to CIN0 Input: 134/266-State Conversion) ................................................. 857
Table 29.17 D/A Conversion Characteristics ............................................................................. 858
Table 29.18 Flash Memory Characteristics................................................................................ 859
Rev. 3.00 Jan 25, 2006 page li of lii
Page 54
Rev. 3.00 Jan 25, 2006 page lii of lii
Page 55
Section 1 Overview
1.1 Features
• High-speed H8S/2000 CPU with an internal 16-bit architecture
Upward-compatible with H8/300 CPU and H8/300H CPU on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
Data transfer controller (DTC)
RAM-FIFO unit (RFU)
8-bit PWM timer (PWM)
14-bit PWM timer (PWMX)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Timer connection
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
CRC operator (CRC)
2
I
C bus interface (IIC)
Universal serial bus interface (USB)
Multimedia card interface (MCIF)
Encryption operation circuit (DES, GF)
8-bit D/A converter
10-bit A/D converter
User debug interface (H-UDI)
Clock pulse generator
• On-chip memory
ROM Model ROM RAM
F-ZTAT Version HD64F2158 256 kbytes 10 kbytes
Section 1 Overview
• General I/O ports
I/O pins: 65
Input-only pins: 7
• Supports various power-down modes
Rev. 3.00 Jan 25, 2006 page 1 of 872
REJ09B0286-0300
Page 56
Section 1 Overview
• Compact package
Package Code Body Size Pin Pitch
TFBGA-112 TBP-112A 10.0 × 10.0 mm 0.8 mm
1.2 Internal Block Diagram
VCC
VCL
XTAL
EXTAL
X1
X2
MD2
MD1
MD0
RES
RESO
STBY
FWE
NMI
ETRST
ETMS
ETDO
ETDI
ETCK
USDP
USDM
LWR/P90
CPCS2/P91
CPCS1/P92
CPOE/RD/P93
CPWE/HWR/P94
IOS/AS/P95
EXCL/φ/P96
CS256/CPWAIT/WAIT/P97
SPEED/HFBACKI/DBA_S/KIN0/CIN0/FTCI/CPD0/D0/P60
SUSPEND/VSYNCO/DBA_R/KIN1/CIN1/FTOA/CPD1/D1/P61
TXENL/VSYNCI/DBB_S/KIN2/CIN2/FTIA/CPD2/D2/P62
TXDMNS/VFBACKI/DBB_R/KIN3/CIN3/FTIB/CPD3/D3/P63
TXDPLS/CLAMPO/DBC_S/KIN4/CIN4/FTIC/CPD4/D4/P64
XVERDATA/CSYNCI/DBC_R/KIN5/CIN5/FTID/CPD5/D5/P65
DMNS/CBLANK/DBD_S/KIN6/CIN6/FTOB/CPD6/D6/P66
DPLS/DBD_R/KIN7/CIN7/CPD7/D7/P67
AN2/ExIRQ2/P72
AN3/ExIRQ3/P73
AN4/ExIRQ4/P74
AN5/ExIRQ5/P75
DA0/AN6/ExIRQ6/P76
DA1/AN7/ExIRQ7/P77
AVCC/DrVCC
AVref
AVSS/DrVSS
Port 7 Port 6 Port 9
VSS
generator
Clock pulse
DTC
RFU
RAM
ROM
8-bit timer × 4 channels
Timer connection
SCI × 3 channels
(IrDA × 1 channel)
10-bit A/D
8-bit D/A
IIC × 2 channels
Port 8
H8S/2000 CPU
Internal address bus
Internal data bus
Interrupt
controller
Bus controller
8-bit PWM
14-bit PWM × 2 channels
WDT × 2 channels
16-bit FRT
MCIF
CRC operator
DES
GF
USB
Sub data bus
Sub address bus
PA0/A16/KIN8/SSE0I
PA1/A17/KIN9/SSE2I
P10/A0/PW0/CPA0
P11/A1/PW1/CPA1
P12/A2/PW2/CPA2
P13/A3/PW3/CPA3
P14/A4/PW4/CPA4
P15/A5/PW5/CPA5
P16/A6/PW6/CPA6
P17/A7/PW7/CPA7
P20/A8/PW8/CPA8
P21/A9/PW9/CPA9
P22/A10/PW10/CPA10
P23/A11/PW11/CPREG
P24/A12/PW12
P25/A13/PW13
P26/A14/PW14
P27/A15/PW15
P30/D8/CPD8/WUE8/MCCLK
P31/D9/CPD9/WUE9/MCCMD/MCTxD
P32/D10/CPD10/WUE10/MCDAT/MCRxD
P33/D11/CPD11/WUE11/MCDATDIR/MCCSA
P34/D12/CPD12/WUE12/MCCMDDIR/MCCSB
P35/D13/CPD13/WUE13
P36/D14/CPD14/WUE14
Peripheral data bus
Peripheral address bus
P37/D15/CPD15/WUE15
P50/IRQ8/TxD0
P51/IRQ9/RxD0
P52/IRQ10/TxD1/IrTxD
P53/IRQ11/RxD1/IrRxD
P54/IRQ12/TxD2
P55/IRQ13/RxD2
P56/IRQ14/PWX0
P57/IRQ15/PWX1
P40/IRQ0/TMI0/ExMCCLK
P41/IRQ1/TMI1/ExMCCMD/ExMCTxD/HSYNCI
P42/IRQ2/TMO0/ExMCDAT/ExMCRxD
P43/IRQ3/TMO1/ExMCDATDIR/ExMCCSA/HSYNCO
P44/IRQ4/TMIX/ExMCCMDDIR/ExMCCSB
Port 4 Port 5 Port 3 Port 2 Port 1 Port A
P45/IRQ5/TMIY
P46/IRQ6/TMOX
P47/IRQ7/TMOY
Figure 1.1 Internal Block Diagram
Rev. 3.00 Jan 25, 2006 page 2 of 872
REJ09B0286-0300
SCL0/ExIRQ8/P80
SDA0/ExIRQ9/P81
SCL1/ExIRQ10/P82
SDA1/ExIRQ11/P83
ExTMI1/SCK1/ExIRQ13/P85
ExTMI0/SCK0/ExIRQ12/P84
ExTMIX/SCK2/ExIRQ14/P86
USEXCL/ExTMIY/ADTRG/ExIRQ15/P87
Page 57
1.3 Pin Description
1.3.1 Pin Arrangement
Pin
No.
A1
(Reserved)
A2
FWE
A3
P83/ExIRQ11/SDA1
A4
P80/ExIRQ8/SCL0
A5
P84/ExIRQ12/SCK0/ExTMI0
A6
P36/D14/CPD14/WUE14
A7
P33/D11/CPD11/WUE11/MCDATDIR/MCCSA
A8
P30/D8/CPD8/WUE8/MCCLK
A9
P87/ExIRQ15/ADTRG/ExTMIY/USEXCL
A10
P12/A2/PW2/CPA2
A11
(Reserved)
B1
XTAL
B2
RES
B3
P53/IRQ11/RxD1/IrRxD
B4
P82/ExIRQ10/SCL1
B5
VSS
B6
P37/D15/CPD15/WUE15
B7
P34/D12/CPD12/WUE12/MCCMDDIR/MCCSB
B8
(Reserved)
B9
P10/A0/PW0/CPA0
B10
P13/A3/PW3/CPA3
B11
P15/A5/PW5/CPA5
C1
MD2
C2
EXTAL
C3
RESO
C4
P52/IRQ10/TxD1/IrTxD
C5
VSS
C6
P35/D13/CPD13/WUE13
C7
P32/D10/CPD10/WUE10/MCDAT/MCRxD
C8
P86/ExIRQ14/SCK2/ExTMIX
C9
P14/A4/PW4/CPA4
C10
P16/A6/PW6/CPA6
C11
VSS
D1
NMI
D2
MD0
D3
MD1
D4
(Reserved)
D5
P81/ExIRQ9/SDA0
D6
P85/ExIRQ13/SCK1/ExTMI1
D7
P31/D9/CPD9/WUE9/MCCMD/MCTxD
D8
P11/A1/PW1/CPA1
D9
P17/A7/PW7/CPA7
D10
VSS
D11
ETDO
Pin Name Pin Name
1234567891011
A
B
C
D
E
F
G
H
J
K
L
Pin
No.
X1
E1
X2
E2
VCL
E3
STBY
E4
VSS
E8
ETMS
E9
P20/A8/PW8/CPA8
E10
P21/A9/PW9/CPA9
E11
P51/IRQ9/RxD0
F1
P50/IRQ8/TxD0
F2
ETRST
F3
VSS
F4
P22/A10/PW10/CPA10
F8
P25/A13/PW13
F9
P23/A11/PW11/CPREG
F10
P24/A12/PW12
F11
VSS
G1
P97/WAIT/CPWAIT/CS256
G2
P96/φ/EXCL
G3
P94/HWR/CPWE
G4
VCC
G8
VCC
G9
P26/A14/PW14
G10
P27/A15/PW15
G11
P95/AS/IOS
H1
P56/IRQ14/PWX0
H2
P93/RD/CPOE
H3
P62/D2/CPD2/FTIA/CIN2/KIN2/VSYNCI/TXENL
H4
P66/D6/CPD6/FTOB/CIN6/KIN6/CBLANK/DMNS
H5
P72/ExIRQ2/AN2
H6
P77/ExIRQ7/AN7/DA1
H7
P42/IRQ2/TMO0/ExMCDAT/ExMCRxD
H8
P45/IRQ5/TMIY
H9
P46/IRQ6/TMOX
H10
P47/IRQ7/TMOY
H11
TBP-112A
(Top View)
Section 1 Overview
Pin
No.
P57/IRQ15/PWX1
J1
P92/CPCS1
J2
P90/LWR
J3
ETCK
J4
P67/D7/CPD7/CIN7/KIN7/DPLS
J5
AVCC/DrVCC
J6
P75/ExIRQ5/AN5
J7
PA1/A17/KIN9/SSE2I
J8
P55/IRQ13/RxD2
J9
P43/IRQ3/TMO1/ExMCDATDIR/ExMCCSA/HSYNCO
J10
P44/IRQ4/TMIX/ExMCCMDDIR/ExMCCSB
J11
P91/CPCS2
K1
P60/D0/CPD0/FTCI/CIN0/KIN0/HFBACKI/SPEED
K2
P63/D3/CPD3/FTIB/CIN3/KIN3/VFBACKI/TXDMNS
K3
P64/D4/CPD4/FTIC/CIN4/KIN4/CLAMPO/TXDPLS
K4
AVCC/DrVCC
K5
USDM
K6
P74/ExIRQ4/AN4
K7
AVSS/DrVSS
K8
PA0/A16/KIN8/SSE0I
K9
P40/IRQ0/TMI0/ExMCCLK
K10
P41/IRQ1/TMI1/ExMCCMD/ExMCTxD/HSYNCI
K11
(Reserved)
L1
P61/D1/CPD1/FTOA/CIN1/KIN1/VSYNCO/SUSPEND
L2
ETDI
L3
P65/D5/CPD5/FTID/CIN5/KIN5/CSYNCI/XVERDATA
L4
AVref
L5
USDP
L6
P73/ExIRQ3/AN3
L7
P76/ExIRQ6/AN6/DA0
L8
AVSS/DrVSS
L9
P54/IRQ12/TxD2
L10
(Reserved)
L11
Pin Name
Figure 1.2 Pin Arrangement (TBP-112A: Top View)
Rev. 3.00 Jan 25, 2006 page 3 of 872
REJ09B0286-0300
Page 58
Section 1 Overview
1.3.2 Pin Arrangement in Each Operating Mode
Table 1.1 Pin Arrangement in Each Operating Mode
Pin No. Pin Name
Extended Mode Single-Chip Mode
TBP-112A
Modes 2 and 3
(EXPE = 1)
Modes 2 and 3
(EXPE = 0)
B2 RES RES RES
B1 XTAL XTAL XTAL
C2 EXTAL EXTAL EXTAL
C1 MD2 MD2 VCC
D3 MD1 MD1 VSS
D2 MD0 MD0 VSS
D1 NMI NMI FA9
E4 STBY STBY VCC
E3 VCL VCL VCL
E1 X1 X1 NC
E2 X2 X2 NC
F3 ETRST ETRST VSS
F1 P51/IRQ9/RxD0 P51/IRQ9/RxD0 FA17
F2 P50/IRQ8/TxD0 P50/IRQ8/TxD0 NC
F4, G1 VSS VSS VSS
G2 P97/WAIT/CPWAIT/CS256 P97 VCC
G3 P96/φ/EXCL P96/φ/EXCL NC
H1 AS/IOS P95 FA16
G4 HWR/CPWE P94 FA15
H2 P56/IRQ14/PWX0 P56/IRQ14/PWX0 NC
J1 P57/IRQ15/PWX1 P57/IRQ15/PWX1 NC
H3 RD/CPOE P93 WE
J2 P92/CPCS1 P92 VSS
K1 P91/CPCS2 P91 VCC
J3 P90/LWR P90 VCC
2
K2 P60/FTCI/CIN0/
KIN0/HFBACKI
1
*
D0/CPD0
*
P60/FTCI/CIN0/KIN0/
HFBACKI/SPEED
Flash Memory
Programmer
Mode
NC
Rev. 3.00 Jan 25, 2006 page 4 of 872
REJ09B0286-0300
Page 59
Section 1 Overview
Pin No. Pin Name
Extended Mode Single-Chip Mode
Modes 2 and 3
TBP-112A
(EXPE = 1)
L2 P61/FTOA/CIN1/
KIN1/VSYNCO
H4 P62/FTIA/CIN2/
KIN2/VSYNCI
1
*
K3 P63/FTIB/CIN3/
KIN3/VFBACKI
1
*
1
*
D1/CPD1
D2/CPD2
D3/CPD3
Modes 2 and 3
(EXPE = 0)
2
*
P61/FTOA/CIN1/KIN1/
VSYNCO/SUSPEND
2
*
P62/FTIA/CIN2/KIN2/
VSYNCI/TXENL
2
*
P63/FTIB/CIN3/KIN3/
VFBACKI/TXDMNS
Flash Memory
Programmer
Mode
NC
NC
NC
L3 ETDI ETDI NC
J4 ETCK ETCK NC
2
K4 P64/FTIC/CINk4/
KIN4/CLAMPO
L4 P65/FTID/CIN5/
KIN5/CSYNCI
*
1
*
H5 P66/FTOB/CIN6/
KIN6/CBLANK
*
J5 P67/CIN7/KIN7
1
1
1
*
D4/CPD4
D5/CPD5
D6/CPD6
D7/CPD7
*
P64/FTIC/CIN4/KIN4/
CLAMPO/TXDPLS
2
*
P65/FTID/CIN5/KIN5/
CSYNCI/XVERDATA
2
*
P66/FTOB/CIN6/KIN6/
CBLANK/DMNS
2
*
P67/CIN7/KIN7/DPLS VSS
NC
NC
NC
L5 AVref AVref VCC
K5, J6 AVCC/DrVCC AVCC/DrVCC VCC
L6 USDP USDP NC
K6 USDM USDM NC
H6 P72/ExIRQ2/AN2 P72/ExIRQ2/AN2 NC
L7 P73/ExIRQ3/AN3 P73/ExIRQ3/AN3 NC
K7 P74/ExIRQ4/AN4 P74/ExIRQ4/AN4 NC
J7 P75/ExIRQ5/AN5 P75/ExIRQ5/AN5 NC
L8 P76/ExIRQ6/AN6/DA0 P76/ExIRQ6/AN6/DA0 NC
H7 P77/ExIRQ7/AN7/DA1 P77/ExIRQ7/AN7/DA1 NC
K8, L9 AVSS/DrVSS AVSS/DrVSS VSS
J8 PA1/A17/KIN9/
K9 PA0/A16/KIN8/
SSE2I
SSE0I
3
*
3
*
PA1/KIN9/
4
*
SSE2I
PA0/KIN8/
4
*
SSE0I
PA1/KIN9/SSE2I NC
PA0/KIN8/SSE0I NC
L10 P54/IRQ12/TxD2 P54/IRQ12/TxD2 NC
J9 P55/IRQ13/RxD2 P55/IRQ13/RxD2 NC
Rev. 3.00 Jan 25, 2006 page 5 of 872
REJ09B0286-0300
Page 60
Section 1 Overview
Pin No. Pin Name
Extended Mode Single-Chip Mode
Modes 2 and 3
TBP-112A
K10 P40/IRQ0/TMI0/ExMCCLK P40/IRQ0/TMI0/ExMCCLK NC
K11 P41/IRQ1/TMI1/ExMCCMD/
H8 P42/IRQ2/TMO0/ExMCDAT/
J10 P43/IRQ3/TMO1/
J11 P44/IRQ4/TMIX/
H9 P45/IRQ5/TMIY P45/IRQ5/TMIY NC
H10 P46/IRQ6/TMOX P46/IRQ6/TMOX NC
H11 P47/IRQ7/TMOY P47/IRQ7/TMOY NC
G8, G9 VCC VCC VCC
G11 P27/A15 P27/PW15 CE
G10 P26/A14 P26/PW14 FA14
F9 P25/A13 P25/PW13 FA13
F11 P24/A12 P24/PW12 FA12
F10 P23/A11/CPREG P23/PW11 FA11
F8 P22/A10/CPA10 P22/PW10 FA10
E11 P21/A9/CPA9 P21/PW9 OE
E10 P20/A8/CPA8 P20/PW8 FA8
E9 ETMS ETMS NC
D11 ETDO ETDO NC
E8, D10 VSS VSS VSS
C11 VSS VSS VSS
D9 P17/A7/CPA7 P17/PW7 FA7
C10 P16/A6/CPA6 P16/PW6 FA6
B11 P15/A5/CPA5 P15/PW5 FA5
C9 P14/A4/CPA4 P14/PW4 FA4
B10 P13/A3/CPA3 P13/PW3 FA3
(EXPE = 1)
ExMCTxD/HSYNCI
ExMCRxD
ExMCDATDIR/ExMCCSA/
HSYNCO
ExMCCMDDIR/ExMCCSB
Modes 2 and 3
(EXPE = 0)
P41/IRQ1/TMI1/ExMCCMD/
ExMCTxD/HSYNCI
P42/IRQ2/TMO0/ExMCDAT/
ExMCRxD
P43/IRQ3/TMO1/
ExMCDATDIR/ExMCCSA/
HSYNCO
P44/IRQ4/TMIX/
ExMCCMDDIR/ExMCCSB
Flash Memory
Programmer
Mode
NC
NC
NC
NC
Rev. 3.00 Jan 25, 2006 page 6 of 872
REJ09B0286-0300
Page 61
Section 1 Overview
Pin No. Pin Name
Extended Mode Single-Chip Mode
Modes 2 and 3
TBP-112A
A10 P12/A2/CPA2 P12/PW2 FA2
D8 P11/A1/CPA1 P11/PW1 FA1
B9 P10/A0/CPA0 P10/PW0 FA0
A9 P87/ExIRQ15/ADTRG/ExTMIY/
C8 P86/ExIRQ14/SCK2/ExTMIX P86/ExIRQ14/SCK2/ExTMIX NC
A8 D8/CPD8 P30/WUE8/MCCLK FO0
D7 D9/CPD9 P31/WUE9/MCCMD/MCTxD FO1
C7 D10/CPD10 P32/WUE10/MCDAT/MCRxD FO2
A7 D11/CPD11 P33/WUE11/MCDATDIR/
B7 D12/CPD12 P34/WUE12/MCCMDDIR/
C6 D13/CPD13 P35/WUE13 FO5
A6 D14/CPD14 P36/WUE14 FO6
B6 D15/CPD15 P37/WUE15 FO7
D6 P85/ExIRQ13/SCK1/ExTMI1 P85/ExIRQ13/SCK1/ExTMI1 NC
A5 P84/ExIRQ12/SCK0/ExTMI0 P84/ExIRQ12/SCK0/ExTMI0 NC
B5, C5 VSS VSS VSS
A4 P80/ExIRQ8/SCL0 P80/ExIRQ8/SCL0 NC
D5 P81/ExIRQ9/SDA0 P81/ExIRQ9/SDA0 NC
B4 P82/ExIRQ10/SCL1 P82/ExIRQ10/SCL1 NC
A3 P83/ExIRQ11/SDA1 P83/ExIRQ11/SDA1 NC
C4 P52/IRQ10/TxD1/IrTxD P52/IRQ10/TxD1/IrTxD FA18
B3 P53/IRQ11/RxD1/IrRxD P53/IRQ11/RxD1/IrRxD NC
A2 FWE FW E FWE
C3 RESO RESO NC
Notes: 1. 8-bit data bus
(EXPE = 1)
USEXCL
2. 16-bit data bus
3. Extended mode (mode 2)
4. Extended mode (mode 3)
Modes 2 and 3
(EXPE = 0)
P87/ExIRQ15/ADTRG/ExTMIY/
USEXCL
MCCSA
MCCSB
Flash Memory
Programmer
Mode
NC
FO3
FO4
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Section 1 Overview
1.3.3 Pin Functions
Table 1.2 Pin Functions
Pin No.
Type Symbol TBP-112A I/O Name and Function
Power
supply
Clock
Operating
mode
control
System
control
VCC G8, G9 Input Power supply pins. Connect all these
pins to the system power supply.
VCL E3 Input Power supply pin. Connect this pin to
VCC.
VSS F4, G1
E8, D10
C11, B5
C5
XTAL B1 Input
EXTAL C2 Input
φ G3 Output Supplies the system clock to external
EXCL G3 Input 32.768-kHz external clock for subclock
X1 E1 Input
X2 E2 Input
MD2
MD1
MD0
RES B2 Input Reset pin. When this pin is low, the chip
RESO C3 Output Outputs a reset signal to an external
STBY E4 Input When this pin is low, a transition is made
FWE A2 Input Pin for use by flash memory.
C1
D3
D2
Input Ground pins. Connect all these pins to
the system power supply (0 V).
For connection to a crystal resonator. An
external clock can be supplied from the
EXTAL pin. For an example of crystal
resonator connection, see section 26,
Clock Pulse Generator.
devices.
should be supplied.
For connection to a crystal resonator. An
external clock can be supplied from the
X2 pin. For an example of crystal
resonator connection, see section 26,
Clock Pulse Generator.
Input These pins set the operating mode.
Inputs at these pins should not be
changed during operation.
is reset.
device.
to hardware standby mode.
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Pin No.
Type Symbol TBP-112A I/O Name and Function
Address
bus
CompactFlash
control
A17 to A0 J8, K9
G11, G10
F9, F11
F10, F8
E11, E10
D9, C10
B11, C9
B10, A10
D8, B9
D15 to D8 B6, A6
C6, B7
A7, C7
D7, A8
D7 to D0 J5, H5
L4, K4
K3, H4
L2, K2
CPREG
CPA10 to
CPA0
CPD15 to
CPD0
CPCS2
CPCS1
CPWAIT G2 Input CompactFlash wait input pin
CPOE H3 Output CompactFlash output enable output pin
CPWE G4 Output CompactFlash write enable output pin
F10
F8, E11
E10, D9
C10, B11
C9, B10
A10, D8
B9
B6, A6
C6, B7
A7, C7
D7, A8
J5, H5
L4, K4
K3, H4
L2, K2
K1
J2
Output Address output pins
Input/
Output
Output CompactFlash address output pins
Input/
Output
Output CompactFlash chip select output pins
Upper bidirectional data busData bus
Lower bidirectional data bus
CompactFlash bidirectional data bus
Section 1 Overview
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Section 1 Overview
Pin No.
Type Symbol TBP-112A I/O Name and Function
Bus
control
Interrupts
On-chip
emulator
WAIT G2 Input Requests insertion of a wait state in the
bus cycle when accessing an external 3state address space.
RD H3 Output This pin is low when the external
address space is being read from.
HWR G4 Output This pin is low when the external
address space is being written to, and
the upper half of the data bus is enabled.
LWR J3 Output This pin is low when the external space
is being written to, and the lower half of
the data bus is enabled.
AS/IOS H1 Output This pin is low when address output on
the address bus is valid.
CS256 G2 Output Indicates that the 256-kbyte area from
H'F80000 to H'FBFFFF is accessed.
NMI D1 Input Nonmaskable interrupt request input pin
IRQ15 to
IRQ0
ExIRQ15 to
ExIRQ2
ETRST
ETMS
ETDO
ETDI
ETCK
J1, H2
J9, L10
B3, C4
F1, F2
H11, H10
H9, J11
J10, H8
K11, K10
A9, C8
D6, A5
A3, B4
D5, A4
H7, L8
J7, K7
L7, H6
F3
E9
D11
L3
J4
Input These pins request a maskable interrupt.
Selectable to which pin of IRQn or
ExIRQn to insert IRQ15 to IRQ0
interrupts.
Input
Input
Output
Input
Input
On-chip emulator interface pins
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Pin No.
Type Symbol TBP-112A I/O Name and Function
PWM timer
(PWM)
14-bit
PWM timer
(PWMX)
16-bit free
running
timer (FRT)
8-bit timer
(TMR_0,
TMR_1,
TMR_X,
TMR_Y)
Timer
connection
PW15 to PW0 G11, G10
F9, F11
F10, F8
E11, E10
D9, C10
B11, C9
B10, A10
D8, B9
PWX1
PWX0
FTCI K2 Input External event input pin
FTOA
FTOB
FTIA to
FTID
TMO0
TMO1
TMOX
TMOY
TMI0
TMI1
TMIX
TMIY
ExTMI0
ExTMI1
ExTMIX
ExTMIY
VSYNCI
HSYNCI
CSYNCI
VFBACKI
HFBACKI
VSYNCO
HSYNCO
CLAMPO
CBLANK
J1
H2
L2
H5
H4, K3
K4, L4
H8
J10
H10
H11
K10
K11
J11
H9
A5
D6
C8
A9
H4
K11
L4
K3
K2
L2
J10
K4
H5
Output PWM timer pulse output pins
Output PWMX (D/A) pulse output pins
Output
Output
Input Input capture input pins
Output Waveform output pins with output
Input External event input pins and counter
Input Timer connection synchronization signal
Output Timer connection synchronization signal
Output compare output pins
compare function
reset input pins. Selectable to which pin
of TMIn or ExTMIn to insert external
event and counter reset.
input pins
output pins
Section 1 Overview
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Section 1 Overview
Pin No.
Type Symbol TBP-112A I/O Name and Function
Serial
communication
Interface
(SCI_0,
SCI_1,
SCI_2)
IrDA (SCI)
I2C bus
interface
(IIC)
Keyboard
control
A/D
converter
D/A
converter
TxD0 to TxD2 F2, C4
L10
RxD0 to RxD2 F1, B3
J9
SCK0 to SCK2 A5, D6
C8
SSE0I K9 Input Input pin to halt SCI_0
SSE2I J8 Input Input pin to halt SCI_2
IrTxD C4 Output Encoded data output pin for IrDASCI with
IrRxD B3 Input Encoded data input pin for IrDA
SCL0
SCL1
SDA0
SDA1
KIN9 to KIN0 J8, K9
WUE15 to
WUE8
AN7 to AN2 H7, L8
CIN7 to CIN0 J5, H5
ADTRG A9 Input External trigger input pin to start A/D
DA1
DA0
A4
B4
D5
A3
J5, H5
L4, K4
K3, H4
L2, K2
B6, A6
C6, B7
A7, C7
D7, A8
J7, K7
L7, H6
L4, K4
K3, H4
L2, K2
H7
L8
Output Transmit data output pins
Input Receive data input pins
Input/
Output
Input/
Output
Input/
Output
Input Keyboard matrix input pins. All pins have
Input Wake-up event input pins. Same wake
Input Analog input pins
Input Extended A/D conversion input pins
Output Analog output pins
Clock input/output pins. Output format is
NMOS push-pull output.
IIC clock input/output pins. These pins
can drive a bus directly with the NMOS
open drain output.
IIC data input/output pins. These pins
can drive a bus directly with the NMOS
open drain output.
a wake-up function. Normally, KIN9 to
KIN0 function as key scan inputs, and
P17 to P10 and P27 to P20 function as
key scan outputs. Thus, at a maximum
of 16 outputs x 8 inputs, 128-key matrix
can be configured.
up as key wake up can be performed
with various sources.
conversion
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Pin No.
Type Symbol TBP-112A I/O Name and Function
A/D
converter
D/A
converter
Universal
serial bus
(USB)
AVCC K5, J6 Input Analog power supply pins for the A/D
converter and D/A converter. When the
A/D converter and D/A converter are not
used, these pins should be connected to
the system power supply. These pins are
used with the USB internal
driver/receiver power supply, and should
therefore be connected to a power
supply of 3.3 V ± 0.3 V whenever the
USB is used.
AVref L5 Input Reference voltage input pin for the A/D
converter and D/A converter. When the
A/D converter and D/A converter are not
used, this pin should be connected to the
system power supply.
AVSS K8, L9 Input Ground pins for the A/D converter and
D/A converter. These pins should be
connected to the system power supply
(0 V).
USDP
USDM
USEXCL A9 Input USB external clock input pin
DrVCC K5, J6 Input These pins should be connected to the
DrVSS K8, L9 Input These pins should be connected to the
SPEED K2 Output
SUSPEND L2 Output
TXENL H4 Output
TXDMNS K3 Output
TXDPLS K4 Output
XVERDATA L4 Input
DMNS H5 Input
DPLS J5 Input
L6
K6
Input/
Output
USB serial data I/O pins
internal driver/receiver power supply
(3.3 V ± 0.3 V).
internal driver/receiver power supply
(0 V).
External driver/receiver connection
signals.
These pins are for connection to a
driver/receiver compatible with
PDIUSBP11A manufactured by Philips
Electronics.
Section 1 Overview
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Section 1 Overview
Pin No.
Type Symbol TBP-112A I/O Name and Function
Multimedia
card
interface
(MCIF)
I/O ports P17 to P10 D9, C10
ExMCCLK
MCCLK
ExMCTxD
MCTxD
ExMCRxD
MCRxD
ExMCCSA
ExMCCSB
MCCSA
MCCSB
ExMCCMD
MCCMD
ExMCDAT
MCDAT
ExMCDATDIR
ExMCCMDDIR
MCDATDIR
MCCMDDIR
P27 to P20 G11, G10
P37 to P30 B6, A6
P47 to P40 H11, H10
P57 to P50 J1, H2
K10
A8
K11
D7
H8
C7
J10
J11
A7
B7
K11
D7
H8
C7
J10
J11
A7
B7
B11, C9
B10, A10
D8, B9
F9, F11
F10, F8
E11, E10
C6, B7
A7, C7
D7, A8
H9, J11
J10, H8
K11, K10
J9, L10
B3, C4
F1, F2
Output Common clock output pins for MMC
mode*/SPI mode
Output Command/data output pins in SPI mode
Input Response/data input pins in SPI mode
Output Chip select output pins to select
multimedia card in SPI mode
Input/
Output
Input/
Output
Output Output pins indicating I/O direction of
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Command output/response input pins in
MMC mode
Data I/O pins in MMC mode
MCCMD and MCDAT pins
Eight input/output pins
Eight input/output pins
Eight input/output pins
Eight input/output pins
Eight input/output pins
*
*
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Pin No.
Type Symbol TBP-112A I/O Name and Function
I/O ports P67 to P60 J5, H5
L4, K4
K3, H4
L2, K2
P77 to P72 H7, L8
J7, K7
L7, H6
P87 to P80 A9, C8
D6, A5
A3, B4
D5, A4
P97 to P90 G2, G3
H1, G4
H3, J2
K1, J3
PA1, PA0 J8, K9 Input/
Note: * MMC mode is MultiMediaCard mode.
Input/
Output
Input Six input pins
Input/
Output
Input/
Output
Output
Eight input/output pins
Eight input/output pins
Eight input/output pins. Note that pin P96
cannot be used as a general output port.
Two input/output pins
Section 1 Overview
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Section 1 Overview
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Section 2 CPU
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, see section 3, MCU Operating Modes.
2.1 Features
• Upward-compatibility with H8/300 and H8/300H CPUs
Can execute H8/300 CPU and H8/300H CPU object programs
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes
• High-speed operation
All frequently-used instructions are executed in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
CPUS210A_000020020300
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Section 2 CPU
16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
• Two CPU operating modes
Normal mode
Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruction
Selectable CPU clock speed
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MULXU MULXU.B Rs, Rd 3 12
MULXU.W Rs, ERd 4 20
MULXS MULXS.B Rs, Rd 4 13
MULXS.W Rs, ERd 5 21
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
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Section 2 CPU
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit extended registers and one 8-bit control register have been added.
• Extended address space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions are executed twice as fast.
2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
One 8-bit control register has been added.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions are executed twice as fast.
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Section 2 CPU
2.2 CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space.
The mode is selected by the LSI's mode pins.
2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU in normal
mode.
• Address space
Linear access to a maximum address space of 64 kbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When extended register En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. (If general register Rn is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended
register (En) will be affected.)
• Instruction set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception vector table and memory indirect branch addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
• Stack structure
In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call
in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.2. The extended control register
(EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.
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Section 2 CPU
SP
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
(Reserved for system use)
Exception vector 1
Exception vector 2
Exception
vector table
Figure 2.1 Exception Vector Table (Normal Mode)
PC
(16 bits)
SP
CCR
CCR
PC
(16 bits)
*
(a) Subroutine Branch (b) Exception Handling
Note: * Ignored when returning.
Figure 2.2 Stack Structure in Normal Mode
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Section 2 CPU
2.2.2 Advanced Mode
• Address space
Linear access to a maximum address space of 16 Mbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the
upper 16-bit segments of 32-bit registers or address registers.
• Instruction set
All instructions and addressing modes can be used.
• Exception vector table and memory indirect branch addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored
in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section 4,
Exception Handling.
H'00000000
H'00000003
H'00000004
H'00000007
H'00000008
H'0000000B
H'0000000C
H'00000010
Reserved
Reset exception vector
Reserved
(Reserved for system use)
Exception vector table
(Reserved for system use)
Reserved
Exception vector 1
Figure 2.3 Exception Vector Table (Advanced Mode)
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Section 2 CPU
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the top area of this range is also used for the exception vector table.
• Stack structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC and condition-code register (CCR) are pushed onto the stack in exception
handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not
pushed onto the stack. For details, see section 4, Exception Handling.
SP
Reserved
PC
(24 bits)
(a) Subroutine Branch (b) Exception Handling
SP
CCR
PC
(24 bits)
Figure 2.4 Stack Structure in Advanced Mode
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Section 2 CPU
2.3 Address Space
Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, see section 3, MCU Operating
Modes.
H'0000
H'FFFF
H'00000000
64 kbytes 16 Mbytes
H'00FFFFFF
Not available
in this LSI
H'FFFFFFFF
(b) Advanced Mode(a) Normal Mode
Figure 2.5 Memory Map
Program area
Data area
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Section 2 CPU
2.4 Register Configuration
The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit
extended control register (EXR), and an 8-bit condition code register (CCR).
General Registers (Rn) and Extended Registers (En)
15 0 7 0 7 0
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
Control Registers
23 0
Legend:
SP
: Stack pointer
PC
: Program counter
EXR
: Extended control register
T
: Trace bit
I2 to I0
: Interrupt mask bits
CCR
: Condition-code register
: Interrupt mask bit
I
UI
: User bit or interrupt mask bit
H
U
N
Z
V
C
Note: * Does not affect operation in this LSI.
Figure 2.6 CPU Internal Registers
: Half-carry flag
: User bit
: Negative flag
: Zero flag
: Overflow flag
: Carry flag
PC
76543210
*
TI2I1I0
EXR
----
76543210
CCR
IUIHUNZVC
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Section 2 CPU
2.4.1 General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7)
are also referred to as extended registers.
When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing a maximum sixteen 8-bit registers.
The usage of each register can be selected independently.
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
E registers (extended registers)
ER registers
(ER0 to ER7)
Figure 2.7 Usage of General Registers
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• 16-bit registers • 8-bit registers
(E0 to E7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Page 81
Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.8 Stack
2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3 Extended Control Register (EXR)
EXR does not affect operation in this LSI.
Bit Bit Name Initial Value R/W Description
7 T 0 R/W Trace Bit
Does not affect operation in this LSI.
6 to 3 — All 1 R Reserved
These bits are always read as 1.
2
1
0
I2
I1
I0
1
1
1
R/W Interrupt Mask Bits 2 to 0
Do not affect operation in this LSI.
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Section 2 CPU
2.4.4 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit Bit Name Initial Value R/W Description
7 I 1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to
1 at the start of an exception-handling sequence. For
details, see section 5, Interrupt Controller.
6 UI Undefined R/W User Bit or Interrupt Mask Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
5 H Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if there
is a carry or borrow at bit 3, and cleared to 0 otherwise.
When the ADD.W, SUB.W, CMP.W, or NEG.W
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and cleared to 0 otherwise.
When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is
executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
4 U Undefined R/W User Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
3 N Undefined R/W Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2 Z Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to indicate
non-zero data.
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Section 2 CPU
Bit Bit Name Initial Value R/W Description
1 V Undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and cleared
to 0 otherwise.
0 C Undefined R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0 otherwise.
Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
2.4.5 Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR
bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
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Section 2 CPU
2.5 Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figure 2.9 shows the data formats of general registers.
Data Type Register Number Data Image
70
1-bit data
1-bit data
4-bit BCD data
RnH
RnL
RnH
65432710
Don't care
7043
Upper Lower
Don't care
70
65432710
Don't care
4-bit BCD data
Byte data
Byte data
RnL
RnH
RnL
Figure 2.9 General Register Data Formats (1)
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7043
Don't care
70
MSB LSB
Don't care
Upper Lower
Don't care
70
MSB LSB
Page 85
Data Type Data ImageRegister Number
Section 2 CPU
Word data
Word data
15 0
MSB LSB
Longword data
31 16
MSB
Rn
En
ERn
En Rn
Legend:
: General register ER
ERn
: General register E
En
: General register R
Rn
: General register RH
RnH
: General register RL
RnL
: Most significant bit
MSB
: Least significant bit
LSB
Figure 2.9 General Register Data Formats (2)
15 0
MSB LSB
15 0
LSB
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Section 2 CPU
2.5.2 Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Data T ype Address
70
1-bit data
Byte data
Word data
Longword data Address 2N
Address L
Address L
Address 2M
Address 2M + 1
Address 2N + 1
Address 2N + 2
Address 2N + 3
76 543210
MSB
MSB
MSB
Figure 2.10 Memory Data Formats
Data Image
LSB
LSB
LSB
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Section 2 CPU
2.6 Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
Data transfer
Arithmetic
operations
Logic operations AND, OR, XOR, NOT B/W/L 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
Branch B
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
Block data transfer EEPMOV — 1
Legend: B: Byte size
W: Word size
L: Longword size
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and
MOV.L ERn, @-SP.
2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot
be used as an STM/LDM register.
3. Cannot be used in this LSI.
4. B
CC
MOV B/W/L 5
1
*
POP
, PUSH
LDM, STM
MOVFPE
1
*
2
*
3
*
, MOVTPE
3
*
ADD, SUB, CMP, NEG B/W/L 19
ADDX, SUBX, DAA, DAS B
INC, DEC B/W/L
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
EXTU, EXTS W/L
TAS B
ROTXR
BIAND, BOR, BIOR, BXOR, BIXOR
4
*
, JMP, BSR, JSR, RTS — 5
CC
NOP
is the general name for conditional branch instructions.
W/L
L
B
B/W/L 8
B14
—9
Total: 65
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Section 2 CPU
2.6.1 Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2 Operation Notation
Symbol Description
Rd General register (destination)
Rs General register (source)
Rn General register
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical exclusive OR
→ Move
∼ NOT (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
*
*
*
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Table 2.3 Data Transfer Instructions
1
Instruction Size
MOV B/W/L (EAs) → Rd, Rs → (EAd)
MOVFPE B Cannot be used in this LSI.
MOVTPE B Cannot be used in this LSI.
POP W/L @SP+ → Rn
PUSH W/L Rn → @-SP
2
*
LDM
2
*
STM
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot
be used as an STM/LDM register.
*
Function
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
L @SP+ → Rn (register list)
Pops two or more general registers from the stack.
L Rn (register list) → @-SP
Pushes two or more general registers onto the stack.
Section 2 CPU
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Section 2 CPU
Table 2.4 Arithmetic Operations Instructions (1)
Instruction Size
ADD
SUB
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
MULXU B/W Rd × Rs → Rd
MULXS B/W Rd × Rs → Rd
DIVXU B/W Rd ÷ Rs → Rd
Note: * Size refers to the operand size.
*
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
B Rd (decimal adjust) → Rd
B: Byte
W: Word
L: Longword
Function
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Subtraction on
immediate data and data in a general register cannot be performed in
bytes. Use the SUBX or ADD instruction.)
Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.
Adds or subtracts the value 1 or 2 to or from data in a general register.
(Only the value 1 can be added to or subtracted from byte operands.)
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
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Table 2.4 Arithmetic Operations Instructions (2)
Section 2 CPU
Instruction Size
DIVXS B/W Rd ÷ Rs → Rd
CMP B/W/L Rd – Rs, Rd – #IMM
NEG B/W/L 0 – Rd → Rd
EXTU W/L Rd (zero extension) → Rd
EXTS W/L Rd (sign extension) → Rd
TAS B @ERd – 0, 1 → (<bit 7> of @ERd)
Note: * Size refers to the operand size.
*
B: Byte
W: Word
L: Longword
Function
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
Compares data in a general register with data in another general register
or with immediate data, and sets the CCR bits according to the result.
Takes the two's complement (arithmetic complement) of data in a
general register.
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
Tests memory contents, and sets the most significant bit (bit 7) to 1.
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Section 2 CPU
Table 2.5 Logic Operations Instructions
Instruction Size
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
NOT B/W/L ∼ Rd → Rd
Note: * Size refers to the operand size.
*
B: Byte
W: Word
L: Longword
Function
Performs a logical AND operation on a general register and another
general register or immediate data.
Performs a logical OR operation on a general register and another
general register or immediate data.
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
Takes the one's complement (logical complement) of data in a general
register.
Table 2.6 Shift Instructions
Instruction Size
SHAL
SHAR
SHLL
SHLR
ROTL
ROTR
ROTXL
ROTXR
Note: * Size refers to the operand size.
*
B/W/L Rd (shift) → Rd
B/W/L Rd (shift) → Rd
B/W/L Rd (rotate) → Rd
B/W/L Rd (rotate) → Rd
B: Byte
W: Word
L: Longword
Function
Performs an arithmetic shift on data in a general register. 1-bit or 2 bit
shift is possible.
Performs a logical shift on data in a general register. 1-bit or 2 bit shift is
possible.
Rotates data in a general register. 1-bit or 2 bit rotation is possible.
Rotates data including the carry flag in a general register. 1-bit or 2 bit
rotation is possible.
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Table 2.7 Bit Manipulation Instructions (1)
Section 2 CPU
B: Byte
*
Function
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
Logically ANDs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
Logically ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
Logically ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
Logically ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
Instruction Size
BSET B 1 → (<bit-No.> of <EAd>)
BCLR B 0 → (<bit-No.> of <EAd>)
BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
BTST B ∼ (<bit-No.> of <EAd>) → Z
BAND B C ∧ (<bit-No.> of <EAd>) → C
BIAND B C ∧ (<bit-No.> of <EAd>) → C
BOR B C ∨ (<bit-No.> of <EAd>) → C
BIOR B C ∨ (∼ <bit-No.> of <EAd>) → C
Note: * Size refers to the operand size.
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Section 2 CPU
Table 2.7 Bit Manipulation Instructions (2)
Instruction Size
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
BIXOR B C ⊕ ∼ (<bit-No.> of <EAd>) → C
BLD B (<bit-No.> of <EAd>) → C
BILD B ∼ (<bit-No.> of <EAd>) → C
BST B C → (<bit-No.> of <EAd>)
BIST B ∼ C → (<bit-No.> of <EAd>)
Note: * Size refers to the operand size.
B: Byte
*
Function
Logically exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry flag.
Logically exclusive-ORs the carry flag with the inverse of a specified bit
in a general register or memory operand and stores the result in the
carry flag.
The bit number is specified by 3-bit immediate data.
Transfers a specified bit in a general register or memory operand to the
carry flag.
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
Transfers the carry flag value to a specified bit in a general register or
memory operand.
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
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Section 2 CPU
Table 2.8 Branch Instructions
Instruction Size Function
Bcc — Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC (BHS) Carry clear
(high or same)
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1
C = 0
JMP — Branches unconditionally to a specified address.
BSR — Branches to a subroutine at a specified address
JSR — Branches to a subroutine at a specified address
RTS — Returns from a subroutine
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Section 2 CPU
Table 2.9 System Control Instructions
Instruction Size
TRAPA — Starts trap-instruction exception handling.
RTE — Returns from an exception-handling routine.
SLEEP — Causes a transition to a power-down state.
LDC B/W (EAs) → CCR, (EAs) → EXR
STC B/W CCR → (EAd), EXR → (EAd)
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
NOP — PC + 2 → PC
Note: * Size refers to the operand size.
B: Byte
W: Word
*
Function
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are valid.
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.
Logically ANDs the CCR or EXR contents with immediate data.
Logically ORs the CCR or EXR contents with immediate data.
Logically exclusive-ORs the CCR or EXR contents with immediate
data.
Only increments the program counter.
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Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction Size Function
EEPMOV.B — if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next:
EEPMOV.W — if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next:
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2 Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields, and some have no register field.
• Effective address extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition field
Specifies the branching condition of Bcc instructions.
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Section 2 CPU
(1) Operation field only
op
(2) Operation field and register fields
op
(3) Operation field, register fields, and effective address extension
op
EA (disp)
(4) Operation field, effective address extension, and condition field
op cc EA (disp) BRA d:16
rn
rn rm
rm
NOP, RTS
ADD.B Rn, Rm
MOV.B @(d:16, Rn), Rm
Figure 2.11 Instruction Formats (Examples)
2.7 Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
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Section 2 CPU
Table 2.11 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
@ERn+
@–ERn
2.7.1 Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2 Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction code is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register Indirect with Post-Increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word access, and 4 for longword
access. For word or longword transfer instructions, the register value should be even.
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Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or
longword transfer instructions, the register value should be even.
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address,
the entire address space is accessed.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.12 Absolute Address Access Ranges
Absolute Address Normal Mode Advanced Mode
Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32) H'000000 to H'FFFFFF
Program instruction
address
24 bits (@aa:24)
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in a instruction
code can be used directly as an operand.
The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.
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