Renesas H8S Series, H8S/2100 Series, H8S/2114R, R4F2114R Hardware Manual

REJ09B0098-0300

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16

H8S/2114R R4F2114R

H8S/2114RGroup

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family / H8S/2100 Series

Rev.3.00
Revision Date: Jul. 14, 2005

Rev. 3.00 Jul. 14, 2005 Page ii of xlviii

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 3.00 Jul. 14, 2005 Page iii of xlviii

General Precautions on Handling of Product

1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are hi g h-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfun ction may occur.

3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Rese rved Addresses
Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 3.00 Jul. 14, 2005 Page iv of xlviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)
Product code, Package dimensions, etc.

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 3.00 Jul. 14, 2005 Page v of xlviii

Preface

This H8S/2114R Group is a series of microcomputers (MCUs) made up of the H8S/2000 CPU
with Renesas Technology’s original architecture as its core, and the peripheral functions required
to configure a system.

The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward
compatibility at the object level with the H8/300 and H8/300 H CPUs. This allows the transition
from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU.

This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit
free running timer (FRT), a 16-bit timer pulse unit (TPU), 8-bit timers (TMR), watchdog timer
(WDT), serial communication interface (SCI), I
keyboard buffer control units (KBU), an A/D converter, and I/O ports as on-chip p er ipheral
modules required for system configuration.

A data transfer controller (DTC) and LPC interface (LPC) are included as bus masters.

2

C bus interface (IIC), a LPC interface (LPC), a

A flash memory (F-ZTAT

TM

*) is available for this LSI’s 1 Mbyte ROM. The CPU and ROM are
connected to a 16-bit bus, enabling byte data and word data to be accessed in a single state. This
improves the instruction fetch and process speeds.

Note: * F-ZTAT

TM

is a trademark of Renesas Technology. Corp.

Target Users: This manual was written for users who use the H8S/2114R in the design of

application systems. Target users are expected to understand the fundamentals of
electrical circuits, logic circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2114R Group to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read this manual in the order of the table of contents. This manual can be roughly categorized
into the descriptions on the CPU, system control functions, peripheral functions and electrical
characteristics.

Rev. 3.00 Jul. 14, 2005 Page vi of xlviii

• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

• In order to understand the detailed function of a register whose name is known
Read the index that is the final part of the manual to find the page number of the entry on the

register. The addresses, bits, and initial values of the registers are summarized in section 25,
List of Registers.

Rules: Register name: The following notation is used for cases when the same or a

similar function, e.g., serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel

number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B’xxxx, hexadecimal is H’xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/

H8S/2114R Group manuals:

Document Title Document No.

H8S/2114R Group Hardware Manual This manual

H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139

User's manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual

Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual

H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial REJ10B0024

H8S, H8/300 Series High-performance Embedded Workshop 3 User's
Manual

Rev. 3.00 Jul. 14, 2005 Page vii of xlviii

REJ10B0058

ADE-702-282

REJ10B0026

Rev. 3.00 Jul. 14, 2005 Page viii of xlviii

Main Revisions and Additions in this Edition

Item Page Revisions (See Manual for Details)

All pages  Suffix R is added to group name and product code.

• H8S/2114 Group→ H8S/2114R Group

• R4F2114 → R4F2114R

Appendix

C. Package Dimensions

Figure C.1 Package
Dimensions (TFP-144)

977 Replaced.

Rev. 3.00 Jul. 14, 2005 Page ix of xlviii

Rev. 3.00 Jul. 14, 2005 Page x of xlviii

Contents

Section 1 Overview................................................................................................1

1.1 Overview................................................................................................................................1

1.2 Internal Block Diagram..........................................................................................................3

1.3 Pin Description.......................................................................................................................4

1.3.1 Pin Arrangement....................................................................................................... 4

1.3.2 Pin Arrangement in Each Operating Mode...............................................................5

1.3.3 Pin Functions..........................................................................................................10

Section 2 CPU......................................................................................................19

2.1 Features................................................................................................................................ 19

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU..................................... 20

2.1.2 Differences from H8/300 CPU ...............................................................................21

2.1.3 Differences from H8/300H CPU.............................................................................21

2.2 CPU Operating Modes......................................................................................................... 22

2.2.1 Normal Mode.......................................................................................................... 22

2.2.2 Advanced Mode......................................................................................................24

2.3 Address Space...................................................................................................................... 26

2.4 Register Configuration......................................................................................................... 27

2.4.1 General Registers....................................................................................................28

2.4.2 Program Counter (PC)............................................................................................29

2.4.3 Extended Control Register (EXR)..........................................................................29

2.4.4 Condition-Code Register (CCR).............................................................................30

2.4.5 Initial Register Values.............................................................................................31

2.5 Data Formats........................................................................................................................32

2.5.1 General Register Data Formats...............................................................................32

2.5.2 Memory Data Formats............................................................................................ 34

2.6 Instruction Set......................................................................................................................35

2.6.1 Table of Instructions Classified by Function..........................................................36

2.6.2 Basic Instruction Formats.......................................................................................47

2.7 Addressing Modes and Effective Address Calculation........................................................48

2.7.1 Register Direct—Rn ............................................................................................... 48

2.7.2 Register Indirect—@ERn.......................................................................................48

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).................49

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.....49

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.......................................49

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32....................................................................50

Rev. 3.00 Jul. 14, 2005 Page xi of xlviii

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)......................................50

2.7.8 Memory Indirect—@@aa:8...................................................................................51

2.7.9 Effective Address Calculation................................................................................52

2.8 Processing States..................................................................................................................54

2.9 Usage Notes......................................................................................................................... 56

2.9.1 Note on TAS Instruction Usage.............................................................................. 56

2.9.2 Note on STM/LDM Instruction Usage...................................................................56

2.9.3 Note on Bit Manipulation Instructions ................................................................... 56

2.9.4 EEPMOV Instruction.............................................................................................. 57

Section 3 MCU Operating Modes.......................................................................59

3.1 Operating Mode Selection...................................................................................................59

3.2 Register Descriptions...........................................................................................................60

3.2.1 Mode Control Register (MDCR)............................................................................60

3.2.2 System Control Register (SYSCR)......................................................................... 61

3.2.3 Serial Timer Control Register (STCR)...................................................................63

3.2.4 System Control Register 3 (SYSCR3).................................................................... 66

3.3 Operating Mode Descriptions.............................................................................................. 67

3.3.1 Mode 2.................................................................................................................... 67

3.3.2 Mode 3.................................................................................................................... 67

3.4 Address Map........................................................................................................................ 67

Section 4 Exception Handling.............................................................................69

4.1 Exception Handling Types and Priority............................................................................... 69

4.2 Exception Sources and Exception Vector Table.................................................................. 70

4.3 Reset....................................................................................................................................74

4.3.1 Reset Exception Handling ...................................................................................... 74

4.3.2 Interrupts Immediately after Reset..........................................................................75

4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................... 75

4.4 Interrupt Exception Handling .............................................................................................. 76

4.5 Trap Instruction Exception Handling...................................................................................76

4.6 Stack Status after Exception Handling.................................................................................77

4.7 Usage Note...........................................................................................................................78

Section 5 Interrupt Controller..............................................................................79

5.1 Features................................................................................................................................ 79

5.2 Input/Output Pi ns................................................................................................................. 81

5.3 Register Descriptions...........................................................................................................82

5.3.1 Interrupt Control Registers A to D (ICRA to ICRD).............................................. 83

5.3.2 Address Break Control Register (ABRKCR) .........................................................85

Rev. 3.00 Jul. 14, 2005 Page xii of xlviii

5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 86

5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)...................87

5.3.5 IRQ Enable Registers (IER16, IER).......................................................................90

5.3.6 IRQ Status Registers (ISR16, ISR)......................................................................... 91

5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up

Event Interrupt Mask Registers (WUEMR, WUEMRB)........................................ 93

5.3.8 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register

(ISSR).....................................................................................................................97

5.4 Interrupt Source s.................................................................................................................. 99

5.4.1 External Interrupt Sources ......................................................................................99

5.4.2 Internal Interrupt Sources ..................................................................................... 102

5.5 Interrupt Exception Handling Vector Tables.....................................................................102

5.6 Interrupt Control Modes and Interrupt Operation.............................................................. 109

5.6.1 Interrupt Control Mode 0......................................................................................112

5.6.2 Interrupt Control Mode 1......................................................................................114

5.6.3 Interrupt Exception Handling Sequence...............................................................117

5.6.4 Interrupt Response Times.....................................................................................119

5.6.5 DTC Activation by Interrupt................................................................................. 120

5.7 Address Breaks................................................................................................................. .122

5.7.1 Features................................................................................................................. 122

5.7.2 Block Diagram......................................................................................................122

5.7.3 Operation ..............................................................................................................123

5.7.4 Usage Notes.......................................................................................................... 123

5.8 Usage Notes....................................................................................................................... 125

5.8.1 Conflict between Interrupt Generation and Disabling..........................................125

5.8.2 Instructions for Disabling Interrupts..................................................................... 126

5.8.3 Interrupts during Execution of EEPMOV Instruction...........................................126

5.8.4 Vector Address Switching ....................................................................................126

5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode....................127

5.8.6 Noise Canceller Switching.................................................................................... 127

5.8.7 IRQ Status Register (ISR).....................................................................................127

Section 6 Bus Controller (BSC).........................................................................129

6.1 Features.............................................................................................................................. 129

6.2 Register Descriptions......................................................................................................... 130

6.2.1 Bus Control Register (BCR)................................................................................. 130

6.2.2 Wait State Control Register (WSCR) ...................................................................131

6.3 Bus Arbitration...................................................................................................................132

6.3.1 Priority of Bus Masters......................................................................................... 132

6.3.2 Bus Transfer Timing.............................................................................................132

Rev. 3.00 Jul. 14, 2005 Page xiii of xlviii

Section 7 Data Transfer Controller (DTC)........................................................135

7.1 Features.............................................................................................................................. 136

7.2 Register Descriptions......................................................................................................... 137

7.2.1 DTC Mode Register A (MRA).............................................................................138

7.2.2 DTC Mode Register B (MRB)..............................................................................139

7.2.3 DTC Source Address Register (SAR)...................................................................139

7.2.4 DTC Destination Address Register (DAR)........................................................... 140

7.2.5 DTC Transfer Count Register A (CRA)...............................................................140

7.2.6 DTC Transfer Count Register B (CRB)................................................................ 140

7.2.7 DTC Enable Registers (DTCER).......................................................................... 141

7.2.8 DTC Vector Register (DTVECR)......................................................................... 142

7.3 Activation Sources............................................................................................................. 143

7.4 Location of Register Information and DTC Vector Table................................................. 144

7.5 Operation...........................................................................................................................147

7.5.1 Normal Mode........................................................................................................ 148

7.5.2 Repeat Mode......................................................................................................... 149

7.5.3 Block Transfer Mode............................................................................................ 150

7.5.4 Chain Transfer......................................................................................................151

7.5.5 Interrupt Sources................................................................................................... 152

7.5.6 Operation Timing..................................................................................................152

7.5.7 Number of DTC Execution States........................................................................154

7.6 Procedures for Using DTC.................................................................................................155

7.6.1 Activation by Interrupt.......................................................................................... 155

7.6.2 Activation by Software......................................................................................... 155

7.7 Examples of Use of the DTC ............................................................................................. 156

7.7.1 Normal Mode........................................................................................................ 156

7.7.2 Software Activation.............................................................................................. 157

7.8 Usage Notes....................................................................................................................... 158

7.8.1 Module Stop Mode Setting................................................................................... 158

7.8.2 On-Chip RAM......................................................................................................158

7.8.3 DTCE Bit Setting.................................................................................................. 158

7.8.4 Setting Required on Entering Subactive Mode or Watch Mode........................... 158

7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter......... 158

Section 8 I/O Ports.............................................................................................159

8.1 Port 1..................................................................................................................................164

8.1.1 Port 1 Data Direction Register (P1DDR)..............................................................164

8.1.2 Port 1 Data Register (P1DR) ................................................................................ 165

8.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)................................................... 165

8.1.4 Pin Functions........................................................................................................166

Rev. 3.00 Jul. 14, 2005 Page xiv of xlviii

8.1.5 Port 1 Input Pull-Up MOS.................................................................................... 166

8.2 Port 2..................................................................................................................................167

8.2.1 Port 2 Data Direction Register (P2DDR)..............................................................167

8.2.2 Port 2 Data Register (P2DR).................................................................................168

8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)................................................... 168

8.2.4 Pin Functions........................................................................................................169

8.2.5 Port 2 Input Pull-Up MOS.................................................................................... 170

8.3 Port 3..................................................................................................................................171

8.3.1 8.3.1 Port 3 Data Direction Register (P3DDR).....................................................171

8.3.2 Port 3 Data Register (P3DR).................................................................................172

8.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)................................................... 172

8.3.4 Pin Functions........................................................................................................173

8.3.5 Port 3 Input Pull-Up MOS.................................................................................... 173

8.4 Port 4..................................................................................................................................174

8.4.1 Port 4 Data Direction Register (P4DDR)..............................................................174

8.4.2 Port 4 Data Register (P4DR).................................................................................175

8.4.3 Pin Functions........................................................................................................175

8.5 Port 5..................................................................................................................................178

8.5.1 Port 5 Data Direction Register (P5DDR)..............................................................178

8.5.2 Port 5 Data Register (P5DR).................................................................................178

8.5.3 Pin Functions........................................................................................................179

8.6 Port 6..................................................................................................................................180

8.6.1 Port 6 Data Direction Register (P6DDR)..............................................................180

8.6.2 Port 6 Data Register (P6DR).................................................................................181

8.6.3 Pull-Up MOS Control Register (KMPCR)...........................................................181

8.6.4 Noise Canceller Enable Register (P6NCE)........................................................... 182

8.6.5 Noise Canceller Mode Control Register (P6NCMC)............................................182

8.6.6 Noise Cancel Cycle Setting Register (P6NCCS).................................................. 183

8.6.7 System Control Register 2 (SYSCR2).................................................................. 185

8.6.8 Pin Functions........................................................................................................185

8.6.9 Port 6 Input Pull-Up MOS.................................................................................... 188

8.7 Port 7..................................................................................................................................189

8.7.1 Port 7 Input Data Register (P7PIN) ......................................................................189

8.7.2 Pin Functions........................................................................................................190

8.8 Port 8..................................................................................................................................191

8.8.1 Port 8 Data Direction Register (P8DDR)..............................................................191

8.8.2 Port 8 Data Register (P8DR).................................................................................192

8.8.3 Pin Functions........................................................................................................193

8.9 Port 9..................................................................................................................................196

8.9.1 Port 9 Data Direction Register (P9DDR)..............................................................196

Rev. 3.00 Jul. 14, 2005 Page xv of xlviii

8.9.2 Port 9 Data Register (P9DR) ................................................................................ 197

8.9.3 Port 9 Pull-Up MOS Control Register (P9PCR)................................................... 197

8.9.4 Pin Functions........................................................................................................198

8.9.5 Port 9 Input Pull-Up MOS.................................................................................... 200

8.10 Port A................................................................................................................................. 201

8.10.1 Port A Data Direction Register (PADDR)............................................................ 201

8.10.2 Port A Output Data Register (PAODR)................................................................ 202

8.10.3 Port A Input Data Register (PAPIN) .................................................................... 202

8.10.4 Pin Functions ........................................................................................................ 203

8.11 Port B................................................................................................................................. 204

8.11.1 Port B Data Direction Register (PBDDR) ............................................................ 204

8.11.2 Port B Output Data Register (PBODR) ................................................................ 205

8.11.3 Port B Input Data Register (PBPIN)..................................................................... 205

8.11.4 Pin Functions ........................................................................................................ 206

8.11.5 Port B Input Pull-Up MOS ................................................................................... 208

8.12 Port C................................................................................................................................. 209

8.12.1 Port C Data Direction Register (PCDDR) ............................................................ 209

8.12.2 Port C Output Data Register (PCODR) ................................................................ 210

8.12.3 Port C Input Data Register (PCPIN)..................................................................... 210

8.12.4 Noise Canceller Enable Register (PCNCE).......................................................... 211

8.12.5 Noise Canceller Mode Control Register (PCNCMC)........................................... 211

8.12.6 Noise Cancel Cycle Setting Register (PCNCCS) ................................................. 212

8.12.7 Pin Functions ........................................................................................................ 212

8.12.8 Port C Nch-OD control register (PCNOCR)......................................................... 215

8.12.9 Pin Functions ........................................................................................................ 215

8.12.10 Port C Input Pull-Up MOS...................................................................................216

8.13 Port D................................................................................................................................. 217

8.13.1 Port D Data Direction Register (PDDDR)............................................................ 217

8.13.2 Port D Output Data Register (PDODR)................................................................ 218

8.13.3 Port D Input Data Register (PDPIN) .................................................................... 218

8.13.4 Pin Functions ........................................................................................................ 219

8.13.5 Port D Nch-OD control register (PDNOCR)........................................................ 223

8.13.6 Pin Functions ........................................................................................................ 223

8.13.7 Port D Input Pull-Up MOS...................................................................................224

8.14 Port E.................................................................................................................................225

8.14.1 Port E Input Pull-Up MOS Control Register (PEPCR) ........................................ 225

8.14.2 Port E Input Data Register (PEPIN) ..................................................................... 225

8.14.3 Pin Functions ........................................................................................................ 226

8.14.4 Port E Input Pull-Up MOS.................................................................................... 226

8.15 Port F ................................................................................................................................. 227

Rev. 3.00 Jul. 14, 2005 Page xvi of xlviii

8.15.1 Port F Data Direction Register (PFDDR) ............................................................. 227

8.15.2 Port F Output Data Register (PFODR) ................................................................. 228

8.15.3 Port F Input Data Register (PFPIN)...................................................................... 228

8.15.4 Pin Functions ........................................................................................................ 229

8.15.5 Port F Nch-OD control register (PFNOCR)..........................................................231

8.15.6 Pin Functions ........................................................................................................ 231

8.15.7 Port F Input Pull-Up MOS.................................................................................... 232

8.16 Port G.................................................................................................................................233

8.16.1 Port G Data Direction Register (PGDDR)............................................................ 233

8.16.2 Port G Output Data Register (PGODR)................................................................ 234

8.16.3 Port G Input Data Register (PGPIN)..................................................................... 234

8.16.4 Noise Canceller Enable Register (PGNCE).......................................................... 235

8.16.5 Noise Canceller Mode Control Register (PGNCMC)...........................................235

8.16.6 Noise Cancel Cycle Setting Register (PGNCCS) .................................................236

8.16.7 Pin Functions ........................................................................................................ 237

8.16.8 Port G Nch-OD control register (PGNOCR)........................................................242

8.16.9 Pin Functions ........................................................................................................ 242

8.17 Change of Peripheral Function Pins...................................................................................243

8.17.1 Port Control Register 0 (PTCNT0).......................................................................243

8.17.2 Port Control Register 1 (PTCNT1).......................................................................244

8.17.3 Port Control Register 2 (PTCNT2).......................................................................245

Section 9 8-Bit PWM Timer (PWM).................................................................247

9.1 Features.............................................................................................................................. 247

9.2 Input/Output Pi ns...............................................................................................................249

9.3 Register Descriptions......................................................................................................... 249

9.3.1 PWM Register Select (PWSL)..............................................................................250

9.3.2 PWM Data Registers 15 to 8 (PWDR15 to PWDR8)...........................................251

9.3.3 PWM Data Polarity Register B (PWDPRB)......................................................... 252

9.3.4 PWM Output Enable Register B (PWOERB).......................................................252

9.3.5 Peripheral Clock Select Register (PCSR).............................................................253

9.4 Operation...........................................................................................................................254

9.4.1 PWM Setting Example ......................................................................................... 256

9.4.2 Diagram of PWM Used as D/A Converter ........................................................... 256

9.5 Usage Notes....................................................................................................................... 257

9.5.1 Module Stop Mode Setting................................................................................... 257

Rev. 3.00 Jul. 14, 2005 Page xvii of xlviii

Section 10 14-Bit PWM Timer (PWMX) .........................................................259

10.1 Features.............................................................................................................................. 259

10.2 Input/Output Pins...............................................................................................................260

10.3 Register Descriptions......................................................................................................... 260

10.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 261

10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) ......................... 262

10.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 264

10.3.4 Peripheral Clock Select Register (PCSR).............................................................265

10.4 Bus Master Interface.......................................................................................................... 266

10.5 Operation ........................................................................................................................... 269

10.6 Usage Notes....................................................................................................................... 276

10.6.1 Module Stop Mode Setting...................................................................................276

Section 11 16-Bit Free-Running Timer (FRT)..................................................277

11.1 Features.............................................................................................................................. 277

11.2 Input/Output Pins...............................................................................................................279

11.3 Register Descriptions......................................................................................................... 279

11.3.1 Free-Running Counter (FRC) ............................................................................... 280

11.3.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 280

11.3.3 Input Capture Registers A to D (ICRA to ICRD)................................................. 280

11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) .......................... 281

11.3.5 Output Compare Register DM (OCRDM)............................................................ 281

11.3.6 Timer Interrupt Enable Register (TIER)............................................................... 282

11.3.7 Timer Control/Status Register (TCSR)................................................................. 283

11.3.8 Timer Control Register (TCR).............................................................................. 286

11.3.9 Timer Output Compare Control Register (TOCR) ............................................... 287

11.4 Operation ........................................................................................................................... 289

11.4.1 Pulse Output ......................................................................................................... 289

11.5 Operation Timing............................................................................................................... 290

11.5.1 FRC Increment Timing......................................................................................... 290

11.5.2 Output Compare Output Timing........................................................................... 291

11.5.3 FRC Clear Timing ................................................................................................ 291

11.5.4 Input Capture Input Timing .................................................................................. 292

11.5.5 Buffered Input Capture Input Timing................................................................... 293

11.5.6 Timing of Input Capture Flag (ICF) Setting ......................................................... 294

11.5.7 Timing of Output Compare Flag (OCF) setting.................................................... 295

11.5.8 Timing of FRC Overflow Flag Setting ................................................................. 295

11.5.9 Automatic Addition Timing.................................................................................. 296

11.5.10 Mask Signal Generation Timing........................................................................... 297

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11.6 Interrupt Sources................................................................................................................298

11.7 Usage Notes.......................................................................................................................299

11.7.1 Conflict between FRC Write and Clear ................................................................299

11.7.2 Conflict between FRC Write and Increment......................................................... 300

11.7.3 Conflict between OCR Write and Compare-Match..............................................301

11.7.4 Switching of Internal Clock and FRC Operation.................................................. 302

11.7.5 Module Stop Mode Setting...................................................................................304

Section 12 16-Bit Timer Pulse Unit (TPU) .......................................................305

12.1 Features..............................................................................................................................305

12.2 Input/Output Pins...............................................................................................................309

12.3 Register Descriptions......................................................................................................... 310

12.3.1 Timer Control Register (TCR).............................................................................. 311

12.3.2 Timer Mode Register (TMDR)............................................................................. 315

12.3.3 Timer I/O Control Register (TIOR)...................................................................... 317

12.3.4 Timer Interrupt Enable Register (TIER)............................................................... 326

12.3.5 Timer Status Register (TSR).................................................................................328

12.3.6 Timer Counter (TCNT).........................................................................................331

12.3.7 Timer General Register (TGR) .............................................................................331

12.3.8 Timer Start Register (TSTR) ................................................................................ 331

12.3.9 Timer Synchro Register (TSYR) .......................................................................... 332

12.4 Interface to Bus Master...................................................................................................... 333

12.4.1 16-Bit Registers .................................................................................................... 333

12.4.2 8-Bit Registers ...................................................................................................... 333

12.5 Operation ........................................................................................................................... 335

12.5.1 Basic Functions..................................................................................................... 335

12.5.2 Synchronous Operation.........................................................................................341

12.5.3 Buffer Operation...................................................................................................343

12.5.4 PWM Modes.........................................................................................................347

12.5.5 Phase Counting Mode........................................................................................... 352

12.6 Interrupts............................................................................................................................357

12.6.1 Interrupt Source and Priority ................................................................................ 357

12.6.2 DTC Activation..................................................................................................... 359

12.6.3 A/D Converter Activation..................................................................................... 359

12.7 Operation Timing............................................................................................................... 360

12.7.1 Input/Output Timing.............................................................................................360

12.7.2 Interrupt Signal Timing......................................................................................... 364

12.8 Usage Notes.......................................................................................................................368

12.8.1 Input Clock Restrictions .......................................................................................368

12.8.2 Caution on Period Setting .....................................................................................368

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12.8.3 Conflict between TCNT Write and Clear Operations........................................... 369

12.8.4 Conflict between TCNT Write and Increment Operations ................................... 369

12.8.5 Conflict between TGR Write and Compare Match............................................... 370

12.8.6 Conflict between Buffer Register Write and Compare Match.............................. 371

12.8.7 Conflict between TGR Read and Input Capture...................................................372

12.8.8 Conflict between TGR Write and Input Capture .................................................. 373

12.8.9 Conflict between Buffer Register Write and Input Capture.................................. 374

12.8.10 Conflict between Overflow/Underflow and Counter Clearing.............................375

12.8.11 Conflict between TCNT Write and Overflow/Underflow .................................... 376

12.8.12 Multiplexing of I/O Pins....................................................................................... 376

12.8.13 Module Stop Mode Setting................................................................................... 376

Section 13 8-Bit Timer (TMR)..........................................................................377

13.1 Features.............................................................................................................................. 377

13.2 Input/Output Pins...............................................................................................................381

13.3 Register Descriptions......................................................................................................... 382

13.3.1 Timer Counter (TCNT)......................................................................................... 383

13.3.2 Time Constant Register A (TCORA) ................................................................... 383

13.3.3 Time Constant Register B (TCORB).................................................................... 384

13.3.4 Timer Control Register (TCR).............................................................................. 384

13.3.5 Timer Control/Status Register (TCSR)................................................................. 389

13.3.6 Time Constant Register C (TCORC).................................................................... 394

13.3.7 Input Capture Registers R and F (TICRR and TICRF)......................................... 394

13.3.8 Timer Input Select Register (TISR)...................................................................... 395

13.3.9 Timer Connection Register I (TCONRI)..............................................................395

13.3.10 Timer Connection Register S (TCONRS) ............................................................ 396

13.3.11 Timer XY Control Register (TCRXY).................................................................396

13.4 Operation ........................................................................................................................... 397

13.4.1 Pulse Output ......................................................................................................... 397

13.5 Operation Timing............................................................................................................... 398

13.5.1 TCNT Count Timing ............................................................................................ 398

13.5.2 Timing of CMFA and CMFB Setting at Compare-Match.................................... 399

13.5.3 Timing of Timer Output at Compare-Match......................................................... 399

13.5.4 Timing of Counter Clear at Compare-Match........................................................ 400

13.5.5 TCNT External Reset Timing............................................................................... 400

13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 401

13.6 TMR_0 and TMR_1 Cascaded Connection....................................................................... 402

13.6.1 16-Bit Count Mode...............................................................................................402

13.6.2 Compare-Match Count Mode ............................................................................... 402

13.7 TMR_Y and TMR_X Cascaded Connection..................................................................... 403

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13.7.1 16-Bit Count Mode ...............................................................................................403

13.7.2 Compare-Match Count Mode ............................................................................... 403

13.7.3 Input Capture Operation .......................................................................................404

13.8 Interrupt Sources................................................................................................................406

13.9 Usage Notes.......................................................................................................................407

13.9.1 Conflict between TCNT Write and Counter Clear................................................ 407

13.9.2 Conflict between TCNT Write and Count-Up......................................................408

13.9.3 Conflict between TCOR Write and Compare-Match............................................ 409

13.9.4 Conflict between Compare-Matches A and B ......................................................410

13.9.5 Switching of Internal Clocks and TCNT Operation.............................................. 410

13.9.6 Mode Setting with Cascaded Connection .............................................................412

13.9.7 Module Stop Mode Setting...................................................................................412

Section 14 Watchdog Timer (WDT)..................................................................413

14.1 Features..............................................................................................................................413

14.2 Input/Output Pins...............................................................................................................415

14.3 Register Descriptions......................................................................................................... 415

14.3.1 Timer Counter (TCNT).........................................................................................415

14.3.2 Timer Control/Status Register (TCSR)................................................................. 416

14.4 Operation ........................................................................................................................... 420

14.4.1 Watchdog Timer Mode.........................................................................................420

14.4.2 Interval Timer Mode............................................................................................. 421

14.4.3 RESO Signal Output Timing ................................................................................ 422

14.5 Interrupt Sources................................................................................................................423

14.6 Usage Notes.......................................................................................................................424

14.6.1 Notes on Register Access...................................................................................... 424

14.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 425

14.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 426

14.6.4 Changing Value of PSS Bit................................................................................... 426

14.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode.................426

14.6.6 System Reset by RESO Signal ............................................................................. 426

Section 15 Serial Communication Interface (SCI, IrDA)..................................427

15.1 Features..............................................................................................................................427

15.2 Input/Output Pins...............................................................................................................430

15.3 Register Descriptions......................................................................................................... 431

15.3.1 Receive Shift Register (RSR) ............................................................................... 431

15.3.2 Receive Data Register (RDR)............................................................................... 431

15.3.3 Transmit Data Register (TDR).............................................................................. 432

15.3.4 Transmit Shift Register (TSR)..............................................................................432

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15.3.5 Serial Mode Register (SMR) ................................................................................ 432

15.3.6 Serial Control Register (SCR) .............................................................................. 436

15.3.7 Serial Status Register (SSR) ................................................................................. 439

15.3.8 Smart Card Mode Register (SCMR)..................................................................... 444

15.3.9 Bit Rate Register (BRR) ....................................................................................... 445

15.3.10 Keyboard Comparator Control Register (KBCOMP)........................................... 453

15.4 Operation in Asynchronous Mode..................................................................................... 455

15.4.1 Data Transfer Format............................................................................................ 455

15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous

Mode..................................................................................................................... 457

15.4.3 Clock..................................................................................................................... 458

15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 459

15.4.5 Serial Data Transmission (Asynchronous Mode).................................................460

15.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 462

15.5 Multiprocessor Communication Function..........................................................................466

15.5.1 Multiprocessor Serial Data Transmission.............................................................468

15.5.2 Multiprocessor Serial Data Reception .................................................................. 469

15.6 Operation in Clocked Synchronous Mode......................................................................... 472

15.6.1 Clock..................................................................................................................... 472

15.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 473

15.6.3 Serial Data Transmission (Clocked Synchronous Mode).....................................474

15.6.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 477

15.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode)..............................................................................479

15.7 Smart Card Interface Description ...................................................................................... 481

15.7.1 Sample Connection............................................................................................... 481

15.7.2 Data Format (Except in Block Transfer Mode) .................................................... 481

15.7.3 Block Transfer Mode............................................................................................ 483

15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 483

15.7.5 Initialization..........................................................................................................484

15.7.6 Serial Data Transmission (Except in Block Transfer Mode)................................ 485

15.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 488

15.7.8 Clock Output Control............................................................................................ 490

15.8 IrDA Operation..................................................................................................................492

15.9 Interrupt Sources................................................................................................................ 496

15.9.1 Interrupts in Normal Serial Communication Interface Mode ............................... 496

15.9.2 Interrupts in Smart Card Interface Mode..............................................................497

15.10 Usage Notes ....................................................................................................................... 498

15.10.1 Module Stop Mode Setting................................................................................... 498

15.10.2 Break Detection and Processing...........................................................................498

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15.10.3 Mark State and Break Sending..............................................................................498

15.10.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) .....................................................................498

15.10.5 Relation between Writing to TDR and TDRE Flag.............................................. 498

15.10.6 Restrictions on Using DTC................................................................................... 499

15.10.7 SCI Operations during Mode Transitions............................................................. 499

15.10.8 Notes on Switching from SCK Pins to Port Pins.................................................. 503

Section 16 I2C Bus Interface (IIC).....................................................................505

16.1 Features..............................................................................................................................505

16.2 Input/Output Pins...............................................................................................................509

16.3 Register Descriptions......................................................................................................... 510

16.3.1 I2C Bus Data Register (ICDR)..............................................................................510

16.3.2 Slave Address Register (SAR).............................................................................. 511

16.3.3 Second Slave Address Register (SARX) .............................................................. 512

16.3.4 I2C Bus Mode Register (ICMR)............................................................................ 514

16.3.5 I2C Bus Control Register (ICCR).......................................................................... 517

16.3.6 I2C Bus Status Register (ICSR)............................................................................. 526

16.3.7 DDC Switch Register (DDCSWR).......................................................................530

16.3.8 I2C Bus Extended Control Register (ICXR)..........................................................531

16.4 Operation ........................................................................................................................... 535

16.4.1 I2C Bus Data Format............................................................................................. 535

16.4.2 Initialization..........................................................................................................537

16.4.3 Master Transmit Operation...................................................................................537

16.4.4 Master Receive Operation..................................................................................... 541

16.4.5 Slave Receive Operation....................................................................................... 551

16.4.6 Slave Transmit Operation ..................................................................................... 559

16.4.7 IRIC Setting Timing and SCL Control .................................................................562

16.4.8 Operation by Using DTC......................................................................................565

16.4.9 Noise Canceller..................................................................................................... 567

16.4.10 Initialization of Internal State ...............................................................................568

16.5 Interrupt Sources................................................................................................................569

16.6 Usage Notes.......................................................................................................................570

16.6.1 Module Stop Mode Setting...................................................................................580

Section 17 Keyboard Buffer Control Unit (KBU).............................................581

17.1 Features..............................................................................................................................581

17.2 Input/Output Pins...............................................................................................................584

17.3 Register Descriptions......................................................................................................... 585

17.3.1 Keyboard Control Register 1 (KBCR1)................................................................ 585

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17.3.2 Keyboard Buffer Control Register 2 (KBCR2) .................................................... 587

17.3.3 Keyboard Control Register H (KBCRH)..............................................................588

17.3.4 Keyboard Control Register L (KBCRL)............................................................... 590

17.3.5 Keyboard Data Buffer Register (KBBR)..............................................................592

17.3.6 Keyboard Buffer Transmit Data Register (KBTR)............................................... 592

17.4 Operation ........................................................................................................................... 593

17.4.1 Receive Operation ................................................................................................ 593

17.4.2 Transmit Operation...............................................................................................595

17.4.3 Receive Abort ....................................................................................................... 597

17.4.4 KCLKI and KDI Read Timing ............................................................................. 600

17.4.5 KCLKO and KDO Write Timing ......................................................................... 601

17.4.6 KBF Setting Timing and KCLK Control.............................................................. 602

17.4.7 Receive Timing..................................................................................................... 603

17.4.8 Operation during Data Reception ......................................................................... 604

17.4.9 KCLK Fall Interrupt Operation ............................................................................ 605

17.4.10 First KCLK Falling Interrupt................................................................................ 606

17.5 Usage Notes....................................................................................................................... 611

17.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................. 611

17.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission.................... 612

17.5.3 Module Stop Mode Setting...................................................................................612

17.5.4 Medium Speed Mode............................................................................................ 612

17.5.5 Transmit Completion Flag (KBTE)......................................................................612

Section 18 LPC Interface (LPC)........................................................................613

18.1 Features.............................................................................................................................. 613

18.2 Input/Output Pins...............................................................................................................616

18.3 Register Descriptions......................................................................................................... 617

18.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 619

18.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 625

18.3.3 Host Interface Control Register 4 (HICR4).......................................................... 628

18.3.4 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 629

18.3.5 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 631

18.3.6 Input Data Registers 1 to 4 (IDR1 to IDR4) ......................................................... 632

18.3.7 Output Data Registers 1 to 4 (ODR1 to ODR4) ................................................... 633

18.3.8 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 633

18.3.9 Status Registers 1 to 4 (STR1 to STR4) ............................................................... 634

18.3.10 SERIRQ Control Register 0 (SIRQCR0).............................................................. 640

18.3.11 SERIRQ Control Register 1 (SIRQCR1).............................................................. 644

18.3.12 SERIRQ Control Register 2 (SIRQCR2).............................................................. 649

18.3.13 Host Interface Select Register (HISEL)................................................................ 653

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18.3.14 RAM Buffer Address Register (RBUFAR).......................................................... 654

18.3.15 Flash Memory Programming Address Registers H and L

(FLWARH and FLARL).......................................................................................655

18.3.16 Manufacture ID Code Register (LMCMIDCR) and Device ID Code Register

(LMCDIDCR)....................................................................................................... 656

18.3.17 Erase Block Register (EBLKR)............................................................................ 657

18.3.18 LMC Status Registers 1 and 2 (LMCST1 and LMCST2)..................................... 658

18.3.19 LMC Control Registers 1 and 2 (LMCCR1 and LMCCR2)................................. 662

18.3.20 Host Base Address Registers 1H and 1L (HBAR1H and HBAR1L)....................665

18.3.21 Host Base Address Registers 2H and 2L (HBAR2H and HBAR2L)....................666

18.3.22 On-Chip RAM Host Base Address Registers H and L

(RAMBARH and RAMBARL)............................................................................667

18.3.23 Address Space Set Register (ASSR)..................................................................... 668

18.3.24 On-Chip RAM Address Space Set Register (RAMASSR)................................... 669

18.3.25 Slave Address Register 1 (SAR1).........................................................................670

18.3.26 Slave Address Register 2 (SAR2).........................................................................671

18.3.27 On-Chip RAM Slave Address Register (RAMAR).............................................. 671

18.3.28 Flash Memory Write Protect Registers H, M, and L

(FWPRH, FWPRM, and FWPRL)........................................................................672

18.3.29 Flash Memory Read Protect Registers H, M, and L

(FRPRH, FRPRM, and FRPRL)...........................................................................674

18.3.30 On-Chip RAM Protect Control Register (MPCR)................................................ 676

18.3.31 User Command Register (UCMDTR)..................................................................676

18.4 Operation ........................................................................................................................... 677

18.4.1 LPC interface Activation ...................................................................................... 677

18.4.2 LPC I/O Cycles..................................................................................................... 677

18.4.3 Gate A20...............................................................................................................680

18.4.4 LPC Interface Shutdown Function (LPCPD)........................................................683

18.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) ..................................... 687

18.4.6 LPC Interface Clock Start Request.......................................................................689

18.4.7 LPC/FW Memory Cycle.......................................................................................689

18.4.8 LPC/FW Memory Access Command ................................................................... 692

18.4.9 Flash Memory Address Translation (Host → Slave)............................................ 700

18.4.10 On-Chip RAM Address Translation (Host → Slave)...........................................701

18.4.11 Address Space Priority..........................................................................................702

18.4.12 Example 1 of Address Space Priority...................................................................703

18.4.13 Example 2 of Address Space Priority...................................................................704

18.4.14 Flash Memory Protection......................................................................................705

18.4.15 On-Chip RAM Protection.....................................................................................707

18.4.16 Flash Memory Programming................................................................................ 707

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18.4.17 Flash Memory Erasing.......................................................................................... 709

18.5 Interrupt Sources................................................................................................................ 710

18.5.1 IBFI1, IBFI2, IBFI3, IBFI4, LMC, LMCUI, and ERRI.......................................710

18.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 ........................ 711

18.6 Usage Note......................................................................................................................... 714

18.6.1 Data Conflict......................................................................................................... 714

18.6.2 Module Stop Mode Setting...................................................................................715

18.6.3 Operating Mode in LPC/FW Memory Write Cycle.............................................. 715

Section 19 A/D Converter.................................................................................717

19.1 Features.............................................................................................................................. 717

19.2 Input/Output Pins...............................................................................................................719

19.3 Register Descriptions......................................................................................................... 720

19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 720

19.3.2 A/D Control/Status Register (ADCSR) ................................................................ 721

19.3.3 A/D Control Register (ADCR) ............................................................................. 722

19.4 Operation ........................................................................................................................... 723

19.4.1 Single Mode.......................................................................................................... 723

19.4.2 Scan Mode ............................................................................................................ 723

19.4.3 Input Sampling and A/D Conversion Time .......................................................... 724

19.4.4 External Trigger Input Timing.............................................................................. 726

19.5 Interrupt Source................................................................................................................. 727

19.6 A/D Conversion Accuracy Definitions.............................................................................. 727

19.7 Usage Notes....................................................................................................................... 729

19.7.1 Permissible Signal Source Impedance..................................................................729

19.7.2 Influences on Absolute Accuracy.........................................................................729

19.7.3 Setting Range of Analog Power Supply and Other Pins....................................... 730

19.7.4 Notes on Board Design.........................................................................................730

19.7.5 Notes on Noise Countermeasures.........................................................................730

19.7.6 Module Stop Mode Setting...................................................................................731

Section 20 RAM................................................................................................733

Section 21 Flash Memory (0.18-µm F-ZTAT Version)....................................735

21.1 Features.............................................................................................................................. 735

21.1.1 Mode Transitions..................................................................................................737

21.1.2 Mode Comparison ................................................................................................ 738

21.1.3 Flash Memory MAT Configuration...................................................................... 739

21.1.4 Block Division......................................................................................................739

21.1.5 Programming/Erasing Interface............................................................................ 742

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21.2 Input/Output Pins...............................................................................................................744

21.3 Register Descriptions......................................................................................................... 744

21.3.1 Programming/Erasing Interface Registers ............................................................ 746

21.3.2 Programming/Erasing Interface Parameters ......................................................... 753

21.4 On-Board Programming.....................................................................................................764

21.4.1 Boot Mode ............................................................................................................ 764

21.4.2 User Program Mode.............................................................................................. 768

21.4.3 User Boot Mode.................................................................................................... 779

21.4.4 Storable Areas for Procedure Program and Program Data ................................... 783

21.5 Protection........................................................................................................................... 791

21.5.1 Hardware Protection ............................................................................................. 791

21.5.2 Software Protection............................................................................................... 793

21.5.3 Error Protection..................................................................................................... 793

21.6 Switching between User MAT and User Boot MAT.........................................................795

21.7 Programmer Mode.............................................................................................................796

21.8 Serial Communication Interface Specifications for Boot Mode........................................797

21.9 Usage Notes.......................................................................................................................824

Section 22 Boundary Scan (JTAG) ...................................................................827

22.1 Features..............................................................................................................................827

22.2 Input/Output Pins...............................................................................................................829

22.3 Register Descriptions......................................................................................................... 830

22.3.1 Instruction Register (SDIR)..................................................................................830

22.3.2 Bypass Register (SDBPR) .................................................................................... 832

22.3.3 Boundary Scan Register (SDBSR) ....................................................................... 832

22.3.4 ID Code Register (SDIDR)................................................................................... 842

22.4 Operation ........................................................................................................................... 842

22.4.1 TAP Controller State Transitions..........................................................................842

22.4.2 JTAG Reset........................................................................................................... 843

22.5 Boundary Scan...................................................................................................................844

22.5.1 Supported Instructions ..........................................................................................844

22.5.2 Notes.....................................................................................................................846

22.6 Usage Notes.......................................................................................................................846

Section 23 Clock Pulse Generator .....................................................................849

23.1 Oscillator............................................................................................................................ 850

23.1.1 Connecting Crystal Resonator ..............................................................................850

23.1.2 External Clock Input Method................................................................................ 851

23.2 Duty Correction Circuit .....................................................................................................854

23.3 Medium-Speed Clock Divider...........................................................................................854

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23.4 Bus Master Clock Select Circuit........................................................................................ 854

23.5 Subclock Input Circuit....................................................................................................... 855

23.6 Subclock Waveform Forming Circuit................................................................................ 856

23.7 Clock Select Circuit........................................................................................................... 856

23.8 Handling of X1 and X2 Pins.............................................................................................. 857

23.9 Usage Notes....................................................................................................................... 857

23.9.1 Notes on Resonator............................................................................................... 857

23.9.2 Notes on Board Design.........................................................................................857

Section 24 Power-Down Modes........................................................................859

24.1 Register Descriptions......................................................................................................... 860

24.1.1 Standby Control Register (SBYCR).....................................................................860

24.1.2 Low-Power Control Register (LPWRCR)............................................................ 862

24.1.3 Module Stop Control Registers H, L, and A

(MSTPCRH, MSTPCRL, MSTPCRA) ................................................................ 864

24.2 Mode Transitions and LSI States....................................................................................... 866

24.3 Medium-Speed Mode ........................................................................................................ 870

24.4 Sleep Mode........................................................................................................................871

24.5 Software Standby Mode..................................................................................................... 872

24.6 Hardware Standby Mode...................................................................................................874

24.7 Watch Mode....................................................................................................................... 875

24.8 Subsleep Mode...................................................................................................................876

24.9 Subactive Mode ................................................................................................................. 877

24.10 Module Stop Mode ............................................................................................................ 878

24.11 Direct Transitions ..............................................................................................................878

24.12 Usage Notes ....................................................................................................................... 879

24.12.1 I/O Port Status.......................................................................................................879

24.12.2 Current Consumption when Waiting for Oscillation Stabilization....................... 879

24.12.3 DTC Module Stop Mode......................................................................................879

Section 25 List of Registers...............................................................................881

25.1 Register Addresses (Address Order).................................................................................. 883

25.2 Register Bits....................................................................................................................... 897

25.3 Register States in Each Operating Mode ........................................................................... 909

25.4 Register Selection Condition ............................................................................................. 920

25.5 Register Addresses (Classification by Type of Module) ................................................... 933

Section 26 Electrical Characteristics.................................................................947

26.1 Absolute Maximum Ratings..............................................................................................947

26.2 DC Characteristics.............................................................................................................948

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26.3 AC Characteristics.............................................................................................................955

26.3.1 Clock Timing........................................................................................................956

26.3.2 Control Signal Timing .......................................................................................... 958

26.3.3 Timing of On-Chip Peripheral Modules ...............................................................959

26.3.4 A/D Conversion Characteristics ...........................................................................971

26.4 Flash Memory Characteristics ........................................................................................... 972

26.5 Usage Notes.......................................................................................................................973

Appendix .........................................................................................................975

A. I/O Port States in Each Pin State........................................................................................ 975

B. Product Lineup................................................................................................................... 976

C. Package Dimensions ..........................................................................................................977

Index .........................................................................................................979

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Figures

Section 1 Overview

Figure 1.1 H8S/2114R Group Internal Block Diagram .................................................................. 3

Figure 1.2 H8S/2114R Group Pin Arrangement (TFP-144)........................................................... 4

Figure 1.3 Sample Design of Reset Signals with no Affection Each Other.................................. 17

Section 2 CPU

Figure 2.1 Exception Vector Table (Normal Mode).....................................................................23

Figure 2.2 Stack Structure in Normal Mode................................................................................. 23

Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 24

Figure 2.4 Stack Structure in Advanced Mode............................................................................. 25

Figure 2.5 Memory Map............................................................................................................... 26

Figure 2.6 CPU Internal Registers................................................................................................27

Figure 2.7 Usage of General Registers .........................................................................................28

Figure 2.8 Stack............................................................................................................................ 29

Figure 2.9 General Register Data Formats (1).............................................................................. 32

Figure 2.9 General Register Data Formats (2).............................................................................. 33

Figure 2.10 Memory Data Formats...............................................................................................34

Figure 2.11 Instruction Formats (Examples) ................................................................................47

Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode...................... 51

Figure 2.13 State Transitions........................................................................................................ 55

Section 3 MCU Operating Modes

Figure 3.1 Address Map ...............................................................................................................68

Section 4 Exception Handling

Figure 4.1 Reset Sequence (Mode 2)............................................................................................75

Figure 4.2 Stack Status after Exception Handling........................................................................ 77

Figure 4.3 Operation when SP Value Is Odd................................................................................ 78

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 80

Figure 5.2 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts,

WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB

(H8S/2140B Group Compatible Vector Mode: EIVS = 0)..........................................95

Figure 5.3 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts,

WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB

(Extended Vector Mode: EIVS = 1)............................................................................ 96

Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0............................................................ 100

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Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0

(Example of WUE15 to WUE8)................................................................................ 101

Figure 5.6 Block Diagram of Interrupt Control Operation......................................................... 110

Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 .... 113

Figure 5.8 State Transition in Interrupt Control Mode 1 ............................................................ 114

Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 .... 116

Figure 5.10 Interrupt Exception Handling.................................................................................. 118

Figure 5.11 Interrupt Control for DTC ....................................................................................... 120

Figure 5.12 Block Diagram of Address Break Function ............................................................ 122

Figure 5.13 Examples of Address Break Timing........................................................................ 124

Figure 5.14 Conflict between Interrupt Generation and Disabling............................................. 125

Section 6 Bus Controller (BSC)

Figure 6.1 Block Diagram of BSC ............................................................................................. 129

Section 7 Data Transfer Controller (DTC)

Figure 7.1 Block Diagram of DTC............................................................................................. 136

Figure 7.2 Block Diagram of DTC Activation Source Control .................................................. 143

Figure 7.3 DTC Register Information Location in Address Space............................................. 144

Figure 7.4 DTC Operation Flowchart......................................................................................... 147

Figure 7.5 Memory Mapping in Normal Mode.......................................................................... 148

Figure 7.6 Memory Mapping in Repeat Mode ...........................................................................149

Figure 7.7 Memory Mapping in Block Transfer Mode ..............................................................150

Figure 7.8 Chain Transfer Operation.......................................................................................... 151

Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) .....................152

Figure 7.10 DTC Operation Timing

(Example of Block Transfer Mode, with Block Size of 2) ..................................... 153

Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................153

Section 8 I/O Ports

Figure 8.1 Noise Cancel Circuit .................................................................................................184

Figure 8.2 Noise Cancel Operation ............................................................................................ 184

Section 9 8-Bit PWM Timer (PWM)

Figure 9.1 Block Diagram of PWM Timer................................................................................. 248

Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) .....255

Figure 9.3 Example of PWM Setting..........................................................................................256

Figure 9.4 Example when PWM is Used as D/A Converter....................................................... 256

Section 10 14-Bit PWM Timer (PWMX)

Figure 10.1 PWMX (D/A) Block Diagram ................................................................................259

Figure 10.2 (1) DACNT Access Operation (1) [CPU → DACNT(H'AA57) Writing] .............. 267

Figure 10.2 (2) DACNT Access Operation (2) [DACNT → CPU(H'AA57) Reading]..............268

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Figure 10.3 PWMX (D/A) Operation ......................................................................................... 269

Figure 10.4 Output Waveform (OS = 0, DADR corresponds to TL) ..........................................272

Figure 10.5 Output Waveform (OS = 1, DADR corresponds to TH) ..........................................273

Figure 10.6 D/A Data Register Configuration when CFS = 1.................................................... 273

Figure 10.7 Output Waveform when DADR = H'0207 (OS = 1) ............................................... 274

Section 11 16-Bit Free-Running Timer (FRT)

Figure 11.1 Block Diagram of 16-Bit Free-Running Timer .......................................................278

Figure 11.2 Example of Pulse Output......................................................................................... 289

Figure 11.3 Increment Timing with Internal Clock Source........................................................ 290

Figure 11.4 Increment Timing with External Clock Source....................................................... 290

Figure 11.5 Timing of Output Compare A Output .....................................................................291

Figure 11.6 Clearing of FRC by Compare-Match A Signal .......................................................291

Figure 11.7 Input Capture Input Signal Timing (Usual Case).................................................... 292

Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read).......................292

Figure 11.9 Buffered Input Capture Timing ............................................................................... 293

Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) ......................................................294

Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting.................. 294

Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting................................. 295

Figure 11.13 Timing of Overflow Flag (OVF) Setting............................................................... 296

Figure 11.14 OCRA Automatic Addition Timing ......................................................................296

Figure 11.15 Timing of Input Capture Mask Signal Setting....................................................... 297

Figure 11.16 Timing of Input Capture Mask Signal Clearing .................................................... 297

Figure 11.17 Conflict between FRC Write and Clear................................................................. 299

Figure 11.18 Conflict between FRC Write and Increment .........................................................300

Figure 11.19 Conflict between OCR Write and Compare-Match

(When Automatic Addition Function is Not Used) ............................................... 301

Figure 11.20 Conflict between OCR Write and Compare-Match

(When Automatic Addition Function is Used) ...................................................... 302

Section 12 16-Bit Timer Pulse Unit (TPU)

Figure 12.1 Block Diagram of TPU............................................................................................306

Figure 12.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ......................333

Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)].................. 334

Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)].............. 334

Figure 12.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] .......334

Figure 12.6 Example of Counter Operation Setting Procedure ..................................................335

Figure 12.7 Free-Running Counter Operation............................................................................ 336

Figure 12.8 Periodic Counter Operation..................................................................................... 337

Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match.............. 337

Figure 12.10 Example of 0 Output/1 Output Operation .............................................................338

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Figure 12.11 Example of Toggle Output Operation ................................................................... 338

Figure 12.12 Example of Input Capture Operation Setting Procedure....................................... 339

Figure 12.13 Example of Input Capture Operation ....................................................................340

Figure 12.14 Example of Synchronous Operation Setting Procedure ........................................341

Figure 12.15 Example of Synchronous Operation...................................................................... 342

Figure 12.16 Compare Match Buffer Operation......................................................................... 343

Figure 12.17 Input Capture Buffer Operation............................................................................. 343

Figure 12.18 Example of Buffer Operation Setting Procedure................................................... 344

Figure 12.19 Example of Buffer Operation (1) ..........................................................................345

Figure 12.20 Example of Buffer Operation (2) ..........................................................................346

Figure 12.21 Example of PWM Mode Setting Procedure .......................................................... 348

Figure 12.22 Example of PWM Mode Operation (1)................................................................. 349

Figure 12.23 Example of PWM Mode Operation (2)................................................................. 350

Figure 12.24 Example of PWM Mode Operation (3)................................................................. 351

Figure 12.25 Example of Phase Counting Mode Setting Procedure........................................... 352

Figure 12.26 Example of Phase Counting Mode 1 Operation.................................................... 353

Figure 12.27 Example of Phase Counting Mode 2 Operation.................................................... 354

Figure 12.28 Example of Phase Counting Mode 3 Operation.................................................... 355

Figure 12.29 Example of Phase Counting Mode 4 Operation.................................................... 356

Figure 12.30 Count Timing in Internal Clock Operation............................................................360

Figure 12.31 Count Timing in External Clock Operation .......................................................... 360

Figure 12.32 Output Compare Output Timing ........................................................................... 361

Figure 12.33 Input Capture Input Signal Timing........................................................................ 361

Figure 12.34 Counter Clear Timing (Compare Match) ..............................................................362

Figure 12.35 Counter Clear Timing (Input Capture).................................................................. 362

Figure 12.36 Buffer Operation Timing (Compare Match) .........................................................363

Figure 12.37 Buffer Operation Timing (Input Capture) ............................................................. 363

Figure 12.38 TGI Interrupt Timing (Compare Match) ............................................................... 364

Figure 12.39 TGI Interrupt Timing (Input Capture)................................................................... 365

Figure 12.40 TCIV Interrupt Setting Timing.............................................................................. 366

Figure 12.41 TCIU Interrupt Setting Timing.............................................................................. 366

Figure 12.42 Timing for Status Flag Clearing by CPU ..............................................................367

Figure 12.43 Timing for Status Flag Clearing by DTC Activation ............................................367

Figure 12.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode................ 368

Figure 12.45 Conflict between TCNT Write and Clear Operations ...........................................369

Figure 12.46 Conflict between TCNT Write and Increment Operations.................................... 370

Figure 12.47 Conflict between TGR Write and Compare Match ............................................... 370

Figure 12.48 Conflict between Buffer Register Write and Compare Match .............................. 371

Figure 12.49 Conflict between TGR Read and Input Capture.................................................... 372

Figure 12.50 Conflict between TGR Write and Input Capture................................................... 373

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Figure 12.51 Conflict between Buffer Register Write and Input Capture ..................................374

Figure 12.52 Conflict between Overflow and Counter Clearing................................................ 375

Figure 12.53 Conflict between TCNT Write and Overflow .......................................................376

Section 13 8-Bit Timer (TMR)

Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 379

Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 380

Figure 13.3 Pulse Output Example............................................................................................. 397

Figure 13.4 Count Timing for Internal Clock Input....................................................................398

Figure 13.5 Count Timing for External Clock Input (Both Edges) ............................................398

Figure 13.6 Timing of CMF Setting at Compare-Match ............................................................ 399

Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal............................. 399

Figure 13.8 Timing of Counter Clear by Compare-Match .........................................................400

Figure 13.9 Timing of Counter Clear by External Reset Input................................................... 400

Figure 13.10 Timing of OVF Flag Setting..................................................................................401

Figure 13.11 Timing of Input Capture Operation....................................................................... 404

Figure 13.12 Timing of Input Capture Signal

(Input capture signal is input during TICRR and TICRF read) ............................. 405

Figure 13.13 Conflict between TCNT Write and Clear.............................................................. 407

Figure 13.14 Conflict between TCNT Write and Count-Up.......................................................408

Figure 13.15 Conflict between TCOR Write and Compare-Match............................................ 409

Section 14 Watchdog Timer (WDT)

Figure 14.1 Block Diagram of WDT.......................................................................................... 414

Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 421

Figure 14.3 Interval Timer Mode Operation............................................................................... 421

Figure 14.4 OVF Flag Set Timing .............................................................................................. 422

Figure 14.5 Output Timing of RESO signal ...............................................................................422

Figure 14.6 Writing to TCNT and TCSR (WDT_0)................................................................... 424

Figure 14.7 Conflict between TCNT Write and Increment ........................................................425

Figure 14.8 Sample Circuit for Resetting the System by the RESO Signal................................ 426

Section 15 Serial Communication Interface (SCI, IrDA)

Figure 15.1 Block Diagram of SCI............................................................................................. 429

Figure 15.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 455

Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode ........................................457

Figure 15.4 Relation between Output Clock and Transmit Data Phase

(Asynchronous Mode) ............................................................................................. 458

Figure 15.5 Sample SCI Initialization Flowchart .......................................................................459

Figure 15.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit) ....................................................460

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Figure 15.7 Sample Serial Transmission Flowchart ................................................................... 461

Figure 15.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 462

Figure 15.9 Sample Serial Reception Flowchart (1)................................................................... 464

Figure 15.9 Sample Serial Reception Flowchart (2)................................................................... 465

Figure 15.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A) .......................................... 467

Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart........................................ 468

Figure 15.12 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 469

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 470

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 471

Figure 15.14 Data Format in Synchronous Communication (LSB-First)................................... 472

Figure 15.15 Sample SCI Initialization Flowchart .....................................................................473

Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode.................. 475

Figure 15.17 Sample Serial Transmission Flowchart................................................................. 476

Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode .................... 477

Figure 15.19 Sample Serial Reception Flowchart ...................................................................... 478

Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 480

Figure 15.21 Pin Connection for Smart Card Interface.............................................................. 481

Figure 15.22 Data Formats in Normal Smart Card Interface Mode ........................................... 482

Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0) ......................................................482

Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1) .................................................... 482

Figure 15.25 Receive Data Sampling Timing in Smart Card Interface Mode

(When Clock Frequency is 372 Times the Bit Rate)............................................. 484

Figure 15.26 Data Re-transfer Operation in SCI Transmission Mode........................................ 486

Figure 15.27 TEND Flag Set Timings during Transmission...................................................... 486

Figure 15.28 Sample Transmission Flowchart ...........................................................................487

Figure 15.29 Data Re-transfer Operation in SCI Reception Mode............................................. 488

Figure 15.30 Sample Reception Flowchart................................................................................. 489

Figure 15.31 Clock Output Fixing Timing .................................................................................490

Figure 15.32 Clock Stop and Restart Procedure......................................................................... 491

Figure 15.33 IrDA Block Diagram............................................................................................. 492

Figure 15.34 IrDA Transmission and Reception........................................................................ 493

Figure 15.35 Sample Transmission using DTC in Clocked Synchronous Mode........................ 499

Figure 15.36 Sample Flowchart for Mode Transition during Transmission............................... 500

Figure 15.37 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 501

Figure 15.38 Pin States during Transmission in Clocked Synchronous Mode

(Internal Clock) .....................................................................................................501

Figure 15.39 Sample Flowchart for Mode Transition during Reception.................................... 502

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Figure 15.40 Switching from SCK Pins to Port Pins.................................................................. 503

Figure 15.41 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins..........504

Section 16 I2C Bus Interface (IIC)

Figure 16.1 Block Diagram of I2C Bus Interface........................................................................ 507

Figure 16.2 I2C Bus Interface Connections (Example: This LSI as Master) .............................. 508

Figure 16.3 I2C Bus Data Format (I2C Bus Format)................................................................... 535

Figure 16.4 I2C Bus Data Format (Serial Format)...................................................................... 535

Figure 16.5 I2C Bus Timing........................................................................................................ 536

Figure 16.6 Sample Flowchart for IIC Initialization................................................................... 537

Figure 16.7 Sample Flowchart for Operations in Master Transmit Mode.................................. 538

Figure 16.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0).......540

Figure 16.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode

(MLS = WAIT = 0) .................................................................................................541

Figure 16.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ............. 542

Figure 16.11 Example of Operation Timing in Master Receive Mode

(MLS = WAIT = 0, HNDS = 1) ............................................................................544

Figure 16.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode

(MLS = WAIT = 0, HNDS = 1) ............................................................................544

Figure 16.13 Sample Flowchart for Operations in Master Receive Mode

(receiving multiple bytes) (WAIT = 1).................................................................. 546

Figure 16.14 Sample Flowchart for Operations in Master Receive Mode

(receiving a single byte) (WAIT = 1) ....................................................................547

Figure 16.15 Example of Master Receive Mode Operation Timing

(MLS = ACKB = 0, WAIT = 1) ............................................................................550

Figure 16.16 Example of Stop Condition Issuance Timing in Master Receive Mode

(MLS = ACKB = 0, WAIT = 1) ............................................................................550

Figure 16.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ............... 552

Figure 16.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) ...554
Figure 16.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) ...555

Figure 16.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ............... 556

Figure 16.21 Example of Slave Receive Mode Operation Timing (1)

(MLS = ACKB = 0, HNDS = 0)............................................................................ 558

Figure 16.22 Example of Slave Receive Mode Operation Timing (2)

(MLS = ACKB = 0, HNDS = 0)............................................................................ 558

Figure 16.23 Sample Flowchart for Slave Transmit Mode......................................................... 559

Figure 16.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) .........................561

Figure 16.25 IRIC Setting Timing and SCL Control (1) ............................................................ 562

Figure 16.26 IRIC Setting Timing and SCL Control (2) ............................................................ 563

Figure 16.27 IRIC Setting Timing and SCL Control (3) ............................................................ 564

Figure 16.28 Block Diagram of Noise Canceller........................................................................ 567

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Figure 16.29 Notes on Reading Master Receive Data................................................................ 573

Figure 16.30 Flowchart for Start Condition Issuance Instruction for Retransmission and

Timing................................................................................................................... 574

Figure 16.31 Stop Condition Issuance Timing ...........................................................................575

Figure 16.32 IRIC Flag Clearing Timing when WAIT = 1........................................................ 576

Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 577

Figure 16.34 TRS Bit Set Timing in Slave Mode....................................................................... 578

Figure 16.35 Diagram of Erroneous Operation when Arbitration is Lost ..................................580

Section 17 Keyboard Buffer Control Unit (KBU)

Figure 17.1 Block Diagram of KBU........................................................................................... 582

Figure 17.2 KBU Connection..................................................................................................... 583

Figure 17.3 Sample Receive Processing Flowchart.................................................................... 594

Figure 17.4 Receive Timing ....................................................................................................... 595

Figure 17.5 Sample Transmit Processing Flowchart .................................................................. 596

Figure 17.6 Transmit Timing...................................................................................................... 597

Figure 17.7 (1) Sample Receive Abort Processing Flowchart.................................................... 598

Figure 17.7 (2) Sample Receive Abort Processing Flowchart.................................................... 599

Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover)

Timing..................................................................................................................... 599

Figure 17.9 KCLKI and KDI Read Timing................................................................................ 600

Figure 17.10 KCLKO and KDO Write Timing.......................................................................... 601

Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing ..................... 602

Figure 17.12 Receive Counter and KBBR Data Load Timing ................................................... 603

Figure 17.13 Receive Timing and KCLK................................................................................... 604

Figure 17.14 Example of KCLK Input Fall Interrupt Operation ................................................ 605

Figure 17.15 Timing of First KCLK Interrupt............................................................................ 606

Figure 17.16 First KCLK Interrupt Path..................................................................................... 608

Figure 17.17 Interrupt Timing in Software Standby Mode, Watch Mode, and Subsleep Mode. 609
Figure 17.18 Internal Flag of First KCLK Falling Interrupt in Software Standby mode,

Watch mode, and Subsleep mode..........................................................................610

Figure 17.19 KBIOE Setting and KCLK Falling Edge Detection Timing .................................611

Figure 17.20 KDO Output .......................................................................................................... 612

Section 18 LPC Interface (LPC)

Figure 18.1 Block Diagram of LPC............................................................................................ 615

Figure 18.2 Typical LFRAME Timing....................................................................................... 679

Figure 18.3 Abort Mechanism.................................................................................................... 679

Figure 18.4 GA20 Output........................................................................................................... 681

Figure 18.5 Power-Down State Termination Timing .................................................................686

Figure 18.6 SERIRQ Timing...................................................................................................... 687

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Figure 18.7 Clock Start Request Timing ....................................................................................689

Figure 18.8 Example of Command Space Setting...................................................................... 692

Figure 18.9 Example of Flash Memory Address Translation ..................................................... 700

Figure 18.10 Example of On-Chip RAM Address Translation ..................................................701

Figure 18.11 Example 1 of Address Space Priority.................................................................... 703

Figure 18.12 Example 2 of Address Space Priority.................................................................... 704

Figure 18.13 Flash Memory Protection ...................................................................................... 706

Figure 18.14 Protected Address Space in On-Chip RAM ..........................................................707

Figure 18.15 Example of Programming Flash Memory .............................................................708

Figure 18.16 Example of Erasing Flash Memory....................................................................... 709

Figure 18.17 HIRQ Flowchart (Example of Channel 1)............................................................. 713

Section 19 A/D Converter

Figure 19.1 Block Diagram of A/D Converter ...........................................................................718

Figure 19.2 A/D Conversion Timing.......................................................................................... 725

Figure 19.3 External Trigger Input Timing ................................................................................726

Figure 19.4 A/D Conversion Accuracy Definitions....................................................................728

Figure 19.5 A/D Conversion Accuracy Definitions....................................................................728

Figure 19.6 Example of Analog Input Circuit ............................................................................729

Figure 19.7 Example of Analog Input Protection Circuit........................................................... 731

Figure 19.8 Analog Input Pin Equivalent Circuit .......................................................................731

Section 21 Flash Memory (0.18-µm F-ZTAT Version)

Figure 21.1 Block Diagram of Flash Memory............................................................................ 736

Figure 21.2 Mode Transition for Flash Memory ........................................................................737

Figure 21.3 Flash Memory Configuration ..................................................................................739

Figure 21.4 Block Division of User MAT (1) ............................................................................740

Figure 21.4 Block Division of User MAT (2) ............................................................................741

Figure 21.5 Overview of User Procedure Program..................................................................... 742

Figure 21.6 System Configuration in Boot Mode....................................................................... 765

Figure 21.7 Automatic-Bit-Rate Adjustment Operation of SCI .................................................765

Figure 21.8 Overview of Boot Mode State Transition Diagram................................................. 767

Figure 21.9 Programming/Erasing Overview Flow.................................................................... 768

Figure 21.10 RAM Map when Programming/Erasing is Executed ............................................769

Figure 21.11 Programming Procedure........................................................................................ 770

Figure 21.12 Erasing Procedure..................................................................................................776

Figure 21.13 Repeating Procedure of Erasing and Programming............................................... 778

Figure 21.14 Procedure for Programming User MAT in User Boot Mode ................................780

Figure 21.15 Procedure for Erasing User MAT in User Boot Mode.......................................... 782

Figure 21.16 Transitions to Error-Protection State..................................................................... 794

Figure 21.17 Switching between User MAT and User Boot MAT ............................................795

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Figure 21.18 Memory Map in Programmer Mode......................................................................796

Figure 21.19 Boot Program States..............................................................................................798

Figure 21.20 Bit-Rate-Adjustment Sequence ............................................................................. 799

Figure 21.21 Communication Protocol Format.......................................................................... 800

Figure 21.22 Sequence of New Bit Rate Selection..................................................................... 811

Figure 21.23 Programming Sequence......................................................................................... 814

Figure 21.24 Erasure Sequence .................................................................................................. 818

Section 22 Boundary Scan (JTAG)

Figure 22.1 JTAG Block Diagram..............................................................................................828

Figure 22.2 TAP Controller State Transitions............................................................................ 843

Figure 22.3 Reset Signal Circuit without Reset Signal Interference .......................................... 847

Figure 22.4 Serial Data Input/Output (1).................................................................................... 848

Figure 22.5 Serial Data Input/Output (2).................................................................................... 848

Section 23 Clock Pulse Generator

Figure 23.1 Block Diagram of Clock Pulse Generator ............................................................... 849

Figure 23.2 Typical Connection to Crystal Resonator................................................................850

Figure 23.3 Equivalent Circuit of Crystal Resonator..................................................................850

Figure 23.4 Example of External Clock Input............................................................................ 851

Figure 23.5 External Clock Input Timing................................................................................... 852

Figure 23.6 Timing of External Clock Output Stabilization Delay Time................................... 853

Figure 23.7 Subclock Input from EXCL Pin and ExEXCL Pin .................................................855

Figure 23.8 Subclock Input Timing............................................................................................ 856

Figure 23.9 Handling of X1 and X2 Pins ...................................................................................857

Figure 23.10 Note on Board Design of Oscillator Section .........................................................857

Section 24 Power-Down Modes

Figure 24.1 Mode Transition Diagram ....................................................................................... 867

Figure 24.2 Medium-Speed Mode Timing .................................................................................871

Figure 24.3 Software Standby Mode Application Example .......................................................873

Figure 24.4 Hardware Standby Mode Timing ............................................................................ 874

Section 26 Electrical Characteristics

Figure 26.1 Darlington Transistor Drive Circuit (Example)....................................................... 954

Figure 26.2 LED Drive Circuit (Example) ................................................................................. 954

Figure 26.3 Output Load Circuit ................................................................................................ 955

Figure 26.4 System Clock Timing.............................................................................................. 956

Figure 26.5 Oscillation Stabilization Timing.............................................................................. 957

Figure 26.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 957

Figure 26.7 Reset Input Timing.................................................................................................. 958

Figure 26.8 Interrupt Input Timing............................................................................................. 959

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Figure 26.9 I/O Port Input/Output Timing.................................................................................. 961

Figure 26.10 FRT Input/Output Timing ......................................................................................961

Figure 26.11 FRT Clock Input Timing....................................................................................... 961

Figure 26.12 TPU Input/Output Timing ..................................................................................... 962

Figure 26.13 TPU Clock Input Timing....................................................................................... 962

Figure 26.14 8-Bit Timer Output Timing ................................................................................... 962

Figure 26.15 8-Bit Timer Clock Input Timing ...........................................................................962

Figure 26.16 8-Bit Timer Reset Input Timing............................................................................ 963

Figure 26.17 PWM, PWMX Output Timing ..............................................................................963

Figure 26.18 SCK Clock Input Timing.......................................................................................963

Figure 26.19 SCI Input/Output Timing (Clock Synchronous Mode) .........................................963

Figure 26.20 A/D Converter External Trigger Input Timing......................................................964

Figure 26.21 WDT Output Timing (RESO) ...............................................................................964

Figure 26.22 Keyboard Buffer Control Unit Timing.................................................................. 965

Figure 26.23 I2C Bus Interface Input/Output Timing................................................................. 967

Figure 26.24 LPC Interface Timing............................................................................................ 968

Figure 26.25 Test Conditions for Tester..................................................................................... 968

Figure 26.26 JTAG ETCK Timing............................................................................................. 969

Figure 26.27 Reset Hold Timing ................................................................................................970

Figure 26.28 JTAG Input/Output Timing................................................................................... 970

Figure 26.29 Connection of VCL Capacitor............................................................................... 973

Appendix

Figure C.1 Package Dimensions (TFP-144) ...............................................................................977

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Tables

Section 1 Overview

Table 1.1

Table 1.2 Pin Functions ..........................................................................................................10

Section 2 CPU

Table 2.1

Table 2.2 Operation Notation .................................................................................................36

Table 2.3 Data Transfer Instructions.......................................................................................37

Table 2.4 Arithmetic Operations Instructions (1) ...................................................................38

Table 2.4 Arithmetic Operations Instructions (2) ...................................................................39

Table 2.5 Logic Operations Instructions................................................................................. 40

Table 2.6 Shift Instructions.....................................................................................................41

Table 2.7 Bit Manipulation Instructions (1)............................................................................ 42

Table 2.7 Bit Manipulation Instructions (2)............................................................................ 43

Table 2.8 Branch Instructions................................................................................................. 44

Table 2.9 System Control Instructions.................................................................................... 45

Table 2.10 Block Data Transfer Instructions............................................................................ 46

Table 2.11 Addressing Modes ..................................................................................................48

Table 2.12 Absolute Address Access Ranges ........................................................................... 50

Table 2.13 Effective Address Calculation (1)........................................................................... 52

Table 2.13 Effective Address Calculation (2)........................................................................... 53

H8S/2114R Group Pin Arrangement in Each Operating Mode................................ 5

Instruction Classification........................................................................................ 35

Section 3 MCU Operating Modes

Table 3.1

Section 4 Exception Handling

Table 4.1
Table 4.2 Exception Handling Vector Table

Table 4.3 Exception Handling Vector Table (Extended Vector Mode).................................. 72

Table 4.4 Status of CCR after Trap Instruction Exception Handling .....................................76

Section 5 Interrupt Controller

Table 5.1
Table 5.2 Correspondence between Interrupt Source and ICR

Table 5.3 Correspondence between Interrupt Source and ICR

MCU Operating Mode Selection ............................................................................ 59

Exception Types and Priority..................................................................................69

(H8S/2140B Group Compatible Vector Mode) ...................................................... 70

Pin Configuration....................................................................................................81

(H8S/2140B Group Compatible Vector Mode: EIVS = 0)..................................... 83

(Extended Vector Mode: EIVS = 1) .......................................................................84

Rev. 3.00 Jul. 14, 2005 Page xliii of xlviii

Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities

(H8S/2140B Group Compatible Vector Mode).................................................... 103

Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities

(Extended Vector Mode) ......................................................................................106

Table 5.6 Interrupt Control Modes ....................................................................................... 109

Table 5.7 Interrupts Selected in Each Interrupt Control Mode............................................. 111

Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode.......... 112

Table 5.9 Interrupt Response Times ..................................................................................... 119

Table 5.10 Interrupt Source Selection and Clearing Control.................................................. 121

Section 7 Data Transfer Controller (DTC)

Table 7.1

Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 145

Table 7.3 Register Functions in Normal Mode..................................................................... 148

Table 7.4 Register Functions in Repeat Mode...................................................................... 149

Table 7.5 Register Functions in Block Transfer Mode......................................................... 150

Table 7.6 DTC Execution Status ..........................................................................................154

Table 7.7 Number of States Required for Each Execution Status ........................................ 154

Section 8 I/O Ports

Table 8.1

Table 8.2 Port 1 Input Pull-Up MOS States.......................................................................... 166

Table 8.3 Port 2 Input Pull-Up MOS States.......................................................................... 170

Table 8.4 Port 3 Input Pull-Up MOS States.......................................................................... 173

Table 8.5 Port 6 Input Pull-Up MOS States.......................................................................... 188

Table 8.6 Port 9 Input Pull-Up MOS States.......................................................................... 200

Table 8.7 Port B Input Pull-Up MOS States......................................................................... 208

Table 8.8 Port C Input Pull-Up MOS States......................................................................... 216

Table 8.9 Port D Input Pull-Up MOS States......................................................................... 224

Table 8.10 Port E Input Pull-Up MOS States......................................................................... 226

Table 8.11 Port F Input Pull-Up MOS States .........................................................................232

Correspondence between Interrupt Sources and DTCER..................................... 141

Port Functions....................................................................................................... 159

Section 9 8-Bit PWM Timer (PWM)

Table 9.1

Table 9.2 Internal Clock Selection........................................................................................ 251

Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20

Table 9.4 Duty Cycle of Basic Pulse .................................................................................... 254

Table 9.5 Position of Pulses Added to Basic Pulses ............................................................. 255

Rev. 3.00 Jul. 14, 2005 Page xliv of xlviii

Pin Configuration..................................................................................................249

MHz...................................................................................................................... 251

Section 10 14-Bit PWM Timer (PWMX)

Table 10.1

Table 10.2 Clock Select of PWMX ........................................................................................265

Table 10.3 Reading/Writing to 16-bit Registers .....................................................................267

Table 10.4 Settings and Operation (Examples when φ = 20 MHz)......................................... 270

Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)................ 275

Section 11 16-Bit Free-Running Timer (FRT)

Table 11.1

Table 11.2 FRT Interrupt Sources ..........................................................................................298

Table 11.3 Switching of Internal Clock and FRC Operation.................................................. 303

Section 12 16-Bit Timer Pulse Unit (TPU)

Table 12.1 TPU Functions...................................................................................................... 307

Table 12.2 Pin Configuration.................................................................................................. 309

Table 12.3 CCLR2 to CCLR0 (channel 0) .............................................................................312

Table 12.4 CCLR2 to CCLR0 (channels 1 and 2) ..................................................................312

Table 12.5 TPSC2 to TPSC0 (channel 0) ...............................................................................313

Table 12.6 TPSC2 to TPSC0 (channel 1) ...............................................................................313

Table 12.7 TPSC2 to TPSC0 (channel 2) ...............................................................................314

Table 12.8 MD3 to MD0 ........................................................................................................316

Table 12.9 TIORH_0 (channel 0) ........................................................................................... 318

Table 12.10 TIORH_0 (channel 0) .......................................................................................319

Table 12.11 TIORL_0 (channel 0)........................................................................................ 320

Table 12.12 TIORL_0 (channel 0)........................................................................................ 321

Table 12.13 TIOR_1 (channel 1) .......................................................................................... 322

Table 12.14 TIOR_1 (channel 1) .......................................................................................... 323

Table 12.15 TIOR_2 (channel 2) .......................................................................................... 324

Table 12.16 TIOR_2 (channel 2) .......................................................................................... 325

Table 12.17 Register Combinations in Buffer Operation .....................................................343

Table 12.18 PWM Output Registers and Output Pins ..........................................................348

Table 12.19 Phase Counting Mode Clock Input Pins ...........................................................352

Table 12.20 Up/Down-Count Conditions in Phase Counting Mode 1.................................. 353

Table 12.21 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 354

Table 12.22 Up/Down-Count Conditions in Phase Counting Mode 3.................................. 355

Table 12.23 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 356

Table 12.24 TPU Interrupts ..................................................................................................358

Pin Configuration.................................................................................................. 260

Pin Configuration.................................................................................................. 279

Section 13 8-Bit Timer (TMR)

Table 13.1

Table 13.2 Clock Input to TCNT and Count Condition (1).................................................... 386

Pin Configuration.................................................................................................. 381

Rev. 3.00 Jul. 14, 2005 Page xlv of xlviii

Table 13.2 Clock Input to TCNT and Count Condition (2).................................................... 387

Table 13.3 Registers Accessible by TMR_X/TMR_Y ...........................................................396

Table 13.4 Input Capture Signal Selection ............................................................................. 405

Table 13.5 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 406

Table 13.6 Timer Output Priorities......................................................................................... 410

Table 13.7 Switching of Internal Clocks and TCNT Operation ............................................. 411

Section 14 Watchdog Timer (WDT)

Table 14.1

Table 14.2 WDT Interrupt Source .......................................................................................... 423

Section 15 Serial Communication Interface (SCI, IrDA)

Table 15.1

Table 15.2 Relationships between N Setting in BRR and Bit Rate B..................................... 445

Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 446

Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 448

Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................450

Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................450

Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 451

Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 452

Table 15.8 BRR Settings for Various Bit Rates

Table 15.9 Maximum Bit Rate for Each Frequency

Table 15.10 Serial Transfer Formats (Asynchronous Mode)................................................ 456

Table 15.11 SSR Status Flags and Receive Data Handling.................................................. 463

Table 15.12 IrCKS2 to IrCKS0 Bit Settings......................................................................... 495

Table 15.13 SCI Interrupt Sources........................................................................................ 496

Table 15.14 SCI Interrupt Sources........................................................................................ 497

Pin Configuration.................................................................................................. 415

Pin Configuration.................................................................................................. 430

(Smart Card Interface Mode, n = 0, s = 372)........................................................ 452

(Smart Card Interface Mode, S = 372).................................................................. 452

Section 16 I2C Bus Interface (IIC)

Table 16.1

Table 16.2 Communication Format........................................................................................ 513

Table 16.3 I2C Transfer Rate .................................................................................................. 516

Table 16.4 Flags and Transfer States (Master Mode)............................................................. 522

Table 16.5 Flags and Transfer States (Slave Mode)............................................................... 524

Table 16.6 I2C Bus Data Format Symbols.............................................................................. 536

Table 16.7 Operation by Using DTC...................................................................................... 566

Table 16.8 IIC Interrupt Sources ............................................................................................569

Table 16.9 I2C Bus Timing (SCL and SDA Outputs)............................................................. 570

Table 16.10 Permissible SCL Rise Time (tsr) Values ...........................................................571

Table 16.11 I2C Bus Timing (with Maximum Influence of tSr/tSf)........................................ 572

Rev. 3.00 Jul. 14, 2005 Page xlvi of xlviii

Pin Configuration.................................................................................................. 509

Section 17 Keyboard Buffer Control Unit (KBU)

Table 17.1

Section 18 LPC Interface (LPC)

Table 18.1

Table 18.2 LPC I/O Cycle ......................................................................................................678

Table 18.3 GA20 (P81) Setting/Clearing Timing................................................................... 680

Table 18.4 Fast Gate A20 Output Signals............................................................................... 682

Table 18.5 Scope of LPC Interface Pin Shutdown .................................................................684

Table 18.6 Scope of Initialization in Each LPC interface Mode.............................................685

Table 18.7 Serialized Interrupt Transfer Cycle Frame Configuration ....................................688

Table 18.8 LPC Memory Cycle.............................................................................................. 690

Table 18.9 FW Memory Cycle (Byte Transfer)...................................................................... 691

Table 18.10 List of LPC/FW Memory Access Commands ..................................................693

Table 18.11 List of Factors that Prevents SYNC Field being Sent Back.............................. 697

Table 18.12 Receive Complete Interrupts and Error Interrupt.............................................. 710

Table 18.13 HIRQ Setting and Clearing Conditions.............................................................712

Table 18.14 Host Address Example...................................................................................... 715

Section 19 A/D Converter

Table 19.1

Table 19.2 Analog Input Channels and Corresponding ADDR.............................................. 720

Table 19.3 A/D Conversion Time (Single Mode)...................................................................726

Table 19.4 A/D Converter Interrupt Source............................................................................ 727

Pin Configuration.................................................................................................. 584

Pin Configuration.................................................................................................. 616

Pin Configuration.................................................................................................. 719

Section 21 Flash Memory (0.18-µm F-ZTAT Version)

Table 21.1

Table 21.2 Pin Configuration.................................................................................................. 744

Table 21.3 Register/Parameter and Target Mode ...................................................................745

Table 21.4 Parameters and Target Modes............................................................................... 754

Table 21.5 On-Board Programming Mode Setting................................................................. 764

Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI......... 766

Table 21.7 Executable MAT................................................................................................... 784

Table 21.8 (1) Usable Area for Programming in User Program Mode................................. 785

Table 21.8 (2) Usable Area for Erasure in User Program Mode ..........................................787

Table 21.8 (3) Usable Area for Programming in User Boot Mode.......................................788

Table 21.8 (4) Usable Area for Erasure in User Boot Mode ................................................790

Table 21.9 Hardware Protection .............................................................................................792

Table 21.10 Software Protection...........................................................................................793

Table 21.11 Inquiry and Selection Commands..................................................................... 801

Table 21.12 Programming/Erasing Commands .................................................................... 813

Table 21.13 Status Code....................................................................................................... 823

Comparison of Programming Modes.................................................................... 738

Rev. 3.00 Jul. 14, 2005 Page xlvii of xlviii

Table 21.14 Error Code ........................................................................................................823

Section 22 Boundary Scan (JTAG)

Table 22.1

Pin Configuration.................................................................................................. 829

Table 22.2 JTAG Register Serial Transfer..............................................................................830

Table 22.3 Correspondence between Pins and Boundary Scan Register................................ 832

Section 23 Clock Pulse Generator

Table 23.1

Damping Resistor Values ..................................................................................... 850

Table 23.2 Crystal Resonator Parameters............................................................................... 851

Table 23.3 External Clock Input Conditions ..........................................................................852

Table 23.4 External Clock Output Stabilization Delay Time .................................................853

Table 23.5 Subclock Input Conditions.................................................................................... 855

Section 24 Power-Down Modes

Table 24.1

Operating Frequency and Wait Time.................................................................... 862

Table 24.2 LSI Internal States in Each Operating Mode ........................................................868

Section 26 Electrical Characteristics

Table 26.1

Absolute Maximum Ratings ................................................................................. 947

Table 26.2 DC Characteristics (1) ..........................................................................................948

Table 26.2 DC Characteristics (2) ..........................................................................................950

Table 26.2 DC Characteristics (3) Using LPC Function.........................................................951

Table 26.3 Permissible Output Currents................................................................................. 952

Table 26.4 Bus Drive Characteristics .....................................................................................953

Table 26.5 Clock Timing........................................................................................................ 956

Table 26.6 Control Signal Timing.......................................................................................... 958

Table 26.7 Timing of On-Chip Peripheral Modules............................................................... 960

Table 26.8 KBU Bus Timing.................................................................................................. 964

Table 26.9 I2C Bus Timing..................................................................................................... 966

Table 26.10 LPC Timing ......................................................................................................967

Table 26.11 JTAG Timing.................................................................................................... 969

Table 26.12 A/D Conversion Characteristics

(AN7 to AN0 Input: 134/266-State Conversion).............................................. 971

Table 26.13 Flash Memory Characteristics ..........................................................................972

Appendix

Table A.1

I/O Port States in Each Pin State........................................................................... 975

Rev. 3.00 Jul. 14, 2005 Page xlviii of xlviii

Section 1 Overview

Section 1 Overview

1.1 Overview

• 16-bit high-speed H8S/2000 CPU
Upward-compatible with the H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions

• Various peripheral functions
Data transfer controller (DTC)
8-bit PWM timer (PWM)
14-bit PWM timer (PWMX)
16-bit timer pulse unit (TPU)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)

2

I

C bus interface (IIC)
Keyboard buffer control unit (KB U)
LPC interface (LPC)
10-bit A/D converter
Boundary scan (JTAG)
Clock pulse generator

• On-chip memory

ROM Type Model ROM RAM Remarks

Flash memory
version

• General I/O ports
I/O pins: 106
Input-only pins: 13

• Supports various power-down states

• Compact package

R4F2114R 1 Mbyte 8 kbytes Being

developed

Rev. 3.00 Jul. 14, 2005 Page 1 of 986

REJ09B0098-0300

Section 1 Overview

Package Code Body Size Pin Pitch

TQFP-144 TFP-144 16.0 × 16.0 mm 0.4 mm

Rev. 3.00 Jul. 14, 2005 Page 2 of 986

REJ09B0098-0300

1.2 Internal Block Diagram

E

Section 1 Overview

VCC
VCC
VCC

VCL
VSS
VSS
VSS
VSS
VSS

RES

XTAL

EXTAL

MD2
MD1
MD0

FWE

NMI

STBY

RESO

TRST

E

40/TMCI0/TxD2/

P

TMO0/R

41/

P

P42/ExIRQ7/

X1
X2

/IRQ2/

90

P

P97/I

P60/KIN0

61/

P

2/FTI

KIN

62/

P

P63/KIN3
P64/KIN4
P65/KIN5

6/KIN6/

IRQ

66/

P

/KIN7/

Q7

R

P67/I

xD2/

TMRI0/SCK2/SD

P

Q3

R

P84/I

P85/IRQ4/

/SCK1

P86/IRQ5

PE0/LID3

E

PE1*/

/ET

E2*

P

TDO

E

PE3*/

TM

PE4*/E

DTRG

A

IRQ1

91/

P
P92/IRQ0

R

P93/I

IRQ

P94/
P95/IRQ14

E

φ/

96/

P

S

Q15/

R

/FTCI/TMIX

1/FTOA

KIN

A/TMIY

/FTIB
/FTIC
/FTID

TO

F
TMOX

SERIRQ

D

CLKRUN

D

TMCI1

43/

P

/TMO1

44

P

TMRI1

45/

P

P46/PWX0
P47/PWX1

P

P80/

P81/GA20

LKRUN

C

82/

PCPD

L

83/

P

IrTxD

/

/TxD1

IrRxD

RxD1/

SCL1

/

TCK

Q12

XCL
DA0

DI

S

13

B

Port 4Port 6Port 9Port E

A1

ME

Port 8

AVSS

A
VrefAVCC

Clock pulse

generator

ROM

(flash memory)

RAM

Interrupt

controller

FR

16-bit

er

t tim

-bi

8

× 4 channels

I × 2 channel

SC

channel)

1

×

(IrDA

channels

IIC × 2

0-bit A/D converter

1

Boundary sca

AG)

(JT

Port 7

P7

P7

P73

P72

P76/AN6

P77/AN7

5/

4/

/

/

Ex

Ex

ExIRQ3/AN

ExIRQ2/AN2

I

I

RQ5/AN5

RQ4/AN4

3

T

n

P71/ExIRQ1/AN1

H8S/2000CPU

s

PG6/E

PG7/

P70/ExIRQ0/AN0

E

xI

xI

R

R

Q

Q

14/ExS

15/ExSCLB

DAB

Note: * Not supported by the system development tool (emulator).

Internal data bus

Internal address bus

DTC

LPC

channels

2

×

WDT

3 channels

×

KBU

t PWM

-bi

8

4-bit PWM

1

× 2 channels

channels

3

PU ×

T

Port G Port C

PC7/WUE15/DLDRQ

PC6/WUE14/LDRQ

P

P

P

PG2/ExIRQ10/

PG3/ExI

PG4/

PG5/

E

E

xI

xI

R

R

Q

Q

12

13

/

/

ExSDAA

ExSCLA

R
Q11/

E
xTM

IY

E
xTMIX

G

G

0/ExIRQ8/

1/ExIRQ9/

E

E

xTMCI0

xTMCI1

C5/

WUE13

Bus controller

P

P

P

PC1/WUE9

C4/

C3/

C2/WUE10

WUE

WUE

12

11

Data bus

PC0/WUE8

Address bus

Port F Port D Port 5 Port B Port 3 Port 1 Port 2 Port A

PA0/KIN8
PA1/KIN9
PA2/KIN10/PS2AC
PA3/KIN11/PS2AD
PA4/KIN12/PS2BC
PA5/KIN13/PS2BD
PA6/KIN14/PS2CC
PA7/KIN15/PS2CD

P20/PW8
P21/PW9
P22/PW10
P23/PW11
P24/PW12
P25/PW13
P26/PW14
P27/PW15

P10
P11
P12
P13
P14

15

P

16

P
P17

P30/LAD0
P31/LAD1
P32/LAD2
P33/LAD3

LFRAME

P34/

ET

LRES

35/

P
P36/LCLK
P37/SERIRQ

SMI

/L

E0

B0/WU

P

WUE1/LSCI

B1/

P

B2/WUE2

P
PB3/WUE3/DLFRAM
PB4/WUE4/DLAD3
PB5/WUE5/DLAD2
PB6/WUE6/DLAD1
PB7/WUE7/

P
P
P

PD0/TI
P
P
P
P
PD5/TIOCB1/TCLKC
PD6/TIOCA2
PD7/TIOCB2/TCLKD

P
PF1/IRQ9
PF2/IRQ10
PF3/IRQ11/ExTMO
PF4/ExPW12
PF5/ExPW13
PF6/ExPW14
PF7/Ex

50/ExEXCL

TMOY

51/

IRQ6/

x

E

52/

O

CA0

O

CB0

I

T

D1/

O

CC

D2/TI

OCD0/TCLKB

D3/TI
D4/TIOCA1

IRQ8

F0/

W15

P

LAD0

D

SCL0

0/TCLKA

X

Figure 1.1 H8S/2114R Group Internal Block Diagram

Rev. 3.00 Jul. 14, 2005 Page 3 of 986

REJ09B0098-0300

Section 1 Overview

1.3 Pin Description

1.3.1 Pin Arrangement

PW9

P13

P14

P15

P16

P17

106

105

4

2

3

TMO1
/

P44

P43/TMCI1

104

P45/TMRI1

5

PWX0
6/

P4

103

6

P20/PW8P21/

102

7

P47/PWX1

PB7/WUE7/DLAD0
PB6/WUE6/DLAD1
PB5/WUE5/DLAD2
PB4/WUE4/DLAD3

PB3/WUE3/DLFRAME

B1/

P

B0/

P

P34/LFRAME

P35/LRESET

P

P82/CLKRUN

IRQ3/TxD1/IrT

84/

P

/RxD1

Q4

R

P85/I

/SC

Q5

R

P86/I

P40/TMCI0/TxD2/DSERIRQ

xD2/DCLKRUN

R

MO0/

T

P41/

xIRQ7/TMRI0/

E

/

P42

Note: * Not supported by the system development tool (emulator).

P12
P11

VSS

P10

PB2/WUE2

WUE1/LSCI
WUE0/LSMI

AD0

L

30/

P

AD1

L

31/

P

32/LAD2

P

AD3

P33/L

P36/LCLK

ERIRQ

S

37/

P80/PME

G

A20

81/

P

P83/LPCPD

/IrRxD

K1/SCL1

DA1

S

CK2/

S

VSS

RESO

XTAL

EXTAL

108

107
109
110
111
112
113
114

5

11
116
117

8

11
119
120
121
122
123
124
125
126
127
128

129

30

1

31

1
132

xD

133

34

1

35

1
136
137

38

1

39

1

X1

140

X2

141
142
143
144

1

VCC

101

VSS

W10
P

22/
P

100

9

8

RES

W12
P

PW13

24/

P23/PW11

P

P25/

98

97

99

10

11

12

NMI

MD1

MD0

W14
P

26/
P

96

13

STBY

5
1

W
P
7/

P2

VSSPC0/WUE8

95

14

VCL

xIRQ6/SCL0
E

P52/

PC1/WUE9

PC2/WUE10

94

93

92

TFP-144

(Top View)

16

17

15

A0

MOY
T

51/
P

IRQ15/SD

P50/ExEXCL

97/
P

91

18

PC3/WUE11

PC4/WUE12

90

89

19

20

EXCL

IRQ14

95/
P

P96/φ/

PC5/WUE13

PC6/WUE14/LDRQ

88

21

22

Q12
IR

93/

P94/IRQ13

P

PC7/WUE15/DLDRQ

87

86

23

RQ0

P92/I

VCC

85

24

RQ1

P91/I

KIN7/TMOX

/

Q7
IR

67/

P66/IRQ6/KIN6/FTOB

P

84

26

25

MD2

P90 /IRQ2/ADTRG

/TMIY

B

C

D

I

I

I

FT

FT

FT

/

3/

5/

N

N

I

I

IN2/FTIA

IN1/FTOA

IN0/FTCI/TMIX

N6

f

K

KIN4

K

/K

63/

65/

P

P64/

P

P62/K

P61

83

82

81

80

79

27

28

29

30

31

T

TDI

FWE

E

ETRS

PE2*/

PE3*/ETDO

PE4*/ETMS

A

e

76/

P60/K

AVr

AVCC

P77/AN7

P

78

32

PE1*/ETCK

P75/ExIRQ5/AN5

77

76

75

74

73

P74/ExIRQ4/AN4

72

P73/ExIRQ3/AN3

71

P72/ExIRQ2/AN2

70
69

P71/ExIRQ1/AN1

68

P70/ExIRQ0/AN0

67

VSS

A

66

IOCA0

T

PD0/

65

O

CB0

I

T

D1/

P

64
63
62
61
60
59
58
57
56
55

54

3

5

2

5
51
50
49
48
47
46
45
44
43
42
41
40
39
38

7

3

35

33

36

34

VCC

S2BD

S2CC
/P

PE0/LID3

IN13/P

IN15/PS2CD
K

/K

A7/

PA5

P

PA6/KIN14

/TCLKA

0

PD2/TIOCC
PD3/TI
PD4/TIOCA1
PD5/
PD6/
PD7/TIOCB2/TCLKD
PG0/
PG1/ExIRQ9/ExTMCI1
PG2/
PG3/ExIRQ11/
PG4/

G5/E

P
PG6/

G7/E

P
PF

PF1/
PF2/I
PF
PF4/ExPW12
PF
PF6/ExPW14
PF

SS

V
PA0/KIN8
PA1/KIN9

A2/

P
PA3/KIN11/

A4/

P

O

CD0/

O

CB1/

I

T

O

CA2

I

T

xIRQ8/Ex

E

xIRQ10/ExTMIX

E

xIRQ12/ExSD

E

XIRQ13/ExSCLA
xIRQ14/ExSD

E

xIRQ15

Q8

R

/I

0

9

IRQ

Q10

R

ExTM

11/

3/IRQ

W13

ExP

/

5

W15

P

/Ex

7

/P

10

N

I

K

P
P

12/

N

I

K

CLKB

T

CLKC

T

MCI0

T

ExT

/ExSCLB

OX

S2AC
S2AD
S2BC

MI

Y

AA

AB

Figure 1.2 H8S/2114R Group Pin Arrangement (TFP-144)

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Section 1 Overview

1.3.2 Pin Arrangement in Each Operating Mode

Table 1.1 H8S/2114R Group Pin Arrangement in Each Operating Mode

Pin No. Pin Name

Single-Chip Mode

TFP-144

Mode 2 and Mode 3 (EXPE = 0)

1 VCC VCC

2 P43/TMCI1 NC

3 P44/TMO1 NC

4 P45/TMRI1 NC

5 P46/PWX0 NC

6 P47/PWX1 NC

7 VSS VSS
8 RES RES

9 MD1 VSS

10 MD0 VSS

11 NMI FA9
12 STBY VCC

13 VCL VCL
14 (N) P52/ExIRQ6/SCL0 FA18

15 P51/TMOY FA17

16 P50/ExEXCL FA19
17 (N) P97/IRQ15/SDA0 VCC

18 P96/φ/EXCL NC
19 P95/IRQ14 FA16
20 P94/IRQ13 FA15
21 P93/IRQ12 WE
22 P92/IRQ0 VSS
23 P91/IRQ1 VCC
24 P90/IRQ2/ADTRG VCC

25 MD2 VSS

26 FWE FWE
27 ETRST RES

Flash Memory Programmer Mode

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Section 1 Overview

Pin No. Pin Name

Single-Chip Mode

TFP-144

Mode 2 and Mode 3 (EXPE = 0)

Flash Memory Programmer Mode

28 PE4*/ETMS NC
29 PE3*/ETDO NC
30 PE2*/ETDI NC
31 PE1*/ETCK NC
32 PE0/LID3 NC
33 (N) PA7/KIN15/PS2CD NC
34 (N) PA6/KIN14/PS2CC NC
35 (N) PA5/KIN13/PS2BD NC

36 VCC VCC
37 (N) PA4/KIN12/PS2BC NC
38 (N) PA3/KIN11/PS2AD NC
39 (N) PA2/KIN10/PS2AC NC
40 (N) PA1/KIN9 NC
41 (N) PA0/KIN8 NC

42 VSS VSS

43 PF7/ExPW15 NC

44 PF6/ExPW14 NC

45 PF5/ExPW13 NC

46 PF4/ExPW12 NC
47 PF3/IRQ11/ExTMOX NC
48 PF2/IRQ10 NC
49 PF1/IRQ9 NC
50 PF0/IRQ8 NC
51 (N) PG7/ExIRQ15/ExSCLB NC
52 (N) PG6/ExIRQ14/ExSDAB NC
53 (N) PG5/ExIRQ13/ExSCLA NC
54 (N) PG4/ExIRQ12/ExSDAA NC
55 (N) PG3/ExIRQ11/ExTMIY NC
56 (N) PG2/ExIRQ10/ExTMIX NC
57 (N) PG1/ExIRQ9/ExTMCI1 NC

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Section 1 Overview

Pin No. Pin Name

Single-Chip Mode

TFP-144

Mode 2 and Mode 3 (EXPE = 0)

Flash Memory Programmer Mode

58 (N) PG0/ExIRQ8/ExTMCI0 NC

59 PD7/TIOCB2/TCLKD NC

60 PD6/TIOCA2 NC

61 PD5/TIOCB1/TCLKC NC

62 PD4/TIOCA1 NC

63 PD3/TIOCD0/TCLKB NC

64 PD2/TIOCC0/TCLKA NC

65 PD1/TIOCB0 NC

66 PD0/TIOCA0 NC

67 AVSS VSS
68 P70/ExIRQ0/AN0 NC
69 P71/ExIRQ1/AN1 NC
70 P72/ExIRQ2/AN2 NC
71 P73/ExIRQ3/AN3 NC
72 P74/ExIRQ4/AN4 NC
73 P75/ExIRQ5/AN5 NC

74 P76/AN6 NC

75 P77/AN7 NC

76 AVCC VCC

77 AVref VCC
78 P60/FTCI/KIN0/TMIX NC
79 P61/FTOA/KIN1 NC
80 P62/FTIA/KIN2/TMIY NC
81 P63/FTIB/KIN3 NC
82 P64/FTIC/KIN4 NC
83 P65/FTID/KIN5 NC
84 P66/IRQ6/FTOB/KIN6 NC
85 P67/IRQ7/TMOX/KIN7 VSS

86 VCC VCC
87 PC7/WUE15/DLDRQ NC

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Section 1 Overview

Pin No. Pin Name

Single-Chip Mode

TFP-144

Mode 2 and Mode 3 (EXPE = 0)

Flash Memory Programmer Mode

88 PC6/WUE14/LDRQ NC
89 PC5/WUE13 NC
90 PC4/WUE12 NC
91 PC3/WUE11 NC
92 PC2/WUE10 NC
93 PC1/WUE9 NC
94 PC0/WUE8 NC

95 VSS VSS
96 P27/PW15 CE

97 P26/PW14 FA14

98 P25/PW13 FA13

99 P24/PW12 FA12

100 P23/PW11 FA11

101 P22/PW10 FA10
102 P21/PW9 OE

103 P20/PW8 FA8

104 P17 FA7

105 P16 FA6

106 P15 FA5

107 P14 FA4

108 P13 FA3

109 P12 FA2

110 P11 FA1

111 VSS VSS

112 P10 FA0
113 PB7/WUE7/DLAD0 NC
114 PB6/WUE6/DLAD1 NC
115 PB5/WUE5/DLAD2 NC
116 PB4/WUE4/DLAD3 NC
117 PB3/WUE3/DLFRAME NC

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Section 1 Overview

Pin No. Pin Name

Single-Chip Mode

TFP-144

Mode 2 and Mode 3 (EXPE = 0)

Flash Memory Programmer Mode

118 PB2/WUE2 NC
119 PB1/WUE1/LSCI NC
120 PB0/WUE0/LSMI NC

121 P30/LAD0 FO0

122 P31/LAD1 FO1

123 P32/LAD2 FO2

124 P33/LAD3 FO3
125 P34/LFRAME FO4
126 P35/LRESET FO5

127 P36/LCLK FO6

128 P37/SERIRQ FO7
129 P80/PME NC

130 P81/GA20 NC
131 P82/CLKRUN NC
132 P83/LPCPD NC
133 P84/IRQ3/TxD1/IrTxD NC
134 P85/IRQ4/RxD1/IrRxD NC
135 (N) P86/IRQ5/SCK1/SCL1 NC

136 P40/TMCI0/TxD2/DSERIRQ NC
137 P41/TMO0/RxD2/DCLKRUN NC
138 (N) P42/ExIRQ7/TMRI0/SCK2/SDA1 NC

139 VSS VSS

140 X1 NC

141 X2 NC
142 RESO NC

143 XTAL XTAL

144 EXTAL EXTAL

Notes: (N) indicates the pin is driven by NMOS push-pull/open drain.
* Not supported by the system development tool (emulator).

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Section 1 Overview

1.3.3 Pin Functions

Table 1.2 Pin Functions

Type Symbol Pin No. I/O Name and Function

Power
supply

Clock

Operating
mode
control

System
control

VCC 1, 36,

86

VCL 13 Input External capacitance pin for internal step-down

VSS 7, 42,

95, 111,
139

XTAL 143 Input

EXTAL 144 Input

φ 18 Output Supplies the system clock to external devices.

EXCL 18 Input

ExEXCL 16 Input

X2
X1

MD2 MD1
MD0

141
140

25
9
10

RES 8 Input Reset pin. When this pin is low, the chip is reset.
RESO 142 Output Outputs a reset signal to an external device.
STBY 12 Input When this pin is low, a transition is made to

FWE 26 Input Control pin for use by flash memory

Input Power supply pins. Connect all these pins to the

system power supply. Connect the bypass
capacitor between VCC and VSS (near VCC).

power. Connect this pin to VSS through an
external capacitor (that is located near this pin) to
stabilize internal step-down power.

Input Ground pins. Connect all these pins to the system

power supply (0 V).

For connection to a crystal resonator. An external
clock can be supplied from the EXTAL pin. For an
example of crystal resonator connection, see
section 23, Clock Pulse Generator.

32.768-kHz external clock for sub clock should be
supplied. To which pin the external clock is input
can be selected from the EXCL and ExEXCL
pins.

Input These pins should be left open.

Input These pins set the operating mode. Inputs at

these pins should not be changed during
operation.

hardware standby mode.

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REJ09B0098-0300

Type Symbol Pin No. I/O Name and Function

Interrupts

NMI 11 Input Nonmaskable interrupt request input pin

IRQ15 to
IRQ0

17, 19,
20, 21,
47 to 50,
85, 84, 135,

Input These pins request a maskable interrupt.

To which pin an IRQ interrupt is input can be
selected from the IRQn and ExIRQn pins.

(n = 15 to 0)
134, 133,
24, 23, 22

ExIRQ15
to ExIRQ0

51
to
58
138
14
73
to
68

Boundary
scan
(JTAG)

ETRST*

ETMS 28 Input

ETDO 29 Output

ETDI 30 Input

ETCK 31 Input

2

27 Input

Interface pins for boundary scan

Reset by holding the ETRST pin to low

regardless of the JTAG activation. At this time,

the ETRST pin should be held low for 20 clocks

of ETCK. For details, see section 26, Electrical

Characteristics. Then, to activate the JTAG, the

ETRST pin should be set to high and the pins

ETCK, ETMS, and ETDI should be set

appropriately. When in the normal operation

without activating the JTAG, pins ETRST, ETCK,

ETMS, and ETDI are set to high or high-

impedance. As these pins are pulled up inside

the chip, take care during standby state.

Section 1 Overview

Rev. 3.00 Jul. 14, 2005 Page 11 of 986

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Section 1 Overview

Type Symbol Pin No. I/O Name and Function

(PWM)

14-bit PWM
timer

PW15 to
PW8

ExPW15 to
ExPW12

PWX1
PWX0

96 to 103 PWM timer

43 to 46

6
5

Output PWM timer pulse output pins.

From which pin pulses are output can be selected
from the PWn and ExPWn pins.
(n = 15 to 12)

Output PWMX pulse output pins

(PWMX)

16-bit free
running
timer (FRT)

FTCI 78 Input External event input pin

FTOA
FTOB

FTIA to

79

Output Output compare output pins

84

80 to 83 Input Input capture input pins

FTID

16-bit timer
pulse unit
(TPU)

8-bit timer
(TMR_0,
TMR_1,
TMR_X,
TMR_Y)

TCLKD
TCLKC
TCLKB
TCLKA

TIOCA0
TIOCB0
TIOCC0
TIOCD0

TIOCA1
TIOCB1

TIOCA2
TIOCB2

TMO0
TMO1
TMOX
ExTMOX
TMOY

TMCI0
TMCI1
ExTMCI0
ExTMCI1

59
61
63
64

66
65
64
63

62
61

60
59

137
3
85
47
15

136
2
58
57

Input Timer external clock input/output pins

Input/
Output

Input/
Output

Input/
Output

Input capture input/output compare output/PWM
output pins for TGRA_0 to TGRD_0

Input capture input/output compare output/PWM
output pins for TGRA_1 and TGRB_1

Input capture input/output compare output/PWM
output pins for TGRA_2 and TGRB_2

Output Waveform output pins with output compare

function.
From which pin waveforms are output can be
selected from the TMOX and ExTMOX pins.

Input Input pins for the external clock input to the

counter. To which pin the external clock is input
can be selected from the TMCIn and ExTMCIn
pins.
(n = 1 or 0)

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REJ09B0098-0300

Type Symbol Pin No. I/O Name and Function

8-bit timer
(TMR_0,
TMR_1,
TMR_X,
TMR_Y)

TMRI0
TMRI1

TMIX
TMIY
ExTMIX
ExTMIY

138
4

78
80
56
55

Input External event input pin and counter reset input

pin

Input External event input pins and counter reset input

pins. To which pin an external event or counter

reset is input can be selected from the TMIn and

ExTMIn pins.

(n = X or Y)

Serial
communi­cation
interface
(SCI_1,
SCI_2)

TxD1
TxD2

RxD1
RxD2

SCK1
SCK2

133
136

134
137

135
138

Output Transmit data output pins

Input Receive data input pins

Input/
Output

Clock input/output pins. Output type is NMOS
push-pull output.

IrTxD 133 Output Encoded data output pin for IrDA SCI with

IrDA (SCI)

I2C bus
interface
(IIC)

IrRxD 134 Input Encoded data input pin for IrDA

SCL0
SCL1
ExSCLA
ExSCLB

14
135
53
51

Input/
Output

I2C clock input/output pins. These pins can drive
a bus directly with the NMOS open drain output.
To which pin the I

2

C clock is input or output can
be selected from the SCLn, ExSCLA, and
ExSCLB pins.
(n = 1 or 0)

2

SDA0
SDA1
ExSDAA
ExSDAB

17
138
54
52

Input/
Output

C data input/output pins. These pins can drive a

I
bus directly with the NMOS open drain output. To
which pin the I

2

C data is input or output can be
selected from the SDAn, ExSDAA, and ExSDAB
pins.
(n = 1 or 0)

Keyboard
buffer
control unit

PS2AC
PS2BC
PS2CC

39
37
34

Input/
Output

Synchronous clock input/output pins for the
keyboard buffer control unit

(KBU)

PS2AD
PS2BD
PS2CD

38
35
33

Input/
Output

Data input/output pins for the keyboard buffer
control unit.

Section 1 Overview

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Section 1 Overview

Type Symbol Pin No. I/O Name and Function

Keyboard
control

KIN15 to
KIN0

33 to 35,
37 to 41,
85 to 78

Input Matrix keyboard input pins. All pins have a wake-

up function. Normally, KIN0 to KIN15 function as
key scan inputs, and P10 to P17 and P20 to P27
function as key scan outputs. Thus, composed
with a maximum of 16 outputs x 16 inputs, a 256­key matrix can be configured.

WUE15 to
WUE8

WUE7 to

87 to 94

113 to 120

Input Wake-up event input pins. Same wake up as key

wake up can be performed with various sources.

WUE0

A/D
converter

AN7 to AN0 75 to 68 Input Analog input pins
ADTRG 24 Input External trigger input pin to start A/D conversion

AVCC 76 Input Analog power supply pin. When the A/D

converter is not used, this pin should be
connected to the system power supply (+3.3 V).

AVref 77 Input Reference power supply pin for the A/D

converter. When the A/D converter is not used,
this pin should be connected to the system power
supply (+3.3 V).

AVSS 67 Input Ground pin for the A/D converter. This pin should

be connected to the system power supply (0 V).

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REJ09B0098-0300

Type Symbol Pin No. I/O Name and Function

LPC
Interface
(LPC)

LAD3 to
LAD0

LFRAME 125 Input Input pin indicating transfer cycle start and forced

124 to 121 Input/

Output

Transfer cycle type, address, and data
input/output pins

termination of an abnormal transfer cycle

LRESET 126 Input LPC reset pin. When this pin is low, a reset state

is entered.

LCLK 127 Input LPC clock input pin

SERIRQ 128 Input/

Output

LSCI

LSMI
PME

119
120
129

Input/
Output

LPC serial host interrupt (HIRQ1, SMI, HIRQ6, or
HIRQ9 to HIRQ12) input/output pin

General input/output ports of LSCI, LSMI, and
PME

GA20 130 Output GATE A20 control signal output pin
CLKRUN 131 Input/

LCLK operation start request input/output pin

Output

LPCPD 132 Input LPC module shutdown control input pin
LID3 32 Input Input pin for setting host address 31

DLAD3 to
DLAD0

116 to 113 Input/

Output

LAD input/output pins for the docking LPC

DLFRAME 117 Output LFRAME output pin for the docking LPC

DSERIRQ 136 Input/

SERIRQ input/output pin for the docking LPC

Output

DCLKRUN 137 Input/

CLKRUN input/output pin for the docking LPC

Output

LDRQ 88 Output Encoded DMA request output pin for the docking

LPC

DLDRQ 87 Input Encoded DMA request input pin for the docking

LPC

Section 1 Overview

Rev. 3.00 Jul. 14, 2005 Page 15 of 986

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Section 1 Overview

Type Symbol Pin No. I/O Name and Function

I/O ports

P17 to P10 104 to 110, 112 Input/

Eight input/output pins

Output

P27 to P20 96 to 103 Input/

Eight input/output pins

Output

P37 to P30 128 to 121 Input/

Eight input/output pins

Output

P47 to P40 6 to 2,

138 to 136

P52 to P50 14 to 16 Input/

Input/
Output

Eight input/output pins

Three input/output pins

Output

P67 to P60 85 to 78 Input/

Eight input/output pins

Output

P77 to P70 75 to 68 Input Eight input pins

P86 to P80 135 to 129 Input/

Seven input/output pins

Output

P97 to P90 17 to 24 Input/

Eight input/output pins

Output

PA7 to PA0 33 to 35,

37 to 41

PB7 to PB0 113 to 120 Input/

Input/
Output

Eight input/output pins

Eight input/output pins

Output

PC7 to PC0 87 to 94 Input/

Eight input/output pins

Output

PD7 to PD0 59 to 66 Input/

Eight input/output pins

Output

PE4 to

1

PE0*

PF7 to PF0 43 to 50 Input/

28 to 32 Input Five input pins

Eight input/output pins

Output

PG7 to PG0 51 to 58 Input/

Eight input/output pins

Output

Notes: 1. Pins PE4 to PE1 are not supported by the system development tool (emulator).

2. Following precautions are required on the power-on reset signal that is applied to the

ETRST pin.
The reset signal should be applied on power supply.
Apart the power on reset circuit from this LSI to prevent the ETRST pin of the board
tester from affecting the operation of this LSI.
Apart the power on reset circuit from this LSI to prevent the system reset of this LSI
from affecting the ETRST pin of the board tester.

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Section 1 Overview

Figure1.3 shows an example of design in which signals for reset do not affect each other.

Board edge pin

System
reset

Power On
Reset circuit

ETRST

This LSI

RES

ETRST

Figure 1.3 Sample Design of Reset Signals with no Affection Each Other

Rev. 3.00 Jul. 14, 2005 Page 17 of 986

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Section 1 Overview

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Section 2 CPU

Section 2 CPU

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16 Mbytes linear address space, and is ideal for realtime control.

This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, see section 3, MCU Operating Modes.

2.1 Features

• Upward-compatibility with H8/300 and H8/300H CPUs
 Can execute H8/300 CPU and H8/300H CPU object programs

• General-register architecture
 Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-five basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions

• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 R egi st er in di rect with displacement [@(d:16,ERn) or @( d:32,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Pr ogram-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]

• 16 Mbytes address space
 Pr og ram: 16 M byt es
 Data: 16 Mbytes

• High-speed operation
 All frequently-used instructions are executed in one or two states
 8/16/32-bit register-register add/subtract: 1 state
 8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
 16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)

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Section 2 CPU

 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)

• Two CPU operating modes
 No rmal mo de
 Advanced mode

• Power-down state
 Transition to power-down state by SLEEP instruction
 Selectable CPU clock speed

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration
The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• The number of execution states of the MULXU and MULXS instructions

Execution States
Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs, Rd 3 12

MULXU.W Rs, ERd 4 20

MULXS MULXS.B Rs, Rd 4 13

MULXS.W Rs, ERd 5 21

In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.

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Section 2 CPU

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.

• More general registers and control registers
 Eight 16-bit extended registers and one 8-bit control register have been added.

• Extended address space
 Normal mode supports the same 64 kbytes address space as the H8/300 CPU.
 Advanced mode supports a maximum 16 Mbytes address space.

• Enhanced addressing
 The addressing modes have been enhanced to make effective use of the 16 Mbytes address

space.

• Enhanced instructions
 Ad d ressi n g modes of bit - manipulation instructions have been enha nced.
 Signed multiply and divide instructions have been added.
 Two-bit shift and two-bit rotate instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.

• Higher speed
 Basic instructions are executed twice as fast.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.

• Additional control register
 One 8-bit control register has been added.

• Enhanced instructions
 Ad d ressi n g modes of bit - manipulation instructions have been enha nced.
 Two-bit shift and two-bit rotate instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.

• Higher speed
 Basic instructions are executed twice as fast.

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Section 2 CPU

2.2 CPU Operating Modes

The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64 kbytes address space. Advanced mode supports a maximum 16 Mbytes address
space. The mode is selected by the LSI's mode pins.

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU in normal
mode.

• Address space
Linear access to a maximum address space of 64 kbytes is possible.

• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers.
When extended register En is used as a 16-bit register it can contain any value, even when the

corresponding general register (Rn) is used as an address register. (If general register Rn is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post­increment (@Rn+) and a carry or borrow occurs, the value in the corresponding extended
register (En) will be affected.)

• Instruction set
All instructions and addressing modes can be used. Only the lower 16 bits of effective

addresses (EA) are valid.

• Exception vector table and memory indirect branch addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vecto r tabl e. One

branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.

• Stack structure
In normal mode, when the program counter (PC) is push ed onto the stack in a subroutine call

in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.2. The extended control register
(EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.

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Section 2 CPU

SP

H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B

Reset exception vector

(Reserved for system use)

(Reserved for system use)

Exception
vector table

Exception vector 1

Exception vector 2

Figure 2.1 Exception Vector Table (Normal Mode)

PC

(16 bits)

SP

CCR

*

CCR

PC

(16 bits)

(a) Subroutine Branch (b) Exception Handling

Note: * Ignored when returning.

Figure 2.2 Stack Structure in Normal Mode

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Section 2 CPU

2.2.2 Advanced Mode

• Address space
Linear access to a maximum address space of 16 Mbytes is possible.

• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the

upper 16-bit segments of 32-bit registers o r add ress re gi st er s.

• Instruction set
All instructions and addressing modes can be used.

• Exception vector table and memory indirect branch addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector

table in 32-bit units. In each 32 bits, the upper eight bits are ignored and a branch address is
stored in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section
4, Exception Handling.

H'00000000

H'00000003

H'00000004

H'00000007

H'00000008

H'0000000B

H'0000000C

H'00000010

Reserved

Reset exception vector

Reserved

(Reserved for system use)

Exception vector table

(Reserved for system use)

Reserved

Exception vector 1

Figure 2.3 Exception Vector Table (Advanced Mode)

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Section 2 CPU

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper eight bits of these 32 bits are a reserved area that
is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to
H'000000FF. Note that the top area of this range is also used for the exception vector table.

• Stack structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine

call, and the PC and condition-code register (CCR) are pushed onto the stack in exception
handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not
pushed onto the stack. For details, see section 4, Exception Handlin g.

SP

Reserved

PC

(24-bit)

(a) Subroutine Branch (b) Exception Handling

SP

CCR

PC

(24-bit)

Figure 2.4 Stack Structure in Advanced Mode

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Section 2 CPU

2.3 Address Space

Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64 kbytes address space in normal mode, and a maximum 16 Mbytes
(architecturally 4 Gbytes) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, see section 3, MCU Operating
Modes.

H'0000

64 kbytes 16 Mbytes

H'FFFF

Note: * Not available in this LSI.

Figure 2.5 Memory Map

H'00000000

H'00FFFFFF

H'FFFFFFFF

Program area

Data area

Not available
in this LSI

(b) Advanced Mode(a) Normal Mode*

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Section 2 CPU

2.4 Register Configuration

The H8S/2000 CPU has the internal registers shown in figure 2.6. These are classified into two
types of registers: general registers and control registers. Control registers refer to a 24-bit
program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code
register (CCR).

General Registers (Rn) and Extended Registers (En)

15 0 7 0 7 0

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

E0

E1

E2

E3

E4

E5

E6

E7

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

Control Registers

23 0

Legend

: Stack pointer

SP

: Program counter

PC

: Extended control register

EXR

: Trace bit

T

: Interrupt mask bits

I2 to I0

: Condition-code register

CCR

: Interrupt mask bit

I

: User bit or interrupt mask bit

UI

Note: * Does not affect operation in this LSI.

Figure 2.6 CPU Internal Registers

PC

H
U
N
Z
V
C

76543210

TI2I1I0

EXR*

----

76543210

CCR

IUIHUNZVC

: Half-carry flag
: User bit
: Negative flag
: Zero flag
: Overflow flag
: Carry flag

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Section 2 CPU

2.4.1 General Registers

The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general regi st er is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).

When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing sixteen 16-bit registers at the maximum. The E registers (E0 to
E7) are also referred to as extended registers.

When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing sixteen 8-bit registers at the maximum.

The usage of each register can be selected independently.

General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.

• Address registers

• 32-bit registers

ER registers

(ER0 to ER7)

• 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

R registers
(R0 to R7)

Figure 2.7 Usage of General Registers

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RH registers

(R0H to R7H)

RL registers
(R0L to R7L)

Section 2 CPU

Free area

SP (ER7)

Stack area

Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)

2.4.3 Extended Control Register (EXR)

EXR does not affect operation in this LSI.

Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

Does not affect operation in this LSI.

6 to 3 – All 1 R Reserved

These bits are always read as 1.

2 to 0 I2

I1

I0

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1

1

1

R/W

R/W

R/W

Interrupt Mask Bits 2 to 0

Do not affect operation in this LSI.

Section 2 CPU

2.4.4 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching condition s for conditional branch
(Bcc) instructions.

Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to 1
at the start of an exception-handling sequence. For details,
see section 5, Interrupt Controller.

6 UI Undefined R/W User Bit or Interrupt Mask Bit

Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.

5 H Undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if there is
a carry or borrow at bit 3, and cleared to 0 otherwise. When
the ADD.W, SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry or borrow
at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag
is set to 1 if there is a carry or borrow at bit 27, and cleared
to 0 otherwise.

4 U Undefined R/W User Bit

Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit of data as a sign
bit.

2 Z Undefined R/W Zero Flag

Set to 1 when data is zero, and cleared to 0 when data is
not zero.

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Section 2 CPU

Bit Bit Name Initial Value R/W Description

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and cleared to
0 otherwise.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0 otherwise.
Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to indicate a carry

The carry flag is also used as a bit accumulator by bit
manipulation instructions.

2.4.5 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other
CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is
undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed
immediately after a reset.

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Section 2 CPU

2.5 Data Formats

The H8S/2000 CPU can process 1-bit, 4-bit B C D, 8- bi t (byt e), 16 -bi t (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instruct i o ns treat byte dat a as two
digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data formats of general registers.

Data Type Register Number Data Image

70

1-bit data

RnH

6543271

Don't care

0

1-bit data

4-bit BCD data

4-bit BCD data

Byte data

Byte data

7

RnL

RnH

RnL

RnH

RnL

Don't care

7

Upper Lower

Don't care

7 0

MSB LSB

Don't care

65432710

04 3

Don't care

704

Upper Lower

7

MSB

Figure 2.9 General Register Data Formats (1)

3

Don't care

0

0

LSB

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Data Type Data ImageRegister Number

Section 2 CPU

Word data

Word data

15 0

MSB

Longword data

31 16

MSB

Rn

En

ERn

En Rn

Legend

ERn

: General register ER

En

: General register E

Rn

: General register R

RnH

: General register RH

RnL

: General register RL

MSB

: Most significant bit

LSB

: Least significant bit

Figure 2.9 General Register Data Formats (2)

15 0

MSB

LSB

15 0

LSB

LSB

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Section 2 CPU

2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.

When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.

Data Type Address

70

1-bit data

Byte data

Word data

Longword data Address 2N

Address L

Address L

Address 2M

Address 2M + 1

Address 2N + 1

Address 2N + 2

Address 2N + 3

76 543210

MSB

MSB

MSB

Figure 2.10 Memory Data Formats

Data Image

LSB

LSB

LSB

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Section 2 CPU

2.6 Instruction Set

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.

Table 2.1 Instruction Classification

Function Instructions Size Types

Data transfer

Arithmetic
operations

Logic operations AND, OR, XOR, NOT B/W/L 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

Branch B

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,

Block data transfer EEPMOV – 1

Notes: B: Byte size; W: Word size; L: Longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-

SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.

2. B

CC

3. Cannot be used in this LSI.

4. To use the TAS instruction, use registers ER0, ER1, ER4, and ER5.

5. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot

be used as an STM/LDM register.

MOV B/W/L
POP*1, PUSH*
LDM*5, STM*
MOVFPE*3, MOVTPE*

1

W/L

5

L

3

B

ADD, SUB, CMP, NEG B/W/L

5

19

ADDX, SUBX, DAA, DAS B

INC, DEC B/W/L

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS B/W

EXTU, EXTS W/L

4

TAS*

B

B/W/L 8

ROTXR

B 14

BIAND, BOR, BIOR, BXOR, BIXOR

2

*

, JMP, BSR, JSR, RTS – 5

CC

– 9

NOP

Total: 65

is the generic name for conditional branch instructions.

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Section 2 CPU

2.6.1 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notation

Symbol Description

Rd General register (destination)*
Rs General register (source)*
Rn General register*

ERn General register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

– Subtraction

× Multiplication

÷ Division

∧ Logical AND

∨ Logical OR

⊕ Logical exclusive OR

→ Move

∼ NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

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Section 2 CPU

Table 2.3 Data Transfer Instructions

Instruction Size*1 Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.

MOVFPE B Cannot be used in this LSI.

MOVTPE B Cannot be used in this LSI.

POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn

PUSH W/L Rn → @-SP

Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.

2

LDM*

L @SP+ → Rn (register list)

Pops two or more general registers from the stack.

2

STM*

L Rn (register list) → @-SP

Pushes two or more general registers onto the stack.

Notes: 1. Size refers to the operand size.

B: Byte
W: Word
L: Longword

2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot

be used as an STM/LDM register.

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Section 2 CPU

Table 2.4 Arithmetic Operations Instructions (1)

Instruction Size* Function

ADD

SUB

ADDX

SUBX

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Subtraction on
immediate data and data in a general register cannot be performed in
bytes. Use the SUBX or ADD instruction.)

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.

INC

DEC

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Adds or subtracts the value 1 or 2 to or from data in a general register.
(Only the value 1 can be added to or subtracted from byte operands.)

ADDS

SUBS

DAA

DAS

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

B Rd (decimal adjust) → Rd

Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers: either
8-bit × 8-bit → 16-bit or 16-bit × 16-bit → 32-bit.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general registers: either 8­bit × 8-bit → 16-bit or 16-bit × 16-bit → 32-bit.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16-bit
÷ 8-bit → 8-bit quotient and 8-bit remainder or 32-bit ÷ 16-bit → 16-bit
quotient and 16-bit remainder.

Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword

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Table 2.4 Arithmetic Operations Instructions (2)

Instruction Size* Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register
or with immediate data, and sets the CCR bits according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of data in a
general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.

2

TAS*

B @ERd – 0, 1 → (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword

2. To use the TAS instruction, use registers ER0, ER1, ER4, and ER5.

Section 2 CPU

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Section 2 CPU

Table 2.5 Logic Operations Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another
general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another
general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and
another general register or immediate data.

NOT B/W/L ∼ Rd → Rd

Takes the one's complement (logical complement) of data in a general
register.

Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword

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Table 2.6 Shift Instructions

Instruction Size* Function

SHAL

SHAR

SHLL

SHLR

ROTL

ROTR

ROTXL

ROTXR

Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on data in a general register. 1-bit or 2 bit
shift is possible.

B/W/L Rd (shift) → Rd

Performs a logical shift on data in a general register. 1-bit or 2 bit shift is
possible.

B/W/L Rd (rotate) → Rd

Rotates data in a general register. 1-bit or 2 bit rotation is possible.

B/W/L Rd (rotate) → Rd

Rotates data including the carry flag in a general register. 1-bit or 2 bit
rotation is possible.

Section 2 CPU

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Section 2 CPU

Table 2.7 Bit Manipulation Instructions (1)

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.

BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BTST B ∼ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

Logically ANDs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.

BIAND B C ∧ (<bit-No.> of <EAd>) → C

Logically ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.

The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit-No.> of <EAd>) → C

Logically ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.

BIOR B C ∨ (∼ <bit-No.> of <EAd>) → C

Logically ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.

The bit number is specified by 3-bit immediate data.

Note: * Size refers to the operand size.
B: Byte

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Table 2.7 Bit Manipulation Instructions (2)

Instruction Size* Function

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Logically exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry flag.

BIXOR B C ⊕ ∼ (<bit-No.> of <EAd>) → C

Logically exclusive-ORs the carry flag with the inverse of a specified bit
in a general register or memory operand and stores the result in the
carry flag.

The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to the
carry flag.

BILD B ∼ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.

The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register or
memory operand.

Section 2 CPU

BIST B ∼ C → (<bit-No.>. of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.

The bit number is specified by 3-bit immediate data.

Note: * Size refers to the operand size.
B: Byte

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Table 2.8 Branch Instructions

Instruction Size Function

Bcc – Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA (BT) Always (true) Always

BRN (BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC (BHS) Carry clear

(high or same)

BCS (BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z ∨ (N ⊕ V) = 0

BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP – Branches unconditionally to a specified address.

BSR – Branches to a subroutine at a specified address

JSR – Branches to a subroutine at a specified address

RTS – Returns from a subroutine

C = 0

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Table 2.9 System Control Instructions

Instruction Size* Function

TRAPA – Starts trap-instruction exception handling.

RTE – Returns from an exception-handling routine.

SLEEP – Causes a transition to a power-down state.

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper eight bits are
valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper eight
bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with immediate data.

NOP – PC + 2 → PC

Only increments the program counter.

Note: * Size refers to the operand size.
B: Byte
W: Word

Section 2 CPU

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Section 2 CPU

Table 2.10 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B – if R4L ≠ 0 then

Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next:

EEPMOV.W – if R4 ≠ 0 then

Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next:

Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.

Execution of the next instruction begins as soon as the transfer is
completed.

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2.6.2 Basic Instruction Formats

The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).

Figure 2.11 shows examples of instruction formats.

• Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried

out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.

• Register field
Specifies a general register. Address registers are specified by 3-bit, and data registers by 3-bit

or 4-bit. Some instructions have two register fields, and some have no register field.

• Effective address extension
8-, 16-, or 32-bit specifying immediate data, an absolute address, or a displacement.

• Condition field
Specifies the branching condition of Bcc instructions.

(1) Operation field only

op

(2) Operation field and register fields

op

(3) Operation field, register fields, and effective address extension

op

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16

rn

rn rm

rm

NOP, RTS

ADD.B Rn, Rm

MOV.B @(d:16, Rn), Rm

Figure 2.11 Instruction Formats (Examples)

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2.7 Addressing Modes and Effective Address Calculation

The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.

Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

Register indirect with pre-decrement

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

@ERn+

@–ERn

2.7.1 Register Direct—Rn

The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.7.2 Register Indirect—@ERn

The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits ar e
valid and the upper eight bits are all assumed to be 0 (H

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Section 2 CPU

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction code is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn

Register Indirect with Post-Increment—@ERn+: The register field of the instruction code

specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word access, and 4 for longword
access. For word or longword transfer instructions, the register value should be even.

Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or
longword transfer instructions, the register value should be even.

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32

The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address,
the entire address space is accessed.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper eight
bits are all assumed to be 0 (H'00).

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Table 2.12 Absolute Address Access Ranges

Absolute Address Normal Mode Advanced Mode

Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF

16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

32 bits (@aa:32) H'000000 to H'FFFFFF

Program instruction
address

24 bits (@aa:24)

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32

The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction
code can be used directly as an operand.

The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction code is sign-extended to 24-bit and added to the 24-bit address
indicated by the PC value to generate a 24-bit branch address. Only the lower 24-bit of this branch
address are valid; the upper eight bits are all assumed to be 0 (H'00). The PC value to which the
displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128-byte (–63 to +64 words) or –32766 to +32768-byte (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.

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2.7.8 Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand which contains a branch address. The upper bits of
the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to
H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).

In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode, the memory operand is a longword operand, the first byte of which is assumed to
be 0 (H'00).

Note that the top area of the address range in which the branch address is stored is also used for
the exception vector area. For further details, see section 4, Exception Handling.

If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or the instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)

Specified
by @aa:8

Branch address

(a) Normal Mode (b) Advanced Mode

Specified
by @aa:8

Reserved

Branch address

Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode

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2.7.9 Effective Address Calculation

Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode, the upper eight bits of the effective address are ignored in order to generate a 16-bit
address.

Table 2.13 Effective Address Calculation (1)

No

Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1

Register direct (Rn)

op

2

Register indirect (@ERn)

op

Register indirect with displacement

3

@(d:16,ERn) or @(d:32,ERn)

o

Register indirect with post-increment or

4

pre-decrement

• Register indirect with post-increment @ERn+

rn

rm

r

p

r

dis

31

General register contents

31

General register contents

p

31

Sign extension

1

3

General register contents

disp

Operand is general register contents.

312331

0

Don't care

0

312331

on't care

D

0

1

0

1

3

3

Don't care

24

24

3

24

2

0

0

0

p

o

r

• Register indirect with pre-decrement @-ERn

p

o

r

31

General register contents

Operand Size

Byte

Word

Longword

Offset

1
2
4

1, 2, or 4

1, 2, or 4

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0

1

31

3

on't ca

D

23

24

re

0