Renesas H8S-2111B, HD64F2111B User Manual
REJ09B0163-0100Z
16
H8S/2111B HD64F2111B
H8S/2111B
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2100 Series
Rev.1.00
Revision Date: May. 14, 2004
Rev. 1.00, 05/04, page ii of xxxiv
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 1.00, 05/04, page iii of xxxiv
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 1.00, 05/04, page iv of xxxiv
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.00, 05/04, page v of xxxiv
Preface
The H8S/2111B is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas
Technology's original architecture as its core, and the peripheral functions required to configure a
system.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space.
This LSI is equipped with ROM, RAM, a 16-bit free-running timer (FRT), an 8-bit timer (TMR),
a watchdog timer (WDT), a serial communication interface (SCI), a keyboard buffer controller, a
host interface (LPC), an I
required for system configuration.
2
C bus interface (IIC), and I/O ports as on-chip peripheral modules,
A flash memory (F-ZTAT
TM
*) version is available for this LSI's ROM. This provides flexibility as
it can be reprogrammed in no time to cope with all situations from the early stages of mass
production to full-scale mass production. This is particularly applicable to application devices with
specifications that will most probably change.
Note: * F-ZTAT
TM
is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using the H8S/2111B in the design
of application systems. Target users are expected to understand the fundamentals
of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2111B to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 21,
List of Registers.
Rev. 1.00, 05/04, page vi of xxxiv
Rules: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/
H8S/2111B manuals:
Document Title Document No.
H8S/2111B Hardware Manual This manual
H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139
User's manuals for development tools:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual
H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3
User's Manual
REJ10B0058
ADE-702-282
REJ10B0026
Rev. 1.00, 05/04, page vii of xxxiv
Rev. 1.00, 05/04, page viii of xxxiv
Contents
Section 1 Overview............................................................................................1
1.1 Features............................................................................................................................. 1
1.2 Internal Block Diagram.....................................................................................................2
1.3 Pin Description..................................................................................................................3
1.3.1 Pin Arrangement.................................................................................................. 3
1.3.2 Pin Functions in Each Operating Mode ...............................................................4
1.3.3 Pin Functions ....................................................................................................... 9
Section 2 CPU....................................................................................................13
2.1 Features............................................................................................................................. 13
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 14
2.1.2 Differences from H8/300 CPU ............................................................................15
2.1.3 Differences from H8/300H CPU..........................................................................15
2.2 CPU Operating Modes...................................................................................................... 16
2.2.1 Normal Mode....................................................................................................... 16
2.2.2 Advanced Mode................................................................................................... 18
2.3 Address Space...................................................................................................................20
2.4 Register Configuration...................................................................................................... 21
2.4.1 General Registers................................................................................................. 22
2.4.2 Program Counter (PC) ......................................................................................... 23
2.4.3 Extended Control Register (EXR) ....................................................................... 23
2.4.4 Condition-Code Register (CCR).......................................................................... 24
2.4.5 Initial Register Values..........................................................................................25
2.5 Data Formats..................................................................................................................... 26
2.5.1 General Register Data Formats............................................................................ 26
2.5.2 Memory Data Formats ......................................................................................... 28
2.6 Instruction Set................................................................................................................... 29
2.6.1 Table of Instructions Classified by Function ....................................................... 30
2.6.2 Basic Instruction Formats .................................................................................... 39
2.7 Addressing Modes and Effective Address Calculation..................................................... 40
2.7.1 Register Direct—Rn ............................................................................................40
2.7.2 Register Indirect—@ERn.................................................................................... 40
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 41
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.. 41
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 41
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 42
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................42
2.7.8 Memory Indirect—@@aa:8 ................................................................................ 43
2.7.9 Effective Address Calculation .............................................................................44
Rev. 1.00, 05/04, page ix of xxxiv
2.8 Processing States...............................................................................................................46
2.9 Usage Notes...................................................................................................................... 48
2.9.1 Note on TAS Instruction Usage........................................................................... 48
2.9.2 Note on STM/LDM Instruction Usage ................................................................ 48
2.9.3 Note on Bit Manipulation Instructions ................................................................ 48
2.9.4 EEPMOV Instruction........................................................................................... 49
Section 3 MCU Operating Modes ..................................................................... 51
3.1 MCU Operating Mode Selection ......................................................................................51
3.2 Register Descriptions........................................................................................................ 52
3.2.1 Mode Control Register (MDCR) ......................................................................... 52
3.2.2 System Control Register (SYSCR)...................................................................... 53
3.2.3 Serial Timer Control Register (STCR) ................................................................ 55
3.3 Operating Mode Descriptions........................................................................................... 56
3.3.1 Mode 2................................................................................................................. 56
3.3.2 Mode 3................................................................................................................. 56
3.4 Address Map.....................................................................................................................57
Section 4 Exception Handling........................................................................... 59
4.1 Exception Handling Types and Priority............................................................................ 59
4.2 Exception Sources and Exception Vector Table............................................................... 60
4.3 Reset ................................................................................................................................. 61
4.3.1 Reset Exception Handling ................................................................................... 61
4.3.2 Interrupts after Reset............................................................................................ 62
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................62
4.4 Interrupt Exception Handling ........................................................................................... 63
4.5 Trap Instruction Exception Handling................................................................................ 63
4.6 Stack Status after Exception Handling..............................................................................64
4.7 Usage Note........................................................................................................................65
Section 5 Interrupt Controller............................................................................ 67
5.1 Features............................................................................................................................. 67
5.2 Input/Output Pins.............................................................................................................. 68
5.3 Register Descriptions........................................................................................................ 69
5.3.1 Interrupt Control Registers A to C (ICRA to ICRC) ........................................... 69
5.3.2 Address Break Control Register (ABRKCR) ...................................................... 70
5.3.3 Break Address Registers A to C (BARA to BARC)............................................ 71
5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)................................................... 72
5.3.5 IRQ Enable Register (IER).................................................................................. 73
5.3.6 IRQ Status Register (ISR).................................................................................... 73
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
Wake-Up Event Interrupt Mask Register (WUEMRB)....................................... 73
5.4 Interrupt Sources...............................................................................................................76
Rev. 1.00, 05/04, page x of xxxiv
5.4.1 External Interrupts ...............................................................................................76
5.4.2 Internal Interrupts ................................................................................................77
5.5 Interrupt Exception Handling Vector Table...................................................................... 78
5.6 Interrupt Control Modes and Interrupt Operation............................................................. 80
5.6.1 Interrupt Control Mode 0..................................................................................... 80
5.6.2 Interrupt Control Mode 1..................................................................................... 82
5.6.3 Interrupt Exception Handling Sequence .............................................................. 85
5.6.4 Interrupt Response Times ....................................................................................86
5.7 Address Break...................................................................................................................87
5.7.1 Features................................................................................................................ 87
5.7.2 Block Diagram..................................................................................................... 87
5.7.3 Operation .............................................................................................................88
5.7.4 Usage Notes ......................................................................................................... 88
5.8 Usage Notes...................................................................................................................... 90
5.8.1 Conflict between Interrupt Generation and Disabling ......................................... 90
5.8.2 Instructions that Disable Interrupts...................................................................... 91
5.8.3 Interrupts during Execution of EEPMOV Instruction..........................................91
5.8.4 IRQ Status Register (ISR).................................................................................... 91
Section 6 Bus Controller (BSC).........................................................................93
6.1 Register Descriptions........................................................................................................ 93
6.1.1 Bus Control Register (BCR) ................................................................................ 93
6.1.2 Wait State Control Register (WSCR) ..................................................................94
Section 7 I/O Ports.............................................................................................95
7.1 Port 1................................................................................................................................. 100
7.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 100
7.1.2 Port 1 Data Register (P1DR)................................................................................100
7.1.3 Port 1 Pull-Up MOS Control Register (P1PCR).................................................. 101
7.1.4 Pin Functions ....................................................................................................... 101
7.1.5 Port 1 Input Pull-Up MOS ................................................................................... 102
7.2 Port 2................................................................................................................................. 102
7.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 102
7.2.2 Port 2 Data Register (P2DR)) .............................................................................. 103
7.2.3 Port 2 Pull-Up MOS Control Register (P2PCR).................................................. 103
7.2.4 Pin Functions ....................................................................................................... 103
7.2.5 Port 2 Input Pull-Up MOS ................................................................................... 104
7.3 Port 3................................................................................................................................. 104
7.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 104
7.3.2 Port 3 Data Register (P3DR)................................................................................105
7.3.3 Port 3 Pull-Up MOS Control Register (P3PCR).................................................. 105
7.3.4 Pin Functions ....................................................................................................... 106
7.3.5 Port 3 Input Pull-Up MOS ................................................................................... 106
Rev. 1.00, 05/04, page xi of xxxiv
7.4 Port 4................................................................................................................................. 107
7.4.1 Port 4 Data Direction Register (P4DDR)............................................................. 107
7.4.2 Port 4 Data Register (P4DR) ............................................................................... 107
7.4.3 Pin Functions ....................................................................................................... 108
7.5 Port 5................................................................................................................................. 110
7.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 110
7.5.2 Port 5 Data Register (P5DR) ............................................................................... 110
7.5.3 Pin Functions ....................................................................................................... 111
7.6 Port 6................................................................................................................................. 112
7.6.1 Port 6 Data Direction Register (P6DDR)............................................................. 112
7.6.2 Port 6 Data Register (P6DR) ............................................................................... 113
7.6.3 Port 6 Pull-Up MOS Control Register (KMPCR) ............................................... 113
7.6.4 System Control Register 2 (SYSCR2)................................................................. 114
7.6.5 Pin Functions ....................................................................................................... 114
7.6.6 Port 6 Input Pull-Up MOS................................................................................... 116
7.7 Port 7................................................................................................................................. 117
7.7.1 Port 7 Input Data Register (P7PIN) ..................................................................... 117
7.7.2 Pin Functions ....................................................................................................... 117
7.8 Port 8................................................................................................................................. 118
7.8.1 Port 8 Data Direction Register (P8DDR)............................................................. 118
7.8.2 Port 8 Data Register (P8DR) ............................................................................... 118
7.8.3 Pin Functions ....................................................................................................... 119
7.9 Port 9................................................................................................................................. 122
7.9.1 Port 9 Data Direction Register (P9DDR)............................................................. 122
7.9.2 Port 9 Data Register (P9DR) ............................................................................... 122
7.9.3 Pin Functions ....................................................................................................... 123
7.10 Port A................................................................................................................................ 125
7.10.1 Port A Data Direction Register (PADDR)........................................................... 125
7.10.2 Port A Output Data Register (PAODR)............................................................... 125
7.10.3 Port A Input Data Register (PAPIN) ................................................................... 126
7.10.4 Pin Functions .......................................................................................................126
7.10.5 Port A Input Pull-Up MOS .................................................................................. 128
7.11 Port B................................................................................................................................ 129
7.11.1 Port B Data Direction Register (PBDDR) ........................................................... 129
7.11.2 Port B Output Data Register (PBODR) ...............................................................129
7.11.3 Port B Input Data Register (PBPIN) .................................................................... 130
7.11.4 Pin Functions .......................................................................................................130
7.11.5 Port B Input Pull-Up MOS .................................................................................. 131
7.12 Ports C, D.......................................................................................................................... 132
7.12.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR) ........................ 132
7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR) ............................ 133
7.12.3 Port C and Port D Input Data Registers (PCPIN, PDPIN)................................... 133
7.12.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR) ................. 134
Rev. 1.00, 05/04, page xii of xxxiv
7.12.5 Pin Functions .......................................................................................................135
7.12.6 Input Pull-Up MOS in Ports C and D ..................................................................135
7.13 Ports E, F........................................................................................................................... 136
7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR) .......................... 136
7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR).............................. 137
7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)..................................... 138
7.13.4 Pin Functions .......................................................................................................138
7.13.5 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)................... 140
7.13.6 Pin Functions .......................................................................................................141
7.13.7 Input Pull-Up MOS in Ports E and F ................................................................... 141
7.14 Port G................................................................................................................................ 142
7.14.1 Port G Data Direction Register (PGDDR) ........................................................... 142
7.14.2 Port G Output Data Register (PGODR) ............................................................... 143
7.14.3 Port G Input Data Register (PGPIN).................................................................... 143
7.14.4 Pin Functions .......................................................................................................144
7.14.5 Port G Nch-OD Control Register (PGNOCR) ..................................................... 145
7.14.6 Pin Functions .......................................................................................................145
Section 8 8-Bit PWM Timer (PWM).................................................................147
8.1 Features............................................................................................................................. 147
8.2 Input/Output Pins .............................................................................................................. 148
8.3 Register Descriptions........................................................................................................ 148
8.3.1 PWM Register Select (PWSL)............................................................................. 149
8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0).................................................151
8.3.3 PWM Data Polarity Register A (PWDPRA) .......................................................151
8.3.4 PWM Output Enable Register A (PWOERA) ..................................................... 152
8.3.5 Peripheral Clock Select Register (PCSR) ............................................................152
8.4 Operation .......................................................................................................................... 153
8.4.1 PWM Setting Example ........................................................................................155
8.4.2 Diagram of PWM Used as D/A Converter ..........................................................155
8.5 Usage Notes...................................................................................................................... 156
8.5.1 Module Stop Mode Setting .................................................................................. 156
Section 9 16-Bit Free-Running Timer (FRT) ....................................................157
9.1 Features............................................................................................................................. 157
9.2 Input/Output Pins .............................................................................................................. 159
9.3 Register Descriptions........................................................................................................ 159
9.3.1 Free-Running Counter (FRC) .............................................................................. 160
9.3.2 Output Compare Registers A and B (OCRA, OCRB) .........................................160
9.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................160
9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF)............................... 161
9.3.5 Output Compare Register DM (OCRDM)........................................................... 161
9.3.6 Timer Interrupt Enable Register (TIER).............................................................. 162
Rev. 1.00, 05/04, page xiii of xxxiv
9.3.7 Timer Control/Status Register (TCSR)................................................................ 163
9.3.8 Timer Control Register (TCR)............................................................................. 166
9.3.9 Timer Output Compare Control Register (TOCR) .............................................. 167
9.4 Operation .......................................................................................................................... 169
9.4.1 Pulse Output ........................................................................................................ 169
9.5 Operation Timing.............................................................................................................. 170
9.5.1 FRC Increment Timing........................................................................................ 170
9.5.2 Output Compare Output Timing.......................................................................... 171
9.5.3 FRC Clear Timing ...............................................................................................171
9.5.4 Input Capture Input Timing ................................................................................. 172
9.5.5 Buffered Input Capture Input Timing .................................................................. 173
9.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 174
9.5.7 Timing of Output Compare Flag (OCF) setting...................................................174
9.5.8 Timing of FRC Overflow Flag Setting ................................................................ 175
9.5.9 Automatic Addition Timing................................................................................. 175
9.5.10 Mask Signal Generation Timing.......................................................................... 176
9.6 Interrupt Sources...............................................................................................................177
9.7 Usage Notes...................................................................................................................... 177
9.7.1 Conflict between FRC Write and Clear ............................................................... 177
9.7.2 Conflict between FRC Write and Increment........................................................ 178
9.7.3 Conflict between OCR Write and Compare-Match............................................. 178
9.7.4 Switching of Internal Clock and FRC Operation................................................. 180
9.7.5 Module Stop Mode Setting.................................................................................. 181
Section 10 8-Bit Timer (TMR)..........................................................................183
10.1 Features............................................................................................................................. 183
10.2 Input/Output Pins.............................................................................................................. 188
10.3 Register Descriptions........................................................................................................ 189
10.3.1 Timer Counter (TCNT)........................................................................................ 191
10.3.2 Time Constant Register A (TCORA) .................................................................. 191
10.3.3 Time Constant Register B (TCORB) ................................................................... 191
10.3.4 Timer Control Register (TCR)............................................................................. 192
10.3.5 Timer Control/Status Register (TCSR)................................................................ 196
10.3.6 Time Constant Register (TCORC)....................................................................... 202
10.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A) ... 202
10.3.8 Timer Input Select Register (TISR and TISR_B) ................................................ 202
10.3.9 Timer Connection Register I (TCONRI) .............................................................203
10.3.10 Timer Connection Register S (TCONRS) ...........................................................203
10.3.11 Timer XY Control Register (TCRXY) ................................................................ 204
10.3.12 Timer AB Control Register (TCRAB)................................................................. 205
10.4 Operation ..........................................................................................................................206
10.4.1 Pulse Output ........................................................................................................ 206
10.5 Operation Timing.............................................................................................................. 207
Rev. 1.00, 05/04, page xiv of xxxiv
10.5.1 TCNT Count Timing ........................................................................................... 207
10.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 207
10.5.3 Timing of Timer Output at Compare-Match........................................................ 208
10.5.4 Timing of Counter Clear at Compare-Match ....................................................... 208
10.5.5 TCNT External Reset Timing ..............................................................................209
10.5.6 Timing of Overflow Flag (OVF) Setting .............................................................209
10.6 TMR_0 and TMR_1 Cascaded Connection...................................................................... 210
10.6.1 16-Bit Count Mode ..............................................................................................210
10.6.2 Compare-Match Count Mode ..............................................................................210
10.7 TMR_Y and TMR_X Cascaded Connection ....................................................................211
10.7.1 16-Bit Count Mode ..............................................................................................211
10.7.2 Compare-Match Count Mode ..............................................................................211
10.7.3 Input Capture Operation ...................................................................................... 212
10.8 TMR_B and TMR_A Cascaded Connection ....................................................................212
10.8.1 16-Bit Count Mode ..............................................................................................212
10.8.2 Compare-Match Count Mode ..............................................................................212
10.8.3 Input Capture Operation ...................................................................................... 213
10.9 Interrupt Sources...............................................................................................................215
10.10 Usage Notes ......................................................................................................................216
10.10.1 Conflict between TCNT Write and Counter Clear...............................................216
10.10.2 Conflict between TCNT Write and Count-Up..................................................... 216
10.10.3 Conflict between TCOR Write and Compare-Match...........................................217
10.10.4 Conflict between Compare-Matches A and B .....................................................217
10.10.5 Switching of Internal Clocks and TCNT Operation.............................................218
10.10.6 Mode Setting with Cascaded Connection ............................................................ 219
10.10.7 Module Stop Mode Setting.................................................................................. 219
Section 11 Watchdog Timer (WDT)..................................................................221
11.1 Features............................................................................................................................. 221
11.2 Input/Output Pins.............................................................................................................. 223
11.3 Register Descriptions........................................................................................................ 223
11.3.1 Timer Counter (TCNT)........................................................................................ 223
11.3.2 Timer Control/Status Register (TCSR)................................................................ 224
11.4 Operation ..........................................................................................................................227
11.4.1 Watchdog Timer Mode ........................................................................................ 227
11.4.2 Interval Timer Mode ............................................................................................ 229
11.4.3 RESO Signal Output Timing ...............................................................................230
11.5 Interrupt Sources...............................................................................................................230
11.6 Usage Notes ...................................................................................................................... 231
11.6.1 Notes on Register Access..................................................................................... 231
11.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 232
11.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 232
11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 232
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11.6.5 System Reset by RESO Signal ............................................................................ 233
11.6.6 Counter Values during Transitions between High-Speed, Sub-Active,
and Watch Modes ................................................................................................ 233
Section 12 Serial Communication Interface (SCI)............................................ 235
12.1 Features............................................................................................................................. 235
12.2 Input/Output Pins.............................................................................................................. 236
12.3 Register Descriptions........................................................................................................ 237
12.3.1 Receive Shift Register (RSR) .............................................................................. 237
12.3.2 Receive Data Register (RDR).............................................................................. 237
12.3.3 Transmit Data Register (TDR)............................................................................. 237
12.3.4 Transmit Shift Register (TSR) ............................................................................. 238
12.3.5 Serial Mode Register (SMR) ............................................................................... 238
12.3.6 Serial Control Register (SCR) ............................................................................. 239
12.3.7 Serial Status Register (SSR) ................................................................................241
12.3.8 Serial Interface Mode Register (SCMR).............................................................. 243
12.3.9 Bit Rate Register (BRR) ...................................................................................... 244
12.3.10 Serial Pin Select Register (SPSR)........................................................................ 249
12.4 Operation in Asynchronous Mode .................................................................................... 249
12.4.1 Data Transfer Format........................................................................................... 250
12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 251
12.4.3 Clock.................................................................................................................... 251
12.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 253
12.4.5 Data Transmission (Asynchronous Mode) .......................................................... 254
12.4.6 Serial Data Reception (Asynchronous Mode) ..................................................... 256
12.5 Multiprocessor Communication Function......................................................................... 259
12.5.1 Multiprocessor Serial Data Transmission ............................................................ 260
12.5.2 Multiprocessor Serial Data Reception ................................................................. 261
12.6 Operation in Clocked Synchronous Mode........................................................................ 264
12.6.1 Clock.................................................................................................................... 264
12.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 265
12.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 266
12.6.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 268
12.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) ............................................................................. 269
12.7 Interrupt Sources...............................................................................................................271
12.8 Usage Notes ...................................................................................................................... 272
12.8.1 Module Stop Mode Setting .................................................................................. 272
12.8.2 Break Detection and Processing .......................................................................... 272
12.8.3 Mark State and Break Detection .......................................................................... 272
12.8.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) .................................................................... 272
12.8.5 Relation between Writing to TDR and TDRE Flag ............................................. 272
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12.8.6 SCI Operations during Mode Transitions ............................................................273
12.8.7 Switching from SCK Pins to Port Pins ................................................................276
Section 13 I2C Bus Interface (IIC) .....................................................................277
13.1 Features............................................................................................................................. 277
13.2 Input/Output Pins.............................................................................................................. 280
13.3 Register Descriptions........................................................................................................ 281
13.3.1 I2C Bus Data Register (ICDR) ............................................................................. 282
13.3.2 Slave Address Register (SAR)............................................................................. 283
13.3.3 Second Slave Address Register (SARX) .............................................................284
13.3.4 I2C Bus Mode Register (ICMR)........................................................................... 286
13.3.5 I2C Bus Control Register (ICCR)......................................................................... 289
13.3.6 I2C Bus Status Register (ICSR)............................................................................ 297
13.3.7 DDC Switch Register (DDCSWR) ......................................................................301
13.3.8 I2C Bus Extended Control Register (ICXR)......................................................... 302
13.3.9 Port G Control Register (PGCTL) .......................................................................306
13.4 Operation ..........................................................................................................................307
13.4.1 I2C Bus Data Format ............................................................................................ 307
13.4.2 Initialization ......................................................................................................... 309
13.4.3 Master Transmit Operation .................................................................................. 309
13.4.4 Master Receive Operation.................................................................................... 314
13.4.5 Slave Receive Operation...................................................................................... 321
13.4.6 Slave Transmit Operation ....................................................................................328
13.4.7 IRIC Setting Timing and SCL Control ................................................................331
13.4.8 Noise Canceller.................................................................................................... 334
13.4.9 Initialization of Internal State .............................................................................. 335
13.5 Interrupt Sources...............................................................................................................336
13.6 Usage Notes ...................................................................................................................... 337
13.6.1 Module Stop Mode Setting .................................................................................. 347
Section 14 Keyboard Buffer Controller.............................................................349
14.1 Features............................................................................................................................. 349
14.2 Input/Output Pins.............................................................................................................. 350
14.3 Register Descriptions........................................................................................................ 351
14.3.1 Keyboard Control Register H (KBCRH) ............................................................. 351
14.3.2 Keyboard Control Register L (KBCRL) .............................................................. 353
14.3.3 Keyboard Data Buffer Register (KBBR) .............................................................354
14.4 Operation ..........................................................................................................................355
14.4.1 Receive Operation................................................................................................ 355
14.4.2 Transmit Operation .............................................................................................. 356
14.4.3 Receive Abort ......................................................................................................359
14.4.4 KCLKI and KDI Read Timing............................................................................. 361
14.4.5 KCLKO and KDO Write Timing......................................................................... 361
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14.4.6 KBF Setting Timing and KCLK Control............................................................. 362
14.4.7 Receive Timing.................................................................................................... 363
14.4.8 KCLK Fall Interrupt Operation ........................................................................... 364
14.5 Usage Notes ...................................................................................................................... 365
14.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................365
14.5.2 Module Stop Mode Setting .................................................................................. 366
Section 15 Host Interface (LPC) .......................................................................369
15.1 Features............................................................................................................................. 369
15.2 Input/Output Pins.............................................................................................................. 371
15.3 Register Descriptions........................................................................................................ 372
15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) ................................ 373
15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) ................................ 379
15.3.3 LPC Channel 3 Address Register (LADR3) ........................................................ 381
15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................382
15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) .................................................. 383
15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) .................................... 383
15.3.7 Status Registers 1 to 3 (STR1 to STR3) .............................................................. 383
15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) ...............................389
15.3.9 Host Interface Select Register (HISEL)............................................................... 397
15.4 Operation ..........................................................................................................................398
15.4.1 Host Interface Activation..................................................................................... 398
15.4.2 LPC I/O Cycles.................................................................................................... 399
15.4.3 A20 Gate .............................................................................................................. 400
15.4.4 Host Interface Shutdown Function (LPCPD) ...................................................... 403
15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) ....................................407
15.4.6 Host Interface Clock Start Request (CLKRUN).................................................. 409
15.5 Interrupt Sources...............................................................................................................410
15.5.1 IBFI1, IBFI2, IBFI3, and ERRI ........................................................................... 410
15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 ....................... 410
15.6 Usage Notes ...................................................................................................................... 413
15.6.1 Module Stop Mode Setting .................................................................................. 413
15.6.2 Notes on Using Host Interface............................................................................. 413
Section 16 A/D Converter ................................................................................. 413
16.1 Features............................................................................................................................. 413
16.2 Input/Output Pins.............................................................................................................. 415
16.3 Register Descriptions........................................................................................................ 416
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 416
16.3.2 A/D Control/Status Register (ADCSR) ...............................................................417
16.3.3 A/D Control Register (ADCR) ............................................................................ 418
16.4 Operation ..........................................................................................................................419
16.4.1 Single Mode......................................................................................................... 419
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16.4.2 Scan Mode ...........................................................................................................419
16.4.3 Input Sampling and A/D Conversion Time ......................................................... 421
16.4.4 External Trigger Input Timing............................................................................. 422
16.5 Interrupt Sources...............................................................................................................423
16.6 A/D Conversion Accuracy Definitions............................................................................. 423
16.7 Usage Notes ...................................................................................................................... 425
16.7.1 Permissible Signal Source Impedance ................................................................. 425
16.7.2 Influences on Absolute Accuracy ........................................................................425
16.7.3 Setting Range of Analog Power Supply and Other Pins...................................... 426
16.7.4 Notes on Board Design ........................................................................................ 426
16.7.5 Notes on Noise Countermeasures ........................................................................426
16.7.6 Module Stop Mode Setting .................................................................................. 427
Section 17 RAM ................................................................................................429
Section 18 ROM ................................................................................................431
18.1 Features............................................................................................................................. 431
18.2 Mode Transitions .............................................................................................................. 433
18.3 Block Configuration.......................................................................................................... 436
18.4 Input/Output Pins.............................................................................................................. 437
18.5 Register Descriptions........................................................................................................ 437
18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 438
18.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 439
18.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) .................................................... 440
18.6 Operating Modes............................................................................................................... 441
18.7 On-Board Programming Modes........................................................................................ 441
18.7.1 Boot Mode ...........................................................................................................442
18.7.2 User Program Mode............................................................................................. 445
18.8 Flash Memory Programming/Erasing............................................................................... 446
18.8.1 Program/Program-Verify ..................................................................................... 446
18.8.2 Erase/Erase-Verify............................................................................................... 448
18.9 Program/Erase Protection .................................................................................................450
18.9.1 Hardware Protection ............................................................................................450
18.9.2 Software Protection.............................................................................................. 450
18.9.3 Error Protection.................................................................................................... 450
18.10 Interrupts during Flash Memory Programming/Erasing ................................................... 451
18.11 Programmer Mode ............................................................................................................452
18.12 Usage Notes ......................................................................................................................453
Section 19 Clock Pulse Generator .....................................................................455
19.1 Oscillator........................................................................................................................... 456
19.1.1 Connecting Crystal Resonator ............................................................................. 456
19.1.2 External Clock Input Method............................................................................... 457
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19.2 Duty Correction Circuit .................................................................................................... 459
19.3 Medium-Speed Clock Divider .......................................................................................... 459
19.4 Bus Master Clock Select Circuit....................................................................................... 459
19.5 Subclock Input Circuit ...................................................................................................... 460
19.6 Waveform Forming Circuit............................................................................................... 460
19.7 Clock Select Circuit .......................................................................................................... 461
19.8 Usage Notes ...................................................................................................................... 461
19.8.1 Note on Resonator ............................................................................................... 461
19.8.2 Notes on Board Design ........................................................................................ 461
Section 20 Power-Down Modes........................................................................ 463
20.1 Register Descriptions........................................................................................................ 463
20.1.1 Standby Control Register (SBYCR) .................................................................... 464
20.1.2 Low-Power Control Register (LPWRCR) ........................................................... 465
20.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) ................... 467
20.2 Mode Transitions and LSI States...................................................................................... 468
20.3 Medium-Speed Mode .......................................................................................................470
20.4 Sleep Mode ....................................................................................................................... 471
20.5 Software Standby Mode.................................................................................................... 471
20.6 Hardware Standby Mode .................................................................................................. 473
20.7 Watch Mode......................................................................................................................474
20.8 Subsleep Mode.................................................................................................................. 475
20.9 Subactive Mode ................................................................................................................476
20.10 Module Stop Mode ........................................................................................................... 477
20.11 Direct Transitions ............................................................................................................. 477
20.12 Usage Notes ......................................................................................................................478
20.12.1 I/O Port Status...................................................................................................... 478
20.12.2 Current Consumption when Waiting for Oscillation Stabilization ...................... 478
Section 21 List of Registers............................................................................... 479
21.1 Register Addresses (Address Order)................................................................................. 480
21.2 Register Bits...................................................................................................................... 489
21.3 Register States in Each Operating Mode ..........................................................................497
21.4 Register Select Conditions................................................................................................ 505
Section 22 Electrical Characteristics .................................................................513
22.1 Absolute Maximum Ratings ............................................................................................. 513
22.2 DC Characteristics ............................................................................................................ 514
22.3 AC Characteristics ............................................................................................................ 520
22.3.1 Clock Timing ....................................................................................................... 521
22.3.2 Control Signal Timing .........................................................................................522
22.3.3 Timing of On-Chip Peripheral Modules .............................................................. 523
22.4 A/D Conversion Characteristics ....................................................................................... 526
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22.5 Flash Memory Characteristics ..........................................................................................527
22.6 Usage Note........................................................................................................................ 529
22.7 Timing Chart..................................................................................................................... 529
22.7.1 Clock Timing ....................................................................................................... 529
22.7.2 Control Signal Timing .........................................................................................531
22.7.3 On-Chip Peripheral Module Timing ....................................................................532
Appendix .........................................................................................................537
A. I/O Port States in Each Processing State........................................................................... 537
B. Product Codes ...................................................................................................................538
C. Package Dimensions .........................................................................................................539
Index .........................................................................................................541
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Rev. 1.00, 05/04, page xxii of xxxiv
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram.................................................................................................2
Figure 1.2 Pin Arrangement............................................................................................................3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 17
Figure 2.2 Stack Structure in Normal Mode................................................................................. 17
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 18
Figure 2.4 Stack Structure in Advanced Mode............................................................................. 19
Figure 2.5 Memory Map............................................................................................................... 20
Figure 2.6 CPU Internal Registers................................................................................................ 21
Figure 2.7 Usage of General Registers .........................................................................................22
Figure 2.8 Stack............................................................................................................................ 23
Figure 2.9 General Register Data Formats (1).............................................................................. 26
Figure 2.9 General Register Data Formats (2).............................................................................. 27
Figure 2.10 Memory Data Formats...............................................................................................28
Figure 2.11 Instruction Formats (Examples) ................................................................................ 39
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode...................... 43
Figure 2.13 State Transitions........................................................................................................ 47
Section 3 MCU Operating Modes
Figure 3.1 Address Map for H8S/2111B-B .................................................................................. 57
Figure 3.2 Address Map for H8S/2111B-C .................................................................................. 58
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Mode 3)............................................................................................61
Figure 4.2 Stack Status after Exception Handling........................................................................ 64
Figure 4.3 Operation when SP Value is Odd................................................................................ 65
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 68
Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0,
Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB..... 75
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0................................................................ 76
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0.......81
Figure 5.5 State Transition in Interrupt Control Mode 1 .............................................................. 82
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 84
Figure 5.7 Interrupt Exception Handling...................................................................................... 85
Figure 5.8 Address Break Block Diagram.................................................................................... 87
Figure 5.9 Address Break Timing Example .................................................................................89
Figure 5.10 Conflict between Interrupt Generation and Disabling............................................... 90
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Section 8 8-Bit PWM Timer (PWM)
Figure 8.1 Block Diagram of PWM Timer................................................................................. 147
Figure 8.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 154
Figure 8.3 Example of PWM Setting..........................................................................................155
Figure 8.4 Example when PWM is Used as D/A Converter....................................................... 155
Section 9 16-Bit Free-Running Timer (FRT)
Figure 9.1 Block Diagram of 16-Bit Free-Running Timer ......................................................... 158
Figure 9.2 Example of Pulse Output...........................................................................................169
Figure 9.3 Increment Timing with Internal Clock Source .......................................................... 170
Figure 9.4 Increment Timing with External Clock Source......................................................... 170
Figure 9.5 Timing of Output Compare A Output....................................................................... 171
Figure 9.6 Clearing of FRC by Compare-Match A Signal ......................................................... 171
Figure 9.7 Input Capture Input Signal Timing (Usual Case)...................................................... 172
Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read) ......................172
Figure 9.9 Buffered Input Capture Timing................................................................................. 173
Figure 9.10 Buffered Input Capture Timing (BUFEA = 1)........................................................ 173
Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting.................... 174
Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting................................... 174
Figure 9.13 Timing of Overflow Flag (OVF) Setting................................................................. 175
Figure 9.14 OCRA Automatic Addition Timing ........................................................................ 175
Figure 9.15 Timing of Input Capture Mask Signal Setting......................................................... 176
Figure 9.16 Timing of Input Capture Mask Signal Clearing ...................................................... 176
Figure 9.17 FRC Write-Clear Conflict ....................................................................................... 177
Figure 9.18 FRC Write-Increment Conflict................................................................................ 178
Figure 9.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used) .................................................179
Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function is Used) ........................................................ 179
Section 10 8-Bit Timer (TMR)
Figure 10.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 185
Figure 10.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 186
Figure 10.3 Block Diagram of 8-Bit Timer (TMR_B and TMR_A).......................................... 187
Figure 10.4 Pulse Output Example............................................................................................. 206
Figure 10.5 Count Timing for Internal Clock Input ...................................................................207
Figure 10.6 Count Timing for External Clock Input (Both Edges) ............................................207
Figure 10.7 Timing of CMF Setting at Compare-Match............................................................ 208
Figure 10.8 Timing of Toggled Timer Output by Compare-Match A Signal............................. 208
Figure 10.9 Timing of Counter Clear by Compare-Match ......................................................... 208
Figure 10.10 Timing of Counter Clear by External Reset Input................................................. 209
Figure 10.11 Timing of OVF Flag Setting ................................................................................. 209
Figure 10.12 Timing of Input Capture Operation....................................................................... 213
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Figure 10.13 Timing of Input Capture Signal
(Input capture signal is input during TICRR and TICRF read) ............................. 213
Figure 10.14 Conflict between TCNT Write and Clear.............................................................. 216
Figure 10.15 Conflict between TCNT Write and Count-Up.......................................................216
Figure 10.16 Conflict between TCOR Write and Compare-Match............................................ 217
Section 11 Watchdog Timer (WDT)
Figure 11.1 Block Diagram of WDT.......................................................................................... 222
Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 228
Figure 11.3 Interval Timer Mode Operation............................................................................... 229
Figure 11.4 OVF Flag Set Timing .............................................................................................. 229
Figure 11.5 Output Timing of RESO signal ...............................................................................230
Figure 11.6 Writing to TCNT and TCSR (WDT_0)................................................................... 231
Figure 11.7 Conflict between TCNT Write and Increment ........................................................ 232
Figure 11.8 Sample Circuit for Resetting System by RESO Signal ...........................................233
Section 12 Serial Communication Interface (SCI)
Figure 12.1 Block Diagram of SCI............................................................................................. 236
Figure 12.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................249
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................251
Figure 12.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode) ............................................................................................ 252
Figure 12.5 Sample SCI Initialization Flowchart .......................................................................253
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 254
Figure 12.7 Sample Serial Transmission Flowchart ................................................................... 255
Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 256
Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 257
Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 258
Figure 12.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A).......................................... 259
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart........................................ 260
Figure 12.12 Example of SCI Receive Operation
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 261
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 262
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 263
Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 264
Figure 12.15 Sample SCI Initialization Flowchart ..................................................................... 265
Figure 12.16 Example of SCI Transmit Operation in Clocked Synchronous Mode................... 266
Figure 12.17 Sample Serial Transmission Flowchart................................................................. 267
Figure 12.18 Example of SCI Receive Operation in Clocked Synchronous Mode ....................268
Figure 12.19 Sample Serial Reception Flowchart ......................................................................269
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Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 270
Figure 12.21 Sample Flowchart for Mode Transition during Transmission............................... 274
Figure 12.22 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............274
Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock)..................................................................................................... 275
Figure 12.24 Sample Flowchart for Mode Transition during Reception.................................... 275
Figure 12.25 Switching from SCK Pins to Port Pins.................................................................. 276
Figure 12.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins..........276
Section 13 I2C Bus Interface (IIC)
Figure 13.1 Block Diagram of I2C Bus Interface ....................................................................... 278
Figure 13.2 I2C Bus Interface Connections (Example: This LSI as Master).............................. 279
Figure 13.3 I2C Bus Data Format (I2C Bus Format)................................................................... 307
Figure 13.4 I2C Bus Data Format (Serial Format)...................................................................... 307
Figure 13.5 I2C Bus Timing........................................................................................................ 308
Figure 13.6 Sample Flowchart for IIC Initialization .................................................................. 309
Figure 13.7 Sample Flowchart for Operations in Master Transmit Mode.................................. 310
Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ...... 312
Figure 13.9 Example of Stop Condition Issuance Operation Timing
in Master Transmit Mode (MLS = WAIT = 0)....................................................... 313
Figure 13.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)............. 314
Figure 13.11 Example of Operation Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)............................................................................ 316
Figure 13.12 Example of Stop Condition Issuance Operation Timing
in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ...................................316
Figure 13.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1)................................................................. 317
Figure 13.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1) ................................................................... 318
Figure 13.15 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1) ...........................................................................320
Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ...........................................................................321
Figure 13.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)............... 322
Figure 13.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) ... 324
Figure 13.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) ... 324
Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)............... 325
Figure 13.21 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0, HNDS = 0)........................................................................... 327
Figure 13.22 Example of Slave Receive Mode Operation Timing (2)
(MLS = ACKB = 0, HNDS = 0)........................................................................... 327
Figure 13.23 Sample Flowchart for Slave Transmit Mode......................................................... 328
Figure 13.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) ......................... 330
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Figure 13.25 IRIC Setting Timing and SCL Control (1) ............................................................ 331
Figure 13.26 IRIC Setting Timing and SCL Control (2) ............................................................ 332
Figure 13.27 IRIC Setting Timing and SCL Control (3) ............................................................ 333
Figure 13.28 Block Diagram of Noise Canceler......................................................................... 334
Figure 13.29 Notes on Reading Master Receive Data................................................................ 340
Figure 13.30 Flowchart for Start Condition Issuance Instruction for Retransmission
and Timing............................................................................................................. 341
Figure 13.31 Stop Condition Issuance Timing ........................................................................... 342
Figure 13.32 IRIC Flag Clearing Timing when WAIT = 1 ........................................................ 343
Figure 13.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 344
Figure 13.34 TRS Bit Set Timing in Slave Mode....................................................................... 345
Figure 13.35 Diagram of Erroneous Operation when Arbitration is Lost................................... 347
Section 14 Keyboard Buffer Controller
Figure 14.1 Block Diagram of Keyboard Buffer Controller....................................................... 349
Figure 14.2 Keyboard Buffer Controller Connection................................................................. 350
Figure 14.3 Sample Receive Processing Flowchart.................................................................... 355
Figure 14.4 Receive Timing .......................................................................................................356
Figure 14.5 Sample Transmit Processing Flowchart (1)............................................................ 357
Figure 14.5 Sample Transmit Processing Flowchart (2)............................................................. 358
Figure 14.6 Transmit Timing...................................................................................................... 358
Figure 14.7 Sample Receive Abort Processing Flowchart (1)................................................... 359
Figure 14.7 Sample Receive Abort Processing Flowchart (2)................................................... 360
Figure 14.8 Receive Abort and Transmit Start
(Transmission/Reception Switchover) Timing ....................................................... 360
Figure 14.9 KCLKI and KDI Read Timing................................................................................ 361
Figure 14.10 KCLKO and KDO Write Timing.......................................................................... 361
Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing ..................... 362
Figure 14.12 Receive Counter and KBBR Data Load Timing ...................................................363
Figure 14.13 Example of KCLK Input Fall Interrupt Operation ................................................ 364
Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing .................................365
Section 15 Host Interface (LPC)
Figure 15.1 Block Diagram of LPC............................................................................................ 370
Figure 15.2 Typical LFRAME Timing ....................................................................................... 400
Figure 15.3 Abort Mechanism.................................................................................................... 400
Figure 15.4 GA20 Output........................................................................................................... 401
Figure 15.5 Power-Down State Termination Timing ................................................................. 406
Figure 15.6 SERIRQ Timing...................................................................................................... 407
Figure 15.7 Clock Start Request Timing ....................................................................................409
Figure 15.8 HIRQ Flowchart (Example of Channel 1)............................................................... 412
Rev. 1.00, 05/04, page xxvii of xxxiv
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ........................................................................... 414
Figure 16.2 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)....................................................... 420
Figure 16.3 A/D Conversion Timing.......................................................................................... 421
Figure 16.4 External Trigger Input Timing ................................................................................ 422
Figure 16.5 A/D Conversion Accuracy Definitions ...................................................................424
Figure 16.6 A/D Conversion Accuracy Definitions ...................................................................424
Figure 16.7 Example of Analog Input Circuit ............................................................................ 425
Figure 16.8 Example of Analog Input Protection Circuit........................................................... 427
Figure 16.9 Equivalent Circuit of Analog Input Pin................................................................... 427
Section 18 ROM
Figure 18.1 Block Diagram of Flash Memory............................................................................ 432
Figure 18.2 Flash Memory State Transitions.............................................................................. 433
Figure 18.3 Boot Mode............................................................................................................... 434
Figure 18.4 User Program Mode (Example) ..............................................................................435
Figure 18.5 Flash Memory Block Configuration........................................................................ 436
Figure 18.6 On-Chip RAM Area in Boot Mode......................................................................... 444
Figure 18.7 ID Code Area ..........................................................................................................444
Figure 18.8 Programming/Erasing Flowchart Example in User Program Mode........................ 445
Figure 18.9 Program/Program-Verify Flowchart .......................................................................447
Figure 18.10 Erase/Erase-Verify Flowchart ............................................................................... 449
Figure 18.11 Memory Map in Programmer Mode......................................................................452
Section 19 Clock Pulse Generator
Figure 19.1 Block Diagram of Clock Pulse Generator ............................................................... 455
Figure 19.2 Typical Connection to Crystal Resonator................................................................ 456
Figure 19.3 Equivalent Circuit of Crystal Resonator..................................................................456
Figure 19.4 Example of External Clock Input............................................................................ 457
Figure 19.5 External Clock Input Timing................................................................................... 458
Figure 19.6 Timing of External Clock Output Stabilization Delay Time................................... 459
Figure 19.7 Subclock Input Timing............................................................................................ 460
Figure 19.8 Note on Board Design of Oscillator Circuit Section............................................... 461
Section 20 Power-Down Modes
Figure 20.1 Mode Transition Diagram ....................................................................................... 468
Figure 20.2 Medium-Speed Mode Timing ................................................................................. 470
Figure 20.3 Application Example in Software Standby Mode ................................................... 472
Figure 20.4 Hardware Standby Mode Timing ............................................................................ 473
Section 22 Electrical Characteristics
Figure 22.1 Darlington Pair Drive Circuit (Example) ................................................................ 518
Figure 22.2 LED Drive Circuit (Example) ................................................................................. 519
Figure 22.3 Output Load Circuit ................................................................................................ 520
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Figure 22.4 Connection of VCL Capacitor................................................................................. 529
Figure 22.5 System Clock Timing.............................................................................................. 529
Figure 22.6 Oscillation Settling Timing .....................................................................................530
Figure 22.7 Oscillation Setting Timing (Exiting Software Standby Mode)................................ 530
Figure 22.8 Reset Input Timing.................................................................................................. 531
Figure 22.9 Interrupt Input Timing............................................................................................. 531
Figure 22.10 I/O Port Input/Output Timing................................................................................ 532
Figure 22.11 FRT Input/Output Timing ..................................................................................... 532
Figure 22.12 FRT Clock Input Timing....................................................................................... 532
Figure 22.13 8-Bit Timer Output Timing ................................................................................... 533
Figure 22.14 8-Bit Timer Clock Input Timing ........................................................................... 533
Figure 22.15 8-Bit Timer Reset Input Timing............................................................................ 533
Figure 22.16 PWM, PWMX Output Timing .............................................................................. 533
Figure 22.17 SCK Clock Input Timing.......................................................................................534
Figure 22.18 SCI Input/Output Timing (Synchronous Mode).................................................... 534
Figure 22.19 A/D Converter External Trigger Input Timing...................................................... 534
Figure 22.20 WDT Output Timing (RESO) ...............................................................................534
Figure 22.21 Keyboard Buffer Controller Timing...................................................................... 535
Figure 22.22 I2C Bus Interface Input/Output Timing................................................................. 535
Figure 22.23 Host Interface (LPC) Timing................................................................................. 536
Figure 22.24 Tester Measurement Condition .............................................................................536
Appendix
Figure C.1 Package Dimensions (TFP-144) ............................................................................... 539
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