Renesas H8S-2111B, HD64F2111B User Manual

REJ09B0163-0100Z

16

H8S/2111B HD64F2111B

H8S/2111B

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family / H8S/2100 Series

Rev.1.00
Revision Date: May. 14, 2004

Rev. 1.00, 05/04, page ii of xxxiv

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 1.00, 05/04, page iii of xxxiv

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 1.00, 05/04, page iv of xxxiv

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 1.00, 05/04, page v of xxxiv

Preface

The H8S/2111B is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas
Technology's original architecture as its core, and the peripheral functions required to configure a
system.

The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space.

This LSI is equipped with ROM, RAM, a 16-bit free-running timer (FRT), an 8-bit timer (TMR),
a watchdog timer (WDT), a serial communication interface (SCI), a keyboard buffer controller, a
host interface (LPC), an I
required for system configuration.

2

C bus interface (IIC), and I/O ports as on-chip peripheral modules,

A flash memory (F-ZTAT

TM

*) version is available for this LSI's ROM. This provides flexibility as
it can be reprogrammed in no time to cope with all situations from the early stages of mass
production to full-scale mass production. This is particularly applicable to application devices with
specifications that will most probably change.

Note: * F-ZTAT

TM

is a trademark of Renesas Technology Corp.

Target Users: This manual was written for users who will be using the H8S/2111B in the design

of application systems. Target users are expected to understand the fundamentals
of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2111B to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 21,
List of Registers.

Rev. 1.00, 05/04, page vi of xxxiv

Rules: Register name: The following notation is used for cases when the same or a

similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)

Bit order: The MSB is on the left and the LSB is on the right.

Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/

H8S/2111B manuals:

Document Title Document No.

H8S/2111B Hardware Manual This manual

H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139

User's manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual

Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual

H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial REJ10B0024

H8S, H8/300 Series High-performance Embedded Workshop 3
User's Manual

REJ10B0058

ADE-702-282

REJ10B0026

Rev. 1.00, 05/04, page vii of xxxiv

Rev. 1.00, 05/04, page viii of xxxiv

Contents

Section 1 Overview............................................................................................1

1.1 Features............................................................................................................................. 1

1.2 Internal Block Diagram.....................................................................................................2

1.3 Pin Description..................................................................................................................3

1.3.1 Pin Arrangement.................................................................................................. 3

1.3.2 Pin Functions in Each Operating Mode ...............................................................4

1.3.3 Pin Functions ....................................................................................................... 9

Section 2 CPU....................................................................................................13

2.1 Features............................................................................................................................. 13

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 14

2.1.2 Differences from H8/300 CPU ............................................................................15

2.1.3 Differences from H8/300H CPU..........................................................................15

2.2 CPU Operating Modes...................................................................................................... 16

2.2.1 Normal Mode....................................................................................................... 16

2.2.2 Advanced Mode................................................................................................... 18

2.3 Address Space...................................................................................................................20

2.4 Register Configuration...................................................................................................... 21

2.4.1 General Registers................................................................................................. 22

2.4.2 Program Counter (PC) ......................................................................................... 23

2.4.3 Extended Control Register (EXR) ....................................................................... 23

2.4.4 Condition-Code Register (CCR).......................................................................... 24

2.4.5 Initial Register Values..........................................................................................25

2.5 Data Formats..................................................................................................................... 26

2.5.1 General Register Data Formats............................................................................ 26

2.5.2 Memory Data Formats ......................................................................................... 28

2.6 Instruction Set................................................................................................................... 29

2.6.1 Table of Instructions Classified by Function ....................................................... 30

2.6.2 Basic Instruction Formats .................................................................................... 39

2.7 Addressing Modes and Effective Address Calculation..................................................... 40

2.7.1 Register Direct—Rn ............................................................................................40

2.7.2 Register Indirect—@ERn.................................................................................... 40

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 41

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.. 41

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 41

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 42

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................42

2.7.8 Memory Indirect—@@aa:8 ................................................................................ 43

2.7.9 Effective Address Calculation .............................................................................44

Rev. 1.00, 05/04, page ix of xxxiv

2.8 Processing States...............................................................................................................46

2.9 Usage Notes...................................................................................................................... 48

2.9.1 Note on TAS Instruction Usage........................................................................... 48

2.9.2 Note on STM/LDM Instruction Usage ................................................................ 48

2.9.3 Note on Bit Manipulation Instructions ................................................................ 48

2.9.4 EEPMOV Instruction........................................................................................... 49

Section 3 MCU Operating Modes ..................................................................... 51

3.1 MCU Operating Mode Selection ......................................................................................51

3.2 Register Descriptions........................................................................................................ 52

3.2.1 Mode Control Register (MDCR) ......................................................................... 52

3.2.2 System Control Register (SYSCR)...................................................................... 53

3.2.3 Serial Timer Control Register (STCR) ................................................................ 55

3.3 Operating Mode Descriptions........................................................................................... 56

3.3.1 Mode 2................................................................................................................. 56

3.3.2 Mode 3................................................................................................................. 56

3.4 Address Map.....................................................................................................................57

Section 4 Exception Handling........................................................................... 59

4.1 Exception Handling Types and Priority............................................................................ 59

4.2 Exception Sources and Exception Vector Table............................................................... 60

4.3 Reset ................................................................................................................................. 61

4.3.1 Reset Exception Handling ................................................................................... 61

4.3.2 Interrupts after Reset............................................................................................ 62

4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................62

4.4 Interrupt Exception Handling ........................................................................................... 63

4.5 Trap Instruction Exception Handling................................................................................ 63

4.6 Stack Status after Exception Handling..............................................................................64

4.7 Usage Note........................................................................................................................65

Section 5 Interrupt Controller............................................................................ 67

5.1 Features............................................................................................................................. 67

5.2 Input/Output Pins.............................................................................................................. 68

5.3 Register Descriptions........................................................................................................ 69

5.3.1 Interrupt Control Registers A to C (ICRA to ICRC) ........................................... 69

5.3.2 Address Break Control Register (ABRKCR) ...................................................... 70

5.3.3 Break Address Registers A to C (BARA to BARC)............................................ 71

5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)................................................... 72

5.3.5 IRQ Enable Register (IER).................................................................................. 73

5.3.6 IRQ Status Register (ISR).................................................................................... 73

5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)

Wake-Up Event Interrupt Mask Register (WUEMRB)....................................... 73

5.4 Interrupt Sources...............................................................................................................76

Rev. 1.00, 05/04, page x of xxxiv

5.4.1 External Interrupts ...............................................................................................76

5.4.2 Internal Interrupts ................................................................................................77

5.5 Interrupt Exception Handling Vector Table...................................................................... 78

5.6 Interrupt Control Modes and Interrupt Operation............................................................. 80

5.6.1 Interrupt Control Mode 0..................................................................................... 80

5.6.2 Interrupt Control Mode 1..................................................................................... 82

5.6.3 Interrupt Exception Handling Sequence .............................................................. 85

5.6.4 Interrupt Response Times ....................................................................................86

5.7 Address Break...................................................................................................................87

5.7.1 Features................................................................................................................ 87

5.7.2 Block Diagram..................................................................................................... 87

5.7.3 Operation .............................................................................................................88

5.7.4 Usage Notes ......................................................................................................... 88

5.8 Usage Notes...................................................................................................................... 90

5.8.1 Conflict between Interrupt Generation and Disabling ......................................... 90

5.8.2 Instructions that Disable Interrupts...................................................................... 91

5.8.3 Interrupts during Execution of EEPMOV Instruction..........................................91

5.8.4 IRQ Status Register (ISR).................................................................................... 91

Section 6 Bus Controller (BSC).........................................................................93

6.1 Register Descriptions........................................................................................................ 93

6.1.1 Bus Control Register (BCR) ................................................................................ 93

6.1.2 Wait State Control Register (WSCR) ..................................................................94

Section 7 I/O Ports.............................................................................................95

7.1 Port 1................................................................................................................................. 100

7.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 100

7.1.2 Port 1 Data Register (P1DR)................................................................................100

7.1.3 Port 1 Pull-Up MOS Control Register (P1PCR).................................................. 101

7.1.4 Pin Functions ....................................................................................................... 101

7.1.5 Port 1 Input Pull-Up MOS ................................................................................... 102

7.2 Port 2................................................................................................................................. 102

7.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 102

7.2.2 Port 2 Data Register (P2DR)) .............................................................................. 103

7.2.3 Port 2 Pull-Up MOS Control Register (P2PCR).................................................. 103

7.2.4 Pin Functions ....................................................................................................... 103

7.2.5 Port 2 Input Pull-Up MOS ................................................................................... 104

7.3 Port 3................................................................................................................................. 104

7.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 104

7.3.2 Port 3 Data Register (P3DR)................................................................................105

7.3.3 Port 3 Pull-Up MOS Control Register (P3PCR).................................................. 105

7.3.4 Pin Functions ....................................................................................................... 106

7.3.5 Port 3 Input Pull-Up MOS ................................................................................... 106

Rev. 1.00, 05/04, page xi of xxxiv

7.4 Port 4................................................................................................................................. 107

7.4.1 Port 4 Data Direction Register (P4DDR)............................................................. 107

7.4.2 Port 4 Data Register (P4DR) ............................................................................... 107

7.4.3 Pin Functions ....................................................................................................... 108

7.5 Port 5................................................................................................................................. 110

7.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 110

7.5.2 Port 5 Data Register (P5DR) ............................................................................... 110

7.5.3 Pin Functions ....................................................................................................... 111

7.6 Port 6................................................................................................................................. 112

7.6.1 Port 6 Data Direction Register (P6DDR)............................................................. 112

7.6.2 Port 6 Data Register (P6DR) ............................................................................... 113

7.6.3 Port 6 Pull-Up MOS Control Register (KMPCR) ............................................... 113

7.6.4 System Control Register 2 (SYSCR2)................................................................. 114

7.6.5 Pin Functions ....................................................................................................... 114

7.6.6 Port 6 Input Pull-Up MOS................................................................................... 116

7.7 Port 7................................................................................................................................. 117

7.7.1 Port 7 Input Data Register (P7PIN) ..................................................................... 117

7.7.2 Pin Functions ....................................................................................................... 117

7.8 Port 8................................................................................................................................. 118

7.8.1 Port 8 Data Direction Register (P8DDR)............................................................. 118

7.8.2 Port 8 Data Register (P8DR) ............................................................................... 118

7.8.3 Pin Functions ....................................................................................................... 119

7.9 Port 9................................................................................................................................. 122

7.9.1 Port 9 Data Direction Register (P9DDR)............................................................. 122

7.9.2 Port 9 Data Register (P9DR) ............................................................................... 122

7.9.3 Pin Functions ....................................................................................................... 123

7.10 Port A................................................................................................................................ 125

7.10.1 Port A Data Direction Register (PADDR)........................................................... 125

7.10.2 Port A Output Data Register (PAODR)............................................................... 125

7.10.3 Port A Input Data Register (PAPIN) ................................................................... 126

7.10.4 Pin Functions .......................................................................................................126

7.10.5 Port A Input Pull-Up MOS .................................................................................. 128

7.11 Port B................................................................................................................................ 129

7.11.1 Port B Data Direction Register (PBDDR) ........................................................... 129

7.11.2 Port B Output Data Register (PBODR) ...............................................................129

7.11.3 Port B Input Data Register (PBPIN) .................................................................... 130

7.11.4 Pin Functions .......................................................................................................130

7.11.5 Port B Input Pull-Up MOS .................................................................................. 131

7.12 Ports C, D.......................................................................................................................... 132

7.12.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR) ........................ 132

7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR) ............................ 133

7.12.3 Port C and Port D Input Data Registers (PCPIN, PDPIN)................................... 133

7.12.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR) ................. 134

Rev. 1.00, 05/04, page xii of xxxiv

7.12.5 Pin Functions .......................................................................................................135

7.12.6 Input Pull-Up MOS in Ports C and D ..................................................................135

7.13 Ports E, F........................................................................................................................... 136

7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR) .......................... 136

7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR).............................. 137

7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)..................................... 138

7.13.4 Pin Functions .......................................................................................................138

7.13.5 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)................... 140

7.13.6 Pin Functions .......................................................................................................141

7.13.7 Input Pull-Up MOS in Ports E and F ................................................................... 141

7.14 Port G................................................................................................................................ 142

7.14.1 Port G Data Direction Register (PGDDR) ........................................................... 142

7.14.2 Port G Output Data Register (PGODR) ............................................................... 143

7.14.3 Port G Input Data Register (PGPIN).................................................................... 143

7.14.4 Pin Functions .......................................................................................................144

7.14.5 Port G Nch-OD Control Register (PGNOCR) ..................................................... 145

7.14.6 Pin Functions .......................................................................................................145

Section 8 8-Bit PWM Timer (PWM).................................................................147

8.1 Features............................................................................................................................. 147

8.2 Input/Output Pins .............................................................................................................. 148

8.3 Register Descriptions........................................................................................................ 148

8.3.1 PWM Register Select (PWSL)............................................................................. 149

8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0).................................................151

8.3.3 PWM Data Polarity Register A (PWDPRA) .......................................................151

8.3.4 PWM Output Enable Register A (PWOERA) ..................................................... 152

8.3.5 Peripheral Clock Select Register (PCSR) ............................................................152

8.4 Operation .......................................................................................................................... 153

8.4.1 PWM Setting Example ........................................................................................155

8.4.2 Diagram of PWM Used as D/A Converter ..........................................................155

8.5 Usage Notes...................................................................................................................... 156

8.5.1 Module Stop Mode Setting .................................................................................. 156

Section 9 16-Bit Free-Running Timer (FRT) ....................................................157

9.1 Features............................................................................................................................. 157

9.2 Input/Output Pins .............................................................................................................. 159

9.3 Register Descriptions........................................................................................................ 159

9.3.1 Free-Running Counter (FRC) .............................................................................. 160

9.3.2 Output Compare Registers A and B (OCRA, OCRB) .........................................160

9.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................160

9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF)............................... 161

9.3.5 Output Compare Register DM (OCRDM)........................................................... 161

9.3.6 Timer Interrupt Enable Register (TIER).............................................................. 162

Rev. 1.00, 05/04, page xiii of xxxiv

9.3.7 Timer Control/Status Register (TCSR)................................................................ 163

9.3.8 Timer Control Register (TCR)............................................................................. 166

9.3.9 Timer Output Compare Control Register (TOCR) .............................................. 167

9.4 Operation .......................................................................................................................... 169

9.4.1 Pulse Output ........................................................................................................ 169

9.5 Operation Timing.............................................................................................................. 170

9.5.1 FRC Increment Timing........................................................................................ 170

9.5.2 Output Compare Output Timing.......................................................................... 171

9.5.3 FRC Clear Timing ...............................................................................................171

9.5.4 Input Capture Input Timing ................................................................................. 172

9.5.5 Buffered Input Capture Input Timing .................................................................. 173

9.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 174

9.5.7 Timing of Output Compare Flag (OCF) setting...................................................174

9.5.8 Timing of FRC Overflow Flag Setting ................................................................ 175

9.5.9 Automatic Addition Timing................................................................................. 175

9.5.10 Mask Signal Generation Timing.......................................................................... 176

9.6 Interrupt Sources...............................................................................................................177

9.7 Usage Notes...................................................................................................................... 177

9.7.1 Conflict between FRC Write and Clear ............................................................... 177

9.7.2 Conflict between FRC Write and Increment........................................................ 178

9.7.3 Conflict between OCR Write and Compare-Match............................................. 178

9.7.4 Switching of Internal Clock and FRC Operation................................................. 180

9.7.5 Module Stop Mode Setting.................................................................................. 181

Section 10 8-Bit Timer (TMR)..........................................................................183

10.1 Features............................................................................................................................. 183

10.2 Input/Output Pins.............................................................................................................. 188

10.3 Register Descriptions........................................................................................................ 189

10.3.1 Timer Counter (TCNT)........................................................................................ 191

10.3.2 Time Constant Register A (TCORA) .................................................................. 191

10.3.3 Time Constant Register B (TCORB) ................................................................... 191

10.3.4 Timer Control Register (TCR)............................................................................. 192

10.3.5 Timer Control/Status Register (TCSR)................................................................ 196

10.3.6 Time Constant Register (TCORC)....................................................................... 202

10.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A) ... 202

10.3.8 Timer Input Select Register (TISR and TISR_B) ................................................ 202

10.3.9 Timer Connection Register I (TCONRI) .............................................................203

10.3.10 Timer Connection Register S (TCONRS) ...........................................................203

10.3.11 Timer XY Control Register (TCRXY) ................................................................ 204

10.3.12 Timer AB Control Register (TCRAB)................................................................. 205

10.4 Operation ..........................................................................................................................206

10.4.1 Pulse Output ........................................................................................................ 206

10.5 Operation Timing.............................................................................................................. 207

Rev. 1.00, 05/04, page xiv of xxxiv

10.5.1 TCNT Count Timing ........................................................................................... 207

10.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 207

10.5.3 Timing of Timer Output at Compare-Match........................................................ 208

10.5.4 Timing of Counter Clear at Compare-Match ....................................................... 208

10.5.5 TCNT External Reset Timing ..............................................................................209

10.5.6 Timing of Overflow Flag (OVF) Setting .............................................................209

10.6 TMR_0 and TMR_1 Cascaded Connection...................................................................... 210

10.6.1 16-Bit Count Mode ..............................................................................................210

10.6.2 Compare-Match Count Mode ..............................................................................210

10.7 TMR_Y and TMR_X Cascaded Connection ....................................................................211

10.7.1 16-Bit Count Mode ..............................................................................................211

10.7.2 Compare-Match Count Mode ..............................................................................211

10.7.3 Input Capture Operation ...................................................................................... 212

10.8 TMR_B and TMR_A Cascaded Connection ....................................................................212

10.8.1 16-Bit Count Mode ..............................................................................................212

10.8.2 Compare-Match Count Mode ..............................................................................212

10.8.3 Input Capture Operation ...................................................................................... 213

10.9 Interrupt Sources...............................................................................................................215

10.10 Usage Notes ......................................................................................................................216

10.10.1 Conflict between TCNT Write and Counter Clear...............................................216

10.10.2 Conflict between TCNT Write and Count-Up..................................................... 216

10.10.3 Conflict between TCOR Write and Compare-Match...........................................217

10.10.4 Conflict between Compare-Matches A and B .....................................................217

10.10.5 Switching of Internal Clocks and TCNT Operation.............................................218

10.10.6 Mode Setting with Cascaded Connection ............................................................ 219

10.10.7 Module Stop Mode Setting.................................................................................. 219

Section 11 Watchdog Timer (WDT)..................................................................221

11.1 Features............................................................................................................................. 221

11.2 Input/Output Pins.............................................................................................................. 223

11.3 Register Descriptions........................................................................................................ 223

11.3.1 Timer Counter (TCNT)........................................................................................ 223

11.3.2 Timer Control/Status Register (TCSR)................................................................ 224

11.4 Operation ..........................................................................................................................227

11.4.1 Watchdog Timer Mode ........................................................................................ 227

11.4.2 Interval Timer Mode ............................................................................................ 229

11.4.3 RESO Signal Output Timing ...............................................................................230

11.5 Interrupt Sources...............................................................................................................230

11.6 Usage Notes ...................................................................................................................... 231

11.6.1 Notes on Register Access..................................................................................... 231

11.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 232

11.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 232

11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 232

Rev. 1.00, 05/04, page xv of xxxiv

11.6.5 System Reset by RESO Signal ............................................................................ 233

11.6.6 Counter Values during Transitions between High-Speed, Sub-Active,

and Watch Modes ................................................................................................ 233

Section 12 Serial Communication Interface (SCI)............................................ 235

12.1 Features............................................................................................................................. 235

12.2 Input/Output Pins.............................................................................................................. 236

12.3 Register Descriptions........................................................................................................ 237

12.3.1 Receive Shift Register (RSR) .............................................................................. 237

12.3.2 Receive Data Register (RDR).............................................................................. 237

12.3.3 Transmit Data Register (TDR)............................................................................. 237

12.3.4 Transmit Shift Register (TSR) ............................................................................. 238

12.3.5 Serial Mode Register (SMR) ............................................................................... 238

12.3.6 Serial Control Register (SCR) ............................................................................. 239

12.3.7 Serial Status Register (SSR) ................................................................................241

12.3.8 Serial Interface Mode Register (SCMR).............................................................. 243

12.3.9 Bit Rate Register (BRR) ...................................................................................... 244

12.3.10 Serial Pin Select Register (SPSR)........................................................................ 249

12.4 Operation in Asynchronous Mode .................................................................................... 249

12.4.1 Data Transfer Format........................................................................................... 250

12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 251

12.4.3 Clock.................................................................................................................... 251

12.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 253

12.4.5 Data Transmission (Asynchronous Mode) .......................................................... 254

12.4.6 Serial Data Reception (Asynchronous Mode) ..................................................... 256

12.5 Multiprocessor Communication Function......................................................................... 259

12.5.1 Multiprocessor Serial Data Transmission ............................................................ 260

12.5.2 Multiprocessor Serial Data Reception ................................................................. 261

12.6 Operation in Clocked Synchronous Mode........................................................................ 264

12.6.1 Clock.................................................................................................................... 264

12.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 265

12.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 266

12.6.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 268

12.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode) ............................................................................. 269

12.7 Interrupt Sources...............................................................................................................271

12.8 Usage Notes ...................................................................................................................... 272

12.8.1 Module Stop Mode Setting .................................................................................. 272

12.8.2 Break Detection and Processing .......................................................................... 272

12.8.3 Mark State and Break Detection .......................................................................... 272

12.8.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) .................................................................... 272

12.8.5 Relation between Writing to TDR and TDRE Flag ............................................. 272

Rev. 1.00, 05/04, page xvi of xxxiv

12.8.6 SCI Operations during Mode Transitions ............................................................273

12.8.7 Switching from SCK Pins to Port Pins ................................................................276

Section 13 I2C Bus Interface (IIC) .....................................................................277

13.1 Features............................................................................................................................. 277

13.2 Input/Output Pins.............................................................................................................. 280

13.3 Register Descriptions........................................................................................................ 281

13.3.1 I2C Bus Data Register (ICDR) ............................................................................. 282

13.3.2 Slave Address Register (SAR)............................................................................. 283

13.3.3 Second Slave Address Register (SARX) .............................................................284

13.3.4 I2C Bus Mode Register (ICMR)........................................................................... 286

13.3.5 I2C Bus Control Register (ICCR)......................................................................... 289

13.3.6 I2C Bus Status Register (ICSR)............................................................................ 297

13.3.7 DDC Switch Register (DDCSWR) ......................................................................301

13.3.8 I2C Bus Extended Control Register (ICXR)......................................................... 302

13.3.9 Port G Control Register (PGCTL) .......................................................................306

13.4 Operation ..........................................................................................................................307

13.4.1 I2C Bus Data Format ............................................................................................ 307

13.4.2 Initialization ......................................................................................................... 309

13.4.3 Master Transmit Operation .................................................................................. 309

13.4.4 Master Receive Operation.................................................................................... 314

13.4.5 Slave Receive Operation...................................................................................... 321

13.4.6 Slave Transmit Operation ....................................................................................328

13.4.7 IRIC Setting Timing and SCL Control ................................................................331

13.4.8 Noise Canceller.................................................................................................... 334

13.4.9 Initialization of Internal State .............................................................................. 335

13.5 Interrupt Sources...............................................................................................................336

13.6 Usage Notes ...................................................................................................................... 337

13.6.1 Module Stop Mode Setting .................................................................................. 347

Section 14 Keyboard Buffer Controller.............................................................349

14.1 Features............................................................................................................................. 349

14.2 Input/Output Pins.............................................................................................................. 350

14.3 Register Descriptions........................................................................................................ 351

14.3.1 Keyboard Control Register H (KBCRH) ............................................................. 351

14.3.2 Keyboard Control Register L (KBCRL) .............................................................. 353

14.3.3 Keyboard Data Buffer Register (KBBR) .............................................................354

14.4 Operation ..........................................................................................................................355

14.4.1 Receive Operation................................................................................................ 355

14.4.2 Transmit Operation .............................................................................................. 356

14.4.3 Receive Abort ......................................................................................................359

14.4.4 KCLKI and KDI Read Timing............................................................................. 361

14.4.5 KCLKO and KDO Write Timing......................................................................... 361

Rev. 1.00, 05/04, page xvii of xxxiv

14.4.6 KBF Setting Timing and KCLK Control............................................................. 362

14.4.7 Receive Timing.................................................................................................... 363

14.4.8 KCLK Fall Interrupt Operation ........................................................................... 364

14.5 Usage Notes ...................................................................................................................... 365

14.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................365

14.5.2 Module Stop Mode Setting .................................................................................. 366

Section 15 Host Interface (LPC) .......................................................................369

15.1 Features............................................................................................................................. 369

15.2 Input/Output Pins.............................................................................................................. 371

15.3 Register Descriptions........................................................................................................ 372

15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) ................................ 373

15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) ................................ 379

15.3.3 LPC Channel 3 Address Register (LADR3) ........................................................ 381

15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................382

15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) .................................................. 383

15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) .................................... 383

15.3.7 Status Registers 1 to 3 (STR1 to STR3) .............................................................. 383

15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) ...............................389

15.3.9 Host Interface Select Register (HISEL)............................................................... 397

15.4 Operation ..........................................................................................................................398

15.4.1 Host Interface Activation..................................................................................... 398

15.4.2 LPC I/O Cycles.................................................................................................... 399

15.4.3 A20 Gate .............................................................................................................. 400

15.4.4 Host Interface Shutdown Function (LPCPD) ...................................................... 403

15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) ....................................407

15.4.6 Host Interface Clock Start Request (CLKRUN).................................................. 409

15.5 Interrupt Sources...............................................................................................................410

15.5.1 IBFI1, IBFI2, IBFI3, and ERRI ........................................................................... 410

15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 ....................... 410

15.6 Usage Notes ...................................................................................................................... 413

15.6.1 Module Stop Mode Setting .................................................................................. 413

15.6.2 Notes on Using Host Interface............................................................................. 413

Section 16 A/D Converter ................................................................................. 413

16.1 Features............................................................................................................................. 413

16.2 Input/Output Pins.............................................................................................................. 415

16.3 Register Descriptions........................................................................................................ 416

16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 416

16.3.2 A/D Control/Status Register (ADCSR) ...............................................................417

16.3.3 A/D Control Register (ADCR) ............................................................................ 418

16.4 Operation ..........................................................................................................................419

16.4.1 Single Mode......................................................................................................... 419

Rev. 1.00, 05/04, page xviii of xxxiv

16.4.2 Scan Mode ...........................................................................................................419

16.4.3 Input Sampling and A/D Conversion Time ......................................................... 421

16.4.4 External Trigger Input Timing............................................................................. 422

16.5 Interrupt Sources...............................................................................................................423

16.6 A/D Conversion Accuracy Definitions............................................................................. 423

16.7 Usage Notes ...................................................................................................................... 425

16.7.1 Permissible Signal Source Impedance ................................................................. 425

16.7.2 Influences on Absolute Accuracy ........................................................................425

16.7.3 Setting Range of Analog Power Supply and Other Pins...................................... 426

16.7.4 Notes on Board Design ........................................................................................ 426

16.7.5 Notes on Noise Countermeasures ........................................................................426

16.7.6 Module Stop Mode Setting .................................................................................. 427

Section 17 RAM ................................................................................................429

Section 18 ROM ................................................................................................431

18.1 Features............................................................................................................................. 431

18.2 Mode Transitions .............................................................................................................. 433

18.3 Block Configuration.......................................................................................................... 436

18.4 Input/Output Pins.............................................................................................................. 437

18.5 Register Descriptions........................................................................................................ 437

18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 438

18.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 439

18.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) .................................................... 440

18.6 Operating Modes............................................................................................................... 441

18.7 On-Board Programming Modes........................................................................................ 441

18.7.1 Boot Mode ...........................................................................................................442

18.7.2 User Program Mode............................................................................................. 445

18.8 Flash Memory Programming/Erasing............................................................................... 446

18.8.1 Program/Program-Verify ..................................................................................... 446

18.8.2 Erase/Erase-Verify............................................................................................... 448

18.9 Program/Erase Protection .................................................................................................450

18.9.1 Hardware Protection ............................................................................................450

18.9.2 Software Protection.............................................................................................. 450

18.9.3 Error Protection.................................................................................................... 450

18.10 Interrupts during Flash Memory Programming/Erasing ................................................... 451

18.11 Programmer Mode ............................................................................................................452

18.12 Usage Notes ......................................................................................................................453

Section 19 Clock Pulse Generator .....................................................................455

19.1 Oscillator........................................................................................................................... 456

19.1.1 Connecting Crystal Resonator ............................................................................. 456

19.1.2 External Clock Input Method............................................................................... 457

Rev. 1.00, 05/04, page xix of xxxiv

19.2 Duty Correction Circuit .................................................................................................... 459

19.3 Medium-Speed Clock Divider .......................................................................................... 459

19.4 Bus Master Clock Select Circuit....................................................................................... 459

19.5 Subclock Input Circuit ...................................................................................................... 460

19.6 Waveform Forming Circuit............................................................................................... 460

19.7 Clock Select Circuit .......................................................................................................... 461

19.8 Usage Notes ...................................................................................................................... 461

19.8.1 Note on Resonator ............................................................................................... 461

19.8.2 Notes on Board Design ........................................................................................ 461

Section 20 Power-Down Modes........................................................................ 463

20.1 Register Descriptions........................................................................................................ 463

20.1.1 Standby Control Register (SBYCR) .................................................................... 464

20.1.2 Low-Power Control Register (LPWRCR) ........................................................... 465

20.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) ................... 467

20.2 Mode Transitions and LSI States...................................................................................... 468

20.3 Medium-Speed Mode .......................................................................................................470

20.4 Sleep Mode ....................................................................................................................... 471

20.5 Software Standby Mode.................................................................................................... 471

20.6 Hardware Standby Mode .................................................................................................. 473

20.7 Watch Mode......................................................................................................................474

20.8 Subsleep Mode.................................................................................................................. 475

20.9 Subactive Mode ................................................................................................................476

20.10 Module Stop Mode ........................................................................................................... 477

20.11 Direct Transitions ............................................................................................................. 477

20.12 Usage Notes ......................................................................................................................478

20.12.1 I/O Port Status...................................................................................................... 478

20.12.2 Current Consumption when Waiting for Oscillation Stabilization ...................... 478

Section 21 List of Registers............................................................................... 479

21.1 Register Addresses (Address Order)................................................................................. 480

21.2 Register Bits...................................................................................................................... 489

21.3 Register States in Each Operating Mode ..........................................................................497

21.4 Register Select Conditions................................................................................................ 505

Section 22 Electrical Characteristics .................................................................513

22.1 Absolute Maximum Ratings ............................................................................................. 513

22.2 DC Characteristics ............................................................................................................ 514

22.3 AC Characteristics ............................................................................................................ 520

22.3.1 Clock Timing ....................................................................................................... 521

22.3.2 Control Signal Timing .........................................................................................522

22.3.3 Timing of On-Chip Peripheral Modules .............................................................. 523

22.4 A/D Conversion Characteristics ....................................................................................... 526

Rev. 1.00, 05/04, page xx of xxxiv

22.5 Flash Memory Characteristics ..........................................................................................527

22.6 Usage Note........................................................................................................................ 529

22.7 Timing Chart..................................................................................................................... 529

22.7.1 Clock Timing ....................................................................................................... 529

22.7.2 Control Signal Timing .........................................................................................531

22.7.3 On-Chip Peripheral Module Timing ....................................................................532

Appendix .........................................................................................................537

A. I/O Port States in Each Processing State........................................................................... 537

B. Product Codes ...................................................................................................................538

C. Package Dimensions .........................................................................................................539

Index .........................................................................................................541

Rev. 1.00, 05/04, page xxi of xxxiv

Rev. 1.00, 05/04, page xxii of xxxiv

Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram.................................................................................................2

Figure 1.2 Pin Arrangement............................................................................................................3

Section 2 CPU

Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 17

Figure 2.2 Stack Structure in Normal Mode................................................................................. 17

Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 18

Figure 2.4 Stack Structure in Advanced Mode............................................................................. 19

Figure 2.5 Memory Map............................................................................................................... 20

Figure 2.6 CPU Internal Registers................................................................................................ 21

Figure 2.7 Usage of General Registers .........................................................................................22

Figure 2.8 Stack............................................................................................................................ 23

Figure 2.9 General Register Data Formats (1).............................................................................. 26

Figure 2.9 General Register Data Formats (2).............................................................................. 27

Figure 2.10 Memory Data Formats...............................................................................................28

Figure 2.11 Instruction Formats (Examples) ................................................................................ 39

Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode...................... 43

Figure 2.13 State Transitions........................................................................................................ 47

Section 3 MCU Operating Modes

Figure 3.1 Address Map for H8S/2111B-B .................................................................................. 57

Figure 3.2 Address Map for H8S/2111B-C .................................................................................. 58

Section 4 Exception Handling

Figure 4.1 Reset Sequence (Mode 3)............................................................................................61

Figure 4.2 Stack Status after Exception Handling........................................................................ 64

Figure 4.3 Operation when SP Value is Odd................................................................................ 65

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 68

Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0,

Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB..... 75

Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0................................................................ 76

Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0.......81

Figure 5.5 State Transition in Interrupt Control Mode 1 .............................................................. 82

Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 84

Figure 5.7 Interrupt Exception Handling...................................................................................... 85

Figure 5.8 Address Break Block Diagram.................................................................................... 87

Figure 5.9 Address Break Timing Example .................................................................................89

Figure 5.10 Conflict between Interrupt Generation and Disabling............................................... 90

Rev. 1.00, 05/04, page xxiii of xxxiv

Section 8 8-Bit PWM Timer (PWM)

Figure 8.1 Block Diagram of PWM Timer................................................................................. 147

Figure 8.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 154

Figure 8.3 Example of PWM Setting..........................................................................................155

Figure 8.4 Example when PWM is Used as D/A Converter....................................................... 155

Section 9 16-Bit Free-Running Timer (FRT)

Figure 9.1 Block Diagram of 16-Bit Free-Running Timer ......................................................... 158

Figure 9.2 Example of Pulse Output...........................................................................................169

Figure 9.3 Increment Timing with Internal Clock Source .......................................................... 170

Figure 9.4 Increment Timing with External Clock Source......................................................... 170

Figure 9.5 Timing of Output Compare A Output....................................................................... 171

Figure 9.6 Clearing of FRC by Compare-Match A Signal ......................................................... 171

Figure 9.7 Input Capture Input Signal Timing (Usual Case)...................................................... 172

Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read) ......................172

Figure 9.9 Buffered Input Capture Timing................................................................................. 173

Figure 9.10 Buffered Input Capture Timing (BUFEA = 1)........................................................ 173

Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting.................... 174

Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting................................... 174

Figure 9.13 Timing of Overflow Flag (OVF) Setting................................................................. 175

Figure 9.14 OCRA Automatic Addition Timing ........................................................................ 175

Figure 9.15 Timing of Input Capture Mask Signal Setting......................................................... 176

Figure 9.16 Timing of Input Capture Mask Signal Clearing ...................................................... 176

Figure 9.17 FRC Write-Clear Conflict ....................................................................................... 177

Figure 9.18 FRC Write-Increment Conflict................................................................................ 178

Figure 9.19 Conflict between OCR Write and Compare-Match

(When Automatic Addition Function is Not Used) .................................................179

Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match

(When Automatic Addition Function is Used) ........................................................ 179

Section 10 8-Bit Timer (TMR)

Figure 10.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 185

Figure 10.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 186

Figure 10.3 Block Diagram of 8-Bit Timer (TMR_B and TMR_A).......................................... 187

Figure 10.4 Pulse Output Example............................................................................................. 206

Figure 10.5 Count Timing for Internal Clock Input ...................................................................207

Figure 10.6 Count Timing for External Clock Input (Both Edges) ............................................207

Figure 10.7 Timing of CMF Setting at Compare-Match............................................................ 208

Figure 10.8 Timing of Toggled Timer Output by Compare-Match A Signal............................. 208

Figure 10.9 Timing of Counter Clear by Compare-Match ......................................................... 208

Figure 10.10 Timing of Counter Clear by External Reset Input................................................. 209

Figure 10.11 Timing of OVF Flag Setting ................................................................................. 209

Figure 10.12 Timing of Input Capture Operation....................................................................... 213

Rev. 1.00, 05/04, page xxiv of xxxiv

Figure 10.13 Timing of Input Capture Signal

(Input capture signal is input during TICRR and TICRF read) ............................. 213

Figure 10.14 Conflict between TCNT Write and Clear.............................................................. 216

Figure 10.15 Conflict between TCNT Write and Count-Up.......................................................216

Figure 10.16 Conflict between TCOR Write and Compare-Match............................................ 217

Section 11 Watchdog Timer (WDT)

Figure 11.1 Block Diagram of WDT.......................................................................................... 222

Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 228

Figure 11.3 Interval Timer Mode Operation............................................................................... 229

Figure 11.4 OVF Flag Set Timing .............................................................................................. 229

Figure 11.5 Output Timing of RESO signal ...............................................................................230

Figure 11.6 Writing to TCNT and TCSR (WDT_0)................................................................... 231

Figure 11.7 Conflict between TCNT Write and Increment ........................................................ 232

Figure 11.8 Sample Circuit for Resetting System by RESO Signal ...........................................233

Section 12 Serial Communication Interface (SCI)

Figure 12.1 Block Diagram of SCI............................................................................................. 236

Figure 12.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................249

Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................251

Figure 12.4 Relation between Output Clock and Transmit Data Phase

(Asynchronous Mode) ............................................................................................ 252

Figure 12.5 Sample SCI Initialization Flowchart .......................................................................253

Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 254

Figure 12.7 Sample Serial Transmission Flowchart ................................................................... 255

Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 256

Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 257

Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 258

Figure 12.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A).......................................... 259

Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart........................................ 260

Figure 12.12 Example of SCI Receive Operation

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 261

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 262

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 263

Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 264

Figure 12.15 Sample SCI Initialization Flowchart ..................................................................... 265

Figure 12.16 Example of SCI Transmit Operation in Clocked Synchronous Mode................... 266

Figure 12.17 Sample Serial Transmission Flowchart................................................................. 267

Figure 12.18 Example of SCI Receive Operation in Clocked Synchronous Mode ....................268

Figure 12.19 Sample Serial Reception Flowchart ......................................................................269

Rev. 1.00, 05/04, page xxv of xxxiv

Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 270

Figure 12.21 Sample Flowchart for Mode Transition during Transmission............................... 274

Figure 12.22 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............274

Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode

(Internal Clock)..................................................................................................... 275

Figure 12.24 Sample Flowchart for Mode Transition during Reception.................................... 275

Figure 12.25 Switching from SCK Pins to Port Pins.................................................................. 276

Figure 12.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins..........276

Section 13 I2C Bus Interface (IIC)

Figure 13.1 Block Diagram of I2C Bus Interface ....................................................................... 278

Figure 13.2 I2C Bus Interface Connections (Example: This LSI as Master).............................. 279

Figure 13.3 I2C Bus Data Format (I2C Bus Format)................................................................... 307

Figure 13.4 I2C Bus Data Format (Serial Format)...................................................................... 307

Figure 13.5 I2C Bus Timing........................................................................................................ 308

Figure 13.6 Sample Flowchart for IIC Initialization .................................................................. 309

Figure 13.7 Sample Flowchart for Operations in Master Transmit Mode.................................. 310

Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ...... 312

Figure 13.9 Example of Stop Condition Issuance Operation Timing

in Master Transmit Mode (MLS = WAIT = 0)....................................................... 313

Figure 13.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)............. 314

Figure 13.11 Example of Operation Timing in Master Receive Mode

(MLS = WAIT = 0, HNDS = 1)............................................................................ 316

Figure 13.12 Example of Stop Condition Issuance Operation Timing

in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ...................................316

Figure 13.13 Sample Flowchart for Operations in Master Receive Mode

(receiving multiple bytes) (WAIT = 1)................................................................. 317

Figure 13.14 Sample Flowchart for Operations in Master Receive Mode

(receiving a single byte) (WAIT = 1) ................................................................... 318

Figure 13.15 Example of Master Receive Mode Operation Timing

(MLS = ACKB = 0, WAIT = 1) ...........................................................................320

Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode

(MLS = ACKB = 0, WAIT = 1) ...........................................................................321

Figure 13.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)............... 322

Figure 13.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) ... 324
Figure 13.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) ... 324

Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)............... 325

Figure 13.21 Example of Slave Receive Mode Operation Timing (1)

(MLS = ACKB = 0, HNDS = 0)........................................................................... 327

Figure 13.22 Example of Slave Receive Mode Operation Timing (2)

(MLS = ACKB = 0, HNDS = 0)........................................................................... 327

Figure 13.23 Sample Flowchart for Slave Transmit Mode......................................................... 328

Figure 13.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) ......................... 330

Rev. 1.00, 05/04, page xxvi of xxxiv

Figure 13.25 IRIC Setting Timing and SCL Control (1) ............................................................ 331

Figure 13.26 IRIC Setting Timing and SCL Control (2) ............................................................ 332

Figure 13.27 IRIC Setting Timing and SCL Control (3) ............................................................ 333

Figure 13.28 Block Diagram of Noise Canceler......................................................................... 334

Figure 13.29 Notes on Reading Master Receive Data................................................................ 340

Figure 13.30 Flowchart for Start Condition Issuance Instruction for Retransmission

and Timing............................................................................................................. 341

Figure 13.31 Stop Condition Issuance Timing ........................................................................... 342

Figure 13.32 IRIC Flag Clearing Timing when WAIT = 1 ........................................................ 343

Figure 13.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 344

Figure 13.34 TRS Bit Set Timing in Slave Mode....................................................................... 345

Figure 13.35 Diagram of Erroneous Operation when Arbitration is Lost................................... 347

Section 14 Keyboard Buffer Controller

Figure 14.1 Block Diagram of Keyboard Buffer Controller....................................................... 349

Figure 14.2 Keyboard Buffer Controller Connection................................................................. 350

Figure 14.3 Sample Receive Processing Flowchart.................................................................... 355

Figure 14.4 Receive Timing .......................................................................................................356

Figure 14.5 Sample Transmit Processing Flowchart (1)............................................................ 357

Figure 14.5 Sample Transmit Processing Flowchart (2)............................................................. 358

Figure 14.6 Transmit Timing...................................................................................................... 358

Figure 14.7 Sample Receive Abort Processing Flowchart (1)................................................... 359

Figure 14.7 Sample Receive Abort Processing Flowchart (2)................................................... 360

Figure 14.8 Receive Abort and Transmit Start

(Transmission/Reception Switchover) Timing ....................................................... 360

Figure 14.9 KCLKI and KDI Read Timing................................................................................ 361

Figure 14.10 KCLKO and KDO Write Timing.......................................................................... 361

Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing ..................... 362

Figure 14.12 Receive Counter and KBBR Data Load Timing ...................................................363

Figure 14.13 Example of KCLK Input Fall Interrupt Operation ................................................ 364

Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing .................................365

Section 15 Host Interface (LPC)

Figure 15.1 Block Diagram of LPC............................................................................................ 370

Figure 15.2 Typical LFRAME Timing ....................................................................................... 400

Figure 15.3 Abort Mechanism.................................................................................................... 400

Figure 15.4 GA20 Output........................................................................................................... 401

Figure 15.5 Power-Down State Termination Timing ................................................................. 406

Figure 15.6 SERIRQ Timing...................................................................................................... 407

Figure 15.7 Clock Start Request Timing ....................................................................................409

Figure 15.8 HIRQ Flowchart (Example of Channel 1)............................................................... 412

Rev. 1.00, 05/04, page xxvii of xxxiv

Section 16 A/D Converter

Figure 16.1 Block Diagram of A/D Converter ........................................................................... 414

Figure 16.2 Example of A/D Converter Operation

(Scan Mode, Channels AN0 to AN2 Selected)....................................................... 420

Figure 16.3 A/D Conversion Timing.......................................................................................... 421

Figure 16.4 External Trigger Input Timing ................................................................................ 422

Figure 16.5 A/D Conversion Accuracy Definitions ...................................................................424

Figure 16.6 A/D Conversion Accuracy Definitions ...................................................................424

Figure 16.7 Example of Analog Input Circuit ............................................................................ 425

Figure 16.8 Example of Analog Input Protection Circuit........................................................... 427

Figure 16.9 Equivalent Circuit of Analog Input Pin................................................................... 427

Section 18 ROM

Figure 18.1 Block Diagram of Flash Memory............................................................................ 432

Figure 18.2 Flash Memory State Transitions.............................................................................. 433

Figure 18.3 Boot Mode............................................................................................................... 434

Figure 18.4 User Program Mode (Example) ..............................................................................435

Figure 18.5 Flash Memory Block Configuration........................................................................ 436

Figure 18.6 On-Chip RAM Area in Boot Mode......................................................................... 444

Figure 18.7 ID Code Area ..........................................................................................................444

Figure 18.8 Programming/Erasing Flowchart Example in User Program Mode........................ 445

Figure 18.9 Program/Program-Verify Flowchart .......................................................................447

Figure 18.10 Erase/Erase-Verify Flowchart ............................................................................... 449

Figure 18.11 Memory Map in Programmer Mode......................................................................452

Section 19 Clock Pulse Generator

Figure 19.1 Block Diagram of Clock Pulse Generator ............................................................... 455

Figure 19.2 Typical Connection to Crystal Resonator................................................................ 456

Figure 19.3 Equivalent Circuit of Crystal Resonator..................................................................456

Figure 19.4 Example of External Clock Input............................................................................ 457

Figure 19.5 External Clock Input Timing................................................................................... 458

Figure 19.6 Timing of External Clock Output Stabilization Delay Time................................... 459

Figure 19.7 Subclock Input Timing............................................................................................ 460

Figure 19.8 Note on Board Design of Oscillator Circuit Section............................................... 461

Section 20 Power-Down Modes

Figure 20.1 Mode Transition Diagram ....................................................................................... 468

Figure 20.2 Medium-Speed Mode Timing ................................................................................. 470

Figure 20.3 Application Example in Software Standby Mode ................................................... 472

Figure 20.4 Hardware Standby Mode Timing ............................................................................ 473

Section 22 Electrical Characteristics

Figure 22.1 Darlington Pair Drive Circuit (Example) ................................................................ 518

Figure 22.2 LED Drive Circuit (Example) ................................................................................. 519

Figure 22.3 Output Load Circuit ................................................................................................ 520

Rev. 1.00, 05/04, page xxviii of xxxiv

Figure 22.4 Connection of VCL Capacitor................................................................................. 529

Figure 22.5 System Clock Timing.............................................................................................. 529

Figure 22.6 Oscillation Settling Timing .....................................................................................530

Figure 22.7 Oscillation Setting Timing (Exiting Software Standby Mode)................................ 530

Figure 22.8 Reset Input Timing.................................................................................................. 531

Figure 22.9 Interrupt Input Timing............................................................................................. 531

Figure 22.10 I/O Port Input/Output Timing................................................................................ 532

Figure 22.11 FRT Input/Output Timing ..................................................................................... 532

Figure 22.12 FRT Clock Input Timing....................................................................................... 532

Figure 22.13 8-Bit Timer Output Timing ................................................................................... 533

Figure 22.14 8-Bit Timer Clock Input Timing ........................................................................... 533

Figure 22.15 8-Bit Timer Reset Input Timing............................................................................ 533

Figure 22.16 PWM, PWMX Output Timing .............................................................................. 533

Figure 22.17 SCK Clock Input Timing.......................................................................................534

Figure 22.18 SCI Input/Output Timing (Synchronous Mode).................................................... 534

Figure 22.19 A/D Converter External Trigger Input Timing...................................................... 534

Figure 22.20 WDT Output Timing (RESO) ...............................................................................534

Figure 22.21 Keyboard Buffer Controller Timing...................................................................... 535

Figure 22.22 I2C Bus Interface Input/Output Timing................................................................. 535

Figure 22.23 Host Interface (LPC) Timing................................................................................. 536

Figure 22.24 Tester Measurement Condition .............................................................................536

Appendix

Figure C.1 Package Dimensions (TFP-144) ............................................................................... 539

Rev. 1.00, 05/04, page xxix of xxxiv

Rev. 1.00, 05/04, page xxx of xxxiv

Tables

Section 1 Overview

Table 1.1

Table 1.2 Pin Functions ............................................................................................................ 9

Section 2 CPU

Table 2.1

Table 2.2 Operation Notation .................................................................................................30

Table 2.3 Data Transfer Instructions.......................................................................................31

Table 2.4 Arithmetic Operations Instructions (1) ................................................................... 32

Table 2.4 Arithmetic Operations Instructions (2) ................................................................... 33

Table 2.5 Logic Operations Instructions................................................................................. 34

Table 2.6 Shift Instructions..................................................................................................... 34

Table 2.7 Bit Manipulation Instructions (1)............................................................................ 35

Table 2.7 Bit Manipulation Instructions (2)............................................................................ 36

Table 2.8 Branch Instructions................................................................................................. 37

Table 2.9 System Control Instructions.................................................................................... 38

Table 2.10 Block Data Transfer Instructions............................................................................ 38

Table 2.11 Addressing Modes .................................................................................................. 40

Table 2.12 Absolute Address Access Ranges ........................................................................... 41

Table 2.13 Effective Address Calculation (1)........................................................................... 44

Table 2.13 Effective Address Calculation (2)........................................................................... 45

Pin Functions in Each Operating Mode .................................................................... 4

Instruction Classification........................................................................................ 29

Section 3 MCU Operating Modes

Table 3.1

Section 4 Exception Handling

Table 4.1

Table 4.2 Exception Handling Vector Table...........................................................................60

Table 4.3 Status of CCR after Trap Instruction Exception Handling .....................................63

Section 5 Interrupt Controller

Table 5.1

Table 5.2 Correspondence between Interrupt Source and ICR............................................... 70

Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities.................................78

Table 5.4 Interrupt Control Modes .........................................................................................80

Table 5.5 Interrupt Response Times .......................................................................................86

Table 5.6 Number of States in Interrupt Handling Routine Execution Status ........................ 86

Section 7 I/O Ports

Table 7.1

Table 7.2 Input Pull-Up MOS States (Port 1)....................................................................... 102

Table 7.3 Input Pull-Up MOS States (Port 2)....................................................................... 104

MCU Operating Mode Selection ............................................................................ 51

Exception Types and Priority..................................................................................59

Pin Configuration....................................................................................................68

Port Functions......................................................................................................... 96

Rev. 1.00, 05/04, page xxxi of xxxiv

Table 7.4 Input Pull-Up MOS States (Port 3)....................................................................... 106

Table 7.5 Input Pull-Up MOS States (Port 6)....................................................................... 116

Table 7.6 Input Pull-Up MOS States (Port A)...................................................................... 128

Table 7.7 Input Pull-Up MOS States (Port B) ...................................................................... 131

Table 7.8 Input Pull-Up MOS States (Port C and port D) .................................................... 135

Table 7.9 Input Pull-Up MOS States (Port E and port F) ..................................................... 141

Section 8 8-Bit PWM Timer (PWM)

Table 8.1

Table 8.2 Internal Clock Selection........................................................................................ 150

Table 8.3 Resolution, PWM Conversion Period,

Table 8.4 Duty Cycle of Basic Pulse .................................................................................... 153

Table 8.5 Position of Pulses Added to Basic Pulses ............................................................. 154

Section 9 16-Bit Free-Running Timer (FRT)

Table 9.1

Table 9.2 FRT Interrupt Sources .......................................................................................... 177

Table 9.3 Switching of Internal Clock and FRC Operation.................................................. 180

Section 10 8-Bit Timer (TMR)

Table 10.1

Table 10.2 Pin Configuration.................................................................................................. 188

Table 10.3 Clock Input to TCNT and Count Condition (1).................................................... 193

Table 10.3 Clock Input to TCNT and Count Condition (2).................................................... 194

Table 10.3 Clock Input to TCNT and Count Condition (3).................................................... 195

Table 10.4 Registers Accessible by TMR_X/TMR_Y ........................................................... 204

Table 10.5 Input Capture Signal Selection ............................................................................. 214

Table 10.6 Input Capture Signal Selection ............................................................................. 214

Table 10.7 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y,

Table 10.8 Timer Output Priorities......................................................................................... 217

Table 10.9 Switching of Internal Clocks and TCNT Operation ............................................. 218

Pin Configuration..................................................................................................148

and Carrier Frequency when φ = 10 MHz ............................................................150

Pin Configuration..................................................................................................159

TMR Function ...................................................................................................... 184

TMR_X TMR_B, and TMR_A ............................................................................ 215

Section 11 Watchdog Timer (WDT)

Table 11.1

Table 11.2 WDT Interrupt Source .......................................................................................... 230

Section 12 Serial Communication Interface (SCI)

Table 12.1

Table 12.2 Relationships between N Setting in BRR and Bit Rate B..................................... 244

Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)........................... 245

Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)........................... 246

Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................247

Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................247

Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 248

Rev. 1.00, 05/04, page xxxii of xxxiv

Pin Configuration.................................................................................................. 223

Pin Configuration.................................................................................................. 236

Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ....248

Table 12.8 Serial Transfer Formats (Asynchronous Mode).................................................... 250

Table 12.9 SSR Status Flags and Receive Data Handling...................................................... 257

Table 12.10 SCI Interrupt Sources........................................................................................ 271

Section 13 I2C Bus Interface (IIC)

Table 13.1

Table 13.2 Communication Format ........................................................................................ 285

Table 13.3 I2C Transfer Rate .................................................................................................. 288

Table 13.4 Flags and Transfer States (Master Mode)............................................................. 294

Table 13.5 Flags and Transfer States (Slave Mode) ............................................................... 295

Table 13.5 Flags and Transfer States (Slave Mode) (cont)..................................................... 296

Table 13.6 I2C Bus Data Format Symbols.............................................................................. 308

Table 13.7 IIC Interrupt Sources ............................................................................................336

Table 13.8 I2C Bus Timing (SCL and SDA Outputs) ............................................................. 337

Table 13.9 Permissible SCL Rise Time (tsr) Values ...............................................................338

Table 13.10 I2C Bus Timing (with Maximum Influence of tSr/tSf)........................................ 339

Section 14 Keyboard Buffer Controller

Table 14.1

Section 15 Host Interface (LPC)

Table 15.1

Table 15.2 Register Selection ................................................................................................. 382

Table 15.3 GA20 (P81) Set/Clear Timing ..............................................................................401

Table 15.4 Fast A20 Gate Output Signals..............................................................................402

Table 15.5 Scope of Host Interface Pin Shutdown ................................................................. 404

Table 15.6 Scope of Initialization in Each Host Interface Mode............................................ 405

Table 15.7 Receive Complete Interrupts and Error Interrupt.................................................. 410

Table 15.8 HIRQ Setting and Clearing Conditions ................................................................411

Pin Configuration.................................................................................................. 280

Pin Configuration.................................................................................................. 350

Pin Configuration.................................................................................................. 371

Section 16 A/D Converter

Table 16.1

Table 16.2 Analog Input Channels and Corresponding ADDR Registers .............................. 416

Table 16.3 A/D Conversion Time (Single Mode)...................................................................422

Section 18 ROM

Table 18.1

Table 18.2 Pin Configuration.................................................................................................. 437

Table 18.3 Operating Modes and ROM.................................................................................. 441

Table 18.4 On-Board Programming Mode Settings ...............................................................441

Table 18.5 Boot Mode Operation ........................................................................................... 443

Table 18.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Pin Configuration.................................................................................................. 415

Differences between Boot Mode and User Program Mode .................................. 433

Possible................................................................................................................. 444

Rev. 1.00, 05/04, page xxxiii of xxxiv

Section 19 Clock Pulse Generator

Table 19.1

Damping Resistance Values ................................................................................. 456

Table 19.2 Crystal Resonator Parameters............................................................................... 456

Table 19.3 External Clock Input Conditions ..........................................................................458

Table 19.4 External Clock Output Stabilization Delay Time ................................................. 458

Table 19.5 Subclock Input Conditions.................................................................................... 460

Section 20 Power-Down Modes

Table 20.1

Operating Frequency and Wait Time.................................................................... 465

Table 20.2 LSI Internal States in Each Operating Mode ........................................................ 469

Section 22 Electrical Characteristics

Table 22.1

Absolute Maximum Ratings ................................................................................. 513

Table 22.2 DC Characteristics (1) ..........................................................................................514

Table 22.2 DC Characteristics (2) ..........................................................................................516

Table 22.2 DC Characteristics (3) When LPC Function is Used............................................ 517

Table 22.3 Permissible Output Currents................................................................................. 518

Table 22.4 Bus Drive Characteristics .....................................................................................519

Table 22.5 Clock Timing........................................................................................................ 521

Table 22.6 Control Signal Timing.......................................................................................... 522

Table 22.7 Timing of On-Chip Peripheral Modules (1) ......................................................... 523

Table 22.8 Keyboard Buffer Controller Timing ..................................................................... 524

Table 22.9 I2C Bus Timing..................................................................................................... 525

Table 22.10 LPC Module Timing......................................................................................... 526

Table 22.11 A/D Conversion Characteristics

(AN5 to AN0 Input: 134/266-State Conversion).............................................. 526

Table 22.12 Flash Memory Characteristics ..........................................................................527

Appendix

Table A.1

Rev. 1.00, 05/04, page xxxiv of xxxiv

I/O Port States in Each Processing State............................................................... 537

Section 1 Overview

1.1 Features

• High-speed H8S/2000 central processing unit with an internal 16-bit architecture

Upward-compatible with H8/300 and H8/300H CPUs on an object level

Sixteen 16-bit general registers

65 basic instructions

• Various peripheral functions

8-bit PWM timer (PWM)

16-bit free-running timer (FRT)

8-bit timer (TMR)

Watchdog timer (WDT)

Asynchronous or clocked synchronous serial communication interface (SCI)

2

I

C bus interface (IIC)

Keyboard buffer controller

Host interface (LPC)

10-bit A/D converter

Clock pulse generator

• On-chip memory

ROM Model ROM RAM Remarks

F-ZTAT Version HD64F2111BVB* 64 Kbytes 2 Kbytes

HD64F2111BVC* 64 Kbytes 3 Kbytes

Note: * 3-V version product

• General I/O ports

I/O pins: 114

Input-only pins: 8

• Supports various power-down states

• Compact package

Product Package Code Body Size Pin Pitch

H8S/2111B TQFP-144 TFP-144 18.0 × 18.0 mm 0.4 mm

Rev. 1.00, 05/04, page 1 of 544

1.2 Internal Block Diagram

VCC

VCC

VCL

VSS

VSS

VSS

VSS

VSS

X1
X2

RES

XTAL

EXTAL

VCCB

MD1
MD0

NMI

STBY

RESO

P97/SDA0

P96/φ/EXCL

P95
P94
P93

P92/IRQ0
P91/IRQ1

P90/IRQ2/ADTRG

P67/TMOX/KIN7/IRQ7

P66/FTOB/KIN6/IRQ6

P65/FTID/KIN5
P64/FTIC/KIN4
P63/FTIB/KIN3

P62/FTIA/KIN2/TMIY

P61/FTOA/KIN1

P60/FTCI/KIN0/TMIX

P47
P46

P45/TMRI1

P44/TMO1

P43/TMCI1

P42/TMRI0/SDA1

P41/TMO0

P40/TMCI0

P52/ExSCK1*/SCL0

P51/ExRxD1*
P50/ExTxD1*

Port 8 Port 7 Port G Port F Port E

P84/IRQ3/TxD1

P85/IRQ4/RxD1

P86/IRQ5/SCK1/SCL1

P83/LPCPD

P82/CLKRUN

AVref

P80/PME

P81/GA20

Port 9Port 6Port 4Port 5

AVCC

AVSS

P77

P76

P75/AN5

Note: * The program development tool (emulator) does not support this function.

Clock pulse

(Flash memory)

16-bit FRT

8-bit timer × 6 channels

SCI × 1 channel

IIC × 2 channels

P74/AN4

P73/AN3

P72/AN2

P71/AN1

P70/AN0

generator

Interrup

controller

ROM

RAM

PG7/ExSCLB*

PG5/ExSCLA*

PG6/ExSDAB*

H8S/2000 CPU

PG3

PG2

PG4/ExSDAA*

controller × 3 channels

10-bit A/D converter

PG1

PG0

PF7/TMOY*

PF6/ExTMOX*

Internal data bus

WDT× 2 channels

Keyboard buffer

8-bit PWM

Host interfaces

(LPC)

PF1/TMIB

PF0/TMIA

PF3/TMOB

PF2/TMOA

PF5/ExTMIY*

PF4/ExTMIX*

Bus controller

Internal address bus

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

Port APort 2Port 1Port 3Port BPort CPort D

PA7/KIN15/PS2CD
PA6/KIN14/PS2CC
PA5/KIN13/PS2BD
PA4/KIN12/PS2BC
PA3/KIN11/PS2AD
PA2/KIN10/PS2AC
PA1/KIN9
PA0/KIN8

P27
P26
P25
P24
P23
P22
P21
P20

P17/PW7
P16/PW6
P15/PW5
P14/PW4
P13/PW3
P12/PW2
P11/PW1
P10/PW0

P37/SERIRQ
P36/LCLK
P35/LRESET
P34/LFRAME
P33/LAD3
P32/LAD2
P31/LAD1
P30/LAD0

PB7/WUE7
PB6/WUE6
PB5/WUE5
PB4/WUE4
PB3/WUE3
PB2/WUE2
PB1/WUE1/LSCI
PB0/WUE0/LSMI

PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0

PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0

Rev. 1.00, 05/04, page 2 of 544

Figure 1.1 Internal Block Diagram

1.3 Pin Description

7

1.3.1 Pin Arrangement

P13/PW3

P14/PW4

P15/PW5

P16/PW6

P17/PW7

P20

P21

P22

108

107

106

105

104

103

102

P12/PW2
P11/PW1

VSS

P10/PW0

PB7/WUE7
PB6/WUE6
PB5/WUE5
PB4/WUE4
PB3/WUE3

PB2/WUE2
PB1/WUE1/LSCI
PB0/WUE0/LSMI

P30/LAD0
P31/LAD1
P32/LAD2
P33/LAD3

P34/LFRAME

P35/LRESET

P36/LCLK

P37/SERIRQ

P80/PME

P81/GA20

P82/CLKRUN

P83/LPCPD

P84/IRQ3/TxD1

P85/IRQ4/RxD1

P86/IRQ5/SCK1/SCL1

P40/TMCI0

P41/TMO0

P42/TMRI0/SDA1

VSS

RESO

XTAL

EXTAL

109
110

111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

X1

141

X2

142
143
144

123456789

101

P64/FTIC/KIN4

P63/FTIB/KIN3

P62/FTIA/KIN2/TMIY

P60/FTCI/KIN0/TMIX

P23

P24

P25

P26

P27

VSS

PC0

PC1

PC2

PC3

PC4

PC5

999897969594939291908988878685848382818079787776757473

100

PC6

PC7

VCC

P67/TMOX/KIN7/IRQ

P66/FTOB/KIN6/IRQ6

P65/FTID/KIN5

AVref

AVCC

P61/FTOA/KIN1

TFP-144

(Top view)

101112131415161718192021222324252627282930313233343536

P77

P76

P75/AN5

72

P74/AN4

71

P73/AN3

70

P72/AN2

69

P71/AN1

68

P70/AN0

67

AVSS

66

PD0

65

PD1

64

PD2

63

PD3

62

PD4

61

PD5

60

PD6

59

PD7

58

PG0

57

PG1

56

PG2

55

PG3

54

PG4/ExSDAA*

53

PG5/ExSCLA*

52

PG6/ExSDAB*

51

PG7/ExSCLB*

50

PF0/TMIA

49

PF1/TMIB

48

PF2/TMOA

47

PF3/TMOB

46

PF4/ExTMIX*

45

PF5/ExTMIY*

44

PF6/ExTMOX*

43

PF7/TMOY*

42

VSS

41

PA0/KIN8

40

PA1/KIN9

39

PA2/KIN10/PS2AC

38

PA3/KIN11/PS2AD

37

PA4/KIN12/PS2BC

P46

VCC

P43/TMCI1

P44/TMO1

P45/TMRI1

P47

VSS

RES

MD1

MD0

NMI

STBY

VCL

P51/ExRxD1*

P52/ExSCK1*/SCL0

P97/SDA0

P50/ExTxD1*

P95

P96/φ/ EXCL

P94

P93

P92/IRQ0

P91/IRQ1

PE7

P90/IRQ2/ADTRG

PE6

PE5

PE4

PE3

PE2

PE1

PE0

Note: * The program development tool (emulator) does not support this function.

Figure 1.2 Pin Arrangement

Rev. 1.00, 05/04, page 3 of 544

PA7/KIN15/PS2CD

PA6/KIN14/PS2CC

VCCB

PA5/KIN13/PS2BD

1.3.2 Pin Functions in Each Operating Mode

Table 1.1 Pin Functions in Each Operating Mode

Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode

1 VCC VCC

2 P43/TMCI1 NC

3 P44/TMO1 NC

4 P45/TMRI1 NC

5 P46 NC

6 P47 NC

7 VSS VSS
8 RES RES

9 MD1 VSS

10 MD0 VSS

11 NMI FA9
12 STBY VCC

13 VCL VCC

14 (N) P52/ExSCK1*/SCL0 FA18

15 P51/ExRxD1* FA17

16 P50/ExTxD1* NC

17 (N) P97/SDA0 VCC

18 P96/φ/EXCL NC

19 P95 FA16

20 P94 FA15
21 P93 WE
22 P92/IRQ0 VSS
23 P91/IRQ1 VCC
24 P90/IRQ2/ADTRG VCC

25 PE7 NC

26 PE6 NC

27 PE5 NC

28 PE4 NC

29 PE3 NC

30 PE2 NC

Rev. 1.00, 05/04, page 4 of 544

Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode

31 PE1 NC

32 PE0 NC
33 (B) PA7/KIN15/PS2CD NC
34 (B) PA6/KIN14/PS2CC NC
35 (B) PA5/KIN13/PS2BD NC

36 VCCB VCC
37 (B) PA4/KIN12/PS2BC NC
38 (B) PA3/KIN11/PS2AD NC
39 (B) PA2/KIN10/PS2AC NC
40 (B) PA1/KIN9 NC
41 (B) PA0/KIN8 NC

42 VSS VSS

43 PF7/TMOY* NC

44 PF6/ExTMOX* NC

45 PF5/ExTMIY* NC

46 PF4/ExTMIX* NC

47 PF3/TMOB NC

48 PF2/TMOA NC

49 PF1/TMIB NC

50 PF0/TMIA NC

51 (N) PG7/ExSCLB* NC

52 (N) PG6/ExSDAB* NC

53 (N) PG5/ExSCLA* NC

54 (N) PG4/ExSDAA* NC

55 (N) PG3 NC

56 (N) PG2 NC

57 (N) PG1 NC

58 (N) PG0 NC

59 PD7 NC

60 PD6 NC

Rev. 1.00, 05/04, page 5 of 544

Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode

61 PD5 NC

62 PD4 NC

63 PD3 NC

64 PD2 NC

65 PD1 NC

66 PD0 NC

67 AVSS VSS

68 P70/AN0 NC

69 P71/AN1 NC

70 P72/AN2 NC

71 P73/AN3 NC

72 P74/AN4 NC

73 P75/AN5 NC

74 P76 NC

75 P77 NC

76 AVCC VCC

77 AVref VCC
78 P60/FTCI/KIN0/TMIX NC
79 P61/FTOA/KIN1 NC
80 P62/FTIA/KIN2/TMIY NC
81 P63/FTIB/KIN3 NC
82 P64/FTIC/KIN4 NC
83 P65/FTID/KIN5 NC
84 P66/FTOB/KIN6/IRQ6 NC
85 P67/TMOX/KIN7/IRQ7 VSS

86 VCC VCC

87 PC7 NC

88 PC6 NC

89 PC5 NC

90 PC4 NC

Rev. 1.00, 05/04, page 6 of 544

Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode

91 PC3 NC

92 PC2 NC

93 PC1 NC

94 PC0 NC

95 VSS VSS
96 P27 CE

97 P26 FA14

98 P25 FA13

99 P24 FA12

100 P23 FA11

101 P22 FA10
102 P21 OE

103 P20 FA8

104 P17/PW7 FA7

105 P16/PW6 FA6

106 P15/PW5 FA5

107 P14/PW4 FA4

108 P13/PW3 FA3

109 P12/PW2 FA2

110 P11/PW1 FA1

111 VSS VSS

112 P10/PW0 FA0
113 PB7/WUE7 NC
114 PB6/WUE6 NC
115 PB5/WUE5 NC
116 PB4/WUE4 NC
117 PB3/WUE3 NC
118 PB2/WUE2 NC
119 PB1/WUE1/LSCI NC
120 PB0/WUE0/LSMI NC

Rev. 1.00, 05/04, page 7 of 544

Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode

121 P30/LAD0 FO0

122 P31/LAD1 FO1

123 P32/LAD2 FO2

124 P33/LAD3 FO3
125 P34/LFRAME FO4
126 P35/LRESET FO5

127 P36/LCLK FO6

128 P37/SERIRQ FO7
129 P80/PME NC

130 P81/GA20 NC
131 P82/CLKRUN NC
132 P83/LPCPD NC
133 P84/IRQ3/TxD1 NC
134 P85/IRQ4/RxD1 NC
135 (N) P86/IRQ5/SCK1/SCL1 NC

136 P40/TMCI0 NC

137 P41/TMO0 NC

138 (N) P42/TMRI0/SDA1 NC

139 VSS VSS

140 X1 NC

141 X2 NC
142 RESO NC

143 XTAL XTAL

144 EXTAL EXTAL

Note: The (B) in Pin No. means the VCCB drive and the (N) in Pin No. means the NMOS

push-pull/open-drain drive.

* The program development tool (emulator) does not support this function.

Rev. 1.00, 05/04, page 8 of 544

1.3.3 Pin Functions

Table 1.2 Pin Functions

Pin No.
Type Symbol TFP-144 I/O Name and Function

Power

Clock

Operating
mode control

System
control

signals

VCC 1, 86 Input Power supply pin. Connect the pin to the

system power supply.

VCL 13 Input Power supply pin. Connect the pin to VCC.

VCCB 36 Input The power supply for the port A input/output

buffer.

VSS 7, 42, 95,

111, 139

XTAL 143 Input

EXTAL 144 Input

φ 18 Output Supplies the system clock to external

EXCL 18 Input Input a 32.768 kHz external subclock.
X1 140 Input Leave open.
X2 141 Input Leave open.

MD1
MD0

RES 8 Input Reset pin.

RESO 142 Output Outputs reset signal to external device.
STBY 12 Input When this pin is driven low, a transition is

NMI

IRQ0 to
IRQ7

9
10

11 Input Input pin for a nonmaskable interrupt request.Interrupt

22 to 24,
133 to 135,
84, 85

Input Ground pin. Connect to the system power

supply (0 V).

Pins for connection to crystal resonators. The
EXTAL pin can also input an external clock.

See section 19, Clock Pulse Generator, for
typical connection diagrams.

devices.

Input These pins set the operating mode. These

pins should not be changed while the MCU is
operating.

When this pin becomes low, the chip is reset.

made to hardware standby mode.

Input These pins request a maskable interrupt.

Rev. 1.00, 05/04, page 9 of 544

Pin No.
Type Symbol TFP-144 I/O Name and Function

16-bit free­running timer
(FRT)

8-bit timer
(TMR_0,
TMR_1,
TMR_X,
TMR_Y,
TMR_A,
TMR_B)

8-bit timer
(TMR_X,
TMR_Y,
TMR_A,
TMR_B)

8-bit PWM
timer (PWM)

Serial
communi­cation
interface
(SCI_1)

Keyboard
buffer
controller

FTCI 78 Input The counter clock input pin.

FTOA 79 Output The output compare A output pin.

FTOB 84 Output The output compare B output pin.

FTIA 80 Input The input capture A input pin.

FTIB 81 Input The input capture B input pin.

FTIC 82 Input The input capture C input pin.

FTID 83 Input The input capture D input pin.

TMO0
TMO1
TMOX
TMOY*
TMOA
TMOB
ExTMOX*

TMCI0
TMCI1

TMRI0
TMRI1

TMIX
TMIY
TMIA
TMIB
ExTMIX*
ExTMIY*

PW7 to
PW0

TxD1
ExTxD1*

RxD1
ExRxD1*

SCK1
ExSCK1*

PS2AC
PS2BC
PS2CC

PS2AD
PS2BD
PS2CD

137
3
85
43
48
47
44

136
2

138
4

78
80
50
49
46
45

104 to 110,
112

133
16

134
15

135
14

39
37
34

38
35
33

Output The waveform output pins for the output

compare function.

Input Input pins for the external clock input to

counters.

Input The counter reset input pins.

Input The counter event input and counter reset

input pins.

Output PWM timer pulse output pins.

Output Transmit data output pins.

Input Receive data input pins.

Input/
Output

Input/
Output

Input/
Output

Clock input/output pins.
The output type is NMOS push-pull.

Keyboard buffer controller synchronization
clock input/output pins.

Keyboard buffer controller data input/output
pins.

Rev. 1.00, 05/04, page 10 of 544

Pin No.
Type Symbol TFP-144 I/O Name and Function

Host interface
(LPC)

Keyboard
buffer
controller

A/D converter

LAD3 to
LAD0

LFRAME 125 Input Input pin that indicates the start of an LPC

LRESET 126 Input Input pin that indicates an LPC reset.

LCLK 127 Input The LPC clock input pin.

SERIRQ 128 Input/

LSCI, LSMI,
PME

GA20 130 Input/

CLKRUN 131 Input/

LPCPD 132 Input Input pin that controls LPC module shutdown.
KIN0 to

KIN15

WUE0 to
WUE7

AN5 to AN0 73 to 68 Input Analog input pins.
ADTRG 24 Input Pin for input of an external trigger to start A/D

AVCC 76 Input The analog power supply pin for the A/D

AVref 77 Input The reference power supply pin for the A/D

AVSS 67 Input The ground pin for the A/D converter. This

124 to 121 Input/

Output

Output

119, 120,
129

78 to 85,
41 to 37,
35 to 33

120 to 113 Input Wakeup event input pins. These pins allow

Input/
Output

Output

Output

Input Matrix keyboard input pins. KIN0 to KIN15

LPC command, address, and data
input/output pins.

cycle or forced termination of an abnormal
LPC cycle.

Input/output pin for LPC serialized host
interrupts (HIRQ1, SMI, HIRQ6, HIRQ9 to
HIRQ12).

LPC auxiliary output pins. Functionally, they
are general I/O ports.

A20 gate control signal output pin. Output
state monitoring input is possible.

Input/output pin that requests the start of
LCLK operation when LCLK is stopped.

are used as key-scan inputs, and P10 to P17
and P20 to P27 are used as key-scan
outputs. This allows a maximum 16-output ×
16-input, 256-key matrix to be configured.

the same kind of wakeup as key-wakeup
from various sources.

conversion.

converter.
When the A/D is not used, this pin should be

connected to the system power supply (+3
V).

converter and.
When the A/D is not used, this pin should be

connected to the system power supply (+3
V).

pin should be connected to the system power
supply
(0 V).

Rev. 1.00, 05/04, page 11 of 544

Pin No.
Type Symbol TFP-144 I/O Name and Function

I2C bus
interface (IIC)

SDA0

I/O ports P17 to P10 104 to 110,

P27 to P20 96 to 103 Input/

P37 to P30 128 to 121 Input/

P47 to P40 6 to 2,

P52 to P50 14 to 16 Input/

P67 to P60 85 to 78 Input/

P77 to P70 75 to 68 Input Eight input pins.

P86 to P80 135 to 129 Input/

P97 to P90 17 to 24 Input/

PA7 to PA0 33 to 35,

PB7 to PB0 113 to 120 Input/

PC7 to PC0 87 to 94 Input/

PD7 to PD0 59 to 66 Input/

PE7 to PE0 25 to 32 Input/

Note: * The program development tool (emulator) does not support this function.

SCL0
SCL1

ExSCLA*
ExSCLB*

SDA1
ExSDAA*
ExSDAB*

PF7 to PF0 43 to 50 Input/

PG7 to PG0 51 to 58 Input/

14
135
53
51

17
138
54
52

112

138 to 136

37 to 41

Input/
Output

Input/
Output

Input/
Output

Output

Output

Input/
Output

Output

Output

Output

Output

Input/
Output

Output

Output

Output

Output

Output

Output

I2C clock I/O pins. The output type is NMOS
open-drain output.

I2C data I/O pins. The output type is NMOS
open-drain output.

Eight input/output pins.

Eight input/output pins.

Eight input/output pins.

Eight input/output pins.
(The output type of P42 is NMOS push-pull.)

Three input/output pins.
(The output type of P52 is NMOS push-pull.)

Eight input/output pins.

Seven input/output pins.
(The output type of P86 is NMOS push-pull.)

Eight input/output pins.
(The output type of P97 is NMOS push-pull.)

Eight input/output pins.

Eight input/output pins.

Eight input/output pins.

Eight input/output pins.

Eight input/output pins.

Eight input/output pins.

Eight input/output pins.
(The output type of PG7 to PG0 is NMOS

push-pull.)

Rev. 1.00, 05/04, page 12 of 544

Section 2 CPU

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1 Features

• Upward-compatibility with H8/300 and H8/300H CPUs

Can execute H8/300 CPU and H8/300H CPU object programs

• General-register architecture

Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-five basic instructions

8/16/32-bit arithmetic and logic instructions

Multiply and divide instructions

Powerful bit-manipulation instructions

• Eight addressing modes

Register direct [Rn]

Register indirect [@ERn]

Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]

Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

Immediate [#xx:8, #xx:16, or #xx:32]

Program-counter relative [@(d:8,PC) or @(d:16,PC)]

Memory indirect [@@aa:8]

• 16-Mbyte address space

Program: 16 Mbytes

Data: 16 Mbytes

• High-speed operation

All frequently-used instructions are executed in one or two states

8/16/32-bit register-register add/subtract: 1 state

8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)

16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)

16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)

32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)

CPU210A_020020040200 Rev. 1.00, 05/04, page 13 of 544

• Two CPU operating modes

Normal mode

Advanced mode

• Power-down state

Transition to power-down state by SLEEP instruction

Selectable CPU clock speed

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration

The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.

• The number of execution states of the MULXU and MULXS instructions

Execution States

Instruction Mnemonic

MULXU.B Rs, Rd 3 12 MULXU

MULXU.W Rs, ERd 4 20

MULXS.B Rs, Rd 4 13 MULXS

MULXS.W Rs, ERd 5 21

H8S/2600 H8S/2000

In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.

Rev. 1.00, 05/04, page 14 of 544

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.

• More general registers and control registers

Eight 16-bit extended registers and one 8-bit control register have been added.

• Expanded address space

Normal mode supports the same 64-Kbyte address space as the H8/300 CPU.

Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.

• Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.

Signed multiply and divide instructions have been added.

Two-bit shift and two-bit rotate instructions have been added.

Instructions for saving and restoring multiple registers have been added.

A test and set instruction has been added.

• Higher speed

Basic instructions are executed twice as fast.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.

• Additional control register

One 8-bit control register has been added.

• Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.

Two-bit shift and two-bit rotate instructions have been added.

Instructions for saving and restoring multiple registers have been added.

A test and set instruction has been added.

• Higher speed

Basic instructions are executed twice as fast.

Rev. 1.00, 05/04, page 15 of 544

2.2 CPU Operating Modes

The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte address
space. The mode is selected by the LSI's mode pins.

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU in normal
mode.

• Address space

Linear access to a maximum address space of 64 Kbytes is possible.

• Extended registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.

When extended register En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. (If general register Rn is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post­increment (@Rn+) and a carry or borrow occurs, the value in the corresponding extended
register (En) will be affected.)

• Instruction set

All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.

• Exception vector table and memory indirect branch addresses

In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details on the exception vector table, see section 4, Exception Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.

• Stack structure

In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call
in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.2. The extended control register
(EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.

Rev. 1.00, 05/04, page 16 of 544

H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B

Reset exception vector

(Reserved for system use)

(Reserved for system use)

Exception
vector table

Exception vector 1

Exception vector 2

Figure 2.1 Exception Vector Table (Normal Mode)

SP

PC

SP

(16 bits)

(a) Subroutine Branch (b) Exception Handling

Note: * Ignored when returning.

Figure 2.2 Stack Structure in Normal Mode

CCR

*

CCR

PC

(16 bits)

Rev. 1.00, 05/04, page 17 of 544

2.2.2 Advanced Mode

• Address space

Linear access to a maximum address space of 16 Mbytes is possible.

• Extended registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the
upper 16-bit segments of 32-bit registers or address registers.

• Instruction set

All instructions and addressing modes can be used.

• Exception vector table and memory indirect branch addresses

In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored
in the lower 24 bits (see figure 2.3). For details on the exception vector table, see section 4,
Exception Handling.

H'00000000

H'00000003

H'00000004

H'00000007

H'00000008

H'0000000B

H'0000000C

H'00000010

Reserved

Reset exception vector

Reserved

(Reserved for system use)

Exception vector table

(Reserved for system use)

Reserved

Exception vector 1

Figure 2.3 Exception Vector Table (Advanced Mode)

Rev. 1.00, 05/04, page 18 of 544

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the top area of this range is also used for the exception vector table.

• Stack structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC and condition-code register (CCR) are pushed onto the stack in exception
handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not
pushed onto the stack. For details, see section 4, Exception Handling.

SP

Reserved

PC

(24 bits)

(a) Subroutine Branch (b) Exception Handling

SP

CCR

PC

(24 bits)

Figure 2.4 Stack Structure in Advanced Mode

Rev. 1.00, 05/04, page 19 of 544

2.3 Address Space

Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.

H'0000

H'FFFF

64 Kbytes

H'00000000

16 Mbytes

H'00FFFFFF

Not available
in this LSI

H'FFFFFFFF

(b) Advanced Mode(a) Normal Mode

Figure 2.5 Memory Map

Program area

Data area

Rev. 1.00, 05/04, page 20 of 544

2.4 Register Configuration

The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit
extended control register (EXR), and an 8-bit condition code register (CCR).

General Registers (Rn) and Extended Registers (En)

15 0 7 0 7 0

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

E0

E1

E2

E3

E4

E5

E6

E7

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

Control Registers

[Legend]

SP:

Stack pointer

PC:

Program counter

EXR:

Extended control register

T:

Trace bit

I2 to I0:

Interrupt mask bits

CCR:

Condition-code register

I:

Interrupt mask bit

UI:

User bit or interrupt mask bit

Note: * Does not affect operation in this LSI.

23 0

H:
U:
N:
Z:
V:
C:

Figure 2.6 CPU Internal Registers

Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag

PC

76543210

TI2I1I0EXR*

----

76543210

CCR

IUIHUNZVC

Rev. 1.00, 05/04, page 21 of 544

2.4.1 General Registers

The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers.

When the general registers are used as 32-bit registers or address registers, they are designated by
the letters ER (ER0 to ER7).

When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7)
are also referred to as extended registers.

When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing a maximum sixteen 8-bit registers.

The usage of each register can be selected independently.

General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.

• Address registers

• 32-bit registers

ER registers

(ER0 to ER7)

Figure 2.7 Usage of General Registers

Rev. 1.00, 05/04, page 22 of 544

• 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Free area

SP (ER7)

Stack area

Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)

2.4.3 Extended Control Register (EXR)

EXR does not affect operation in this LSI.

Initial

Bit Bit Name

7 T 0 R/W Trace Bit

6 to 3 — All 1 R Reserved

2 to 0 I2

I1
I0

Value

All 1 R/W Interrupt Mask Bits 2 to 0

R/W Description

Does not affect operation in this LSI.

These bits are always read as 1.

Do not affect operation in this LSI.

Rev. 1.00, 05/04, page 23 of 544

2.4.4 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be
performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V,
and C flags are used as branching conditions for conditional branch (Bcc) instructions.

Initial

Bit Bit Name

7 I 1 R/W Interrupt Mask Bit

6 UI Undefined R/W User Bit or Interrupt Mask Bit

5 H Undefined R/W Half-Carry Flag

4 U Undefined R/W User Bit

3 N Undefined R/W Negative Flag

2 Z Undefined R/W Zero Flag

1 V Undefined R/W Overflow Flag

Value R/W Description

Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence. For
details, refer to section 5, Interrupt Controller.

Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.

Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.

Stores the value of the most significant bit of data as a
sign bit.

Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.

Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.

Rev. 1.00, 05/04, page 24 of 544

Initial

Bit Bit Name

0 C Undefined R/W Carry Flag

Value R/W Description

Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by

Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit

manipulation instructions.

2.4.5 Initial Register Values

The program counter (PC) among CPU internal registers is initialized when reset exception
handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the
interrupt mask (I) bits in CCR and EXR are set to 1. The other CCR bits and the general registers
are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should
therefore be initialized by an MOV.L instruction executed immediately after a reset.

Rev. 1.00, 05/04, page 25 of 544

2.5 Data Formats

The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data formats of general registers.

Data Type Register Number Data Image

70

1-bit data

RnH

6543271

0

Don't care

1-bit data

4-bit BCD data

4-bit BCD data

Byte data

Byte data

7

RnL

RnH

RnL

RnH

RnL

Don't care

7

Upper Lower

7

MSB LSB

3

Don't care

Don't care

65432710

04

Don't care

704

Upper Lower

0

7

MSB LSB

Figure 2.9 General Register Data Formats (1)

0

3

Don't care

0

Rev. 1.00, 05/04, page 26 of 544

Data Type Data ImageRegister Number

Word data

Word data

15 0

MSB LSB

Longword data

31 16

MSB

[Legend]

ERn:

General register ER

En:

General register E

Rn:

General register R

RnH:

General register RH

RnL:

General register RL

MSB:

Most significant bit

LSB :

Least significant bit

Rn

En

ERn

En Rn

Figure 2.9 General Register Data Formats (2)

15 0

MSB LSB

15 0

LSB

Rev. 1.00, 05/04, page 27 of 544

2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.

When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.

Data Type Address

70

1-bit data

Byte data

Word data

Longword data Address 2N

Address L

Address L

Address 2M

Address 2M + 1

Address 2N + 1

Address 2N + 2

Address 2N + 3

76 543210

MSB

MSB

MSB

Figure 2.10 Memory Data Formats

Data Image

LSB

LSB

LSB

Rev. 1.00, 05/04, page 28 of 544

2.6 Instruction Set

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.

Table 2.1 Instruction Classification

Function Instructions Size Types

Data transfer

Arithmetic
operations

Logic operations AND, OR, XOR, NOT B/W/L 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST,

Branch BCC*2, JMP, BSR, JSR, RTS — 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,

Block data transfer EEPMOV — 1

Notes: B: Byte size; W: Word size; L: Longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @­SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.

2. B

3. Cannot be used in this LSI.

4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5.

5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using

CC

STM/LDM instruction, because ER7 is the stack pointer.

MOV B/W/L

POP*1, PUSH*1 W/L

LDM*5, STM*5 L

MOVFPE*3, MOVTPE*3 B

ADD, SUB, CMP, NEG B/W/L

ADDX, SUBX, DAA, DAS B

INC, DEC B/W/L

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS B/W

EXTU, EXTS W/L

TAS*4 B

B/W/L 8

ROTXR

B 14

BAND, BIAND, BOR, BIOR, BXOR, BIXOR

— 9

NOP

is the general name for conditional branch instructions.

5

19

Total: 65

Rev. 1.00, 05/04, page 29 of 544

2.6.1 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notation

Symbol Description

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

– Subtraction

× Multiplication

÷ Division

∧ Logical AND

∨ Logical OR

⊕ Logical exclusive OR

→ Move

∼ NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Rev. 1.00, 05/04, page 30 of 544

Table 2.3 Data Transfer Instructions

Instruction Size*1 Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.

MOVFPE B Cannot be used in this LSI.

MOVTPE B Cannot be used in this LSI.

POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn

PUSH W/L Rn → @-SP

Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.

LDM*2 L @SP+ → Rn (register list)

Pops two or more general registers from the stack.

STM*2 L Rn (register list) → @-SP

Pushes two or more general registers onto the stack.

Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword

2. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using
STM/LDM instruction, because ER7 is the stack pointer.

Rev. 1.00, 05/04, page 31 of 544

Table 2.4 Arithmetic Operations Instructions (1)

Instruction Size* Function

ADD
SUB

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or
on immediate data and data in a general register. (Subtraction on
immediate data and data in a general register cannot be performed in
bytes. Use the SUBX or ADD instruction.)

ADDX
SUBX

INC
DEC

ADDS
SUBS

DAA
DAS

MULXU B/W Rd × Rs → Rd

MULXS B/W Rd × Rs → Rd

DIVXU B/W Rd ÷ Rs → Rd

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Adds or subtracts the value 1 or 2 to or from data in a general
register. (Only the value 1 can be added to or subtracted from byte
operands.)

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit
register.

B Rd (decimal adjust) → Rd

Decimal-adjusts an addition or subtraction result in a general register
by referring to CCR to produce 4-bit BCD data.

Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs signed multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits
→ 16-bit quotient and 16-bit remainder.

Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword

Rev. 1.00, 05/04, page 32 of 544

Table 2.4 Arithmetic Operations Instructions (2)

Instruction Size*1 Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits
→ 16-bit quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general
register or with immediate data, and sets the CCR bits according to
the result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of data in a
general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower
16 bits of a 32-bit register to longword size, by padding with zeros on
the left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower
16 bits of a 32-bit register to longword size, by extending the sign bit.

TAS*2 B @ERd – 0, 1 → (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword

2. When using the TAS instruction, use registers ER0, ER1, ER4 and ER5.

Rev. 1.00, 05/04, page 33 of 544

Table 2.5 Logic Operations Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another
general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another
general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and
another general register or immediate data.

NOT B/W/L ∼ Rd → Rd

Takes the one's complement (logical complement) of data in a
general register.

Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword

Table 2.6 Shift Instructions

Instruction Size* Function

SHAL
SHAR

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on data in a general register. 1-bit or 2
bit shift is possible.

SHLL
SHLR

ROTL
ROTR

ROTXL
ROTXR

Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword

Rev. 1.00, 05/04, page 34 of 544

B/W/L Rd (shift) → Rd

Performs a logical shift on data in a general register. 1-bit or 2 bit
shift is possible.

B/W/L Rd (rotate) → Rd

Rotates data in a general register. 1-bit or 2 bit rotation is possible.

B/W/L Rd (rotate) → Rd

Rotates data including the carry flag in a general register. 1-bit or 2
bit rotation is possible.

Table 2.7 Bit Manipulation Instructions (1)

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.

BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The
bit number is specified by 3-bit immediate data or the lower three bits
of a general register.

BTST B ∼ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and
sets or clears the Z flag accordingly. The bit number is specified by
3-bit immediate data or the lower three bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

Logically ANDs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.

BIAND B C ∧ (<bit-No.> of <EAd>) → C

Logically ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.

The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit-No.> of <EAd>) → C

Logically ORs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.

BIOR B C ∨ (∼ <bit-No.> of <EAd>) → C

Logically ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.

The bit number is specified by 3-bit immediate data.

Note: * Size refers to the operand size.
B: Byte

Rev. 1.00, 05/04, page 35 of 544

Table 2.7 Bit Manipulation Instructions (2)

Instruction Size* Function

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Logically exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry flag.

BIXOR B C ⊕ ∼ (<bit-No.> of <EAd>) → C

Logically exclusive-ORs the carry flag with the inverse of a specified
bit in a general register or memory operand and stores the result in
the carry flag.

The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to
the carry flag.

BILD B ∼ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or
memory operand to the carry flag.

The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register
or memory operand.

BIST B ∼ C → (<bit-No.>. of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.

The bit number is specified by 3-bit immediate data.

Note: * Size refers to the operand size.
B: Byte

Rev. 1.00, 05/04, page 36 of 544

Table 2.8 Branch Instructions

Instruction Size Function

Bcc —

JMP — Branches unconditionally to a specified address.

BSR — Branches to a subroutine at a specified address

JSR — Branches to a subroutine at a specified address

RTS — Returns from a subroutine

Branches to a specified address if a specified condition is true. The
branching conditions are listed below.

Mnemonic Description Condition

BRA (BT) Always (true) Always

BRN (BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC (BHS) Carry clear

(high or same)

BCS (BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z ∨ (N ⊕ V) = 0

BLE Less or equal Z ∨ (N ⊕ V) = 1

C = 0

Rev. 1.00, 05/04, page 37 of 544

Table 2.9 System Control Instructions

Instruction Size* Function

TRAPA — Starts trap-instruction exception handling.

RTE — Returns from an exception-handling routine.

SLEEP — Causes a transition to a power-down state.

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are
valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with immediate
data.

NOP — PC + 2 → PC

Only increments the program counter.

Note: * Size refers to the operand size.
B: Byte
W: Word

Table 2.10 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B —

EEPMOV.W —

Rev. 1.00, 05/04, page 38 of 544

if R4L ≠ 0 then
Repeat @ER5 + → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;

if R4 ≠ 0 then
Repeat @ER5 + → @ER6+
R4–1 → R4
Until R4 = 0
else next;

Transfers a data block. Starting from the address set in ER5,
transfers data for the number of bytes set in R4L or R4 to the
address location set in ER6.

Execution of the next instruction begins as soon as the transfer is
completed.

2.6.2 Basic Instruction Formats

The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).

Figure 2.11 shows examples of instruction formats.

• Operation field

Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.

• Register field

Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields, and some have no register field.

• Effective address extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition field

Specifies the branching condition of Bcc instructions.

(1) Operation field only

op

NOP, RTS

(2) Operation field and register fields

op

(3) Operation field, register fields, and effective address extension

op

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16

rn

rn rm

rm

Figure 2.11 Instruction Formats (Examples)

ADD.B Rn, Rm

MOV.B @(d:16, Rn), Rm

Rev. 1.00, 05/04, page 39 of 544

2.7 Addressing Modes and Effective Address Calculation

The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.

Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

Register indirect with pre-decrement

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

@ERn+
@–ERn

2.7.1 Register Direct—Rn

The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.7.2 Register Indirect—@ERn

The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).

Rev. 1.00, 05/04, page 40 of 544

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction code is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn

Register Indirect with Post-Increment—@ERn+: The register field of the instruction code

specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word access, and 4 for longword
access. For word or longword transfer instructions, the register value should be even.

Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an

address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or
longword transfer instructions, the register value should be even.

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32

The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address,
the entire address space is accessed.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).

Table 2.12 Absolute Address Access Ranges

Absolute Address Normal Mode Advanced Mode

Data address

Program instruction
address

8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF

16 bits (@aa:16) H'000000 to H'007FFF,

32 bits (@aa:32)

24 bits (@aa:24)

H'0000 to H'FFFF

H'FF8000 to H'FFFFFF

H'000000 to H'FFFFFF

Rev. 1.00, 05/04, page 41 of 544

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32

The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction
code can be used directly as an operand.

The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address
indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this
branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which
the displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.

Rev. 1.00, 05/04, page 42 of 544

2.7.8 Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand which contains a branch address. The upper bits of
the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to
H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).

In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode, the memory operand is a longword operand, the first byte of which is assumed to
be 0 (H'00). Note that the top area of the address range in which the branch address is stored is
also used for the exception vector area. For further details, refer to section 4, Exception Handling.

If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or the instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)

Specified
by @aa:8

Branch address

(a) Normal Mode (b) Advanced Mode

Specified
by @aa:8

Reserved

Branch address

Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode

Rev. 1.00, 05/04, page 43 of 544

2.7.9 Effective Address Calculation

Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Table 2.13 Effective Address Calculation (1)

No

Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1

Register direct (Rn)

op

2

Register indirect (@ERn)

op

Register indirect with displacement

3

@(d:16,ERn) or @(d:32,ERn)

op

Register indirect with post-increment or

4

pre-decrement

• Register indirect with post-increment @ERn+

p

o

• Register indirect with pre-decrement @-ERn

op

rn

rm

r

r

r

r

disp

31

General register contents

31

General register contents

1

3

Sign extension

31

General register contents

31

General register contents

Operand Size

Byte

Word

Longword

Offset

1
2
4

disp

1, 2, or 4

1, 2, or 4

Operand is general register contents.

0

0

0

0

0

312331

Don't care

312331

Don't care

312331

Don't care

31

31

Don't care

24

24

24

23

24

0

0

0

0

Rev. 1.00, 05/04, page 44 of 544

Table 2.13 Effective Address Calculation (2)

Addressing Mode and Instruction Format

No

5

Absolute address

@aa:8

op

abs

Effective Address Calculation Effective Address (EA)

312331

Don't care

0

7

24

8

H'FFFF

@aa:16

@aa:24

op

@aa:32

6

Immediate

/#xx:16/#xx:3

#xx:8

7

rogram-counter relative

P

(d:8,PC)/@(d:16,PC)

@

8

Memory indirect @@aa:8

op

23

24

31

31

op

op

2

op

op

abs

abs

abs

abs

IMM

disp

disp

0

0

0

7

8

bs

a

0

23

PC contents

23

Sign

extension

31

H'000000

15

Memory contents

Sign extension

Don't care

24

312331

Don't care

312331

24

Don't care

Operand is immediate data.

312331

24

Don't care

3

31

2

31

24

Don't care

H

15

16

5

1

16

'00

0

0

0

0

0

p

o

abs

31

H'000000

31

Memory contents

8

0

7

abs

31

23

31

24

on't care

D

0

0

Rev. 1.00, 05/04, page 45 of 544

2.8 Processing States

The H8S/2000 CPU has four main processing states: the reset state, exception handling state,
program execution state, and program stop state. Figure 2.13 indicates the state transitions.

• Reset state

In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, refer to section 4, Exception Handling.

The reset state can also be entered by a watchdog timer overflow.

• Exception-handling state

The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.

• Program execution state

In this state the CPU executes program instructions in sequence.

• Program stop state

This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
refer to section 20, Power-Down Modes.

Rev. 1.00, 05/04, page 46 of 544

End of
exception
handling

Exception-handling state

RES = high

Program execution

state

Request for
exception
handling

Interrupt
request

External interrupt
request

SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1

SLEEP
instruction
with
LSON = 0,
SSBY = 0

Sleep mode

Software standby mode

Notes: 1.

Reset state*

From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.

2.
The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details,

3.
refer to section 20, Power-Down Modes.

1

STBY = high, RES = low

Hardware standby mode*

Power-down state*

3

Figure 2.13 State Transitions

2

Rev. 1.00, 05/04, page 47 of 544

2.9 Usage Notes

2.9.1 Note on TAS Instruction Usage

When using the TAS instruction, use registers ER0, ER1, ER4 and ER5.

The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++
compilers. When the TAS instruction is used as a user-defined intrinsic function, use registers
ER0, ER1, ER4 and ER5.

2.9.2 Note on STM/LDM Instruction Usage

ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM
instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored
by one STM/LDM instruction. The following ranges can be specified in the register list.

Two registers: ER0—ER1, ER2—ER3, or ER4—ER5

Three registers: ER0—ER2 or ER4—ER6

Four registers: ER0—ER3

The STM/LDM instruction including ER7 is not generated by the Renesas Technology H8S and
H8/300 series C/C++ compilers.

2.9.3 Note on Bit Manipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions read data in byte units, manipulate the
data of the target bit, and write data in byte units. Special care is required when using these
instructions in cases where a register containing a write-only bit is used or a bit is directly
manipulated for a port.

In addition, the BCLR instruction can be used to clear the flag of the internal I/O register. In this
case, if the flag to be cleared has been set to 1 by an interrupt processing routine, the flag need not
be read before executing the BCLR instruction.

Rev. 1.00, 05/04, page 48 of 544

2.9.4 EEPMOV Instruction

1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6.

R5

R6

R5 + R4L

R6 + R4L

2. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does
not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during
execution).

R5

R6

R5 + R4L

Invalid

H'FFFF

R6 + R4L

Rev. 1.00, 05/04, page 49 of 544

Rev. 1.00, 05/04, page 50 of 544

Section 3 MCU Operating Modes

3.1 MCU Operating Mode Selection

This LSI has two operating modes (modes 2 and 3). The operating mode is determined by the
setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU operating mode selection.

Table 3.1 lists the MCU operating modes.

Table 3.1 MCU Operating Mode Selection

MCU
Operating
Mode

2 0 Advanced Single-chip mode

3

MD1 MD0

1

CPU
Operating
Mode

1 Normal Single-chip mode

Description On-Chip ROM

Enabled

Modes 2 and 3 set the operation in single-chip mode.

Modes 0 and 1 cannot be used in this LSI. Thus, mode pins should be set to enable mode 2 or 3 in
normal program execution state. Mode pins should not be changed during operation.

Rev. 1.00, 05/04, page 51 of 544

3.2 Register Descriptions

The following registers are related to the operating mode.

Mode control register (MDCR)

System control register (SYSCR)

Serial timer control register (STCR)

3.2.1 Mode Control Register (MDCR)

MDCR is used to monitor the current operating mode.

Initial

Bit Bit Name

7 EXPE 0

6
to
2

1

0

Note: * The initial values are determined by the settings of the MD1 and MD0 pins.

— All 0 R Reserved

MDS1

MDS0

Value R/W Description

R/W Reserved

The initial value should not be changed.

These bits are always read as 0. These bits cannot be
modified.

—*

—*

R

R

Mode Select 1 and 0

These bits indicate the input levels at mode pins (MD1
and MD0) (the current operating mode). Bits MDS1
and MDS0 correspond to MD1 and MD0, respectively.
These bits are read-only bits and they cannot be
written to. The mode pin (MD1 and MD0) input levels
are latched into these bits when MDCR is read. These
latches are canceled by a reset.

Rev. 1.00, 05/04, page 52 of 544

3.2.2 System Control Register (SYSCR)

SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, pin location selection, enables or disables register access to the
on-chip peripheral modules, and enables or disables on-chip RAM address space.

Initial

Bit Bit Name

7 and 6 — All 0 R/W Reserved

5

4

3 XRST 1 R External Reset

2 NMIEG 0 R/W NMI Edge Select

INTM1

INTM0 0 0

Value R/W Description

The initial value should not be changed.

R

R/W

These bits select the control mode of the interrupt
controller. For details on the interrupt control modes
and interrupt control select modes 1 and 0, see
section 5.6, Interrupt Control Modes and Interrupt
Operation.

00: Interrupt control mode 0

01: Interrupt control mode 1

10: Setting prohibited

11: Setting prohibited

This bit indicates the reset source. A reset is caused
by an external reset input, or when the watchdog
timer overflows.

0: A reset is caused when the watchdog timer

overflows.

1: A reset is caused by an external reset.

Selects the valid edge of the NMI interrupt input.

0: An interrupt is requested at the falling edge of NMI

input

1: An interrupt is requested at the rising edge of NMI

input

Rev. 1.00, 05/04, page 53 of 544

Initial

Bit Bit Name

1 HIE 0 R/W Host Interface Enable

0 RAME 1 R/W RAM Enable

Value R/W Description

Controls CPU access to the keyboard matrix interrupt,
input pull-up MOS control registers (KMIMR, KMPCR,
and KMIMRA), and the 8-bit timer (TMR_X and
TMR_Y) registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y,
TICRR/TCORA_Y, TICRF/TCORB_Y,
TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and
TCORB_X, TCONRI, and TCONRS).

0: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC

to H'(FF)FFFF, CPU access to 8-bit timer (TMR_X
and TMR_Y) is permitted.

1: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC

to H'(FF)FFFF, CPU access to keyboard matrix
interrupt and input pull-up MOS control registers is
permitted.

Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.

0: On-chip RAM is disabled

1: On-chip RAM is enabled

Rev. 1.00, 05/04, page 54 of 544

3.2.3 Serial Timer Control Register (STCR)

STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.

Initial

Bit Bit Name

7 IICS 0 R/W I2C Extra Buffer Select

6

5

IICX1

IICX0

4 IICE 0 R/W I2C Master Enable

Value R/W Description

Specifies bits 7 to 4 of port A as output buffers similar
to SLC and SDA. These pins are used to implement

2

C interface only by software.

an I

0: PA7 to PA4 are normal input/output pins.

1: PA7 to PA4 are input/output pins enabling bus

driving.

0

0

R/W

R/W

I2C Transfer Rate Select 1 and 0

These bits control the IIC operation. These bits select
a transfer rate in master mode together with bits
CKS2 to CKS0 in the I
For details on the transfer rate, refer to table 13.3.

Enables or disables CPU access for IIC registers
(ICCR, ICSR, ICDR/SARX, ICMR/SAR), and SCI
registers (SMR, BRR, SCMR).

0: SCI_1 registers are accessed in an area from

H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.

1: IIC_1 registers are accessed in an area from

H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.

IIC_0 registers are accessed in an area from
H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to
H'(FF)FFDF.

2

C bus mode register (ICMR).

Rev. 1.00, 05/04, page 55 of 544

Initial

Bit Bit Name

3 FLSHE 0 R/W Flash Memory Control Register Enable

2 — 0 R/(W) Reserved

1

0

ICKS1

ICKS0 0 0

Value R/W Description

Enables or disables CPU access for flash memory
registers (FLMCR1, FLMCR2, EBR1, EBR2), control
registers in power-down state (SBYCR, LPWRCR,
MSTPCRH, MSTPCRL), and control registers of on­chip peripheral modules (PCSR, SYSCR2).

0: Registers in power-down state and control registers

of on-chip peripheral modules are accessed in an
area from H'(FF)FF80 to H'(FF)FF87.

1: Control registers of flash memory are accessed in

an area from H'(FF)FF80 to H'(FF)FF87.

The initial value should not be changed.

R/W

R/W

Internal Clock Source Select 1, 0

These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register (TCR).
For details, refer to section 10.3.4, Timer Control
Register (TCR).

3.3 Operating Mode Descriptions

3.3.1 Mode 2

The CPU can access a 16-Mbyte address space in advanced single-chip mode. The on-chip ROM
is enabled.

3.3.2 Mode 3

The CPU can access a 64-Kbyte address space in normal single-chip mode. The on-chip ROM is
enabled. The CPU can access a 56-kbyte address space in mode 3.

Rev. 1.00, 05/04, page 56 of 544

3.4 Address Map

Figures 3.1 and 3.2 show the address map in each operating mode.

H'000000

H'00FFFF

H'01FFFF

H'FFE080
H'FFE880

H'FFEFFF

Mode 2 (EXPE = 0)
Advanced mode
Single-chip mode

On-chip ROM

Reserved area

Reserved area

On-chip RAM

H'0000

H'DFFF

H'E080

H'E880

H'EFFF

Mode 3 (EXPE = 0)
Normal mode
Single-chip mode

On-chip ROM

Reserved area

On-chip RAM

H'FFF800
H'FFFE4F

H'FFFE50
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF

Internal I/O

registers 3

Internal I/O

registers 2

On-chip RAM

(128 bytes)
Internal I/O

registers 1

H'F800
H'FE4F

H'FE50
H'FEFF
H'FF00
H'FF7F
H'FF80
H'FFFF

Internal I/O
registers 3

Internal I/O
registers 2

On-chip RAM

(128 bytes)
Internal I/O

registers 1

Figure 3.1 Address Map for H8S/2111B-B

Rev. 1.00, 05/04, page 57 of 544

H'000000

Mode 2 (EXPE = 0)
Advanced mode
Single-chip mode

On-chip ROM

Mode 3 (EXPE = 0)
Normal mode
Single-chip mode

H'0000

H'00FFFF

H'01FFFF

H'FFE080
H'FFE480

H'FFEFFF

H'FFF800
H'FFFE4F

H'FFFE50
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF

On-chip ROM

Reserved area

H'DFFF

Reserved area

On-chip RAM

Internal I/O

registers 3

Internal I/O

registers 2

On-chip RAM

(128 bytes)
Internal I/O

registers 1

H'E080

H'E480

H'EFFF

H'F800
H'FE4F

H'FE50
H'FEFF
H'FF00
H'FF7F
H'FF80
H'FFFF

Reserved area

On-chip RAM

Internal I/O

registers 3

Internal I/O

registers 2

On-chip RAM

(128 bytes)
Internal I/O

registers 1

Figure 3.2 Address Map for H8S/2111B-C

Rev. 1.00, 05/04, page 58 of 544

Section 4 Exception Handling

4.1 Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or
trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority.

Table 4.1 Exception Types and Priority

Priority Exception Type Start of Exception Handling

High

Low

Reset Starts immediately after a low-to-high transition of the RES

pin, or when the watchdog timer overflows.

Interrupt Starts when execution of the current instruction or exception

handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.

Direct transition Starts when a direction transition occurs as the result of

SLEEP instruction execution.

Trap instruction Started by execution of a trap (TRAPA) instruction. Trap

instruction exception handling requests are accepted at all
times in program execution state.

Rev. 1.00, 05/04, page 59 of 544

4.2 Exception Sources and Exception Vector Table

Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses.

Table 4.2 Exception Handling Vector Table

Vector Address

Exception Source Vector Number Normal Mode Advanced Mode

Reset 0 H'0000 to H'0001 H'000000 to H'000003

Reserved for system use 1


5

Direct transition 6 H'000C to H'000D H'000018 to H'00001B

External interrupt (NMI) 7 H'000E to H'000F H'00001C to H'00001F

Trap instruction (four
sources)

Reserved for system use 12

External interrupt

Internal interrupt* 24

Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception

Handling Vector Table.

IRQ0 16 H'0020 to H'0021 H'000040 to H'000043

IRQ1 17 H'0022 to H'0023 H'000044 to H'000047

IRQ2 18 H'0024 to H'0025 H'000048 to H'00004B

IRQ3 19 H'0026 to H'0027 H'00004C to H'00004F

IRQ4 20 H'0028 to H'0029 H'000050 to H'000053

IRQ5 21 H'002A to H'002B H'000054 to H'000057

IRQ6 22 H'002C to H'002D H'000058 to H'00005B

IRQ7 23 H'002E to H'002F H'00005C to H'00005F

8 H'0010 to H'0011 H'000020 to H'000023

9 H'0012 to H'0013 H'000024 to H'000027

10 H'0014 to H'0015 H'000028 to H'00002B

11 H'0016 to H'0017 H'00002C to H'00002F


15


111

H'0002 to H'0003
|
H'000A to H'000B

H'0018 to H'0019
|
H'001E to H'001F

H'0030 to H'0031

H'00DE to H'00DF

H'000004 to H'000007
|
H'000014 to H'000017

H'000030 to H'000033
|
H'00003C to H'00003F

H'000060 to H'000063

H'0001BC to H'0001BF

Rev. 1.00, 05/04, page 60 of 544

4.3 Reset

A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip
can also be reset by overflow of the watchdog timer. For details, see section 11, Watchdog Timer
(WDT).

4.3.1 Reset Exception Handling

When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized
and the I bit is set to 1 in CCR.

2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.

Figure 4.1 shows an example of the reset sequence.

Vector

fetch

φ

RES

Internal address bus

Internal read signal

Internal write signal

Internal data bus

(1) Reset exception handling vector address ((1) = H'0000)
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First program instruction

Internal

processing

(1) (3)

(2) (4)

Prefetch of first program
instruction

High

Figure 4.1 Reset Sequence (Mode 3)

Rev. 1.00, 05/04, page 61 of 544

4.3.2 Interrupts after Reset

If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).

4.3.3 On-Chip Peripheral Modules after Reset is Cancelled

After a reset is cancelled, the module stop control registers (MSTPCR) are initialized, and all
modules operate in module stop mode. Therefore, the registers of on-chip peripheral modules
cannot be read from or written to. To read from and write to these registers, clear module stop
mode.

Rev. 1.00, 05/04, page 62 of 544

4.4 Interrupt Exception Handling

Interrupts are controlled by the interrupt controller. The sources to start interrupt exception
handling are external interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to
WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt
with the highest priority. For details, refer to section 5, Interrupt Controller.

Interrupt exception handling is conducted as follows:

1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.

2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution begins from that address.

4.5 Trap Instruction Exception Handling

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.

Trap instruction exception handling is conducted as follows:

1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.

2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.

Table 4.3 shows the status of CCR after execution of trap instruction exception handling.

Table 4.3 Status of CCR after Trap Instruction Exception Handling

CCR

Interrupt Control Mode I UI

0 1 —

1 1 1

[Legend]
1: Set to 1
—: Retains value prior to execution

Rev. 1.00, 05/04, page 63 of 544

4.6 Stack Status after Exception Handling

Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.

Normal mode

SP SP

Note: Ignored on return.

CCR

CCR*

PC

(16 bits)

Figure 4.2 Stack Status after Exception Handling

Advanced mode

CCR

PC

(24 bits)

Rev. 1.00, 05/04, page 64 of 544

4.7 Usage Note

When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed in words or longwords, and the value of the stack pointer (SP:
ER7) should always be kept even.

Use the following instructions to save registers:

PUSH.W Rn (or MOV.W Rn, @-SP)

PUSH.L ERn (or MOV.L ERn, @-SP)

Use the following instructions to restore registers:

POP.W Rn (or MOV.W @SP+, Rn)

POP.L ERn

Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what
happens when the SP value is odd.

(or MOV.L @SP+, ERn)

Address

CCR

SP

PC

SP

TRAPA instruction executed

SP set to H'FFFEFF Data saved above SP

[Legend]

CCR:

Condition code register

PC:

Program counter

R1L:

General register R1L

SP:

Stack pointer

Note: This diagram illustrates an example in which the interrupt control mode is 0 in advanced mode.

SP

MOV.B R1L, @-ER7 executed

R1L

PC

Contents of CCR lost

Figure 4.3 Operation when SP Value is Odd

Rev. 1.00, 05/04, page 65 of 544

H'FFEFFA

H'FFEFFB

H'FFEFFC

H'FFEFFD

H'FFEFFF

Rev. 1.00, 05/04, page 66 of 544