1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
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7. If these products or technologies are subject to the Japanese export control restrictions, they must
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
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8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 1.00, 05/04, page iii of xxxiv
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 1.00, 05/04, page iv of xxxiv
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.00, 05/04, page v of xxxiv
Preface
The H8S/2111B is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas
Technology's original architecture as its core, and the peripheral functions required to configure a
system.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space.
This LSI is equipped with ROM, RAM, a 16-bit free-running timer (FRT), an 8-bit timer (TMR),
a watchdog timer (WDT), a serial communication interface (SCI), a keyboard buffer controller, a
host interface (LPC), an I
required for system configuration.
2
C bus interface (IIC), and I/O ports as on-chip peripheral modules,
A flash memory (F-ZTAT
TM
*) version is available for this LSI's ROM. This provides flexibility as
it can be reprogrammed in no time to cope with all situations from the early stages of mass
production to full-scale mass production. This is particularly applicable to application devices with
specifications that will most probably change.
Note: * F-ZTAT
TM
is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using the H8S/2111B in the design
of application systems. Target users are expected to understand the fundamentals
of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2111B to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 21,
List of Registers.
Rev. 1.00, 05/04, page vi of xxxiv
Rules: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/
H8S/2111B manuals:
Document Title Document No.
H8S/2111B Hardware Manual This manual
H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139
Keyboard buffer controller data input/output
pins.
Rev. 1.00, 05/04, page 10 of 544
Pin No.
Type Symbol TFP-144 I/O Name and Function
Host interface
(LPC)
Keyboard
buffer
controller
A/D converter
LAD3 to
LAD0
LFRAME 125 Input Input pin that indicates the start of an LPC
LRESET 126 Input Input pin that indicates an LPC reset.
LCLK 127 Input The LPC clock input pin.
SERIRQ 128 Input/
LSCI, LSMI,
PME
GA20 130 Input/
CLKRUN 131 Input/
LPCPD 132 Input Input pin that controls LPC module shutdown.
KIN0 to
KIN15
WUE0 to
WUE7
AN5 to AN0 73 to 68 Input Analog input pins.
ADTRG 24 Input Pin for input of an external trigger to start A/D
AVCC 76 Input The analog power supply pin for the A/D
AVref 77 Input The reference power supply pin for the A/D
AVSS 67 Input The ground pin for the A/D converter. This
124 to 121 Input/
Output
Output
119, 120,
129
78 to 85,
41 to 37,
35 to 33
120 to 113 Input Wakeup event input pins. These pins allow
Input/
Output
Output
Output
Input Matrix keyboard input pins. KIN0 to KIN15
LPC command, address, and data
input/output pins.
cycle or forced termination of an abnormal
LPC cycle.
Input/output pin for LPC serialized host
interrupts (HIRQ1, SMI, HIRQ6, HIRQ9 to
HIRQ12).
LPC auxiliary output pins. Functionally, they
are general I/O ports.
A20 gate control signal output pin. Output
state monitoring input is possible.
Input/output pin that requests the start of
LCLK operation when LCLK is stopped.
are used as key-scan inputs, and P10 to P17
and P20 to P27 are used as key-scan
outputs. This allows a maximum 16-output ×
16-input, 256-key matrix to be configured.
the same kind of wakeup as key-wakeup
from various sources.
conversion.
converter.
When the A/D is not used, this pin should be
connected to the system power supply (+3
V).
converter and.
When the A/D is not used, this pin should be
connected to the system power supply (+3
V).
pin should be connected to the system power
supply
(0 V).
Rev. 1.00, 05/04, page 11 of 544
Pin No.
Type Symbol TFP-144 I/O Name and Function
I2C bus
interface (IIC)
SDA0
I/O ports P17 to P10 104 to 110,
P27 to P20 96 to 103 Input/
P37 to P30 128 to 121 Input/
P47 to P40 6 to 2,
P52 to P50 14 to 16 Input/
P67 to P60 85 to 78 Input/
P77 to P70 75 to 68 Input Eight input pins.
P86 to P80 135 to 129 Input/
P97 to P90 17 to 24 Input/
PA7 to PA0 33 to 35,
PB7 to PB0 113 to 120 Input/
PC7 to PC0 87 to 94 Input/
PD7 to PD0 59 to 66 Input/
PE7 to PE0 25 to 32 Input/
Note: * The program development tool (emulator) does not support this function.
SCL0
SCL1
ExSCLA*
ExSCLB*
SDA1
ExSDAA*
ExSDAB*
PF7 to PF0 43 to 50 Input/
PG7 to PG0 51 to 58 Input/
14
135
53
51
17
138
54
52
112
138 to 136
37 to 41
Input/
Output
Input/
Output
Input/
Output
Output
Output
Input/
Output
Output
Output
Output
Output
Input/
Output
Output
Output
Output
Output
Output
Output
I2C clock I/O pins. The output type is NMOS
open-drain output.
I2C data I/O pins. The output type is NMOS
open-drain output.
Eight input/output pins.
Eight input/output pins.
Eight input/output pins.
Eight input/output pins.
(The output type of P42 is NMOS push-pull.)
Three input/output pins.
(The output type of P52 is NMOS push-pull.)
Eight input/output pins.
Seven input/output pins.
(The output type of P86 is NMOS push-pull.)
Eight input/output pins.
(The output type of P97 is NMOS push-pull.)
Eight input/output pins.
Eight input/output pins.
Eight input/output pins.
Eight input/output pins.
Eight input/output pins.
Eight input/output pins.
Eight input/output pins.
(The output type of PG7 to PG0 is NMOS
push-pull.)
Rev. 1.00, 05/04, page 12 of 544
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1 Features
• Upward-compatibility with H8/300 and H8/300H CPUs
Can execute H8/300 CPU and H8/300H CPU object programs
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes
• High-speed operation
All frequently-used instructions are executed in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
CPU210A_020020040200 Rev. 1.00, 05/04, page 13 of 544
• Two CPU operating modes
Normal mode
Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruction
Selectable CPU clock speed
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction Mnemonic
MULXU.B Rs, Rd 3 12 MULXU
MULXU.W Rs, ERd 4 20
MULXS.B Rs, Rd 4 13 MULXS
MULXS.W Rs, ERd 5 21
H8S/2600 H8S/2000
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
Rev. 1.00, 05/04, page 14 of 544
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit extended registers and one 8-bit control register have been added.
• Expanded address space
Normal mode supports the same 64-Kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions are executed twice as fast.
2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
One 8-bit control register has been added.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions are executed twice as fast.
Rev. 1.00, 05/04, page 15 of 544
2.2 CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte address
space. The mode is selected by the LSI's mode pins.
2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU in normal
mode.
• Address space
Linear access to a maximum address space of 64 Kbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When extended register En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. (If general register Rn is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended
register (En) will be affected.)
• Instruction set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception vector table and memory indirect branch addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details on the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
• Stack structure
In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call
in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.2. The extended control register
(EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.
Linear access to a maximum address space of 16 Mbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the
upper 16-bit segments of 32-bit registers or address registers.
• Instruction set
All instructions and addressing modes can be used.
• Exception vector table and memory indirect branch addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored
in the lower 24 bits (see figure 2.3). For details on the exception vector table, see section 4,
Exception Handling.
H'00000000
H'00000003
H'00000004
H'00000007
H'00000008
H'0000000B
H'0000000C
H'00000010
Reserved
Reset exception vector
Reserved
(Reserved for system use)
Exception vector table
(Reserved for system use)
Reserved
Exception vector 1
Figure 2.3 Exception Vector Table (Advanced Mode)
Rev. 1.00, 05/04, page 18 of 544
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the top area of this range is also used for the exception vector table.
• Stack structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC and condition-code register (CCR) are pushed onto the stack in exception
handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not
pushed onto the stack. For details, see section 4, Exception Handling.
SP
Reserved
PC
(24 bits)
(a) Subroutine Branch(b) Exception Handling
SP
CCR
PC
(24 bits)
Figure 2.4 Stack Structure in Advanced Mode
Rev. 1.00, 05/04, page 19 of 544
2.3 Address Space
Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.
H'0000
H'FFFF
64 Kbytes
H'00000000
16 Mbytes
H'00FFFFFF
Not available
in this LSI
H'FFFFFFFF
(b) Advanced Mode(a) Normal Mode
Figure 2.5 Memory Map
Program area
Data area
Rev. 1.00, 05/04, page 20 of 544
2.4 Register Configuration
The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit
extended control register (EXR), and an 8-bit condition code register (CCR).
General Registers (Rn) and Extended Registers (En)
150 70 70
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
Control Registers
[Legend]
SP:
Stack pointer
PC:
Program counter
EXR:
Extended control register
T:
Trace bit
I2 to I0:
Interrupt mask bits
CCR:
Condition-code register
I:
Interrupt mask bit
UI:
User bit or interrupt mask bit
Note: * Does not affect operation in this LSI.
230
H:
U:
N:
Z:
V:
C:
Figure 2.6 CPU Internal Registers
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
PC
76543210
TI2I1I0EXR*
----
76543210
CCR
IUIHUNZVC
Rev. 1.00, 05/04, page 21 of 544
2.4.1 General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers.
When the general registers are used as 32-bit registers or address registers, they are designated by
the letters ER (ER0 to ER7).
When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7)
are also referred to as extended registers.
When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing a maximum sixteen 8-bit registers.
The usage of each register can be selected independently.
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
ER registers
(ER0 to ER7)
Figure 2.7 Usage of General Registers
Rev. 1.00, 05/04, page 22 of 544
• 16-bit registers• 8-bit registers
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Free area
SP (ER7)
Stack area
Figure 2.8 Stack
2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3 Extended Control Register (EXR)
EXR does not affect operation in this LSI.
Initial
Bit Bit Name
7 T 0 R/W Trace Bit
6 to 3 — All 1 R Reserved
2 to 0 I2
I1
I0
Value
All 1 R/W Interrupt Mask Bits 2 to 0
R/W Description
Does not affect operation in this LSI.
These bits are always read as 1.
Do not affect operation in this LSI.
Rev. 1.00, 05/04, page 23 of 544
2.4.4 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be
performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V,
and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Initial
Bit Bit Name
7 I 1 R/W Interrupt Mask Bit
6 UI Undefined R/W User Bit or Interrupt Mask Bit
5 H Undefined R/W Half-Carry Flag
4 U Undefined R/W User Bit
3 N Undefined R/W Negative Flag
2 Z Undefined R/W Zero Flag
1 V Undefined R/W Overflow Flag
Value R/W Description
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence. For
details, refer to section 5, Interrupt Controller.
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
Stores the value of the most significant bit of data as a
sign bit.
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.
Rev. 1.00, 05/04, page 24 of 544
Initial
Bit Bit Name
0 C Undefined R/W Carry Flag
Value R/W Description
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
2.4.5 Initial Register Values
The program counter (PC) among CPU internal registers is initialized when reset exception
handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the
interrupt mask (I) bits in CCR and EXR are set to 1. The other CCR bits and the general registers
are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should
therefore be initialized by an MOV.L instruction executed immediately after a reset.
Rev. 1.00, 05/04, page 25 of 544
2.5 Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figure 2.9 shows the data formats of general registers.
Data TypeRegister NumberData Image
70
1-bit data
RnH
6543271
0
Don't care
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
7
RnL
RnH
RnL
RnH
RnL
Don't care
7
UpperLower
7
MSBLSB
3
Don't care
Don't care
65432710
04
Don't care
704
UpperLower
0
7
MSBLSB
Figure 2.9 General Register Data Formats (1)
0
3
Don't care
0
Rev. 1.00, 05/04, page 26 of 544
Data TypeData ImageRegister Number
Word data
Word data
150
MSBLSB
Longword data
3116
MSB
[Legend]
ERn:
General register ER
En:
General register E
Rn:
General register R
RnH:
General register RH
RnL:
General register RL
MSB:
Most significant bit
LSB :
Least significant bit
Rn
En
ERn
EnRn
Figure 2.9 General Register Data Formats (2)
150
MSBLSB
150
LSB
Rev. 1.00, 05/04, page 27 of 544
2.5.2 Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Data TypeAddress
70
1-bit data
Byte data
Word data
Longword dataAddress 2N
Address L
Address L
Address 2M
Address 2M + 1
Address 2N + 1
Address 2N + 2
Address 2N + 3
76 543210
MSB
MSB
MSB
Figure 2.10 Memory Data Formats
Data Image
LSB
LSB
LSB
Rev. 1.00, 05/04, page 28 of 544
2.6 Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
Data transfer
Arithmetic
operations
Logic operations AND, OR, XOR, NOT B/W/L 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST,
Branch BCC*2, JMP, BSR, JSR, RTS — 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
Block data transfer EEPMOV — 1
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. B
3. Cannot be used in this LSI.
4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5.
5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using
CC
STM/LDM instruction, because ER7 is the stack pointer.
MOV B/W/L
POP*1, PUSH*1 W/L
LDM*5, STM*5 L
MOVFPE*3, MOVTPE*3 B
ADD, SUB, CMP, NEG B/W/L
ADDX, SUBX, DAA, DAS B
INC, DEC B/W/L
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
EXTU, EXTS W/L
TAS*4 B
B/W/L 8
ROTXR
B 14
BAND, BIAND, BOR, BIOR, BXOR, BIXOR
— 9
NOP
is the general name for conditional branch instructions.
5
19
Total: 65
Rev. 1.00, 05/04, page 29 of 544
2.6.1 Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2 Operation Notation
Symbol Description
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical exclusive OR
→ Move
∼ NOT (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev. 1.00, 05/04, page 30 of 544
Table 2.3 Data Transfer Instructions
Instruction Size*1 Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
MOVFPE B Cannot be used in this LSI.
MOVTPE B Cannot be used in this LSI.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn
PUSH W/L Rn → @-SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
LDM*2 L @SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM*2 L Rn (register list) → @-SP
Pushes two or more general registers onto the stack.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using
STM/LDM instruction, because ER7 is the stack pointer.
Rev. 1.00, 05/04, page 31 of 544
Table 2.4 Arithmetic Operations Instructions (1)
Instruction Size* Function
ADD
SUB
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or
on immediate data and data in a general register. (Subtraction on
immediate data and data in a general register cannot be performed in
bytes. Use the SUBX or ADD instruction.)
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
MULXU B/W Rd × Rs → Rd
MULXS B/W Rd × Rs → Rd
DIVXU B/W Rd ÷ Rs → Rd
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts the value 1 or 2 to or from data in a general
register. (Only the value 1 can be added to or subtracted from byte
operands.)
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit
register.
B Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register
by referring to CCR to produce 4-bit BCD data.
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Performs signed multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits
→ 16-bit quotient and 16-bit remainder.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00, 05/04, page 32 of 544
Table 2.4 Arithmetic Operations Instructions (2)
Instruction Size*1 Function
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits
→ 16-bit quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets the CCR bits according to
the result.
NEG B/W/L 0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower
16 bits of a 32-bit register to longword size, by padding with zeros on
the left.
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower
16 bits of a 32-bit register to longword size, by extending the sign bit.
TAS*2 B @ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. When using the TAS instruction, use registers ER0, ER1, ER4 and ER5.
Rev. 1.00, 05/04, page 33 of 544
Table 2.5 Logic Operations Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L ∼ Rd → Rd
Takes the one's complement (logical complement) of data in a
general register.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6 Shift Instructions
Instruction Size* Function
SHAL
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on data in a general register. 1-bit or 2
bit shift is possible.
SHLL
SHLR
ROTL
ROTR
ROTXL
ROTXR
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00, 05/04, page 34 of 544
B/W/L Rd (shift) → Rd
Performs a logical shift on data in a general register. 1-bit or 2 bit
shift is possible.
B/W/L Rd (rotate) → Rd
Rotates data in a general register. 1-bit or 2 bit rotation is possible.
B/W/L Rd (rotate) → Rd
Rotates data including the carry flag in a general register. 1-bit or 2
bit rotation is possible.
Table 2.7 Bit Manipulation Instructions (1)
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.
BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The
bit number is specified by 3-bit immediate data or the lower three bits
of a general register.
BTST B ∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and
sets or clears the Z flag accordingly. The bit number is specified by
3-bit immediate data or the lower three bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.
BIAND B C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BOR B C ∨ (<bit-No.> of <EAd>) → C
Logically ORs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.
BIOR B C ∨ (∼ <bit-No.> of <EAd>) → C
Logically ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
Rev. 1.00, 05/04, page 35 of 544
Table 2.7 Bit Manipulation Instructions (2)
Instruction Size* Function
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry flag.
BIXOR B C ⊕ ∼ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with the inverse of a specified
bit in a general register or memory operand and stores the result in
the carry flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to
the carry flag.
BILD B ∼ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or
memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register
or memory operand.
BIST B ∼ C → (<bit-No.>. of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
Rev. 1.00, 05/04, page 36 of 544
Table 2.8 Branch Instructions
Instruction Size Function
Bcc —
JMP — Branches unconditionally to a specified address.
BSR — Branches to a subroutine at a specified address
JSR — Branches to a subroutine at a specified address
RTS — Returns from a subroutine
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC (BHS) Carry clear
(high or same)
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1
C = 0
Rev. 1.00, 05/04, page 37 of 544
Table 2.9 System Control Instructions
Instruction Size* Function
TRAPA — Starts trap-instruction exception handling.
RTE — Returns from an exception-handling routine.
SLEEP — Causes a transition to a power-down state.
LDC B/W (EAs) → CCR, (EAs) → EXR
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are
valid.
STC B/W CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate
data.
NOP — PC + 2 → PC
Only increments the program counter.
Note: * Size refers to the operand size.
B: Byte
W: Word
Table 2.10 Block Data Transfer Instructions
Instruction Size Function
EEPMOV.B —
EEPMOV.W —
Rev. 1.00, 05/04, page 38 of 544
if R4L ≠ 0 then
Repeat @ER5 + → @ER6+
R4L–1 → R4L Until R4L = 0
else next;
if R4 ≠ 0 then
Repeat @ER5 + → @ER6+
R4–1 → R4 Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5,
transfers data for the number of bytes set in R4L or R4 to the
address location set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2 Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields, and some have no register field.
• Effective address extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition field
Specifies the branching condition of Bcc instructions.
(1) Operation field only
op
NOP, RTS
(2) Operation field and register fields
op
(3) Operation field, register fields, and effective address extension
op
EA (disp)
(4) Operation field, effective address extension, and condition field
opccEA (disp)BRA d:16
rn
rnrm
rm
Figure 2.11 Instruction Formats (Examples)
ADD.B Rn, Rm
MOV.B @(d:16, Rn), Rm
Rev. 1.00, 05/04, page 39 of 544
2.7 Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
@ERn+
@–ERn
2.7.1 Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2 Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).
Rev. 1.00, 05/04, page 40 of 544
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction code is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register Indirect with Post-Increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word access, and 4 for longword
access. For word or longword transfer instructions, the register value should be even.
Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or
longword transfer instructions, the register value should be even.
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address,
the entire address space is accessed.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.12 Absolute Address Access Ranges
Absolute Address Normal Mode Advanced Mode
Data address
Program instruction
address
8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits (@aa:16) H'000000 to H'007FFF,
32 bits (@aa:32)
24 bits (@aa:24)
H'0000 to H'FFFF
H'FF8000 to H'FFFFFF
H'000000 to H'FFFFFF
Rev. 1.00, 05/04, page 41 of 544
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction
code can be used directly as an operand.
The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address
indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this
branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which
the displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
Rev. 1.00, 05/04, page 42 of 544
2.7.8 Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand which contains a branch address. The upper bits of
the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to
H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode, the memory operand is a longword operand, the first byte of which is assumed to
be 0 (H'00). Note that the top area of the address range in which the branch address is stored is
also used for the exception vector area. For further details, refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or the instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
Specified
by @aa:8
Branch address
(a) Normal Mode(b) Advanced Mode
Specified
by @aa:8
Reserved
Branch address
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
Rev. 1.00, 05/04, page 43 of 544
2.7.9 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Table 2.13 Effective Address Calculation (1)
No
Addressing Mode and Instruction FormatEffective Address CalculationEffective Address (EA)
The H8S/2000 CPU has four main processing states: the reset state, exception handling state,
program execution state, and program stop state. Figure 2.13 indicates the state transitions.
• Reset state
In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
• Program execution state
In this state the CPU executes program instructions in sequence.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
refer to section 20, Power-Down Modes.
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
2.
The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details,
3.
refer to section 20, Power-Down Modes.
1
STBY = high, RES = low
Hardware standby mode*
Power-down state*
3
Figure 2.13 State Transitions
2
Rev. 1.00, 05/04, page 47 of 544
2.9 Usage Notes
2.9.1 Note on TAS Instruction Usage
When using the TAS instruction, use registers ER0, ER1, ER4 and ER5.
The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++
compilers. When the TAS instruction is used as a user-defined intrinsic function, use registers
ER0, ER1, ER4 and ER5.
2.9.2 Note on STM/LDM Instruction Usage
ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM
instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored
by one STM/LDM instruction. The following ranges can be specified in the register list.
Two registers: ER0—ER1, ER2—ER3, or ER4—ER5
Three registers: ER0—ER2 or ER4—ER6
Four registers: ER0—ER3
The STM/LDM instruction including ER7 is not generated by the Renesas Technology H8S and
H8/300 series C/C++ compilers.
2.9.3 Note on Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read data in byte units, manipulate the
data of the target bit, and write data in byte units. Special care is required when using these
instructions in cases where a register containing a write-only bit is used or a bit is directly
manipulated for a port.
In addition, the BCLR instruction can be used to clear the flag of the internal I/O register. In this
case, if the flag to be cleared has been set to 1 by an interrupt processing routine, the flag need not
be read before executing the BCLR instruction.
Rev. 1.00, 05/04, page 48 of 544
2.9.4 EEPMOV Instruction
1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6.
R5
R6
R5 + R4L
R6 + R4L
2. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does
not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during
execution).
R5
R6
R5 + R4L
Invalid
H'FFFF
R6 + R4L
Rev. 1.00, 05/04, page 49 of 544
Rev. 1.00, 05/04, page 50 of 544
Section 3 MCU Operating Modes
3.1 MCU Operating Mode Selection
This LSI has two operating modes (modes 2 and 3). The operating mode is determined by the
setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU operating mode selection.
Table 3.1 lists the MCU operating modes.
Table 3.1 MCU Operating Mode Selection
MCU
Operating
Mode
2 0 Advanced Single-chip mode
3
MD1 MD0
1
CPU
Operating
Mode
1 Normal Single-chip mode
Description On-Chip ROM
Enabled
Modes 2 and 3 set the operation in single-chip mode.
Modes 0 and 1 cannot be used in this LSI. Thus, mode pins should be set to enable mode 2 or 3 in
normal program execution state. Mode pins should not be changed during operation.
Rev. 1.00, 05/04, page 51 of 544
3.2 Register Descriptions
The following registers are related to the operating mode.
Mode control register (MDCR)
System control register (SYSCR)
Serial timer control register (STCR)
3.2.1 Mode Control Register (MDCR)
MDCR is used to monitor the current operating mode.
Initial
Bit Bit Name
7 EXPE 0
6
to
2
1
0
Note: * The initial values are determined by the settings of the MD1 and MD0 pins.
— All 0 R Reserved
MDS1
MDS0
Value R/W Description
R/W Reserved
The initial value should not be changed.
These bits are always read as 0. These bits cannot be
modified.
—*
—*
R
R
Mode Select 1 and 0
These bits indicate the input levels at mode pins (MD1
and MD0) (the current operating mode). Bits MDS1
and MDS0 correspond to MD1 and MD0, respectively.
These bits are read-only bits and they cannot be
written to. The mode pin (MD1 and MD0) input levels
are latched into these bits when MDCR is read. These
latches are canceled by a reset.
Rev. 1.00, 05/04, page 52 of 544
3.2.2 System Control Register (SYSCR)
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, pin location selection, enables or disables register access to the
on-chip peripheral modules, and enables or disables on-chip RAM address space.
Initial
Bit Bit Name
7 and 6 — All 0 R/W Reserved
5
4
3 XRST 1 R External Reset
2 NMIEG 0 R/W NMI Edge Select
INTM1
INTM0 0 0
Value R/W Description
The initial value should not be changed.
R
R/W
These bits select the control mode of the interrupt
controller. For details on the interrupt control modes
and interrupt control select modes 1 and 0, see
section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
This bit indicates the reset source. A reset is caused
by an external reset input, or when the watchdog
timer overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
Rev. 1.00, 05/04, page 53 of 544
Initial
Bit Bit Name
1 HIE 0 R/W Host Interface Enable
0 RAME 1 R/W RAM Enable
Value R/W Description
Controls CPU access to the keyboard matrix interrupt,
input pull-up MOS control registers (KMIMR, KMPCR,
and KMIMRA), and the 8-bit timer (TMR_X and
TMR_Y) registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y,
TICRR/TCORA_Y, TICRF/TCORB_Y,
TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and
TCORB_X, TCONRI, and TCONRS).
0: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC
to H'(FF)FFFF, CPU access to 8-bit timer (TMR_X
and TMR_Y) is permitted.
1: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC
to H'(FF)FFFF, CPU access to keyboard matrix
interrupt and input pull-up MOS control registers is
permitted.
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Rev. 1.00, 05/04, page 54 of 544
3.2.3 Serial Timer Control Register (STCR)
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Initial
Bit Bit Name
7 IICS 0 R/W I2C Extra Buffer Select
6
5
IICX1
IICX0
4 IICE 0 R/W I2C Master Enable
Value R/W Description
Specifies bits 7 to 4 of port A as output buffers similar
to SLC and SDA. These pins are used to implement
2
C interface only by software.
an I
0: PA7 to PA4 are normal input/output pins.
1: PA7 to PA4 are input/output pins enabling bus
driving.
0
0
R/W
R/W
I2C Transfer Rate Select 1 and 0
These bits control the IIC operation. These bits select
a transfer rate in master mode together with bits
CKS2 to CKS0 in the I
For details on the transfer rate, refer to table 13.3.
Enables or disables CPU access for IIC registers
(ICCR, ICSR, ICDR/SARX, ICMR/SAR), and SCI
registers (SMR, BRR, SCMR).
0: SCI_1 registers are accessed in an area from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
1: IIC_1 registers are accessed in an area from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
IIC_0 registers are accessed in an area from
H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to
H'(FF)FFDF.
2
C bus mode register (ICMR).
Rev. 1.00, 05/04, page 55 of 544
Initial
Bit Bit Name
3 FLSHE 0 R/W Flash Memory Control Register Enable
2 — 0 R/(W) Reserved
1
0
ICKS1
ICKS0 0 0
Value R/W Description
Enables or disables CPU access for flash memory
registers (FLMCR1, FLMCR2, EBR1, EBR2), control
registers in power-down state (SBYCR, LPWRCR,
MSTPCRH, MSTPCRL), and control registers of onchip peripheral modules (PCSR, SYSCR2).
0: Registers in power-down state and control registers
of on-chip peripheral modules are accessed in an
area from H'(FF)FF80 to H'(FF)FF87.
1: Control registers of flash memory are accessed in
an area from H'(FF)FF80 to H'(FF)FF87.
The initial value should not be changed.
R/W
R/W
Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register (TCR).
For details, refer to section 10.3.4, Timer Control
Register (TCR).
3.3 Operating Mode Descriptions
3.3.1 Mode 2
The CPU can access a 16-Mbyte address space in advanced single-chip mode. The on-chip ROM
is enabled.
3.3.2 Mode 3
The CPU can access a 64-Kbyte address space in normal single-chip mode. The on-chip ROM is
enabled. The CPU can access a 56-kbyte address space in mode 3.
Rev. 1.00, 05/04, page 56 of 544
3.4 Address Map
Figures 3.1 and 3.2 show the address map in each operating mode.
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or
trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High
Low
Reset Starts immediately after a low-to-high transition of the RES
pin, or when the watchdog timer overflows.
Interrupt Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
Direct transition Starts when a direction transition occurs as the result of
SLEEP instruction execution.
Trap instruction Started by execution of a trap (TRAPA) instruction. Trap
instruction exception handling requests are accepted at all
times in program execution state.
Rev. 1.00, 05/04, page 59 of 544
4.2 Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses.
Table 4.2 Exception Handling Vector Table
Vector Address
Exception Source Vector Number Normal Mode Advanced Mode
Reset 0 H'0000 to H'0001 H'000000 to H'000003
Reserved for system use 1
5
Direct transition 6 H'000C to H'000D H'000018 to H'00001B
External interrupt (NMI) 7 H'000E to H'000F H'00001C to H'00001F
Trap instruction (four
sources)
Reserved for system use 12
External interrupt
Internal interrupt* 24
Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception
Handling Vector Table.
IRQ0 16 H'0020 to H'0021 H'000040 to H'000043
IRQ1 17 H'0022 to H'0023 H'000044 to H'000047
IRQ2 18 H'0024 to H'0025 H'000048 to H'00004B
IRQ3 19 H'0026 to H'0027 H'00004C to H'00004F
IRQ4 20 H'0028 to H'0029 H'000050 to H'000053
IRQ5 21 H'002A to H'002B H'000054 to H'000057
IRQ6 22 H'002C to H'002D H'000058 to H'00005B
IRQ7 23 H'002E to H'002F H'00005C to H'00005F
8 H'0010 to H'0011 H'000020 to H'000023
9 H'0012 to H'0013 H'000024 to H'000027
10 H'0014 to H'0015 H'000028 to H'00002B
11 H'0016 to H'0017 H'00002C to H'00002F
15
111
H'0002 to H'0003
|
H'000A to H'000B
H'0018 to H'0019
|
H'001E to H'001F
H'0030 to H'0031
H'00DE to H'00DF
H'000004 to H'000007
|
H'000014 to H'000017
H'000030 to H'000033
|
H'00003C to H'00003F
H'000060 to H'000063
H'0001BC to H'0001BF
Rev. 1.00, 05/04, page 60 of 544
4.3 Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip
can also be reset by overflow of the watchdog timer. For details, see section 11, Watchdog Timer
(WDT).
4.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized
and the I bit is set to 1 in CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figure 4.1 shows an example of the reset sequence.
Vector
fetch
φ
RES
Internal address bus
Internal read signal
Internal write signal
Internal data bus
(1) Reset exception handling vector address ((1) = H'0000)
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First program instruction
Internal
processing
(1)(3)
(2)(4)
Prefetch of first program
instruction
High
Figure 4.1 Reset Sequence (Mode 3)
Rev. 1.00, 05/04, page 61 of 544
4.3.2 Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled
After a reset is cancelled, the module stop control registers (MSTPCR) are initialized, and all
modules operate in module stop mode. Therefore, the registers of on-chip peripheral modules
cannot be read from or written to. To read from and write to these registers, clear module stop
mode.
Rev. 1.00, 05/04, page 62 of 544
4.4 Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The sources to start interrupt exception
handling are external interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to
WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt
with the highest priority. For details, refer to section 5, Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution begins from that address.
4.5 Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.3 shows the status of CCR after execution of trap instruction exception handling.
Table 4.3 Status of CCR after Trap Instruction Exception Handling
CCR
Interrupt Control Mode I UI
0 1 —
1 1 1
[Legend]
1: Set to 1
—: Retains value prior to execution
Rev. 1.00, 05/04, page 63 of 544
4.6 Stack Status after Exception Handling
Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Normal mode
SPSP
Note: Ignored on return.
CCR
CCR*
PC
(16 bits)
Figure 4.2 Stack Status after Exception Handling
Advanced mode
CCR
PC
(24 bits)
Rev. 1.00, 05/04, page 64 of 544
4.7 Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed in words or longwords, and the value of the stack pointer (SP:
ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W Rn (or MOV.W Rn, @-SP)
PUSH.L ERn (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn
Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what
happens when the SP value is odd.
(or MOV.L @SP+, ERn)
Address
CCR
SP
PC
SP
TRAPA instruction executed
SP set to H'FFFEFFData saved above SP
[Legend]
CCR:
Condition code register
PC:
Program counter
R1L:
General register R1L
SP:
Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0 in advanced mode.
SP
MOV.B R1L, @-ER7 executed
R1L
PC
Contents of CCR lost
Figure 4.3 Operation when SP Value is Odd
Rev. 1.00, 05/04, page 65 of 544
H'FFEFFA
H'FFEFFB
H'FFEFFC
H'FFEFFD
H'FFEFFF
Rev. 1.00, 05/04, page 66 of 544
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