Renesas H8S Series, H8S/2100 Series, H8S/2114R, R4F2114R Hardware Manual

REJ09B0098-0300

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16

H8S/2114R R4F2114R

H8S/2114RGroup

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family / H8S/2100 Series

Rev.3.00
Revision Date: Jul. 14, 2005

Rev. 3.00 Jul. 14, 2005 Page ii of xlviii

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 3.00 Jul. 14, 2005 Page iii of xlviii

General Precautions on Handling of Product

1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are hi g h-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfun ction may occur.

3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Rese rved Addresses
Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 3.00 Jul. 14, 2005 Page iv of xlviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)
Product code, Package dimensions, etc.

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 3.00 Jul. 14, 2005 Page v of xlviii

Preface

This H8S/2114R Group is a series of microcomputers (MCUs) made up of the H8S/2000 CPU
with Renesas Technology’s original architecture as its core, and the peripheral functions required
to configure a system.

The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward
compatibility at the object level with the H8/300 and H8/300 H CPUs. This allows the transition
from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU.

This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit
free running timer (FRT), a 16-bit timer pulse unit (TPU), 8-bit timers (TMR), watchdog timer
(WDT), serial communication interface (SCI), I
keyboard buffer control units (KBU), an A/D converter, and I/O ports as on-chip p er ipheral
modules required for system configuration.

A data transfer controller (DTC) and LPC interface (LPC) are included as bus masters.

2

C bus interface (IIC), a LPC interface (LPC), a

A flash memory (F-ZTAT

TM

*) is available for this LSI’s 1 Mbyte ROM. The CPU and ROM are
connected to a 16-bit bus, enabling byte data and word data to be accessed in a single state. This
improves the instruction fetch and process speeds.

Note: * F-ZTAT

TM

is a trademark of Renesas Technology. Corp.

Target Users: This manual was written for users who use the H8S/2114R in the design of

application systems. Target users are expected to understand the fundamentals of
electrical circuits, logic circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2114R Group to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read this manual in the order of the table of contents. This manual can be roughly categorized
into the descriptions on the CPU, system control functions, peripheral functions and electrical
characteristics.

Rev. 3.00 Jul. 14, 2005 Page vi of xlviii

• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

• In order to understand the detailed function of a register whose name is known
Read the index that is the final part of the manual to find the page number of the entry on the

register. The addresses, bits, and initial values of the registers are summarized in section 25,
List of Registers.

Rules: Register name: The following notation is used for cases when the same or a

similar function, e.g., serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel

number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B’xxxx, hexadecimal is H’xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/

H8S/2114R Group manuals:

Document Title Document No.

H8S/2114R Group Hardware Manual This manual

H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139

User's manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual

Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual

H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial REJ10B0024

H8S, H8/300 Series High-performance Embedded Workshop 3 User's
Manual

Rev. 3.00 Jul. 14, 2005 Page vii of xlviii

REJ10B0058

ADE-702-282

REJ10B0026

Rev. 3.00 Jul. 14, 2005 Page viii of xlviii

Main Revisions and Additions in this Edition

Item Page Revisions (See Manual for Details)

All pages  Suffix R is added to group name and product code.

• H8S/2114 Group→ H8S/2114R Group

• R4F2114 → R4F2114R

Appendix

C. Package Dimensions

Figure C.1 Package
Dimensions (TFP-144)

977 Replaced.

Rev. 3.00 Jul. 14, 2005 Page ix of xlviii

Rev. 3.00 Jul. 14, 2005 Page x of xlviii

Contents

Section 1 Overview................................................................................................1

1.1 Overview................................................................................................................................1

1.2 Internal Block Diagram..........................................................................................................3

1.3 Pin Description.......................................................................................................................4

1.3.1 Pin Arrangement....................................................................................................... 4

1.3.2 Pin Arrangement in Each Operating Mode...............................................................5

1.3.3 Pin Functions..........................................................................................................10

Section 2 CPU......................................................................................................19

2.1 Features................................................................................................................................ 19

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU..................................... 20

2.1.2 Differences from H8/300 CPU ...............................................................................21

2.1.3 Differences from H8/300H CPU.............................................................................21

2.2 CPU Operating Modes......................................................................................................... 22

2.2.1 Normal Mode.......................................................................................................... 22

2.2.2 Advanced Mode......................................................................................................24

2.3 Address Space...................................................................................................................... 26

2.4 Register Configuration......................................................................................................... 27

2.4.1 General Registers....................................................................................................28

2.4.2 Program Counter (PC)............................................................................................29

2.4.3 Extended Control Register (EXR)..........................................................................29

2.4.4 Condition-Code Register (CCR).............................................................................30

2.4.5 Initial Register Values.............................................................................................31

2.5 Data Formats........................................................................................................................32

2.5.1 General Register Data Formats...............................................................................32

2.5.2 Memory Data Formats............................................................................................ 34

2.6 Instruction Set......................................................................................................................35

2.6.1 Table of Instructions Classified by Function..........................................................36

2.6.2 Basic Instruction Formats.......................................................................................47

2.7 Addressing Modes and Effective Address Calculation........................................................48

2.7.1 Register Direct—Rn ............................................................................................... 48

2.7.2 Register Indirect—@ERn.......................................................................................48

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).................49

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.....49

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.......................................49

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32....................................................................50

Rev. 3.00 Jul. 14, 2005 Page xi of xlviii

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)......................................50

2.7.8 Memory Indirect—@@aa:8...................................................................................51

2.7.9 Effective Address Calculation................................................................................52

2.8 Processing States..................................................................................................................54

2.9 Usage Notes......................................................................................................................... 56

2.9.1 Note on TAS Instruction Usage.............................................................................. 56

2.9.2 Note on STM/LDM Instruction Usage...................................................................56

2.9.3 Note on Bit Manipulation Instructions ................................................................... 56

2.9.4 EEPMOV Instruction.............................................................................................. 57

Section 3 MCU Operating Modes.......................................................................59

3.1 Operating Mode Selection...................................................................................................59

3.2 Register Descriptions...........................................................................................................60

3.2.1 Mode Control Register (MDCR)............................................................................60

3.2.2 System Control Register (SYSCR)......................................................................... 61

3.2.3 Serial Timer Control Register (STCR)...................................................................63

3.2.4 System Control Register 3 (SYSCR3).................................................................... 66

3.3 Operating Mode Descriptions.............................................................................................. 67

3.3.1 Mode 2.................................................................................................................... 67

3.3.2 Mode 3.................................................................................................................... 67

3.4 Address Map........................................................................................................................ 67

Section 4 Exception Handling.............................................................................69

4.1 Exception Handling Types and Priority............................................................................... 69

4.2 Exception Sources and Exception Vector Table.................................................................. 70

4.3 Reset....................................................................................................................................74

4.3.1 Reset Exception Handling ...................................................................................... 74

4.3.2 Interrupts Immediately after Reset..........................................................................75

4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................... 75

4.4 Interrupt Exception Handling .............................................................................................. 76

4.5 Trap Instruction Exception Handling...................................................................................76

4.6 Stack Status after Exception Handling.................................................................................77

4.7 Usage Note...........................................................................................................................78

Section 5 Interrupt Controller..............................................................................79

5.1 Features................................................................................................................................ 79

5.2 Input/Output Pi ns................................................................................................................. 81

5.3 Register Descriptions...........................................................................................................82

5.3.1 Interrupt Control Registers A to D (ICRA to ICRD).............................................. 83

5.3.2 Address Break Control Register (ABRKCR) .........................................................85

Rev. 3.00 Jul. 14, 2005 Page xii of xlviii

5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 86

5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)...................87

5.3.5 IRQ Enable Registers (IER16, IER).......................................................................90

5.3.6 IRQ Status Registers (ISR16, ISR)......................................................................... 91

5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up

Event Interrupt Mask Registers (WUEMR, WUEMRB)........................................ 93

5.3.8 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register

(ISSR).....................................................................................................................97

5.4 Interrupt Source s.................................................................................................................. 99

5.4.1 External Interrupt Sources ......................................................................................99

5.4.2 Internal Interrupt Sources ..................................................................................... 102

5.5 Interrupt Exception Handling Vector Tables.....................................................................102

5.6 Interrupt Control Modes and Interrupt Operation.............................................................. 109

5.6.1 Interrupt Control Mode 0......................................................................................112

5.6.2 Interrupt Control Mode 1......................................................................................114

5.6.3 Interrupt Exception Handling Sequence...............................................................117

5.6.4 Interrupt Response Times.....................................................................................119

5.6.5 DTC Activation by Interrupt................................................................................. 120

5.7 Address Breaks................................................................................................................. .122

5.7.1 Features................................................................................................................. 122

5.7.2 Block Diagram......................................................................................................122

5.7.3 Operation ..............................................................................................................123

5.7.4 Usage Notes.......................................................................................................... 123

5.8 Usage Notes....................................................................................................................... 125

5.8.1 Conflict between Interrupt Generation and Disabling..........................................125

5.8.2 Instructions for Disabling Interrupts..................................................................... 126

5.8.3 Interrupts during Execution of EEPMOV Instruction...........................................126

5.8.4 Vector Address Switching ....................................................................................126

5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode....................127

5.8.6 Noise Canceller Switching.................................................................................... 127

5.8.7 IRQ Status Register (ISR).....................................................................................127

Section 6 Bus Controller (BSC).........................................................................129

6.1 Features.............................................................................................................................. 129

6.2 Register Descriptions......................................................................................................... 130

6.2.1 Bus Control Register (BCR)................................................................................. 130

6.2.2 Wait State Control Register (WSCR) ...................................................................131

6.3 Bus Arbitration...................................................................................................................132

6.3.1 Priority of Bus Masters......................................................................................... 132

6.3.2 Bus Transfer Timing.............................................................................................132

Rev. 3.00 Jul. 14, 2005 Page xiii of xlviii

Section 7 Data Transfer Controller (DTC)........................................................135

7.1 Features.............................................................................................................................. 136

7.2 Register Descriptions......................................................................................................... 137

7.2.1 DTC Mode Register A (MRA).............................................................................138

7.2.2 DTC Mode Register B (MRB)..............................................................................139

7.2.3 DTC Source Address Register (SAR)...................................................................139

7.2.4 DTC Destination Address Register (DAR)........................................................... 140

7.2.5 DTC Transfer Count Register A (CRA)...............................................................140

7.2.6 DTC Transfer Count Register B (CRB)................................................................ 140

7.2.7 DTC Enable Registers (DTCER).......................................................................... 141

7.2.8 DTC Vector Register (DTVECR)......................................................................... 142

7.3 Activation Sources............................................................................................................. 143

7.4 Location of Register Information and DTC Vector Table................................................. 144

7.5 Operation...........................................................................................................................147

7.5.1 Normal Mode........................................................................................................ 148

7.5.2 Repeat Mode......................................................................................................... 149

7.5.3 Block Transfer Mode............................................................................................ 150

7.5.4 Chain Transfer......................................................................................................151

7.5.5 Interrupt Sources................................................................................................... 152

7.5.6 Operation Timing..................................................................................................152

7.5.7 Number of DTC Execution States........................................................................154

7.6 Procedures for Using DTC.................................................................................................155

7.6.1 Activation by Interrupt.......................................................................................... 155

7.6.2 Activation by Software......................................................................................... 155

7.7 Examples of Use of the DTC ............................................................................................. 156

7.7.1 Normal Mode........................................................................................................ 156

7.7.2 Software Activation.............................................................................................. 157

7.8 Usage Notes....................................................................................................................... 158

7.8.1 Module Stop Mode Setting................................................................................... 158

7.8.2 On-Chip RAM......................................................................................................158

7.8.3 DTCE Bit Setting.................................................................................................. 158

7.8.4 Setting Required on Entering Subactive Mode or Watch Mode........................... 158

7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter......... 158

Section 8 I/O Ports.............................................................................................159

8.1 Port 1..................................................................................................................................164

8.1.1 Port 1 Data Direction Register (P1DDR)..............................................................164

8.1.2 Port 1 Data Register (P1DR) ................................................................................ 165

8.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)................................................... 165

8.1.4 Pin Functions........................................................................................................166

Rev. 3.00 Jul. 14, 2005 Page xiv of xlviii

8.1.5 Port 1 Input Pull-Up MOS.................................................................................... 166

8.2 Port 2..................................................................................................................................167

8.2.1 Port 2 Data Direction Register (P2DDR)..............................................................167

8.2.2 Port 2 Data Register (P2DR).................................................................................168

8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)................................................... 168

8.2.4 Pin Functions........................................................................................................169

8.2.5 Port 2 Input Pull-Up MOS.................................................................................... 170

8.3 Port 3..................................................................................................................................171

8.3.1 8.3.1 Port 3 Data Direction Register (P3DDR).....................................................171

8.3.2 Port 3 Data Register (P3DR).................................................................................172

8.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)................................................... 172

8.3.4 Pin Functions........................................................................................................173

8.3.5 Port 3 Input Pull-Up MOS.................................................................................... 173

8.4 Port 4..................................................................................................................................174

8.4.1 Port 4 Data Direction Register (P4DDR)..............................................................174

8.4.2 Port 4 Data Register (P4DR).................................................................................175

8.4.3 Pin Functions........................................................................................................175

8.5 Port 5..................................................................................................................................178

8.5.1 Port 5 Data Direction Register (P5DDR)..............................................................178

8.5.2 Port 5 Data Register (P5DR).................................................................................178

8.5.3 Pin Functions........................................................................................................179

8.6 Port 6..................................................................................................................................180

8.6.1 Port 6 Data Direction Register (P6DDR)..............................................................180

8.6.2 Port 6 Data Register (P6DR).................................................................................181

8.6.3 Pull-Up MOS Control Register (KMPCR)...........................................................181

8.6.4 Noise Canceller Enable Register (P6NCE)........................................................... 182

8.6.5 Noise Canceller Mode Control Register (P6NCMC)............................................182

8.6.6 Noise Cancel Cycle Setting Register (P6NCCS).................................................. 183

8.6.7 System Control Register 2 (SYSCR2).................................................................. 185

8.6.8 Pin Functions........................................................................................................185

8.6.9 Port 6 Input Pull-Up MOS.................................................................................... 188

8.7 Port 7..................................................................................................................................189

8.7.1 Port 7 Input Data Register (P7PIN) ......................................................................189

8.7.2 Pin Functions........................................................................................................190

8.8 Port 8..................................................................................................................................191

8.8.1 Port 8 Data Direction Register (P8DDR)..............................................................191

8.8.2 Port 8 Data Register (P8DR).................................................................................192

8.8.3 Pin Functions........................................................................................................193

8.9 Port 9..................................................................................................................................196

8.9.1 Port 9 Data Direction Register (P9DDR)..............................................................196

Rev. 3.00 Jul. 14, 2005 Page xv of xlviii

8.9.2 Port 9 Data Register (P9DR) ................................................................................ 197

8.9.3 Port 9 Pull-Up MOS Control Register (P9PCR)................................................... 197

8.9.4 Pin Functions........................................................................................................198

8.9.5 Port 9 Input Pull-Up MOS.................................................................................... 200

8.10 Port A................................................................................................................................. 201

8.10.1 Port A Data Direction Register (PADDR)............................................................ 201

8.10.2 Port A Output Data Register (PAODR)................................................................ 202

8.10.3 Port A Input Data Register (PAPIN) .................................................................... 202

8.10.4 Pin Functions ........................................................................................................ 203

8.11 Port B................................................................................................................................. 204

8.11.1 Port B Data Direction Register (PBDDR) ............................................................ 204

8.11.2 Port B Output Data Register (PBODR) ................................................................ 205

8.11.3 Port B Input Data Register (PBPIN)..................................................................... 205

8.11.4 Pin Functions ........................................................................................................ 206

8.11.5 Port B Input Pull-Up MOS ................................................................................... 208

8.12 Port C................................................................................................................................. 209

8.12.1 Port C Data Direction Register (PCDDR) ............................................................ 209

8.12.2 Port C Output Data Register (PCODR) ................................................................ 210

8.12.3 Port C Input Data Register (PCPIN)..................................................................... 210

8.12.4 Noise Canceller Enable Register (PCNCE).......................................................... 211

8.12.5 Noise Canceller Mode Control Register (PCNCMC)........................................... 211

8.12.6 Noise Cancel Cycle Setting Register (PCNCCS) ................................................. 212

8.12.7 Pin Functions ........................................................................................................ 212

8.12.8 Port C Nch-OD control register (PCNOCR)......................................................... 215

8.12.9 Pin Functions ........................................................................................................ 215

8.12.10 Port C Input Pull-Up MOS...................................................................................216

8.13 Port D................................................................................................................................. 217

8.13.1 Port D Data Direction Register (PDDDR)............................................................ 217

8.13.2 Port D Output Data Register (PDODR)................................................................ 218

8.13.3 Port D Input Data Register (PDPIN) .................................................................... 218

8.13.4 Pin Functions ........................................................................................................ 219

8.13.5 Port D Nch-OD control register (PDNOCR)........................................................ 223

8.13.6 Pin Functions ........................................................................................................ 223

8.13.7 Port D Input Pull-Up MOS...................................................................................224

8.14 Port E.................................................................................................................................225

8.14.1 Port E Input Pull-Up MOS Control Register (PEPCR) ........................................ 225

8.14.2 Port E Input Data Register (PEPIN) ..................................................................... 225

8.14.3 Pin Functions ........................................................................................................ 226

8.14.4 Port E Input Pull-Up MOS.................................................................................... 226

8.15 Port F ................................................................................................................................. 227

Rev. 3.00 Jul. 14, 2005 Page xvi of xlviii

8.15.1 Port F Data Direction Register (PFDDR) ............................................................. 227

8.15.2 Port F Output Data Register (PFODR) ................................................................. 228

8.15.3 Port F Input Data Register (PFPIN)...................................................................... 228

8.15.4 Pin Functions ........................................................................................................ 229

8.15.5 Port F Nch-OD control register (PFNOCR)..........................................................231

8.15.6 Pin Functions ........................................................................................................ 231

8.15.7 Port F Input Pull-Up MOS.................................................................................... 232

8.16 Port G.................................................................................................................................233

8.16.1 Port G Data Direction Register (PGDDR)............................................................ 233

8.16.2 Port G Output Data Register (PGODR)................................................................ 234

8.16.3 Port G Input Data Register (PGPIN)..................................................................... 234

8.16.4 Noise Canceller Enable Register (PGNCE).......................................................... 235

8.16.5 Noise Canceller Mode Control Register (PGNCMC)...........................................235

8.16.6 Noise Cancel Cycle Setting Register (PGNCCS) .................................................236

8.16.7 Pin Functions ........................................................................................................ 237

8.16.8 Port G Nch-OD control register (PGNOCR)........................................................242

8.16.9 Pin Functions ........................................................................................................ 242

8.17 Change of Peripheral Function Pins...................................................................................243

8.17.1 Port Control Register 0 (PTCNT0).......................................................................243

8.17.2 Port Control Register 1 (PTCNT1).......................................................................244

8.17.3 Port Control Register 2 (PTCNT2).......................................................................245

Section 9 8-Bit PWM Timer (PWM).................................................................247

9.1 Features.............................................................................................................................. 247

9.2 Input/Output Pi ns...............................................................................................................249

9.3 Register Descriptions......................................................................................................... 249

9.3.1 PWM Register Select (PWSL)..............................................................................250

9.3.2 PWM Data Registers 15 to 8 (PWDR15 to PWDR8)...........................................251

9.3.3 PWM Data Polarity Register B (PWDPRB)......................................................... 252

9.3.4 PWM Output Enable Register B (PWOERB).......................................................252

9.3.5 Peripheral Clock Select Register (PCSR).............................................................253

9.4 Operation...........................................................................................................................254

9.4.1 PWM Setting Example ......................................................................................... 256

9.4.2 Diagram of PWM Used as D/A Converter ........................................................... 256

9.5 Usage Notes....................................................................................................................... 257

9.5.1 Module Stop Mode Setting................................................................................... 257

Rev. 3.00 Jul. 14, 2005 Page xvii of xlviii

Section 10 14-Bit PWM Timer (PWMX) .........................................................259

10.1 Features.............................................................................................................................. 259

10.2 Input/Output Pins...............................................................................................................260

10.3 Register Descriptions......................................................................................................... 260

10.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 261

10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) ......................... 262

10.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 264

10.3.4 Peripheral Clock Select Register (PCSR).............................................................265

10.4 Bus Master Interface.......................................................................................................... 266

10.5 Operation ........................................................................................................................... 269

10.6 Usage Notes....................................................................................................................... 276

10.6.1 Module Stop Mode Setting...................................................................................276

Section 11 16-Bit Free-Running Timer (FRT)..................................................277

11.1 Features.............................................................................................................................. 277

11.2 Input/Output Pins...............................................................................................................279

11.3 Register Descriptions......................................................................................................... 279

11.3.1 Free-Running Counter (FRC) ............................................................................... 280

11.3.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 280

11.3.3 Input Capture Registers A to D (ICRA to ICRD)................................................. 280

11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) .......................... 281

11.3.5 Output Compare Register DM (OCRDM)............................................................ 281

11.3.6 Timer Interrupt Enable Register (TIER)............................................................... 282

11.3.7 Timer Control/Status Register (TCSR)................................................................. 283

11.3.8 Timer Control Register (TCR).............................................................................. 286

11.3.9 Timer Output Compare Control Register (TOCR) ............................................... 287

11.4 Operation ........................................................................................................................... 289

11.4.1 Pulse Output ......................................................................................................... 289

11.5 Operation Timing............................................................................................................... 290

11.5.1 FRC Increment Timing......................................................................................... 290

11.5.2 Output Compare Output Timing........................................................................... 291

11.5.3 FRC Clear Timing ................................................................................................ 291

11.5.4 Input Capture Input Timing .................................................................................. 292

11.5.5 Buffered Input Capture Input Timing................................................................... 293

11.5.6 Timing of Input Capture Flag (ICF) Setting ......................................................... 294

11.5.7 Timing of Output Compare Flag (OCF) setting.................................................... 295

11.5.8 Timing of FRC Overflow Flag Setting ................................................................. 295

11.5.9 Automatic Addition Timing.................................................................................. 296

11.5.10 Mask Signal Generation Timing........................................................................... 297

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11.6 Interrupt Sources................................................................................................................298

11.7 Usage Notes.......................................................................................................................299

11.7.1 Conflict between FRC Write and Clear ................................................................299

11.7.2 Conflict between FRC Write and Increment......................................................... 300

11.7.3 Conflict between OCR Write and Compare-Match..............................................301

11.7.4 Switching of Internal Clock and FRC Operation.................................................. 302

11.7.5 Module Stop Mode Setting...................................................................................304

Section 12 16-Bit Timer Pulse Unit (TPU) .......................................................305

12.1 Features..............................................................................................................................305

12.2 Input/Output Pins...............................................................................................................309

12.3 Register Descriptions......................................................................................................... 310

12.3.1 Timer Control Register (TCR).............................................................................. 311

12.3.2 Timer Mode Register (TMDR)............................................................................. 315

12.3.3 Timer I/O Control Register (TIOR)...................................................................... 317

12.3.4 Timer Interrupt Enable Register (TIER)............................................................... 326

12.3.5 Timer Status Register (TSR).................................................................................328

12.3.6 Timer Counter (TCNT).........................................................................................331

12.3.7 Timer General Register (TGR) .............................................................................331

12.3.8 Timer Start Register (TSTR) ................................................................................ 331

12.3.9 Timer Synchro Register (TSYR) .......................................................................... 332

12.4 Interface to Bus Master...................................................................................................... 333

12.4.1 16-Bit Registers .................................................................................................... 333

12.4.2 8-Bit Registers ...................................................................................................... 333

12.5 Operation ........................................................................................................................... 335

12.5.1 Basic Functions..................................................................................................... 335

12.5.2 Synchronous Operation.........................................................................................341

12.5.3 Buffer Operation...................................................................................................343

12.5.4 PWM Modes.........................................................................................................347

12.5.5 Phase Counting Mode........................................................................................... 352

12.6 Interrupts............................................................................................................................357

12.6.1 Interrupt Source and Priority ................................................................................ 357

12.6.2 DTC Activation..................................................................................................... 359

12.6.3 A/D Converter Activation..................................................................................... 359

12.7 Operation Timing............................................................................................................... 360

12.7.1 Input/Output Timing.............................................................................................360

12.7.2 Interrupt Signal Timing......................................................................................... 364

12.8 Usage Notes.......................................................................................................................368

12.8.1 Input Clock Restrictions .......................................................................................368

12.8.2 Caution on Period Setting .....................................................................................368

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12.8.3 Conflict between TCNT Write and Clear Operations........................................... 369

12.8.4 Conflict between TCNT Write and Increment Operations ................................... 369

12.8.5 Conflict between TGR Write and Compare Match............................................... 370

12.8.6 Conflict between Buffer Register Write and Compare Match.............................. 371

12.8.7 Conflict between TGR Read and Input Capture...................................................372

12.8.8 Conflict between TGR Write and Input Capture .................................................. 373

12.8.9 Conflict between Buffer Register Write and Input Capture.................................. 374

12.8.10 Conflict between Overflow/Underflow and Counter Clearing.............................375

12.8.11 Conflict between TCNT Write and Overflow/Underflow .................................... 376

12.8.12 Multiplexing of I/O Pins....................................................................................... 376

12.8.13 Module Stop Mode Setting................................................................................... 376

Section 13 8-Bit Timer (TMR)..........................................................................377

13.1 Features.............................................................................................................................. 377

13.2 Input/Output Pins...............................................................................................................381

13.3 Register Descriptions......................................................................................................... 382

13.3.1 Timer Counter (TCNT)......................................................................................... 383

13.3.2 Time Constant Register A (TCORA) ................................................................... 383

13.3.3 Time Constant Register B (TCORB).................................................................... 384

13.3.4 Timer Control Register (TCR).............................................................................. 384

13.3.5 Timer Control/Status Register (TCSR)................................................................. 389

13.3.6 Time Constant Register C (TCORC).................................................................... 394

13.3.7 Input Capture Registers R and F (TICRR and TICRF)......................................... 394

13.3.8 Timer Input Select Register (TISR)...................................................................... 395

13.3.9 Timer Connection Register I (TCONRI)..............................................................395

13.3.10 Timer Connection Register S (TCONRS) ............................................................ 396

13.3.11 Timer XY Control Register (TCRXY).................................................................396

13.4 Operation ........................................................................................................................... 397

13.4.1 Pulse Output ......................................................................................................... 397

13.5 Operation Timing............................................................................................................... 398

13.5.1 TCNT Count Timing ............................................................................................ 398

13.5.2 Timing of CMFA and CMFB Setting at Compare-Match.................................... 399

13.5.3 Timing of Timer Output at Compare-Match......................................................... 399

13.5.4 Timing of Counter Clear at Compare-Match........................................................ 400

13.5.5 TCNT External Reset Timing............................................................................... 400

13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 401

13.6 TMR_0 and TMR_1 Cascaded Connection....................................................................... 402

13.6.1 16-Bit Count Mode...............................................................................................402

13.6.2 Compare-Match Count Mode ............................................................................... 402

13.7 TMR_Y and TMR_X Cascaded Connection..................................................................... 403

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13.7.1 16-Bit Count Mode ...............................................................................................403

13.7.2 Compare-Match Count Mode ............................................................................... 403

13.7.3 Input Capture Operation .......................................................................................404

13.8 Interrupt Sources................................................................................................................406

13.9 Usage Notes.......................................................................................................................407

13.9.1 Conflict between TCNT Write and Counter Clear................................................ 407

13.9.2 Conflict between TCNT Write and Count-Up......................................................408

13.9.3 Conflict between TCOR Write and Compare-Match............................................ 409

13.9.4 Conflict between Compare-Matches A and B ......................................................410

13.9.5 Switching of Internal Clocks and TCNT Operation.............................................. 410

13.9.6 Mode Setting with Cascaded Connection .............................................................412

13.9.7 Module Stop Mode Setting...................................................................................412

Section 14 Watchdog Timer (WDT)..................................................................413

14.1 Features..............................................................................................................................413

14.2 Input/Output Pins...............................................................................................................415

14.3 Register Descriptions......................................................................................................... 415

14.3.1 Timer Counter (TCNT).........................................................................................415

14.3.2 Timer Control/Status Register (TCSR)................................................................. 416

14.4 Operation ........................................................................................................................... 420

14.4.1 Watchdog Timer Mode.........................................................................................420

14.4.2 Interval Timer Mode............................................................................................. 421

14.4.3 RESO Signal Output Timing ................................................................................ 422

14.5 Interrupt Sources................................................................................................................423

14.6 Usage Notes.......................................................................................................................424

14.6.1 Notes on Register Access...................................................................................... 424

14.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 425

14.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 426

14.6.4 Changing Value of PSS Bit................................................................................... 426

14.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode.................426

14.6.6 System Reset by RESO Signal ............................................................................. 426

Section 15 Serial Communication Interface (SCI, IrDA)..................................427

15.1 Features..............................................................................................................................427

15.2 Input/Output Pins...............................................................................................................430

15.3 Register Descriptions......................................................................................................... 431

15.3.1 Receive Shift Register (RSR) ............................................................................... 431

15.3.2 Receive Data Register (RDR)............................................................................... 431

15.3.3 Transmit Data Register (TDR).............................................................................. 432

15.3.4 Transmit Shift Register (TSR)..............................................................................432

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15.3.5 Serial Mode Register (SMR) ................................................................................ 432

15.3.6 Serial Control Register (SCR) .............................................................................. 436

15.3.7 Serial Status Register (SSR) ................................................................................. 439

15.3.8 Smart Card Mode Register (SCMR)..................................................................... 444

15.3.9 Bit Rate Register (BRR) ....................................................................................... 445

15.3.10 Keyboard Comparator Control Register (KBCOMP)........................................... 453

15.4 Operation in Asynchronous Mode..................................................................................... 455

15.4.1 Data Transfer Format............................................................................................ 455

15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous

Mode..................................................................................................................... 457

15.4.3 Clock..................................................................................................................... 458

15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 459

15.4.5 Serial Data Transmission (Asynchronous Mode).................................................460

15.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 462

15.5 Multiprocessor Communication Function..........................................................................466

15.5.1 Multiprocessor Serial Data Transmission.............................................................468

15.5.2 Multiprocessor Serial Data Reception .................................................................. 469

15.6 Operation in Clocked Synchronous Mode......................................................................... 472

15.6.1 Clock..................................................................................................................... 472

15.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 473

15.6.3 Serial Data Transmission (Clocked Synchronous Mode).....................................474

15.6.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 477

15.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode)..............................................................................479

15.7 Smart Card Interface Description ...................................................................................... 481

15.7.1 Sample Connection............................................................................................... 481

15.7.2 Data Format (Except in Block Transfer Mode) .................................................... 481

15.7.3 Block Transfer Mode............................................................................................ 483

15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 483

15.7.5 Initialization..........................................................................................................484

15.7.6 Serial Data Transmission (Except in Block Transfer Mode)................................ 485

15.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 488

15.7.8 Clock Output Control............................................................................................ 490

15.8 IrDA Operation..................................................................................................................492

15.9 Interrupt Sources................................................................................................................ 496

15.9.1 Interrupts in Normal Serial Communication Interface Mode ............................... 496

15.9.2 Interrupts in Smart Card Interface Mode..............................................................497

15.10 Usage Notes ....................................................................................................................... 498

15.10.1 Module Stop Mode Setting................................................................................... 498

15.10.2 Break Detection and Processing...........................................................................498

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15.10.3 Mark State and Break Sending..............................................................................498

15.10.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) .....................................................................498

15.10.5 Relation between Writing to TDR and TDRE Flag.............................................. 498

15.10.6 Restrictions on Using DTC................................................................................... 499

15.10.7 SCI Operations during Mode Transitions............................................................. 499

15.10.8 Notes on Switching from SCK Pins to Port Pins.................................................. 503

Section 16 I2C Bus Interface (IIC).....................................................................505

16.1 Features..............................................................................................................................505

16.2 Input/Output Pins...............................................................................................................509

16.3 Register Descriptions......................................................................................................... 510

16.3.1 I2C Bus Data Register (ICDR)..............................................................................510

16.3.2 Slave Address Register (SAR).............................................................................. 511

16.3.3 Second Slave Address Register (SARX) .............................................................. 512

16.3.4 I2C Bus Mode Register (ICMR)............................................................................ 514

16.3.5 I2C Bus Control Register (ICCR).......................................................................... 517

16.3.6 I2C Bus Status Register (ICSR)............................................................................. 526

16.3.7 DDC Switch Register (DDCSWR).......................................................................530

16.3.8 I2C Bus Extended Control Register (ICXR)..........................................................531

16.4 Operation ........................................................................................................................... 535

16.4.1 I2C Bus Data Format............................................................................................. 535

16.4.2 Initialization..........................................................................................................537

16.4.3 Master Transmit Operation...................................................................................537

16.4.4 Master Receive Operation..................................................................................... 541

16.4.5 Slave Receive Operation....................................................................................... 551

16.4.6 Slave Transmit Operation ..................................................................................... 559

16.4.7 IRIC Setting Timing and SCL Control .................................................................562

16.4.8 Operation by Using DTC......................................................................................565

16.4.9 Noise Canceller..................................................................................................... 567

16.4.10 Initialization of Internal State ...............................................................................568

16.5 Interrupt Sources................................................................................................................569

16.6 Usage Notes.......................................................................................................................570

16.6.1 Module Stop Mode Setting...................................................................................580

Section 17 Keyboard Buffer Control Unit (KBU).............................................581

17.1 Features..............................................................................................................................581

17.2 Input/Output Pins...............................................................................................................584

17.3 Register Descriptions......................................................................................................... 585

17.3.1 Keyboard Control Register 1 (KBCR1)................................................................ 585

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17.3.2 Keyboard Buffer Control Register 2 (KBCR2) .................................................... 587

17.3.3 Keyboard Control Register H (KBCRH)..............................................................588

17.3.4 Keyboard Control Register L (KBCRL)............................................................... 590

17.3.5 Keyboard Data Buffer Register (KBBR)..............................................................592

17.3.6 Keyboard Buffer Transmit Data Register (KBTR)............................................... 592

17.4 Operation ........................................................................................................................... 593

17.4.1 Receive Operation ................................................................................................ 593

17.4.2 Transmit Operation...............................................................................................595

17.4.3 Receive Abort ....................................................................................................... 597

17.4.4 KCLKI and KDI Read Timing ............................................................................. 600

17.4.5 KCLKO and KDO Write Timing ......................................................................... 601

17.4.6 KBF Setting Timing and KCLK Control.............................................................. 602

17.4.7 Receive Timing..................................................................................................... 603

17.4.8 Operation during Data Reception ......................................................................... 604

17.4.9 KCLK Fall Interrupt Operation ............................................................................ 605

17.4.10 First KCLK Falling Interrupt................................................................................ 606

17.5 Usage Notes....................................................................................................................... 611

17.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................. 611

17.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission.................... 612

17.5.3 Module Stop Mode Setting...................................................................................612

17.5.4 Medium Speed Mode............................................................................................ 612

17.5.5 Transmit Completion Flag (KBTE)......................................................................612

Section 18 LPC Interface (LPC)........................................................................613

18.1 Features.............................................................................................................................. 613

18.2 Input/Output Pins...............................................................................................................616

18.3 Register Descriptions......................................................................................................... 617

18.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 619

18.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 625

18.3.3 Host Interface Control Register 4 (HICR4).......................................................... 628

18.3.4 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 629

18.3.5 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 631

18.3.6 Input Data Registers 1 to 4 (IDR1 to IDR4) ......................................................... 632

18.3.7 Output Data Registers 1 to 4 (ODR1 to ODR4) ................................................... 633

18.3.8 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 633

18.3.9 Status Registers 1 to 4 (STR1 to STR4) ............................................................... 634

18.3.10 SERIRQ Control Register 0 (SIRQCR0).............................................................. 640

18.3.11 SERIRQ Control Register 1 (SIRQCR1).............................................................. 644

18.3.12 SERIRQ Control Register 2 (SIRQCR2).............................................................. 649

18.3.13 Host Interface Select Register (HISEL)................................................................ 653

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18.3.14 RAM Buffer Address Register (RBUFAR).......................................................... 654

18.3.15 Flash Memory Programming Address Registers H and L

(FLWARH and FLARL).......................................................................................655

18.3.16 Manufacture ID Code Register (LMCMIDCR) and Device ID Code Register

(LMCDIDCR)....................................................................................................... 656

18.3.17 Erase Block Register (EBLKR)............................................................................ 657

18.3.18 LMC Status Registers 1 and 2 (LMCST1 and LMCST2)..................................... 658

18.3.19 LMC Control Registers 1 and 2 (LMCCR1 and LMCCR2)................................. 662

18.3.20 Host Base Address Registers 1H and 1L (HBAR1H and HBAR1L)....................665

18.3.21 Host Base Address Registers 2H and 2L (HBAR2H and HBAR2L)....................666

18.3.22 On-Chip RAM Host Base Address Registers H and L

(RAMBARH and RAMBARL)............................................................................667

18.3.23 Address Space Set Register (ASSR)..................................................................... 668

18.3.24 On-Chip RAM Address Space Set Register (RAMASSR)................................... 669

18.3.25 Slave Address Register 1 (SAR1).........................................................................670

18.3.26 Slave Address Register 2 (SAR2).........................................................................671

18.3.27 On-Chip RAM Slave Address Register (RAMAR).............................................. 671

18.3.28 Flash Memory Write Protect Registers H, M, and L

(FWPRH, FWPRM, and FWPRL)........................................................................672

18.3.29 Flash Memory Read Protect Registers H, M, and L

(FRPRH, FRPRM, and FRPRL)...........................................................................674

18.3.30 On-Chip RAM Protect Control Register (MPCR)................................................ 676

18.3.31 User Command Register (UCMDTR)..................................................................676

18.4 Operation ........................................................................................................................... 677

18.4.1 LPC interface Activation ...................................................................................... 677

18.4.2 LPC I/O Cycles..................................................................................................... 677

18.4.3 Gate A20...............................................................................................................680

18.4.4 LPC Interface Shutdown Function (LPCPD)........................................................683

18.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) ..................................... 687

18.4.6 LPC Interface Clock Start Request.......................................................................689

18.4.7 LPC/FW Memory Cycle.......................................................................................689

18.4.8 LPC/FW Memory Access Command ................................................................... 692

18.4.9 Flash Memory Address Translation (Host → Slave)............................................ 700

18.4.10 On-Chip RAM Address Translation (Host → Slave)...........................................701

18.4.11 Address Space Priority..........................................................................................702

18.4.12 Example 1 of Address Space Priority...................................................................703

18.4.13 Example 2 of Address Space Priority...................................................................704

18.4.14 Flash Memory Protection......................................................................................705

18.4.15 On-Chip RAM Protection.....................................................................................707

18.4.16 Flash Memory Programming................................................................................ 707

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18.4.17 Flash Memory Erasing.......................................................................................... 709

18.5 Interrupt Sources................................................................................................................ 710

18.5.1 IBFI1, IBFI2, IBFI3, IBFI4, LMC, LMCUI, and ERRI.......................................710

18.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 ........................ 711

18.6 Usage Note......................................................................................................................... 714

18.6.1 Data Conflict......................................................................................................... 714

18.6.2 Module Stop Mode Setting...................................................................................715

18.6.3 Operating Mode in LPC/FW Memory Write Cycle.............................................. 715

Section 19 A/D Converter.................................................................................717

19.1 Features.............................................................................................................................. 717

19.2 Input/Output Pins...............................................................................................................719

19.3 Register Descriptions......................................................................................................... 720

19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 720

19.3.2 A/D Control/Status Register (ADCSR) ................................................................ 721

19.3.3 A/D Control Register (ADCR) ............................................................................. 722

19.4 Operation ........................................................................................................................... 723

19.4.1 Single Mode.......................................................................................................... 723

19.4.2 Scan Mode ............................................................................................................ 723

19.4.3 Input Sampling and A/D Conversion Time .......................................................... 724

19.4.4 External Trigger Input Timing.............................................................................. 726

19.5 Interrupt Source................................................................................................................. 727

19.6 A/D Conversion Accuracy Definitions.............................................................................. 727

19.7 Usage Notes....................................................................................................................... 729

19.7.1 Permissible Signal Source Impedance..................................................................729

19.7.2 Influences on Absolute Accuracy.........................................................................729

19.7.3 Setting Range of Analog Power Supply and Other Pins....................................... 730

19.7.4 Notes on Board Design.........................................................................................730

19.7.5 Notes on Noise Countermeasures.........................................................................730

19.7.6 Module Stop Mode Setting...................................................................................731

Section 20 RAM................................................................................................733

Section 21 Flash Memory (0.18-µm F-ZTAT Version)....................................735

21.1 Features.............................................................................................................................. 735

21.1.1 Mode Transitions..................................................................................................737

21.1.2 Mode Comparison ................................................................................................ 738

21.1.3 Flash Memory MAT Configuration...................................................................... 739

21.1.4 Block Division......................................................................................................739

21.1.5 Programming/Erasing Interface............................................................................ 742

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21.2 Input/Output Pins...............................................................................................................744

21.3 Register Descriptions......................................................................................................... 744

21.3.1 Programming/Erasing Interface Registers ............................................................ 746

21.3.2 Programming/Erasing Interface Parameters ......................................................... 753

21.4 On-Board Programming.....................................................................................................764

21.4.1 Boot Mode ............................................................................................................ 764

21.4.2 User Program Mode.............................................................................................. 768

21.4.3 User Boot Mode.................................................................................................... 779

21.4.4 Storable Areas for Procedure Program and Program Data ................................... 783

21.5 Protection........................................................................................................................... 791

21.5.1 Hardware Protection ............................................................................................. 791

21.5.2 Software Protection............................................................................................... 793

21.5.3 Error Protection..................................................................................................... 793

21.6 Switching between User MAT and User Boot MAT.........................................................795

21.7 Programmer Mode.............................................................................................................796

21.8 Serial Communication Interface Specifications for Boot Mode........................................797

21.9 Usage Notes.......................................................................................................................824

Section 22 Boundary Scan (JTAG) ...................................................................827

22.1 Features..............................................................................................................................827

22.2 Input/Output Pins...............................................................................................................829

22.3 Register Descriptions......................................................................................................... 830

22.3.1 Instruction Register (SDIR)..................................................................................830

22.3.2 Bypass Register (SDBPR) .................................................................................... 832

22.3.3 Boundary Scan Register (SDBSR) ....................................................................... 832

22.3.4 ID Code Register (SDIDR)................................................................................... 842

22.4 Operation ........................................................................................................................... 842

22.4.1 TAP Controller State Transitions..........................................................................842

22.4.2 JTAG Reset........................................................................................................... 843

22.5 Boundary Scan...................................................................................................................844

22.5.1 Supported Instructions ..........................................................................................844

22.5.2 Notes.....................................................................................................................846

22.6 Usage Notes.......................................................................................................................846

Section 23 Clock Pulse Generator .....................................................................849

23.1 Oscillator............................................................................................................................ 850

23.1.1 Connecting Crystal Resonator ..............................................................................850

23.1.2 External Clock Input Method................................................................................ 851

23.2 Duty Correction Circuit .....................................................................................................854

23.3 Medium-Speed Clock Divider...........................................................................................854

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23.4 Bus Master Clock Select Circuit........................................................................................ 854

23.5 Subclock Input Circuit....................................................................................................... 855

23.6 Subclock Waveform Forming Circuit................................................................................ 856

23.7 Clock Select Circuit........................................................................................................... 856

23.8 Handling of X1 and X2 Pins.............................................................................................. 857

23.9 Usage Notes....................................................................................................................... 857

23.9.1 Notes on Resonator............................................................................................... 857

23.9.2 Notes on Board Design.........................................................................................857

Section 24 Power-Down Modes........................................................................859

24.1 Register Descriptions......................................................................................................... 860

24.1.1 Standby Control Register (SBYCR).....................................................................860

24.1.2 Low-Power Control Register (LPWRCR)............................................................ 862

24.1.3 Module Stop Control Registers H, L, and A

(MSTPCRH, MSTPCRL, MSTPCRA) ................................................................ 864

24.2 Mode Transitions and LSI States....................................................................................... 866

24.3 Medium-Speed Mode ........................................................................................................ 870

24.4 Sleep Mode........................................................................................................................871

24.5 Software Standby Mode..................................................................................................... 872

24.6 Hardware Standby Mode...................................................................................................874

24.7 Watch Mode....................................................................................................................... 875

24.8 Subsleep Mode...................................................................................................................876

24.9 Subactive Mode ................................................................................................................. 877

24.10 Module Stop Mode ............................................................................................................ 878

24.11 Direct Transitions ..............................................................................................................878

24.12 Usage Notes ....................................................................................................................... 879

24.12.1 I/O Port Status.......................................................................................................879

24.12.2 Current Consumption when Waiting for Oscillation Stabilization....................... 879

24.12.3 DTC Module Stop Mode......................................................................................879

Section 25 List of Registers...............................................................................881

25.1 Register Addresses (Address Order).................................................................................. 883

25.2 Register Bits....................................................................................................................... 897

25.3 Register States in Each Operating Mode ........................................................................... 909

25.4 Register Selection Condition ............................................................................................. 920

25.5 Register Addresses (Classification by Type of Module) ................................................... 933

Section 26 Electrical Characteristics.................................................................947

26.1 Absolute Maximum Ratings..............................................................................................947

26.2 DC Characteristics.............................................................................................................948

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26.3 AC Characteristics.............................................................................................................955

26.3.1 Clock Timing........................................................................................................956

26.3.2 Control Signal Timing .......................................................................................... 958

26.3.3 Timing of On-Chip Peripheral Modules ...............................................................959

26.3.4 A/D Conversion Characteristics ...........................................................................971

26.4 Flash Memory Characteristics ........................................................................................... 972

26.5 Usage Notes.......................................................................................................................973

Appendix .........................................................................................................975

A. I/O Port States in Each Pin State........................................................................................ 975

B. Product Lineup................................................................................................................... 976

C. Package Dimensions ..........................................................................................................977

Index .........................................................................................................979

Rev. 3.00 Jul. 14, 2005 Page xxix of xlviii

Rev. 3.00 Jul. 14, 2005 Page xxx of xlviii