Renesas H8SX, H8S User Manual
Direct Drive LCD Design Guide Version 2.6
H8S/H8SX Series
User’s Manual
Direct Drive Solution
Rev. 2.60
September, 2009
Renesas Technology America
america.renesas.com
Direct Drive LCD Design Guide
Index
1. INTRODUCTION................................................................................................................................................3
1.1 DIRECT DRIVE LCD OVERVIEW...................................................................................................................... 3
1.1.1 Philosophy...................................................................................................................................3
1.1.2 Capabilities..................................................................................................................................3
2. DRIVER CONFIGURATION.............................................................................................................................4
2.1 LCD DIRECT DRIVE CONFIGURATION MACROS.............................................................................................. 4
2.2 FRAME BUFFER CONFIGURATION....................................................................................................................6
2.2.1 FRAME_HEIGHT .......................................................................................................................6
2.2.2 FRAME_WIDTH .........................................................................................................................6
2.2.3 V_LINES_INVERT.......................................................................................................................6
2.2.4 H_DOT_INVERT.........................................................................................................................6
2.2.5 PANEL_ROTATE.........................................................................................................................6
2.2.6 LCD_FRAMES............................................................................................................................6
2.2.7 MAX_FRAME_REGIONS...........................................................................................................6
2.3 DRIVER MODE SELECTION.............................................................................................................................. 8
2.3.1 SRAM_DD...................................................................................................................................8
2.3.2 SRAM_NOMUX_DD...................................................................................................................8
2.3.3 SDRAM_DD................................................................................................................................8
2.3.4 SDRAM_CLUSTER_DD .............................................................................................................8
2.3.5 Dot Clock Hardware Connections...............................................................................................8
2.4 DRIVER MODE CONFIGURATION .....................................................................................................................9
2.4.1 DOT_CLOCK_FREQUENCY_DATA..........................................................................................9
2.4.2 DOT_CLOCK_FREQUENCY_BLANK.......................................................................................9
2.4.3 DESIRED_FRAME_RATE..........................................................................................................9
2.4.4 MINIMUM_MCU_ACCESS_PCT...............................................................................................9
2.5 LCD PANEL CONFIGURATION..........................................................................................................................9
2.5.1 DOT_INVERT..............................................................................................................................9
2.5.2 V_LINES_xx and H_DOT_xx ......................................................................................................9
2.6 LCD PLATFORM CONFIGURATION................................................................................................................. 10
2.6.1 FRAME_CS ...............................................................................................................................10
2.6.2 FRAME_BUS_CYCLES.............................................................................................................10
2.6.3 CAS_LATENCY.........................................................................................................................10
2.6.4 SDRAM_PAGE_SIZE ................................................................................................................10
2.6.5 EDMAC_DD..............................................................................................................................10
2.6.6 Xxxx_PORT ...............................................................................................................................10
2.6.7 Xxxx_PIN...................................................................................................................................10
2.6.8 Xxxx_INTC ................................................................................................................................10
2.6.9 Xxxx_VECT................................................................................................................................10
2.6.10 Xxxx_TPU_CHANNEL..............................................................................................................11
2.6.11 Xxxx_TPU_PIN .........................................................................................................................11
3. TYPICAL LC D PANEL CONNECTIONS......................................................................................................12
3.1 LCD P ANEL INTERFACE................................................................................................................................. 12
3.1.1 Power Supplies..........................................................................................................................12
3.1.2 Clock..........................................................................................................................................12
3.1.3 HSync.........................................................................................................................................12
3.1.4 VSync.........................................................................................................................................12
3.1.5 Data Enable...............................................................................................................................13
3.1.6 RGB (Red Green Blue) Data .....................................................................................................13
3.1.7 Touch Screen..............................................................................................................................13
3.2 HARDWARE DESIGN ......................................................................................................................................14
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Direct Drive LCD Design Guide
4. LCD API DEFINITION..................................................................................................................................... 15
4.1.1 Standard Redefines ....................................................................................................................15
4.1.2 LCD API Data Ty pes.................................................................................................................15
4.1.3 LCDInit......................................................................................................................................16
4.1.4 LCDBacklight............................................................................................................................17
4.1.5 LCDSetFrameRate.....................................................................................................................18
4.1.6 LCDGetFrameRate....................................................................................................................19
4.1.7 LCDSetActiveRaster..................................................................................................................20
4.1.8 LCDGetActiveFrame.................................................................................................................21
4.1.9 LCDSetRasterOffset...................................................................................................................22
4.1.10 LCDSetLineSource ....................................................................................................................23
WEBSITE AND SUPPORT ......................................................................................................................................24
REVISION RECORD................................................................................................................................................24
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Direct Drive LCD Design Guide
1.
Introduction
This document provides technical information of how to configure the LCD panel parameters required by
Renesas LCD Direct Driver according to the LCD panel datasheet published by the manufacturers. This
document will also describe all the APIs (Application Programming Interface) in the LCD Direct Driver and
their usages.
An overview of the system hardware is also provided
1.1
The H8S and H8SX device families include several peripherals that enable the direct connection of RGB
interface TFT panels directly to the MCU data bus. These peripherals include the ExDMA (external DMA
controller unit) and the TPU (Timer Pulse Unit). With these peripherals and an external RAM device (for
LCD frame buffer use), the LCD panel can be refreshed using less than 5% of the MCU processing
capacity.
Direct Drive LCD Overview
1.1.1 Philosophy
The Direct Drive LCD solution was developed to provide a low cost, long life solution for driving TFT
panels for use in GUI applications with limited animation requirements. This solution reduces the risk for
products with relatively long life on volatile components (such as stand alone LCD controllers, TFT panels
with integrated LCD controllers, or application specific microprocessors).
1.1.2 Capabilities
The current features of the Direct Drive LCD solution are:
• Ability to use standard PSRAM, SRAM or SDRAM as frame buffer.
• Ability to create multiple frame buffers within the available RAM.
• Ability to dynamically modify frame rate to accommodate varying system update requirements.
• Ability to drive RGB panels at 16bpp up to WVGA resolution at up to 60Hz frame rates.
• Ability to pan larger display regions within a portion of the LCD panel area.
• Very simple operation model…user code manipulates images in the frame buffer. The frame buffer
is transparently transferred to the LCD panel.
The Direct Drive LCD solution is highly configurable, and capable of producing many different timing
configurations which drive the input signals of TFT-LCD panels from various panel manufacturers. The
signal timing generated from the Direct Drive LCD solution depends on your choice panel resolution,
frame buffer memory, and desired panel refresh and animation rates.
Although Renesas provides guidelines and examples for configuring the signal timing, Renesas is not
responsible for meeting the AC timing specifications of your specific choice of TFT-LCD panel. Please
contact your TFT-LCD panel manufacturer to ensure the Direct Drive LCD solution complies with the
panel timing limitations.
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Direct Drive LCD Design Guide
2.
Driver Configuration
The LCD Direct Driver is configured through the setting of macro definitions. These macros are illustrated
in the sample code. The following table briefly describes the location of each of these macros and their
location in LCD Direct Drive demonstration code. For examples of each macro usage, refer to the
demonstration code.
2.1
Macro Name Description Units Demo Location
System Clock Configuration
ICLK_FREQUENCY Clock frequency of MCU core Hz HWSetup.h
PCLK_FREQUENCY Clock frequency of peripherals Hz HWSetup.h
BCLK_FREQUENCY Clock frequency of external bus Hz HWSetup.h
FRAME_HEIGHT Frame Buffer Configuration Lines DirectLCD_CNF.h
FRAME_WIDTH Frame Buffer Configuration Dots DirectLCD_CNF.h
V_LINES_INVERT Frame Buffer Configuration Select DirectLCD_CNF.h
H_DOT_INVERT Frame Buffer Configuration Select DirectLCD_CNF.h
PANEL_ROTATE Frame Buffer Configuration Select DirectLCD_CNF.h
LCD_FRAMES Frame Buffer Configuration Frames DirectLCD_CNF.h
MAX_FRAME_REGIONS Frame Buffer Configuration Regions DirectLCD_CNF.h
SRAM_DD Driver Mode Selection Select DirectLCD_CNF.h
SRAM_NOMUX_DD Driver Mode Selection Select DirectLCD_CNF.h
SDRAM_DD Driver Mode Selection Select DirectLCD_CNF.h
SDRAM_CLUSTER_DD Driver Mode Selection Select DirectLCD_CNF.h
DOT_CLOCK_FREQUENCY_DATA Drive r Mode Configuration Hz DirectLCD_CNF.h
DOT_CLOCK_FREQUENCY_BLANK Driver Mode Configuration Hz DirectLCD_CNF.h
DESIRED_FRAME_RATE Driver Mode Configuration Hz DirectLCD_CNF.h
MINIMUM_MCU_ACCESS_PCT Driver Mode Configuration % DirectLCD_CNF.h
DOT_INVERT LCD Panel Configuration Select DirectLCD_CNF(panel).h
V_LINES_PULSE LCD Panel Configuration Lines DirectLCD_CNF(panel).h
V_LINES_BACK_PORCH LCD Panel Configuration Lines DirectLCD_CNF(panel).h
V_LINES_DISPLAY LCD Panel Configuration Lines DirectLCD_CNF(panel).h
V_LINES_FRONT_PORCH LCD Panel Configuration Lines DirectLCD_CNF(panel).h
H_DOT_PULSE LCD Panel Configuration Dots DirectLCD_CNF(panel).h
H_DOT_BACK_PORCH LCD Panel Configuration Dots DirectLCD_CNF(panel).h
H_DOT_DISPLAY LCD Panel Configuration Dots DirectLCD_CNF(panel).h
H_DOT_FRONT_PORCH LCD Panel Configuration Dots DirectLCD_CNF(panel).h
LCD Direct Drive Configuration Macros
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Direct Drive LCD Design Guide
Macro Name Description Units Demo Location
FRAME_CS Platform Configuration CS # DirectLCD_CNF(platform ).h
FRAME_BUS_CYCLES Platform Configuration Bclk DirectLCD_CNF(platform).h
CAS_LATENCY Platform Configuration Bclk DirectLCD_CNF(platform).h
SDRAM_PAGE_SIZE Platform Configuration Words DirectLCD_CNF(platform).h
VSYNC_PORT Platform Configuration Port # DirectLCD_CNF(platform).h
VSYNC_PIN Platform Configuration Pin # DirectLCD_CNF(platform).h
HSYNC_PORT Platform Configuration Port # DirectLCD_CNF(platform).h
HSYNC_PIN Platform Configuration Pin # DirectLCD_CNF(platform).h
DOTCLK_PORT Platform Configuration Port # DirectLCD_CNF(platform).h
DOTCLK_PIN Platform Configuration Pin # DirectLCD_CNF(platform).h
LCD_BACKLIGHT_PORT Platform Configuration Port # DirectLCD_CNF(platform).h
LCD_BACKLIGHT_PIN Platform Configuration Pin # DirectLCD_CNF(platform).h
EXDMAC_DD Platform Configuration SFR root DirectLCD_CNF(platform).h
EXDMAC_DD_INTC Platform Configuration SFR bits DirectLCD_CNF(platform).h
EXDMAC_DD_VECT Platform Configuration Vector # DirectLCD_CNF(platform).h
EXDMAC_DD_REQ_PORT Platform Configuration Port # DirectLCD_CNF(platform).h
EXDMAC_DD_REQ_PIN Platform Configuration Pin # DirectLCD_CNF(platform).h
DOTCLK_TPU_INTC Platform Configuration SFR bits DirectLCD_CNF(platform).h
DOTCLK_TPU_CHANNEL Platform Configuration Channel # DirectLCD_CNF(platform).h
DOTCLK_TPU_PIN Platform Configuration Pin Letter DirectLCD_CNF(platform).h
DOTCLK_TPU_VECT Platform Configuration Vector # DirectLCD_CNF(platform).h
DOTPER_TPU_CHANNEL Platform Configuration Channel # DirectLCD_CNF(platform).h
DOTPER_TPU_PIN Platform Configuration Pin Letter DirectLCD_CNF(platform).h
DOTPER_TPU_VECT Platform Configuration Vector # DirectLCD_CNF(platform).h
HPER_TPU_INTC Platform Configuration SFR bits DirectLCD_CNF(platform).h
HPER_TPU_CHANNEL Platform Configuration Channel # DirectLCD_CNF(platform).h
HPER_TPU_PIN Platform Configuration Pin Letter DirectLCD_CNF(platform).h
HPER_TPU_VECT Platform Configuration Vector # DirectLCD_CNF(platform).h
HSYNC_TPU_INTC Platform Configuration SFR bits DirectLCD_CNF(platform).h
HSYNC_TPU_CHANNEL Platform Configuration Channel # DirectLCD_CNF(platform).h
HSYNC_TPU_PIN Platform Configuration Pin Letter DirectLCD_CNF(platform).h
HSYNC_TPU_VECT Platform Configuration Vector # DirectLCD_CNF(platform).h
VSYNC_TPU_INTC Platform Configuration SFR bits DirectLCD_CNF(platform).h
VSYNC_TPU_CHANNEL Platform Configuration Channel # DirectLCD_CNF(platform).h
VSYNC_TPU_PIN Platform Configuration Pin Letter DirectLCD_CNF(platform).h
VSYNC_TPU_VECT Platform Configuration Vector # DirectLCD_CNF(platform).h
HDEN_TPU_INTC Platform Configuration SFR bits DirectLCD_CNF(platform).h
HDEN_TPU_CHANNEL Platform Configuration Channel # DirectLCD_CNF(platform).h
HDEN_TPU_PIN Platform Configuration Pin Letter DirectLCD_CNF(platform).h
HDEN_TPU_VECT Platform Configuration Vector # DirectLCD_CNF(platform).h
HDEN2_TPU_CHANNEL Platform Configuration Channel # DirectLCD_CNF(platform).h
HDEN2_TPU_PIN Platform Configuration Pin Letter DirectLCD_CNF(platform).h
HDEN2_TPU_VECT Platform Configuration Vector # DirectLCD_CNF(platform). h
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Direct Drive LCD Design Guide
2.2 Frame Buffer Configuration
The frame buffer is the external memory area that is used to store the 16bpp image data that will be
presented on the LCD screen. The quantity of frame buffers is typically 2 or more. This allows the MCU to
be updating one frame wile the ExDMA is transferring the other frame to the LCD panel, this behavior
allows for fast transitions and the user does not see operations occurring in the non-displayed buffers.
Typically, the frame buffer is configured to the same dimensions as the LCD panel; however the frame
buffer can be larger to allow the LCD panel to act as a “window” into the frame buffer (allowing for fast
panning of large images).
The following macros control the sizing of the frame buffer.
2.2.1 FRAME_HEIGHT
Defines the number of lines in each of the frame buffers.
2.2.2 FRAME_WIDTH
Defines the number of dots (columns) in each of the frame buffer lines.
2.2.3 V_LINES_INVERT
If defined flips the presentation of lines on the display.
2.2.4 H_DOT_INVERT
If defined flips the presentation of dots (columns) on the display.
2.2.5 PANEL_ROTATE
Rotates the presentation of data (rows/columns) on the LCD panel. Only available on H8SX SRAM based
modes.
2.2.6 LCD_FRAMES
Defines the number of frame buffers allocated in the driver. The demonstration code value is two by
default. This value can be set to zero in which case, the user code is responsible for the allocation of
frame buffers.
2.2.7 MAX_FRAME_REGIONS
Defines the number of horizontal screen “splits” that can be used within the driver. The demonstration
code default value is 1 (no splits). This capability allows different source regions to be used with horizontal
screen areas (control GUI + panning image view for example).
The default display sequence of a LCD panel is shown in Figure 1. The origin of the display is shown as
the green dot in the picture. By default the driver will send the raster image to the LCD panel in the same
sequence. If necessary, there are two macros available to change the sequence of data presented to the
panel. V_LINES_INVERT sends the top line first and sequences to the bottom and H_DOT_INVERT
sends the right side of the line first and sequences to the left. Either or both of these macros can be
specified at the same time. PANEL_ROTATE (only available on H8SX) is the macro to allow user image to
be rotated in transfer to the panel as shown in the Figure 2.
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Direct Drive LCD Design Guide
Figure 1. RAM Frame Raster Data
Figure 2. PANEL_ROTATE Mode
Figure 3. Images from Various Display Settings
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