Realtek RTL8111H-CG, RTL8111HS-CG DATASHEET

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RTL8111H-CG RTL8111HS-CG

INTEGRATED 10/100/1000M ETHERNET

CONTROLLER FOR PCI EXPRESS APPLICATIONS

DATASHEET

(CONFIDENTIAL: Development Partners Only)

Rev. 1.2

20 August 2014

Track ID: JATR-8275-15

Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com

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RTL8111H/RTL8111HS

©2014 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.

LICENSE

This product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and US6,327,625.

Datasheet

USING THIS DOCUMENT

This document is intended for the software engineer’s reference and provides detailed programming information.

Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.

REVISION HISTORY

Revision Release Date Summary

1.0 2014/01/21 First release.

1.1 2014/04/17 Revised Table 20 Electrostatic Discharge Performance, page 24. Revised Table 22 Oscillator Requirements, page 25. Revised Table 24 DC Characteristics, page 26.

1.2 2014/08/20

Added a new signal type code, type I Pin Descriptions, page 7.

Revised Minimum High Level Input Voltage for I Characteristics, page 26.

for 1.8V/3.3V compatible input, in section 6

Pinout, Table 24 DC

Integrated 10/100/1000M Ethernet Controller for PCI Express ii Track ID: JATR-8275-15 Rev. 1.2

Page 3

Table of Contents

RTL8111H/RTL8111HS

Datasheet

1. GENERAL DESCRIPTION..............................................................................................................................................1

2. FEATURES.........................................................................................................................................................................3

SYSTEM APPLICATIONS...............................................................................................................................................3

4. FUNCTION BLOCK DIAGRAM.....................................................................................................................................4

5. PIN ASSIGNMENTS .........................................................................................................................................................5

5.1.

5.2.

5.3.

5.4.

6. PIN DESCRIPTIONS.........................................................................................................................................................7

6.1.

6.2.

6.3.

6.4.

6.5.

6.6.

6.7.

6.8.

7. FUNCTIONAL DESCRIPTION.....................................................................................................................................10

7.1.

7.2.

7.3.

7.4.

7.5.

7.6.

7.7.

7.8.

7.9.

7.10. ‘R

7.11. L1.O

7.12. G

7.13. XTAL-L

7.14. LAN D

RTL8111H P

ACKAGE IDENTIFICATION

P RTL8111HS P

ACKAGE IDENTIFICATION

OWER MANAGEMENT/ISOLATION

7.1.1. PCI Express Transmitter...................................................................................................................................... 10

7.1.2. PCI Express Receiver...........................................................................................................................................10

7.2.1. LED Blinking Frequency Control.........................................................................................................................13

7.3.1. PHY Transmitter...................................................................................................................................................14

7.3.2. PHY Receiver .......................................................................................................................................................14

7.3.3. Link Down Power Saving Mode...........................................................................................................................15

7.3.4. Next Page .............................................................................................................................................................15

7.5.1. Receive-Side Scaling (RSS) Initialization.............................................................................................................17

7.5.2. Protocol Offload...................................................................................................................................................18

7.5.3. RSS Operation......................................................................................................................................................18

XPRESS INTERFACE

PCI E

RANSCEIVER INTERFACE

T C

LOCK

EGULATOR AND REFERENCE

LEDS...........................................................................................................................................................................9

OWER AND GROUND

GPO PIN......................................................................................................................................................................9

PCI E

XPRESS BUS INTERFACE

USTOMIZABLE

PHY T

OWER MANAGEMENT

ECEIVE-SIDE SCALING

NERGY EFFICIENT ETHERNET

E PHY D L

ATENCY TOLERANCE REPORTING

AKE PACKET INDICATION

EALWO

FF AND

IGA LITE

IN ASSIGNMENTS

.........................................................................................................................................................................8

..................................................................................................................................................9

LED C

ONFIGURATION

RANSCEIVER

ISABLE MODE

W!’ (W

L1.S

(500M) .....................................................................................................................................................20

ESS WAKE-ON

ISABLE MODE

...................................................................................................................................................14

...............................................................................................................................................15

.................................................................................................................................................19

AKE-ON

NOOZE

.................................................................................................................................................20

....................................................................................................................................5

...........................................................................................................................................5

..................................................................................................................................6

...........................................................................................................................................6

..............................................................................................................................7

.............................................................................................................................................7

............................................................................................................................................8

......................................................................................................................................8

....................................................................................................................................10

......................................................................................................................11

(RSS) ..................................................................................................................................17

(EEE)........................................................................................................................18

(LTR) .................................................................................................................19

(WPI) ............................................................................................................................19

-WAN) T

............................................................................................................................................20

-LAN....................................................................................................................................20

ECHNOLOGY

......................................................................................................19

8. SWITCHING REGULATOR (RTL8111HS ONLY)....................................................................................................21

9. LDO REGULATOR (RTL8111H ONLY)......................................................................................................................21

Integrated 10/100/1000M Ethernet Controller for PCI Express iii Track ID: JATR-8275-15 Rev. 1.2

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RTL8111H/RTL8111HS

Datasheet

10.

11.

12.

13.

POWER SEQUENCE..................................................................................................................................................22

10.1. P

CHARACTERISTICS.................................................................................................................................................24

11.1. A

11.2. R

11.3. E

11.4. C

11.5. O

11.6. E

11.7. DC C

11.8. R

11.9. PCI E

11.9.1.

11.9.2.

11.9.3.

11.9.4.

MECHANICAL DIMENSIONS.................................................................................................................................34

ORDERING INFORMATION...................................................................................................................................35

OWER SEQUENCE PARAMETERS

BSOLUTE MAXIMUM RATINGS

ECOMMENDED OPERATING CONDITIONS

LECTROSTATIC DISCHARGE PERFORMANCE

RYSTAL REQUIREMENTS

SCILLATOR REQUIREMENTS

NVIRONMENTAL CHARACTERISTICS

HARACTERISTICS

EFLOW PROFILE RECOMMENDATIONS

XPRESS BUS PARAMETERS

Differential Transmitter Parameters...............................................................................................................28

Differential Receiver Parameters....................................................................................................................29

REFCLK Parameters.......................................................................................................................................29

Auxiliary Signal Timing Parameters ...............................................................................................................33

...............................................................................................................................................26

...............................................................................................................................23

................................................................................................................................24

.................................................................................................................24

............................................................................................................24

..........................................................................................................................................25

....................................................................................................................................25

........................................................................................................................25

.....................................................................................................................27

................................................................................................................................28

Integrated 10/100/1000M Ethernet Controller for PCI Express iv Track ID: JATR-8275-15 Rev. 1.2

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RTL8111H/RTL8111HS

Datasheet

List of Tables

ABLE 1. POWER MANAGEMENT/ISOLATION

ABLE 2.

ABLE 3. TRANSCEIVER INTERFACE

ABLE 4. CLOCK

ABLE 5. REGULATOR AND REFERENCE

ABLE 6.

ABLE 7. POWER AND GROUND

ABLE 8.

ABLE 9.

ABLE

T T

ABLE

T T

ABLE

PCI E

XPRESS INTERFACE

..............................................................................................................................................7

............................................................................................................................................8

..........................................................................................................................................................................8

LEDS............................................................................................................................................................................9

...................................................................................................................................................9

GPO PIN.......................................................................................................................................................................9

ELECT

LED S

USTOMIZED

10. C

IXED

11. F

12. LED F

13. LED F

14. LED O

15. LED B

16. L1.O

17. P

18. A

19. R

20. E

21. C

22. O

23. E

24. DC C

25. R

26. D

27. D

LED M

EATURE CONTROL

PTION 1 & OPTION 2 SETTINGS

LINKING FREQUENCY CONTROL

FF AND

OWER SEQUENCE PARAMETERS

BSOLUTE MAXIMUM RATINGS

ECOMMENDED OPERATING CONDITIONS

LECTROSTATIC DISCHARGE PERFORMANCE

RYSTAL REQUIREMENTS

SCILLATOR REQUIREMENTS

NVIRONMENTAL CHARACTERISTICS

HARACTERISTICS

EFLOW PROFILE RECOMMENDATIONS

IFFERENTIAL TRANSMITTER PARAMETERS

IFFERENTIAL RECEIVER PARAMETERS

28. REFCLK P

UXILIARY SIGNAL TIMING PARAMETERS

29. A

RDERING INFORMATION

30. O

EGISTER OFFSET 18H

(IO R

LEDS...................................................................................................................................................11

ODE

.....................................................................................................................................................11

-1........................................................................................................................................12

-2........................................................................................................................................12

NOOZE

L1.S

PCIE P

..........................................................................................................................................25

...............................................................................................................................................26

ARAMETERS

.............................................................................................................................................29

..........................................................................................................................................35

...............................................................................................................................7

......................................................................................................................................8

~19H) ..........................................................................................................11

.......................................................................................................................12

FFSET 1AH

(IO O

ORT CIRCUIT ON/OFF

) .........................................................................................13

..............................................................................................20

...............................................................................................................................22

................................................................................................................................24

.................................................................................................................24

............................................................................................................24

....................................................................................................................................25

........................................................................................................................25

.....................................................................................................................27

..............................................................................................................28

.....................................................................................................................29

.................................................................................................................33

List of Figures

IGURE 1. FUNCTION BLOCK DIAGRAM

IGURE 2.

IGURE 3.

IGURE 4.

IGURE 5. POWER SEQUENCE

IGURE 6. SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING

IGURE 7. SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT

IGURE 8. SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING

F F

IGURE 9. DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD

IGURE

F F

IGURE

RTL8111H P RTL8111HS P LED B

IN ASSIGNMENTS

LINKING FREQUENCY EXAMPLE

.....................................................................................................................................................22

IFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME

10. D

IFFERENTIAL MEASUREMENT POINTS FOR RINGBACK

11. D

12. R

EFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING

13. A

UXILIARY SIGNAL TIMING

Integrated 10/100/1000M Ethernet Controller for PCI Express v Track ID: JATR-8275-15 Rev. 1.2

.......................................................................................................................................4

....................................................................................................................................5

..................................................................................................................................6

.....................................................................................................................13

..................................................31

...........................................................................31

........................................................31

....................................................................32

...........................................................................32

............................................................................................32

.........................................................................33

......................................................................................................................................33

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RTL8111H/RTL8111HS

Datasheet

1. General Description

The Realtek RTL8111H-CG/RTL8111HS-CG 10/100/1000M Ethernet controller combines a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8111H/RTL8111HS offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection and Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds.

The RTL8111H/RTL8111HS supports the PCI Express 1.1 bus interface for host communications with power management, and complies with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. It supports an auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. The RTL8111H/RTL8111HS features embedded One-Time-Programmable (OTP) memory. The RTL8111H provides a built-in LDO regulator, and the RTL8111HS provides a built-in switching regulator.

Advanced Configuration Power management Interface (ACPI)—power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM)—is supported to achieve the most efficient power management possible. PCI MSI (Message Signaled Interrupt) and MSI-X are also supported.

In addition to the ACPI feature, remote wake-up (including AMD Magic Packet and Microsoft Wake-Up Frame) is supported in both ACPI and APM (Advanced Power Management) environments. To support WOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the RTL8111H/RTL8111HS. To further reduce power consumption, the RTL8111H/RTL8111HS also supports PCIe L1.Off and L1.Snooze.

The RTL8111H/RTL8111HS supports ‘RealWoW!’ technology that enables remote wake-up of a sleeping PC through the Internet. This feature allows PCs to reduce power consumption by remaining in low power sleeping state until needed.

Note: The ‘RealWoW!’ service requires registration on first time use.

The RTL8111H/RTL8111HS supports Protocol offload. It offloads some of the most common protocols to NIC hardware in order to prevent spurious wake-up and further reduce power consumption. The RTL8111H/RTL8111HS can offload ARP (IPv4) and NS (IPv6) protocols while in the D3 power saving state.

Integrated 10/100/1000M Ethernet Controller for PCI Express 1 Track ID: JATR-8275-15 Rev. 1.2

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RTL8111H/RTL8111HS

The RTL8111H/RTL8111HS supports the ECMA (European Computer Manufacturers Association) proxy for sleeping hosts standard. The standard specifies maintenance of network connectivity and presence via proxies in order to extend the sleep duration of higher-powered hosts. It handles some network tasks on behalf of the host, allowing the host to remain in sleep mode for longer periods. Required and optional behavior of an operating proxy includes generating reply packets, ignoring packets, and waking the host.

The RTL8111H/RTL8111HS supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet (EEE). IEEE 802.3az-2010 operates with the IEEE 802.3 Media Access Control (MAC) sublayer to support operation in Low Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both sides of the link to save power.

The RTL8111H/RTL8111HS is fully compliant with Microsoft NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP) Checksum and Segmentation Task-offload (Large send and Giant send) features, and supports IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server.

Datasheet

The RTL8111H/RTL8111HS supports Receive-Side Scaling (RSS) to hash incoming TCP connections and load-balance received data processing across multiple CPUs. RSS improves the number of transactions per second and number of connections per second, for increased network throughput.

The device features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low-pin-count, serial, interconnect technology that offers significant improvements in performance over conventional PCI and also maintains software compatibility with existing PCI infrastructure.

The RTL8111H/RTL8111HS is suitable for multiple market segments and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications.

Integrated 10/100/1000M Ethernet Controller for PCI Express 2 Track ID: JATR-8275-15 Rev. 1.2

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2. Features

RTL8111H/RTL8111HS

Datasheet

Hardware

 Integrated 10/100/1000M transceiver  Supports Giga Lite (500M) mode  Auto-Negotiation with Next Page capability  Supports PCI Express 1.1  Supports pair swap/polarity/skew correction  Crossover Detection & Auto-Correction  Supports 1-Lane 2.5Gbps PCI Express Bus  Embedded OTP memory  Supports hardware ECC (Error Correction

Code) function

 Supports hardware CRC (Cyclic

Redundancy Check) function

 Transmit/Receive on-chip buffer support  Supports PCI MSI (Message Signaled

Interrupt) and MSI-X

 LAN disable with GPIO pin  Supports LTR (Latency Tolerance

Reporting)

 Wake-On-LAN and ‘RealWoW!’

Technology (remote wake-up) support

 Supports 32-set 128-byte Wake-Up Frame

pattern exact matching

 Supports Microsoft WPI (Wake Packet

Indication)

 Supports PCIe L1.Off and L1.Snooze

IEEE

 Fully compliant with IEEE 802.3,

IEEE 802.3u, IEEE 802.3ab

 Supports IEEE 802.1P Layer 2 Priority

Encoding

Supports IEEE 802.1Q VLAN tagging



 Supports IEEE 802.3az-2010 (EEE)  Supports 25MHz or 48MHz Oscillator  Built-in switching (RTL8111HS) and LDO

(RTL8111H) regulator

 Supports power down/link down power

saving/PHY disable mode

 Customized LEDs  Controllable LED Blinking Frequency and

Duty Cycle

 32-pin QFN ‘Green’ package  Supports EMAC-393 ECMA ProxZzzy

Standard for sleeping hosts

 XTAL-Less Wake-On-LAN

 Supports Full Duplex flow control

(IEEE 802.3x)

Software Offload

 Microsoft NDIS5, NDIS6 Checksum

Offload (IPv4, IPv6, TCP, UDP) and Segmentation Task-offload (Large send v1 and Large send v2) support

 Supports jumbo frame to 9K bytes

 Supports quad core Receive-Side Scaling

(RSS)

 Supports Protocol Offload (ARP & NS)

3. System Applications

 PCI Express 10/100/1000M Ethernet on Motherboard, Notebook, or Embedded systems

Integrated 10/100/1000M Ethernet Controller for PCI Express 3 Track ID: JATR-8275-15 Rev. 1.2

Page 9

4. Function Block Diagram

RTL8111H/RTL8111HS

Datasheet

Figure 1. Function Block Diagram

Integrated 10/100/1000M Ethernet Controller for PCI Express 4 Track ID: JATR-8275-15 Rev. 1.2

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5. Pin Assignments

5.1. RTL8111H Pin Assignments

RTL8111H/RTL8111HS

Datasheet

LED2

LED1/GPO

LED0

CKXTAL1

CKXTAL2

AVDD10

RSET

AVDD33

REGOUT

24 23 22 21 20 19 18 17

33 GND ( Exposed Pad)

12345678

DVDD10

VDDREG

LANWAKEB

REALTEK

8111H LLLLLLL

GXXXV

ISOLATEB

PERSTB

HSON

HSOP

REFCLK_N

REFCLK_P

HSIN

HSIP

CLKREQB

AVDD33

MDIN3

MDIP3

MDIP0

MDIN0

MDIP1

AVDD10

MDIP2

MDIN1

MDIN2

AVDD10

Figure 2. RTL8111H Pin Assignments

5.2. Package Identification

Green package is indicated by the ‘G’ in GXXXV (Figure 2).

Integrated 10/100/1000M Ethernet Controller for PCI Express 5 Track ID: JATR-8275-15 Rev. 1.2

Page 11

5.3. RTL8111HS Pin Assignments

RTL8111H/RTL8111HS

Datasheet

Figure 3. RTL8111HS Pin Assignments

5.4. Package Identification

Green package is indicated by the ‘G’ in GXXXV (Figure 3).

Integrated 10/100/1000M Ethernet Controller for PCI Express 6 Track ID: JATR-8275-15 Rev. 1.2

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6. Pin Descriptions

The signal type codes below are used in the following tables:

I: Input O/D: Open Drain

Ic:

1.8V/3.3V compatible input

Output

6.1. Power Management/Isolation

Table 1. Power Management/Isolation

Symbol Type Pin No Description

Power Management Event (Open Drain; Active Low, 1.8V/3.3V compatible

LANWAKEB Ic /O/D 21

ISOLATEB Ic 20

input/output mode with a weak external pull up resistor). Used to reactivate the PCI Express slot’s main power rails and reference clocks.

Isolate Pin (Active Low, 1.8V/3.3V compatible input). Used to isolate the RTL8111H/RTL8111HS from the PCI Express bus. The

RTL8111H/RTL8111HS will not drive its PCI Express outputs (excluding LANWAKEB) and will not sample its PCI Express input as long as the Isolate pin is asserted. The isolate pin will follow the system state S0 to high, and S3/S4 to low.

P: Power

RTL8111H/RTL8111HS

Datasheet

6.2. PCI Express Interface

Table 2. PCI Express Interface

Symbol Type Pin No Description

REFCLK_P I 15

REFCLK_N I 16

HSOP O 17

HSON O 18

HSIP I 13

HSIN I 14

PERSTB Ic 19

CLKREQB Ic /O/D 12

PCI Express Differential Reference Clock Source (100MHz ± 300ppm).

PCI Express Transmit Differential Pair.

PCI Express Receive Differential Pair.

PCI Express Reset Signal (Active Low, 1.8V/3.3V compatible input). When the PERSTB is asserted at power-on state, the RTL8111H/RTL8111HS

returns to a pre-defined reset state and is ready for initialization and configuration after the de-assertion of the PERSTB.

Reference Clock Request Signal (Open Drain; Active Low, 1.8V/3.3V compatible input/output mode with a weak external pull up resistor).

This signal is used by the RTL8111H/RTL8111HS to request starting of the PCI Express reference clock.

The signal is also used by the L1.off mechanism. In this case, CLKREQB can be asserted by either the system or RTL8111H/RTL8111HS to initiate an L1 exit.

Integrated 10/100/1000M Ethernet Controller for PCI Express 7 Track ID: JATR-8275-15 Rev. 1.2

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6.3. Transceiver Interface

Table 3. Transceiver Interface

Symbol Type Pin No Description

MDIP0 IO 1

MDIN0 IO 2

MDIP1 IO 4

MDIN1 IO 5

MDIP2 IO 6

MDIN2 IO 7

MDIP3 IO 9

MDIN3 IO 10

In MDI mode, this is the first pair in 1000Base-T, i.e., the BI_DA+/- pair, and is the transmit pair in 10Base-T and 100Base-TX.

In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair in 10Base-T and 100Base-TX.

In MDI mode, this is the second pair in 1000Base-T, i.e., the BI_DB+/- pair, and is the receive pair in 10Base-T and 100Base-TX.

In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit pair in 10Base-T and 100Base-TX.

In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair.

In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair.

RTL8111H/RTL8111HS

Datasheet

6.4. Clock

Table 4. Clock

Symbol Type Pin No Description

CKXTAL1 I 28 Input of 25MHz or 48MHz Clock Reference.

CKXTAL2 IO 29

Input of External Clock Source. Output of 25MHz or 48MHz Clock Reference.

6.5. Regulator and Refere nce

Table 5. Regulator and Reference

Symbol Type Pin No Description

REGOUT O 24 RTL8111HS: Switching Regulator 1.0V Output.

RTL8111H: LDO Regulator 1.0V Output.

VDDREG P 23 Digital 3.3V Power Supply for Switching/LDO Regulator.

RSET I 31 Reference (External Resistor Reference).

Note: See section 8 Switching Regulator, page 21, and section 9 LDO Regulator, page 21 for additional information.

Integrated 10/100/1000M Ethernet Controller for PCI Express 8 Track ID: JATR-8275-15 Rev. 1.2

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RTL8111H/RTL8111HS

Datasheet

6.6. LEDs

Table 6. LEDs

Symbol Type Pin No Description

LED0 O

LED1/GPO O

LED2 O 25

Note 1: During power down mode, the LED signals are logic high. Note 2: The LED1 pin can be changed to a GPO pin. The setting is changed from the register. Only one function (LED1

or GPIO) may be selected at one time (Default: LED1). For GPO function details, see section 6.8 GPO Pin, page 9.

See Section 7.2 Customizable LED Configuration, Page 11 for Details.

6.7. Power and Ground

Table 7. Power and Ground

Symbol Type Pin No Description

AVDD10 P 3, 8, 30 Analog 1.0V Power Supply.

DVDD10 P 22 1.0V Power Supply.

GND P 33 Ground (Exposed Pad).

AVDD33 P 11, 32 3.3V Power Supply.

Note: Refer to the latest schematic circuit for correct configuration.

6.8. GPO Pin

Table 8. GPO Pin

Symbol Type Pin No Description

GPO/LED1 Ic/O 26

Note: The LED1 pin can be changed to a GPO pin. The setting is changed from the register. Only one function (LED1 or GPIO) may be selected at one time (Default: LED1).

General Purpose Input/Output Pin (1.8V/3.3V compatible input, 3.3V output only).

The setting is changed from the register. Only one function (LED1 or GPIO) may be selected at one time (default: LED1).

Power Saving Feature: Output pin. Link OK Feature: Output pin. PHY Disable Mode (active low): Input pin.

Integrated 10/100/1000M Ethernet Controller for PCI Express 9 Track ID: JATR-8275-15 Rev. 1.2

Page 15

RTL8111H/RTL8111HS

Datasheet

7. Functional Description

7.1. PCI Express Bus Interface

The RTL8111H/RTL8111HS complies with PCI Express Base Specification Revision 1.1, and runs at a

2.5GHz signaling rate with X1 link width, i.e., one transmit and one receive differential pair. The RTL8111H/RTL8111HS supports four types of PCI Express messages: interrupt messages, error messages, power management messages, and hot-plug messages. To ease PCB layout constraints, PCI Express lane polarity reversal is supported.

7.1.1. PCI Express Transmitter

The RTL8111H/RTL8111HS’s PCI Express block receives digital data from the Ethernet interface and performs data scrambling with Linear Feedback Shift Register (LFSR) and 8B/10B coding technology into 10-bit code groups. Data scrambling is used to reduce the possibility of electrical resonance on the link, and 8B/10B coding technology is used to benefit embedded clocking, error detection, and DC balance by adding an overhead to the system through the addition of two extra bits. The data code groups are passed through its serializer for packet framing. The generated 2.5Gbps serial data is transmitted onto the PCB trace to its upstream device via a differential driver.

7.1.2. PCI Express Receiver

The RTL8111H/RTL8111HS’s PCI Express block receives 2.5Gbps serial data from its upstream device to generate parallel data. The receiver’s PLL circuits are re-synchronized to maintain bit and symbol lock. Through 8B/10B decoding technology and data de-scrambling, the original digital data is recovered and passed to the RTL8111H/RTL8111HS’s internal Ethernet MAC to be transmitted onto the Ethernet media.

Integrated 10/100/1000M Ethernet Controller for PCI Express 10 Track ID: JATR-8275-15 Rev. 1.2

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RTL8111H/RTL8111HS

Datasheet

7.2. Customizable LED Configuration

The RTL8111H/RTL8111HS supports customizable LED operation modes via IO register offset 18h~19h. Table 9 describes the different LED actions.

Table 9. LED Select (IO Register Offset 18h~19h)

Bit Symbol RW Description

15:12 LEDCntl RW LED Feature Control.

11:8 LEDSEL2 RW LED Select for PINLED2.

7:4 LEDSEL1 RW LED Select for PINLED1.

3:0 LEDSEL0 RW LED Select for PINLED0.

When implementing customized LEDs:

Configure IO register offset 18h~19h to support your own LED signals. For example, if the value in the IO offset 0x18 is 0x0CA9h (0000110010101001b), the LED actions are:

• LED 0: On only in 10M mode, with blinking during TX/RX

• LED 1: On only in 100M mode, with blinking during TX/RX

• LED 2: On only in 1000M mode, with blinking during TX/RX

Table 10. Customized LEDs

Speed LINK ACT/Full

Link 10M Link 100M Link 1000M

LED 0 Bit 0 Bit 1 Bit 2 Bit 3

LED 1 Bit 4 Bit 5 Bit 6 Bit 7

LED 2 Bit 8 Bit 9 Bit 10 Bit 11

Feature Control Bit 12 Bit 13 Bit 14 Bit 15

Note: There are two special modes: LED OFF Mode: Set all bits to 0. All LED pin output become floating (power saving). Fixed LED Mode: Set Option 1 LED table Mode: LED0=LED1=LED2=1 or 2 (see Table 11).

Table 11. Fixed LED Mode

Bit31~Bit0 V alue LED0 LED1 LED2

1XXX 0001 0001 0001 ACT LINK Full Duplex + Collision

1XXX 0010 0010 0010 Transmit LINK Receive

Note: ‘X’ indicates ‘irrelevant’.

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RTL8111H/RTL8111HS

Table 12. LED Feature Control-1

Feature Control Bit12 Bit13 Bit14 Bit15

0 LED0 Low Active LED1 Low Active LED2 Low Active

Indicates Option 1 of Table 14

is Selected

1 LED0 High Active LED1 High Active LED2 High Active

Indicates Option 2 of Table 14

is Selected

Table 13. LED Feature Control-2

LED Pin ACT=0 ACT=1

LINK=0 Floating All Speed ACT

LINK>0 Selected Speed LINK Option 1 (see Table 14): Selected Speed LINK+ Selected Speed ACT

Option 2 (see Table 14): Selected Speed LINK+ All Speed ACT

Table 14. LED Option 1 & Option 2 Settings

Link Bit Active Bit Description

10 100 1000 Link

0 0 0 0 LED Off

0 0 0 1 - Act10+Act

0 0 1 0 Link

0 0 1 1 Link

0 1 0 0 Link

0 1 0 1 Link

0 1 1 0 Link

0 1 1 1 Link

- -

1000

Act

1000

- -

100

Act

100

+Link

- -

1000

Act

1000

1 0 0 0 Link10 - -

1 0 0 1 Link10 Act10 Act10+Act

1 0 1 0 Link10+Link

1 0 1 1 Link10+Link

1 1 0 0 Link10+Link

1 1 0 1 Link10+Link

1 1 1 0 Link10+Link

1 1 1 1 Link10+Link

100

- -

1000

Act10+Act

1000

- -

100

Act10+Act

100

+Link

1000

+Link

1000

Note: Act10 = LED blinking when Ethernet packets transmitted/rec eived at 10Mb ps. Act

= LED blinking when Ethernet packets transmitted/received at 100Mbps.

100

Act

= LED blinking when Ethernet packets transmitted/received at 1000Mbps.

1000

Link10 = LED lit when Ethernet connection established at 10Mbps. Link

= LED lit when Ethernet connection established at 100Mbps.

100

Link

= LED lit when Ethernet connection established at 1000Mbps.

1000

Option 1 LED

Activity

100

1000

100

+Act

Act10+Act

1000

Act10+Act

1000

Act10+Act

1000

Act10+Act

100

- -

Act10+Act

100

+Act

Act10+Act

1000

Datasheet

Option 2 LED

Activity

+Act

100

+Act

100

+Act

100

+Act

100

+Act

100

+Act

100

+Act

100

+Act

100

1000

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7.2.1. LED Blinking Frequency Contr ol

The RTL8111H/RTL8111HS supports LED blinking frequency control via IO register offset 1Ah to control user’s LED blinking frequency and duty cycle (see Table 15). If the IO offset 0x1A is 0x0B (00001011b), the LED blinking frequency is 80ms and the duty cycle is 75%. The LED State is shown in Figure 4.

Table 15. LED Blinking Frequency Control (IO Offset 1Ah)

Bit RW Description

3:2 RW LED Blinking Frequency.

0: 240ms 1: 160ms (default) 2: 80ms 3: Link Speed Dependent

1:0 RW LED Blinking Duty Cycle.

0: 12.5% 1: 25% 2: 50% (default) 3: 75%

Figure 4. LED Blinking Frequency Example

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7.3. PHY Transceiver

7.3.1. PHY Transmitter

Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the RTL8111H/RTL8111HS operates at 10/100/500/1000Mbps over standard CAT.5 UTP cable (100/1000Mbps), 2-pair CAT.5 UTP cable (100/500Mbps), or CAT.3 UTP cable (10Mbps).

GMII (1000Mbps) Mode

The RTL8111H/RTL8111HS’s PCS layer receives data bytes from the MAC through the GMII interface and performs the generation of continuous code-groups through 4D-PAM5 coding technology. These code groups are passed through a waveform-shaping filter to minimize EMI effects, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a D/A converter.

MII (100Mbps) Mode

The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to 125MHz NRZ and NRZI signals. The NRZI signals are passed to the MLT3 encoder, then to the D/A converter and transmitted onto the media.

MII (10Mbps) Mode

The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. The 10Mbps serial data is converted into a Manchester-encoded data stream and is transmitted onto the media by the D/A converter.

7.3.2. PHY Receiver

GMII (1000Mbps) Mode

Input signals from the media pass through the sophisticated on-chip hybrid circuit to separate the transmitted signal from the input signal for effective reduction of near-end echo. The received signal is processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander) correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5 decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz. The RX MAC retrieves the packet data from the receive MII/GMII interface and sends it to the RX Buffer Manager.

MII (100Mbps) Mode

The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII interface in 4-bit-wide nibbles at a clock speed of 25MHz.

MII (10Mbps) Mode

The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is processed with a Manchester decoder and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz.

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7.3.3. Link Down Power Saving Mode

The RTL8111H/RTL8111HS implements link-down power saving; greatly cutting power consumption when the network cable is disconnected. The RTL8111H/RTL8111HS automatically enters link down power saving mode ten seconds after the cable is disconnected from it. Once it enters link down power saving mode, it transmits normal link pulses on its TX pins and continues to monitor the RX pins to detect incoming signals. After it detects an incoming signal, it wakes up from link down power saving mode and operates in normal mode according to the result of the connection.

7.3.4. Next Page

If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the two link partners. Users can set PHY Reg4.15 to 1 to manually exchange extra Next Pages via Reg7 and Reg8 as defined in IEEE 802.3ab.

7.4. Power Management

The RTL8111H/RTL8111HS complies with ACPI (Rev 1.0, 1.0b, 2.0, 3.0), PCI Power Management (Rev

1.1), PCI Express Active State Power Management (ASPM), and Network Device Class Power Management Reference Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment.

The RTL8111H/RTL8111HS can monitor the network for a Wake-Up Frame or a Magic Packet, and notify the system via a PCI Express Power Management Event (PME) Message, Beacon, or the LANWAKEB pin when such a packet or event occurs. The system can then be restored to a normal state to process incoming jobs.

When the RTL8111H/RTL8111HS is in power down mode (D1~D3):

• The RX state machine is stopped. The RTL8111H/RTL8111HS monitors the network for Wake-Up

events such as a Magic Packet and Wake-Up Frame in order to wake up the system. When in power down mode, the RTL8111H/RTL8111HS will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the RX on-chip buffer.

• The on-chip buffer status and packets that have already been received into the RX on-chip buffer

before entering power down mode are held by the RTL8111H/RTL8111HS.

• Transmission is stopped. PCI Express transactions are stopped. The TX on-chip buffer is held.

• After being restored to D0 state, the RTL8111H/RTL8111HS transmits data that was not moved into

the TX on-chip buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted.

The D3 configuration space depend on the existence of Aux power. If aux. power is absent, the above 4 bits are all 0 in binary.

_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI

cold

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Magic Packet Wake-Up occurs only when the following conditions are met:

• The destination address of the received Magic Packet is acceptable to the RTL8111H/RTL8111HS,

e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8111H/RTL8111HS.

• The received Magic Packet does not contain a CRC error.

• The RTL8111H/RTL8111HS driver has set up the needed registers (automatically set), and the

corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state.

• The Magic Packet pattern matches, i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID)

in any part of a valid Ethernet packet.

A Wake-Up Frame event occurs only when the following conditions are met:

• The destination address of the received Wake-Up Frame is acceptable to the RTL8111H/RTL8111HS,

e.g., a broadcast, multicast, or unicast address to the current RTL8111H/RTL8111HS.

• The received Wake-Up Frame does not contain a CRC error.

Datasheet

• The RTL8111H/RTL8111HS driver has set up the needed registers (automatically set).

• The 16-bit CRC of the received Wake-Up Frame matches the 16-bit CRC of the sample Wake-Up

Frame pattern given by the local machine’s OS. Or, the RTL8111H/RTL8111HS is configured to allow direct packet wake-up, e.g., a broadcast, multicast, or unicast network packet.

• The 128 bytes of the received Wake-Up Frame exactly matches the 128 bytes of the sample Wake-Up

Frame pattern given by the local machine’s OS.

Note 1: 16-bit CRC: The RTL8111H/RTL8111HS supports 32-set 16-bit CRC Wake-Up Frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). CRC16 polynomial=x16+x12+x5+1.

Note 2: 128-byte Wake-Up Frame: The RTL8111H/RTL8111HS supports 32-set 128-byte Wake-Up Frames. If enabled, the 16-bit CRC Wake-Up match will be disabled.

The corresponding wake-up method (message or LANWAKEB) is asserted only when the following conditions are met:

• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.

• The RTL8111H/RTL8111HS may assert the corresponding wake-up method (message or

LANWAKEB) in the current power state or in isolation state, depending on the PME_Support (bit15~11) setting of the PMC register in PCI Configuration Space.

• A Magic Packet, LinkUp, or Wake-Up Frame has been received.

• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears

this bit and causes the RTL8111H/RTL8111HS to stop asserting the corresponding wake-up method (message or LANWAKEB) (if enabled).

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When the RTL8111H/RTL8111HS is in power down mode, e.g., D1~D3, the IO, and MEM accesses to the RTL8111H/RTL8111HS are disabled. After a PERSTB assertion, the device’s power state is restored to D0 automatically if the original power state was D3 device’s power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting). The setting may be changed from the eFUSE, if required.

. There is almost no hardware delay at the

cold

Datasheet

7.5. Receive-Side Scaling (RSS)

The RTL8111H/RTL8111HS complies with the Network Driver Interface Specification (NDIS) 6.0 Receive-Side Scaling (RSS) technology for the Microsoft Windows family of operating systems. RSS allows packet receive-processing from a network adapter to be balanced across the number of available computer processors, increasing performance on multi-CPU platforms.

7.5.1. Receive-Side Scaling (RSS) Initialization

During RSS initialization, the Windows operating system will inform the RTL8111H/RTL8111HS that it should store the following parameters: hash function, hash type, hash bits, indirection table, BaseCPUNumber, and the secret hash key.

Hash Function

The default hash function is the Toeplitz hash function.

Hash Type

The hash types indicate which field of the packet needs to be hashed to get the hash result. There are several combinations of these fields, mainly, TCP/IPv4, IPv4, TCP/IPv6, IPv6, and IPv6 extension headers.

• TCP/IPv4 requires hash calculations over the IPv4 source address, the IPv4 destination address, the

source TCP port and the destination TCP port.

• IPv4 requires hash calculations over the IPv4 source address and the IPv4 destination address.

• TCP/IPv6 requires hash calculations over the IPv6 source address, the IPv6 destination address, the

source TCP port and the destination TCP port.

• IPv6 requires hash calculations over the IPv6 source address and the IPv6 destination address

(Note: The RTL8111H/RTL8111HS does not support the IPv6 extension header hash type in RSS).

Hash Bits

Hash bits are used to index the hash result into the indirection table

Indirection Table

The Indirection Table stores values that are added to the BaseCPUNumber to enable RSS interrupts to be restricted from some CPUs. The OS will update the Indirection Table to rebalance the load.

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BaseCPUNumber

The lowest number CPU to use for RSS. BaseCPUNumber is added to the result of the indirection table lookup.

Secret Hash Key

The key used in the Toeplitz function. For different hash types, the key size is different.

Datasheet

7.5.2. Protocol Offload

Protocol offload is a task offload supported by Microsoft Windows 7. It maintains a network presence for a sleeping higher power host. Protocol offload prevents spurious wake-up and further reduces power consumption. It maintains connectivity while hosts are asleep, including receiving requests from other nodes on the network, ignoring packets, generating packets while in the sleep state (e.g., the Ethernet Controller will generate ARP responses if the same MAC and IPv4 address are provided in the configuration data), and intelligently waking up host systems. The RTL8111H/RTL8111HS supports the ECMA (European Computer Manufacturers Association) specification including proxy configuration and management, IPv4 ARP, IPv6 NDP, and wake-up packets. The RTL8111H/RTL8111HS also supports optional ECMA items such as QoS tagged packets and duplicate address detection.

7.5.3. RSS Operation

After the parameters are set, the RTL8111H/RTL8111HS will start hash calculations on each incoming packet and forward each packet to its correct queue according to the hash result. If the incoming packet is not in the hash type, it will be forwarded to the primary queue. The hash result plus the BaseCPUNumber will be indexed into the indirection table to get the correct CPU number. The RTL8111H/RTL8111HS uses three methods to inform the system of incoming packets: inline interrupt, MSI, and MSIX. Periodically the OS will update the indirection table to rebalance the load across the CPUs.

7.6. Energy Efficient Ethernet (EEE)

The RTL8111H/RTL8111HS supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet (EEE), at 10Mbps, 100Mbps, 500Mbps, and 1000Mbps. It provides a protocol to coordinate transitions to/from a lower power consumption level (Low Power Idle mode) based on link utilization. When no packets are being transmitted, the system goes to Low Power Idle mode to save power. Once packets need to be transmitted, the system returns to normal mode, and does this without changing the link status and without dropping/corrupting frames.

To save power, when the system is in Low Power Idle mode most of the circuits are disabled, however, the transition time to/from Low Power Idle mode is kept small enough to be transparent to upper layer protocols and applications.

EEE also specifies a negotiation method to enable link partners to determine whether EEE is supported and to select the best set of parameters common to both devices.

Refer to http://www.ieee802.org/3/az/index.html for more details.

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7.7. PHY Disable Mode

The RTL8111H/RTL8111HS can power down the PHY using board-level control signals.

7.8. Latency Tolerance Reporting (LTR)

The RTL8111H/RTL8111HS supports PCIe 3.0 LTR (Latency Tolerance Reporting).

The LTR mechanism enables Endpoints to report service latency requirements for Memory Reads/Writes. The CPU utilizes LTR to determine transfers from low power (C7) to high power (C0) mode. See the PCIe 3.0 specification for details.

7.9. Wake Packet Indication (WPI)

The RTL8111H/RTL8111HS supports Microsoft Wake Packet Indication (WPI) to provide Wake-Up Frame information to the OS, e.g., PatternID, OriginalPacketSize, SavedPacketSize, SavedPacketOffset, etc. WPI helps prevent unwanted/unauthorized wake-up of a sleeping computer. Refer to the Microsoft Windows Hardware Certification Requirements for details.

Note: Wake Packet Indication (WPI) and Wake Packet Detection (WPD) are the same technology terms defined by Microsoft, which terms both means the NIC is required to capture at least the first 128 bytes of the packet causing the network wake and generate a status indication to the operating system.

7.10. ‘RealWoW!’ (Wake-On-WAN) Technology

The RTL8111H/RTL8111HS supports Realtek 'RealWoW!' technology that allows the RTL8111H/RTL8111HS to send keep alive packets to the Wake Server when the PC is in sleeping mode. Realtek 'RealWoW!' can pass wake-up packets through a NAT (Network Address Translation) device. This feature allows PCs to reduce power consumption by

remaining in low power sleeping state until needed.

Users can login into the Wake Server via the Internet to wake the selected sleeping PC. Registration of Account information to the Wake Server is required on first time use.

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7.11. L1.Off and L1.Snooze

The RTL8111H/RTL8111HS supports PCIe L1.Off and L1.Snooze power management features. L1+CLKREQ# stops (or provides) the REFCLK to a device by toggling the CLKREQB pin to enter L1.Off and L1.Snooze states (saving more power than L1+CLKREQ# only). Table 16 shows the PCIe Port Circuit On/Off states.

Table 16. L1.Off and L1.Snooze PCIe Port Circuit On/Off

State PLL Common Mode Keeper RX/TX

L1 On On Off/Idle

L1+CLKREQ# Off On Off/Idle

L1.Snooze Off On Off

L1.Off Off Off Off

7.12. Giga Lite (500M)

The RTL8111H/RTL8111HS supports Giga Lite (500M) mode that allows two link partners that both support 1000Base-T and Giga Lite mode to transmit at 500Mbps data rate if only two pairs (AB pairs) can be detected in the CAT.5 UTP cable. This feature is a Realtek proprietary feature and it conforms to the 802.3az-2010(EEE) specification.

7.13. XTAL-Less W ake-On-LAN

The RTL8111H/RTL8111HS supports board level design with an External 25MHz or 48MHz Clock Source instead of a Crystal.

The external clock source may stop generating the clock when in suspend mode (S3/S4/S5). To support the Wake-On-LAN function without an external clock source, the RTL8111H/RTL8111HS will automatically change its source clock from the external clock to an internal self-oscillating auxiliary clock when it enters suspend mode. Note that when in suspend mode, the auxiliary clock can establish only a 10Mbps link and does not support ARP/NS offload and ECMA ProxZzzy.

7.14. LAN Disable Mode

The RTL8111H/RTL8111HS supports ‘LAN Disable Mode’. This mode can use an external signal to control whether the NIC is enabled or disabled.

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8. Switching Regulator (RTL8111HS Only)

The RTL8111HS incorporates a state-of-the-art switching regulator that requires a well-designed PCB layout in order to achieve good power efficiency and lower the output voltage ripple and input overshoot. Note that the switching regulator 1.0V output pin (REGOUT) must be connected only to DVDD10 and AVDD10 (do not provide this power source to other devices).

9. LDO Regulator (RTL8111H Only)

The RTL8111H incorporates a linear Low-Dropout (LDO) regulator that features high power supply ripple rejection and low output noise. The RTL8111H embedded LDO regulator does not require power inductors on the PCB; only a 1.0V output capacitor between its 1.0V output and analog ground for phase compensation, which saves cost and PCB real estate.

The output capacitors (and bypass capacitors) should be placed as close as possible to the power pins (AVDD10 and DVDD10) for adequate filtering.

Note that with regard to voltage conversion efficiency, LDO is inferior to a switching regulator. This balance between cost, size, and efficiency should be taken into consideration when choosing the regulator type.

Note: The embedded LDO is designed for the RTL8111H internal use only. Do not provide this power source to other devices.

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10. Power Sequence

Rt1

Rt3

RTL8111H/RTL8111HS

Datasheet

3.3V

2.5~2.6V

1.0V (REGOUT)

Rt2

Figure 5. Power Sequence

Table 17. Power Sequence Parameters

Symbol Description Min Typical Max Units

Rt1 3.3V Rise Time. 0.5 - 100 ms

Rt2 3.3V Off Time. 50 - - ms

Rt3 1.0V (REGOUT) Settle Time. - - 15 ms

Note: See the following section for power sequence requirements.

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10.1. Power Sequence Parameters

The RTL8111H/RTL8111HS does not support fast 3.3V rising under normal circumstances. The 3.3V rise time must be controlled over 0.5ms.

Rise Time > 0.5ms

No action to take.

Rise Time 0.1ms~0.5ms

If the rise time is between 0.1ms and 0.5ms, the customer MUST ensure that there is at least three times as much margin for inrush current to the RTL8111H/RTL8111HS so as to be safely under the system’s

3.3V OCP threshold.

For example:

• Assume customer supply power rise time of the RTL8111H/RTL8111HS is 0.374ms

• The system 3.3V OCP is 9A

• The inrush current of other 3.3V devices is 5.64A

The inrush current to the RTL8111H/RTL8111HS must be less than 1.12A, otherwise an unanticipated system OCP may be triggered. It can be expressed in the following formula:

Inrush current to the RTL8111H/RTL8111HS < (System 3.3V OCP - inrush current of other 3.3V devices) / 3

Rise Time < 0.1ms

If the rise time is less than 0.1ms, there is risk of an unanticipated ESD trigger event, which may cause permanent damage to the RTL8111H/RTL8111HS.

If there is any action that involves consecutive ON/OFF toggling of the switching regulator source (3.3V), the design must make sure the OFF state of both the switching regulator source (3.3V) and output (1.0V) reach 0V, and the time period between the consecutive ON/OFF toggling action must be longer than 50ms.

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Datasheet

11. Characteristics

11.1. Absolute Maximum Ratings

WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise specified.

Table 18. Absolute Maximum Ratings

Symbol Description Minimum Maximum Unit

AVDD33 Supply Voltage 3.3V -0.3 3.6 V

AVDD10, DVDD10 Supply Voltage 1.0V -0.3 1.2 V

3.3V DCinput

3.3V DCoutput

1.0V DCinput

1.0V DCoutput

N/A Storage Temperature -55 +125

Note: Refer to the most updated schematic circuit for correct configuration.

Input Voltage Output Voltage

-0.3 3.6 V

-0.3 1.2 V

°C

11.2. Recommended Operating Conditions

Table 19. Recommended Operating Conditions

Description Pins Minimum Typical Maximum Unit

Supply Voltage VDD

Ambient Operating Temperature TA - 0 - 70

Maximum Junction Temperature - - - 125

Note: Refer to the most updated schematic circuit for correct configuration.

AVDD33 3.14 3.3 3.46 V

AVDD10, DVDD10 0.95 1.0 1.05 V

11.3. Electrostatic Discharge Performance

Table 20. Electrostatic Discharge Performance

Test Item Results

HBM ESD All Pins: |4KV|

MM ESD All Pins: |150V|

CDM ESD All Pins: |1KV|

Cable ESD*

Latch Up

Note: ‘All MDI pins’ means the ESD current is introduced to each MDI pin separately. ‘All pairs’ means the ESD current is introduced to the aggregated MDI pairs.

All MDI Pins: |8KV|

All Pairs: |16KV|

I/O Pins: 400mA Power Pins: 1.5xVDD

°C

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Datasheet

11.4. Crystal Requirements

Table 21. Crystal Requirements

Symbol Description/Condition Minimum Typical Maximum Unit

ref

Stability

ref

Tolerance

ref

Duty Cycle Reference Clock Input Duty Cycle 40 - 60 %

ref

Parallel Resonant Crystal Frequency Tolerance, Fundamental Mode, AT-Cut Type

Parallel Resonant Crystal Frequency Tolerance, Fundamental Mode, AT-Cut Type. T

=0°C~70°C

Parallel Resonant Crystal Frequency Tolerance, Fundamental Mode, AT-Cut Type. T

=25°C

ESR Equivalent Series Resistance - - 30 

Jitter Broadband Peak-to-Peak Jitter

Drive Level - - 0.3 mW

Note 1: The CLK source can come from other places in the system, but it must accord with the parameters above. Note 2: Broadband RMS=9ps; 25KHz to 25MHz RMS=3ps.

- 25 - MHz

-30 - +30 ppm

-50 - +50 ppm

- - 200 ps

11.5. Oscillator Requirements

Table 22. Oscillator Requirements

Parameter Condition Minimum Typical Maximum Unit

Frequency - - 25/48 - MHz

Frequency Stability

Frequency Tolerance

= 0°C~70°C

= 25°C

-30 - +30 ppm

-50 - +50 ppm

Duty Cycle - 40 - 60 %

Broadband Peak-to-Peak Jitter

- - - 200 ps

Vih - 1.4 - - V

Vil - - - 0.4 V

Rise Time

- - - 10 ns

Fall Time - - - 10 ns

Operation Temp Range -

0 - 70

°C

Note 1: The CLK source can come from other places in the system, but it must accord with the parameters above. Note 2: Broadband RMS=9ps; 25KHz to 48MHz RMS=3ps.

11.6. Environmental Characteristics

Table 23. Environmental Characteristics

Parameter Range Units

Storage Temperature -55 ~ +125

Ambient Operating Temperature 0 ~ 70

Moisture Sensitivity Level (MSL) Level 3 N/A

°C

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RTL8111H/RTL8111HS

Datasheet

11.7. DC Characteristics

Table 24. DC Characteristics

Symbol Parameter Conditions Minimum Typical Maximum Units

AVDD33

AVDD10, DVDD10

Voh

Vol

Vih

Vil

Icc33

Icc10

Isys33

Note 1: Refer to the latest schematic circuit for correct configuration. Note 2: All Supply Mean Voltage power noise <±5% of Mean Voltage. Note 3: The total operating current Isys33=Icc33 + (Icc10 / efficiency / 3.3), Where efficiency=0.75 for SWR-mode or efficiency=0.33 for LDO-mode.

3.3V Supply Mean Voltage

1.0V Supply Mean Voltage

Minimum High Level Output Voltage

Maximum Low Level Output Voltage

Minimum High Level Input Voltage for 3.3V &

1.8V compatible Pinout

Minimum High Level Input Voltage for 3.3V only Pinout

Maximum Low Level Input Voltage

Input Current Vin = VDD33 or GND 0 - 0.5 µA

Average Operating Supply Current from 3.3V (does NOT include 1.0V power consumption)

Average Operating Supply Current from 1.0V

Average Operating Supply Current for total system

3.3V (includes 1.0V power consumption)

At 1Gbps with heavy

- 3.14 3.3 3.46 V

- 0.95 1.0 1.05 V

= -4mA 0.9*VDD33 - VDD33 V

= 4mA 0 - 0.1*VDD33 V

- 1.57 - - V

- 2 - - V

- - - 0.8 V

network traffic

- 65 - mA

- 150 - mA

- Note3 - mA

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RTL8111H/RTL8111HS

11.8. Reflow Profile Recommendations

Table 25. Reflow Profile Recommendations

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Minimum Preheat Temperature (T

Maximum Preheat Temperature (T

Preheat Time (tS) from T

Ramp-Up Rate (TL to Tp) 3°C/second max. 3°C/second max.

Liquidus Temperature (TL)

Time (tL) Maintained above TL 60~150 seconds 60~150 seconds

Peak Package Body Temperature (Tp)

Time (tp)2 within 5°C of Peak TP 20 seconds 20 seconds

Ramp-Down Rate (Tp to TL) 6°C/second max. 6°C/second max.

Time 25°C to Peak Temperature (Tp) 6 minutes max. 8 minutes max.

Note 1: All temperatures refer to the topside of the package, measured on the package body surface. Note 2: Tolerance for Tp is defined as a supplier’s minimum and a user’ s maximum. Note 3: Reference document: IPC/JEDEC J-STD-020D.1.

smin

to T

)

smin

)

smax

60~120 seconds 60~120 seconds

smax

100°C 150°C

150°C 200°C

183°C 217°C

235°C 260°C

Datasheet

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Datasheet

11.9. PCI Express Bus Parameters

11.9.1. Differential Transmitter Parameters

Table 26. Differential Transmitter Parameters

Symbol Parameter Min Typical Max Units

TX-DIFFp-p

TX-DE-RATIO

TX-EYE

TX-EYE-MEDIAN-to-

MAX-JITTER

IDLEDELTA

, T

TX-RISE

TX-CM-ACp

TX-CM-DCACTIVE-

TX-FALL

TX-CM-DCLINE-DELTA

Unit Interval

Differential Peak-to-Peak Output Voltage 0.800 - 1.05 V

De-Emphasized Differential Output Voltage (Ratio) -3.0 -3.5 -4.0 dB

Minimum TX Eye Width 0.75 - - UI

Maximum Time between The Jitter Median and Maximum Deviation from The Median

D+/D- TX Output Rise/Fall Time 0.125 - - UI

RMS AC Peak Common Mode Output Voltage - - 20 mV

Absolute Delta of DC Common Mode Voltage During L0 and Electrical Idle

Absolute Delta of DC Common Mode Voltage between D+ and D-

TX-IDLE-DIFFp

TX-RCV-DETECT

Electrical Idle Differential Peak Output Voltage 0 - 20 mV

The Amount of Voltage Change Allowed During Receiver Detection

TX-DC-CM

TX-SHORT

TX-IDLE-MIN

TX-IDLE- SETTO-IDLE

The TX DC Common Mode Voltage 0 - 3.6 V

TX Short Circuit Current Limit - - 90 mA

Minimum Time Spent in Electrical Idle 50 - - UI

Maximum Time to Transition to A Valid Electrical Idle After Sending An Electrical Idle Ordered Set

TX-IDLE-TOTO-DIFF-

DATA

Maximum Time to Transition to Valid TX Specifications After Leaving An Electrical Idle Condition

TX-DIFF-DC

TX-SKEW

Differential Return Loss 10 - - dB

TX-DIFF

Common Mode Return Loss 6 - - dB

TX-CM

DC Differential TX Impedance 80 100 120 

Lane-to-Lane Output Skew - - 500+2*UI ps

CTX AC Coupling Capacitor 75 - 200 nF

Crosslink Random Timeout 0 - 1 ms

crosslink

Note 1: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter. Note 2: The data rate can be modulated with an SSC (Spread Spectrum Clock) from +0 to -0.5% of the nominal data rate

frequency, at a modulation rate in the range not exceeding 30kHz – 33kHz. The ±300ppm requirement still holds, which requires the two communicating ports be modulated such that they never exceed a total of 600ppm difference.

399.88 400 400.12 ps

- - 0.125 UI

0 - 100 mV

0 - 25 mV

- - 600 mV

- - 20 UI

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Datasheet

11.9.2. Differential Receiver Parameters

Table 27. Differential Receiver Parameters

Symbol Parameter Min. Typical Max. Units

UI Unit Interval 399.88 400 400.12 ps

RX-DIFFp-p

RX-EYE

RX-EYE-MEDIAN-to-

MAX-JITTER

RX-CM-ACp

RX-DIFF-DC

RX-DC

RX-HIGH-IMP-DC

RX-IDLE-DET-DIFFp-p

RX-IDLE-DET-

DIFFENTERTIME

RX-SKEW

Differential Return Loss 10 - - dB

RX-DIFF

RX-CM

DC Differential Input Impedance 80 100 120 

DC Input Impedance 40 50 60 

Total Skew - - 20 ns

Note: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.

Differential Input Peak-to-Peak Voltage 0.175 - 1.05 V

Minimum Receiver Eye Width 0.4 - - UI

Maximum Time Between The Jitter Median and

- - 0.3 UI

Maximum Deviation from The Median

AC Peak Common Mode Input Voltage - - 150 mV

Common Mode Return Loss 6 - - dB

Powered Down DC Input Impedance 200k - - 

Electrical Idle Detect Threshold 65 - 175 mV

Unexpected Electrical Idle Enter Detect Threshold

- - 10 ms

Integration Time

11.9.3. REFCLK Parameters

Table 28. REFCLK Parameters

Symbol Parameter 100MHz Input

Min Max

Rise Edge Rate Rising Edge Rate 0.6 4.0 V/ns 2, 3

Fall Edge Rate Falling Edge Rate 0.6 4.0 V/ns 2, 3

VIH Differential Input High Voltage +150 - mV 2

CROSS

CROSS DELTA

Differential Input Low Voltage - -150 mV 2

Absolute Crossing Point Voltage +250 +550 mV 1, 4, 5

Variation of V

Over All Rising Clock Edges - +140 mV 1, 4, 9

CROSS

VRB Ring-Back Voltage Margin -100 +100 mV 2, 12

STABLE

PERIOD AVG

PERIOD ABS

Average Clock Period Accuracy -300 +2800 ppm 2, 10, 13

Absolute Period

Time before V

is Allowed 500 - ps 2, 12

9.847 10.203 ns 2, 6

(Including Jitter and Spread Spectrum)

CCJITTER

Cycle to Cycle Jitter -

Absolute Maximum Input Voltage - +1.15 V 1, 7

MAX

Absolute Minimum Input Voltage -0.3 - V 1, 8

MIN

150

Units Note

ps 2

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RTL8111H/RTL8111HS

Datasheet

Symbol Parameter 100MHz Input

Min Max

Duty Cycle Duty Cycle 40 60 % 2

Rise-Fall Matching Rising Edge Rate (REFCLK+) to

Falling Edge Rate (REFCLK-) Matching

Clock Source DC Impedance 40 60  1, 11

C-DC

Note 1: Measurement taken from single-ended waveform. Note 2: Measurement taken from differential waveform. Note 3: Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The

signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement wi n dow is centered on the differential zero crossing. See Figure 9, page 32. Note 4: Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. See Figure 6, page 31. Note 5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Figure 6, page 31. Note 6: Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum modulation. See Figure 8, page 31. Note 7: Defined as the maximum instantaneous voltage including overshoot. See Figure 6, page 31.

Note 8: Defined as the minimum instantaneous voltage including undershoot. See Figure 6, page 31. Note 9: Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCRO SS for any parti c ular system. See Figure 6, page 31. Note 10: Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding ppm

considerations. Note 1 1 : System board compliance meas urements must use the test load card described in Figure 12, page 33. REFCLK+

and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load CL=2pF. Note 12: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to droop back into the VRB ±100mV differential range. See Figure 11, page 32. Note 13: PPM refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of

100.000000MHz exactly, or 100Hz. For 300ppm then we have an error budget of 100Hz/ppm*300ppm=30kHz. The period is to be measured with a frequency counter with measurement window set to 100ms or greater. The ±300ppm applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread Spectrum there is an additional 2500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2800ppm.

Note 14: Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 7, page 31.

Note 15: Refer to PCI Express Card Electromechanical Specification, rev.1.1, for correct measurement environment setting of each parameter.

- 20 % 1, 14

Units Note

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RTL8111H/RTL8111HS

Figure 6. Single-Ended Measurement Points for Absolute Cross Point and Swing

Datasheet

Figure 7. Single-Ended Measurement Points for Delta Cross Point

Figure 8. Single-Ended Measurement Points for Rise and Fall Time Matching

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RTL8111H/RTL8111HS

Figure 9. Differential Measurement Points for Duty Cycle and Period

Datasheet

Figure 10. Differential Measurement Points for Rise and Fall Time

Figure 11. Differential Measurement Points for Ringback

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RTL8111H/RTL8111HS

Figure 12. Reference Clock System Measurement Point and Loading

Datasheet

11.9.4. Auxiliary Signal Timing Parameters

Table 29. Auxiliary Signal Timing Parameters

Symbol Parameter Min Max Units

Power Stable to PERSTB Inactive 100 - ms

PVPERL

PERST-CLK

PERST

PERSTB-RTD

FAI L

PWRON

Note 1: T by more than 500 mV). Refer to PCI Local Bus Specification rev. 3.0 for further information. T when implementation and timing of T

Note 2: The ISOLATEB pin should follow the behavior of the 3.3V main power waveform.

REFCLK Stable before PERSTB Inactive 100 - µs

PERSTB Active Time 100 - µs

PERSTB Rising Time Duration 10 - ms

Power Level Invalid to PWRGD Inactive - 500 ns

3.3Vaux Power On Time (Refer to Section 10, Page 22) - - ms

means 500 ns (maximum) from the power rail going out of specification (exceeding the specified tolerances

FAIL

can be disregarded

will not affect any LAN functions.

FAIL

Figure 13. Auxiliary Signal Timing

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Page 39

12. Mechanical Dimensions

RTL8111H/RTL8111HS

Datasheet

Symbol Dimension in mm Dimension in inch

Min Nom Max Min Nom Max

A 0.80 0.85 0.90 0.031 0.033 0.035

A1 0.00 0.02 0.05 0.000 0.001 0.002

A2 - 0.65 0.70 - 0.026 0.028

A3 0.20 REF 0.008 REF

b 0.15 0.20 0.25 0.006 0.008 0.010

D/E 4.00 BSC 0.157 BSC

D2/E2 2.55 2.70 2.85 0.100 0.106 0.112

e 0.40 BSC 0.016 BSC

L 0.30 0.40 0.50 0.012 0.016 0.020

L1 0.282 0.382 0.482 0.011 0.015 0.019

Note 1: CONTROLLING DIMENSION: MILLIMETER (mm). Note 2: REFERENCE DOCUMENT: JEDEC MO-220.

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13. Ordering Information

Table 30. Ordering Information

Part Number Package Status

RTL8111HS-CG 32-Pin QFN ‘Green’ Package (Switching regulator) -

RTL8111H-CG 32-Pin QFN ‘Green’ Package (LDO regulator) -

Note: See page 5 for package identification information.

RTL8111H/RTL8111HS

Datasheet

Realtek Semiconductor Corp. Headquarters

No. 2, Innovation Road II Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com

Integrated 10/100/1000M Ethernet Controller for PCI Express 35 Track ID: JATR-8275-15 Rev. 1.2

Realtek RTL8111H-CG, RTL8111HS-CG DATASHEET

Specifications and Main Features

Frequently Asked Questions

User Manual