Realtek ALC662-GR, ALC662-VCO-GR, ALC662-VC1-GR, ALC662 Datasheet

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ALC662 Series (ALC662-GR, ALC662-VC0-GR, ALC662-VC1-GR)

5.1 CHANNEL HIGH DEFINITION AUDIO CODEC

DATASHEET

Rev. 1.3

03 July 2009

Track ID: JATR-1076-21

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan

Tel.: +886-3-578-0211. Fax: +886-3-577-6047

www.realtek.com

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ALC662 Series

©2009 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.

Datasheet

USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek ALC662 codec IC.

Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.

REVISION HISTORY

Revision Release Date Summary

1.0 2007/01/15 First release for ALC662.

1.1 2008/03/15 Added ALC662-VC (ALC662 C version) data. Update passband ripple information in Table 82, page 64.

1.2 2008/12/02

1.3 2009/07/03 Added ALC662-VC1-GR part number information.

Correct General Description and Software Features sections. The ALC662 supports Dolby Digital Live (Dolby Home Theater is not supported).

ALC662-VC part number corrected to ALC662-VC0-GR.

Revised Table 85, page 66.

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ALC662 Series

Datasheet

Table of Contents

1. GENERAL DESCRIPTION..............................................................................................................................................1

2. FEATURES.........................................................................................................................................................................2

2.1. HARDWARE FEATURES ................................................................................................................................................2

2.2. SOFTWARE FEATURES..................................................................................................................................................3

2.3. ALC662-VC SERIES UPGRADED FEATURES FOR FUTURE WLP ..................................................................................4

3. SYSTEM APPLICATIONS...............................................................................................................................................4

4. BLOCK DIAGRAM...........................................................................................................................................................5

5. PIN ASSIGNMENTS .........................................................................................................................................................6

5.1. PACKAGE AND VERSION IDENTIFICATION ....................................................................................................................6

6. PIN DESCRIPTIONS.........................................................................................................................................................7

6.1. DIGITAL I/O PINS .........................................................................................................................................................7

6.2. ANALOG I/O PINS ........................................................................................................................................................7

6.3. FILTER/REFERENCE......................................................................................................................................................8

6.4. POWER/GROUND..........................................................................................................................................................8

6.5. NC (NOT CONNECTED) PINS ........................................................................................................................................8

7. HIGH DEFINITION AUDIO LINK PROTOCOL .........................................................................................................9

7.1. LINK SIGNALS ..............................................................................................................................................................9

7.1.1. Signal Definitions .................................................................................................................................................10

7.1.2. Signaling Topology...............................................................................................................................................11

7.2. FRAME COMPOSITION ................................................................................................................................................12

7.2.1. Outbound Frame – Single SDO............................................................................................................................12

7.2.2. Outbound Frame – Multiple SDOs.......................................................................................................................13

7.2.3. Inbound Frame – Single SDI................................................................................................................................14

7.2.4. Inbound Frame – Multiple SDIs...........................................................................................................................15

7.2.5. Variable Sample Rates .........................................................................................................................................15

7.3. RESET AND INITIALIZATION .......................................................................................................................................18

7.3.1. Link Reset .............................................................................................................................................................18

7.3.2. Codec Reset ..........................................................................................................................................................19

7.3.3. Codec Initialization Sequence ..............................................................................................................................20

7.4. VERB AND RESPONSE FORMAT ..................................................................................................................................20

7.4.1. Command Verb Format........................................................................................................................................20

7.4.2. Response Format..................................................................................................................................................23

7.5. POWER MANAGEMENT...............................................................................................................................................23

7.5.1. System Power State Definitions............................................................................................................................23

7.5.2. Power Controls in NID 01h..................................................................................................................................24

7.5.3. Powered Down Conditions...................................................................................................................................24

8. SUPPORTED VERBS AND PARAMETERS................................................................................................................25

8.1. VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................25

8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)............................................................................25

8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)..........................................................................25

8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h).....................................................26

8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) ..........................................................26

8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) ...............................................26

8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ..................................................27

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ALC662 Series

8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ................................................28

8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) .................................................29

8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..................................................................29

8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) ..........................30

8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ........................30

8.1.12. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) .......................................................31

8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .................................................31

8.1.14. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)..................................................31

8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)..........................................................32

8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)..............................................32

8.2. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ................................................................................33

8.3. VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................33

8.4. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................34

8.5. VERB – GET PROCESSING STATE (VERB ID=F03H) ...................................................................................................37

8.6. VERB – SET PROCESSING STATE (VERB ID=703H) ....................................................................................................38

8.7. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................38

8.8. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................38

8.9. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................39

8.10. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................39

8.11. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................40

8.12. VERB – SET AMPLIFIER GAIN (VERB ID=3H) ............................................................................................................43

8.13. VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................44

8.14. GET CONVERTER FORMAT SUPPORT ..........................................................................................................................44

8.15. VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................45

8.16. VERB – GET POWER STATE (VERB ID=F05H)............................................................................................................46

8.17. VERB – SET POWER STATE (VERB ID=705H).............................................................................................................46

8.18. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................47

8.19. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ................................................................................47

8.20. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................48

8.21. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................49

8.22. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................50

8.23. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................50

8.24. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................51

8.25. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................51

8.26. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH/F1DH/F1EH/F1FH).........................................................52

8.27. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 52

8.28. VERB – GET BEEP GENERATOR (VERB ID=F0AH) ...................................................................................................53

8.29. VERB – SET BEEP GENERATOR (VERB ID=70AH)....................................................................................................53

8.30. VERB – GET GPIO DATA (VERB ID= F15H) ..............................................................................................................54

8.31. VERB – SET GPIO DATA (VERB ID= 715H)...............................................................................................................54

8.32. VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................55

8.33. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................55

8.34. VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................56

8.35. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................56

8.36. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) .........................................................57

8.37. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................57

8.38. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH)..........................................58

8.39. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH)............................................59

8.40. VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/D22H/F23H) ..................................................................60

8.41. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR

[7:0])..........................................................................................................................................................................60

8.42. VERB – GET EAPD CONTROL (VERB ID=F0CH).......................................................................................................61

8.43. VERB – SET EAPD CONTROL (VERB ID=70CH)........................................................................................................61

8.44. VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................62

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ALC662 Series

9. ELECTRICAL CHARACTERISTICS ..........................................................................................................................63

9.1. DC CHARACTERISTICS...............................................................................................................................................63

9.1.1. Absolute Maximum Ratings..................................................................................................................................63

9.1.2. Threshold Voltage ................................................................................................................................................63

9.1.3. Digital Filter Characteristics ...............................................................................................................................64

9.1.4. SPDIF Output Characteristics .............................................................................................................................64

9.2. AC CHARACTERISTICS...............................................................................................................................................65

9.2.1. Link Reset and Initialization Timing ....................................................................................................................65

9.2.2. Link Timing Parameters at the Codec..................................................................................................................66

9.2.3. SPDIF Output Timing...........................................................................................................................................67

9.2.4. Test Mode .............................................................................................................................................................67

9.3. ANALOG PERFORMANCE ............................................................................................................................................68

10. APPLICATION CIRCUITS .......................................................................................................................................69

10.1. FILTER CONNECTION .................................................................................................................................................69

10.2. ONBOARD FRONT PANEL HEADER CONNECTION AND FRONT PANEL I/O ..................................................................70

10.3. ANALOG INPUT/OUTPUT CONNECTION ......................................................................................................................71

10.4. OPTIONAL SPDIF OUTPUT.........................................................................................................................................71

11. MECHANICAL DIMENSIONS.................................................................................................................................72

11.1. MECHANICAL DIMENSIONS NOTES ............................................................................................................................73

Datasheet

12. ORDERING INFORMATION...................................................................................................................................74

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ALC662 Series

Datasheet

List of Tables

TABLE 1. DIGITAL I/O PINS.........................................................................................................................................................7

TABLE 2. ANALOG I/O PINS ........................................................................................................................................................7

TABLE 3. FILTER/REFERENCE .....................................................................................................................................................8

TABLE 4. POWER/GROUND..........................................................................................................................................................8

TABLE 5. NOT CONNECTED PINS.................................................................................................................................................8

TABLE 6. LINK RESET# ...........................................................................................................................................................10

TABLE 7. HDA SIGNAL DEFINITIONS........................................................................................................................................10

TABLE 8. DEFINED SAMPLE RATE AND TRANSMISSION RATE...................................................................................................16

TABLE 9. 48KHZ VARIABLE RATE OF DELIVERY TIMING .........................................................................................................16

TABLE 10. 44.1KHZ VARIABLE RATE OF DELIVERY TIMING ......................................................................................................17

TABLE 11. 40-BIT COMMANDS IN 4-BIT VERB FORMAT.............................................................................................................20

TABLE 12. 40-BIT COMMANDS IN 12-BIT VERB FORMAT...........................................................................................................20

TABLE 13. SUPPORTED COMMANDS ...........................................................................................................................................21

TABLE 14. SUPPORTED PARAMETERS .........................................................................................................................................22

TABLE 15. SOLICITED RESPONSE FORMAT .................................................................................................................................23

TABLE 16. UNSOLICITED RESPONSE FORMAT .............................................................................................................................23

TABLE 17. SYSTEM POWER STATE DEFINITIONS ........................................................................................................................23

TABLE 18. POWER CONTROLS IN NID 01H .................................................................................................................................24

TABLE 19. POWERED DOWN CONDITIONS ..................................................................................................................................24

TABLE 20. VERB – GET PARAMETERS (VERB ID=F00H) ............................................................................................................25

TABLE 21. PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H).........................................................................25

TABLE 22. PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H) .......................................................................25

TABLE 23. PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H) ..............................................26

TABLE 24. PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H)......................................................26

TABLE 25. PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H).........................................26

TABLE 26. PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H) ............................................27

TABLE 27. PARAMETER – SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH)...........................................28

TABLE 28. PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH) ..........................................29

TABLE 29. PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH)...............................................................29

TABLE 30. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH) ......................30

TABLE 31. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H)....................30

TABLE 32. PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH)......................................................31

TABLE 33. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH)................................................31

TABLE 34. PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H) .................................................31

TABLE 35. PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H)............................................................32

TABLE 36. PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H) ............................................32

TABLE 37. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ...............................................................................33

TABLE 38. VERB – SET CONNECTION SELECT (VERB ID=701H).................................................................................................33

TABLE 39. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H).........................................................................................34

TABLE 40. VERB – GET PROCESSING STATE (VERB ID=F03H)...................................................................................................37

TABLE 41. VERB – SET PROCESSING STATE (VERB ID=703H)....................................................................................................38

TABLE 42. VERB – GET COEFFICIENT INDEX (VERB ID=DH) .....................................................................................................38

TABLE 43. VERB – SET COEFFICIENT INDEX (VERB ID=5H).......................................................................................................38

TABLE 44. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH)............................................................................................39

TABLE 45. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H) .............................................................................................39

TABLE 46. VERB – GET AMPLIFIER GAIN (VERB ID=BH)...........................................................................................................40

TABLE 47. VERB – SET AMPLIFIER GAIN (VERB ID=3H)............................................................................................................43

TABLE 48. VERB – GET CONVERTER FORMAT (VERB ID=AH) ...................................................................................................44

TABLE 49. GET CONVERTER FORMAT SUPPORT .........................................................................................................................44

TABLE 50. VERB – SET CONVERTER FORMAT (VERB ID=2H).....................................................................................................45

TABLE 51. VERB – GET POWER STATE (VERB ID=F05H)...........................................................................................................46

TABLE 52. VERB – SET POWER STATE (VERB ID=705H)............................................................................................................46

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ALC662 Series

TABLE 53. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H)...............................................................................47

TABLE 54. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ...............................................................................47

TABLE 55. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H)..............................................................................................48

TABLE 56. VERB – SET PIN WIDGET CONTROL (VERB ID=707H)...............................................................................................49

TABLE 57. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H)...........................................................................50

TABLE 58. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ...........................................................................50

TABLE 59. VERB – GET PIN SENSE (VERB ID=F09H) .................................................................................................................51

TABLE 60. VERB – EXECUTE PIN SENSE (VERB ID=709H) .........................................................................................................51

TABLE 61. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH/F1DH/F1EH/F1FH) ........................................................52

TABLE 62. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)

..................................................................................................................................................................................52

TABLE 63. VERB – GET BEEP GENERATOR (VERB ID= F0AH)..................................................................................................53

TABLE 64. VERB – SET BEEP GENERATOR (VERB ID= 70AH)...................................................................................................53

TABLE 65. VERB – GET GPIO DATA (VERB ID= F15H) .............................................................................................................54

TABLE 66. VERB – SET GPIO DATA (VERB ID= 715H) ..............................................................................................................54

TABLE 67. VERB – GET GPIO ENABLE MASK (VERB ID= F16H) ...............................................................................................55

TABLE 68. VERB – SET GPIO ENABLE MASK (VERB ID=716H).................................................................................................55

TABLE 69. VERB – GET GPIO DIRECTION (VERB ID=F17H)......................................................................................................56

TABLE 70. VERB – SET GPIO DIRECTION (VERB ID=717H).......................................................................................................56

TABLE 71. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ........................................................57

TABLE 72. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) .........................................................57

TABLE 73. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) .........................................58

TABLE 74. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ...........................................59

TABLE 75. VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H) ..................................................................60

TABLE 76. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR

[7:0]) .........................................................................................................................................................................60

TABLE 77. VERB – GET EAPD CONTROL (VERB ID=F0CH) ......................................................................................................61

TABLE 78. VERB – SET EAPD CONTROL (VERB ID=70CH) .......................................................................................................61

TABLE 79. VERB – FUNCTION RESET (VERB ID=7FFH) .............................................................................................................62

TABLE 80. ABSOLUTE MAXIMUM RATINGS................................................................................................................................63

TABLE 81. THRESHOLD VOLTAGE ..............................................................................................................................................63

TABLE 82. DIGITAL FILTER CHARACTERISTICS ..........................................................................................................................64

TABLE 83. SPDIF OUTPUT CHARACTERISTICS ...........................................................................................................................64

TABLE 84. LINK RESET AND INITIALIZATION TIMING .................................................................................................................65

TABLE 85. LINK TIMING PARAMETERS AT THE CODEC ...............................................................................................................66

TABLE 86. SPDIF OUTPUT TIMING.............................................................................................................................................67

TABLE 87. ANALOG PERFORMANCE ...........................................................................................................................................68

TABLE 88. ORDERING INFORMATION..........................................................................................................................................74

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Datasheet

List of Figures

FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................5

FIGURE 2. PIN ASSIGNMENTS ......................................................................................................................................................6

FIGURE 3. HDA LINK PROTOCOL................................................................................................................................................9

FIGURE 4. BIT TIMING...............................................................................................................................................................10

FIGURE 5. SIGNALING TOPOLOGY .............................................................................................................................................11

FIGURE 6. SDO OUTBOUND FRAME ..........................................................................................................................................12

FIGURE 7. SDO STREAM TAG IS INDICATED IN SYNC..............................................................................................................12

FIGURE 8. STRIPED STREAM ON MULTIPLE SDOS.....................................................................................................................13

FIGURE 9. SDI INBOUND STREAM .............................................................................................................................................14

FIGURE 10. SDI STREAM TAG AND DATA ..................................................................................................................................14

FIGURE 11. CODEC TRANSMITS DATA OVER MULTIPLE SDIS ....................................................................................................15

FIGURE 12. LINK RESET TIMING.................................................................................................................................................19

FIGURE 13. CODEC INITIALIZATION SEQUENCE ..........................................................................................................................20

FIGURE 14. LINK RESET AND INITIALIZATION TIMING................................................................................................................65

FIGURE 15. LINK SIGNAL TIMING ...............................................................................................................................................66

FIGURE 16. OUTPUT TIMING .......................................................................................................................................................67

FIGURE 17. FILTER CONNECTION................................................................................................................................................69

FIGURE 18. ONBOARD FRONT PANEL HEADER CONNECTION AND FRONT PANEL I/O ................................................................70

FIGURE 19. ANALOG INPUT/OUTPUT CONNECTION ....................................................................................................................71

FIGURE 20. OPTIONAL SPDIF OUTPUT .......................................................................................................................................71

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ALC662 Series

Datasheet

1. General Description

ALC662 products are 5.1 Channel High Definition Audio Codecs designed for Windows Vista premium desktop and mobile PCs. The ALC662, ALC662-VC0, and ALC662-VC1 (ALC662 version C series) meet audio performance and function requirements for the latest Microsoft WLP3.10 (Windows Logo Program).

The ALC662-VC series (ALC662-VC0 and ALC662-VC1) are upgraded versions of the ALC662 that pass stricter WLP performance requirements (See section 2.3 ALC662-VC Series Upgraded Features for Future WLP, page 4).

The ALC662 series feature three stereo DACs, two stereo ADCs, and legacy analog input to analog output mixing, to provide fully integrated audio solutions for multimedia PCs and ultra mobile devices.

All analog IO (except CD-IN and PCBEEP) are input and output capable, and three headphone amplifiers are also integrated to drive earphones on front (port-E and port-F) and rear panel (port-D).

The ALC662 series support 16/20/24-bit SPDIF output function and a sampling rate of up to 96kHz. They offer easy connection of PCs to high quality consumer electronic products such as digital decoders and speakers.

The ALC662 series support host audio from Intel chipsets, and also from any other HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2 compatibility, software utilities like Karaoke mode, environment emulation, multi-band software equalizer, 3D positional audio, and optional Dolby® Digital Live and DTS® CONNECT™ programs, the ALC662 series provide an excellent home entertainment package and game experience for PC users.

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ALC662 Series

Datasheet

2. Features

2.1.

Hardware Features

 Meets premium audio requirements for Microsoft WLP 3.10 (ALC662 and ALC662-VC series)

 Meets stricter performance requirements for future WLP (ALC662-VC series)

 Six-channel DAC supports 16/20/24-bit PCM format for 5.1 channel audio solution

 Two stereo ADCs support 16/20-bit PCM format

 All DACs support independent 44.1k/48k/96kHz sample rate

 All ADCs support independent 44.1k/48k/96kHz sample rate

 Supports 44.1k/48k/96kHz SPDIF output

 All analog jack ports are stereo input and output re-tasking

 Analog differential CD input

 Supports analog PCBEEP input

 Integrates digital BEEP generator

 Up to four channels of microphone array input are supported for AEC/BF application

 Supports legacy analog input to analog output mixer

 Three built-in headphone amplifiers for port-D (rear panel), port-E and port-F (front panel)

 Software selectable 2.5V and 3.2V reference output for microphone bias

 Software selectable boost gain (+10/+20/+30dB) for analog microphone input

 Two jack detection pins: each supports detection of up to 4 jacks

 Jack detection function is supported when device is in power down mode (D3)

 Supports two GPIO pins (General Purpose Input Output)

 Supports EAPD (External Amplifier Power Down) control for external amplifier

 Supports 1.5V~3.3V scalable I/O for HD Audio link

 Supports anti-pop mode when analog power AVDD is on and digital power is off

 48-pin LQFP ‘Green’ package

 The ALC662-VC series is fully pin compatible with the ALC662, and both are pin-to-pin compatible

with the ALC88x series and ALC262 series audio codecs

5.1 Channel High Definition Audio Codec 2 Track ID: JATR-1076-21 Rev. 1.3

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2.2.

Software Features

 Meets Microsoft WLP 3.10 and future WLP audio requirements

 WaveRT based audio function driver and logo ready for Windows Vista

 EAX™ 1.0 & 2.0 compatible

 Direct Sound 3D™ compatible

 I3DL2 compatible (Windows XP only)

 3D Positional Audio

 Emulation of 26 sound environments to enhance gaming experience

 Multi-band software equalizer and software tools are provided

 Voice Cancellation and Key Shifting effects

ALC662 Series

Datasheet

 Dynamic range control (expander, compressor, and limiter) with adjustable parameters

 Intuitive Configuration Panel (Realtek Audio Manager) for enhanced audio experience

 Provides 10-foot GUI for Windows Media Center

 Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)

technology for voice application

 Smart multiple streaming operation

 Dolby

 DTS

 SRS® TruSurround HD (optional software feature)

Digital Live (optional software feature)

CONNECT™ (optional software feature)

5.1 Channel High Definition Audio Codec 3 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

2.3.

ALC662-VC Series Upgraded Features for Future WLP

 DAC and ADC keep good THD+N when tested with –1dB test signal (-3dB in WLP3.10)

 DAC and ADC have less than ±0.02dB frequency response ripple (<±0.25dB in WLP3.10)

 Meets performance measurement when sweeping 44.1kHz sample rate content across 20Hz to

20KHz (20Hz to 17.6KHz in WLP3.10)

 The ALC662-VC1 improves anti-pop functions and reduces power consumption when the Audio

system is not in use. This is especially useful when designing equipment to meet the Energy Using Products (EUP) directive for IT equipment

Datasheet

3. System Applications

 Desktop and mobile multimedia PCs

 Ultra mobile PCs

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4. Block Diagram

ALC662 Series

Datasheet

1Dh

1Ch

I/O

Surr

LINE1(Port-C)

Front

19h

I/O

CLfe

18h

MIC2(Port-F)

MIC1(Port-B)

I/O

1Eh

S/PDIF-OUT

:Output w/ Amplifier

CLfe

Boost

16h

CEN/LFE(Port-G)

15h

I/O

CLfe

14h

SURR(Port-A)

I/O

Surr

FRONT(Port-D)

BEEP-IN

CD-IN

I/O

Front

LINE2(Port-E)

1Bh

1Ah

I/O

Boost

CLfe

Front

BEEP Gen

0/10/20/30dB boost

Sample Rate: 44.1K, 48K, 96K

Digital Converter

S/PDIF-OUT

VOLMVOLMVOLMVOL

VOL

Surr DAC

0Dh

Front DAC

-34.5~+12dB (1.5dB/Step)

0Ch

CLfe DAC

0Eh

VOLMVOL M

0Bh

VOL

22h

MMM

23h

MMM

06h

VOLSRC

DAC

04h

SRC VOL

DAC PCM-3

03h

SRC VOL

DAC PCM-2

02h

DAC PCM-1

Sample Rate: 44.1K, 48K, 96K

VOL: -64~0dB (1.0dB/Step)

HDA I/F

Sample Rate: 44.1K, 48K, 96K

VOL: -13.5~+33dB (1.5dB/Step)

Parameters

SRC VOLADC

09h

ADC PCM-2

SRC VOLADC

08h

ADC PCM-1

Figure 1. Block Diagram

5.1 Channel High Definition Audio Codec 5 Track ID: JATR-1076-21 Rev. 1.3

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5. Pin Assignments

ALC662 Series

Datasheet

AVDD2

SURR-L( PORT-A-L)

JDREF

SURR-R( PORT-A-R)

AVSS2

CENTER( PORT-G-L)

LFE( PORT-G-R)

NC NC

EAPD

SPDIFO

FRONT-L(PORT-D-L)

FRONT-R(PORT-D-R)

363534 33

37 38 39 40 41 42 43 44 45

LLLLLLL TXXXVV

46 47 48

LINE2-VREFO

Sense B

MIC1-VREFO-R

323130 29 282726 25

ALC662

7891011 12

MIC2-VREFO

MIC1-VREFO-L

AVSS1

VREF

AVDD1

24 23 22 21 20 19 18 17 16 15 14 13

LINE1-R(PORT-C-R)

LINE1-L(PORT-C-L)

MIC1-R(PORT-B-R) MIC1-L(PORT-B-L)

CD-R CD- GND

CD-L MIC2-R (PORT-F-R) MIC2-L (PORT-F-L) LINE2-R (PORT-E-R)

LINE2-L(PORT-E-L)

Sense A

DVDD

DVSS

GPIO1

GPIO0

DVSS

BITCLK

SDATA-IN

DVDD-IO

SYNC

RESET#

PCBEEP

SDATA-OUT

Figure 2. Pin Assignments

5.1.

Package and Version Identification

Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2. The version number is shown in the location marked ‘VV’. For example, ‘VV=C0’ indicates silicon version ‘C’ and stepping version ‘0’, which is the stepping of the ALC662-VC0.

5.1 Channel High Definition Audio Codec 6 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

Datasheet

6. Pin Descriptions

6.1.

Digital I/O Pins

Table 1. Digital I/O Pins

Name Type Pin Description Characteristic Definition

RESET# I 11 H/W Reset Vt=0.5*DVDDIO

SYNC I 10 Sample Sync (48kHz) Vt=0.5*DVDDIO

BITCLK I 6 24MHz Bit Clock Input Vt=0.5*DVDDIO

SDATA-OUT I 5 Serial TDM Data Input Vt=0.5*DVDDIO

SDATA-IN O 8 Serial TDM Data Output In: Vt=0.5*DVDDIO;

Out: V

SPDIFO O 48 SPDIF Output

EAPD O 47 External Amplifier Power Down VOH=DVDDIO, VOL=DVSS

GPIO0 IO 2 General Purpose Input/Output 0 In: Vt=0.5*DVDD; Out: VOH=DVDD, VOL=DVSS

GPIO1 IO 3 General Purpose Input/Output 1 In: Vt=0.5*DVDD; Out: VOH=DVDD, VOL=DVSS

Total: 9 Pins

TTL output has 12mA@75Ω driving capability

=DVDDIO, VOL=DVSS

6.2.

Analog I/O Pins

Table 2. Analog I/O Pins

Name Type Pin Description Characteristic Definition

LINE2-L IO 14 2nd Line Input Left Channel Analog input/output. Default is input (JACK-E-L)

LINE2-R IO 15 2nd Line Input Right Channel Analog input/output. Default is input (JACK-E-R)

MIC2-L IO 16

MIC2-R IO 17

CD-L I 18 CD Input Left Channel Analog input. 1.6Vrms of full-scale input

CD-GND I 19 CD Input Reference Ground Analog input. 1.6Vrms of full-scale input

CD-R I 20 CD Input Right Channel Analog input. 1.6Vrms of full-scale input

MIC1-L IO 21

MIC1-R IO 22

LINE1-L IO 23 1st Line Input Left Channel Analog input/output. Default is input (JACK-C-L)

LINE1-R IO 24 1st Line Input Right Channel Analog input/output. Default is input (JACK-C-R)

PCBEEP I 12 External PCBEEP Input Analog input. 1.6Vrms of full-scale input

FRONT-L IO 35 Front Output Left Channel Analog output (JACK-D-L)

FRONT-R IO 36 Front Output Right Channel Analog output (JACK-D-R)

SURR-L IO 39 Surround Out Left Channel Analog output (JACK-A-L)

SURR-R IO 41 Surround Out Right Channel Analog output (JACK-A-R)

CENTER O 43 Center Output Analog output (JACK-G-L)

LFE O 44 Low Frequency Effects Output Analog output (JACK-G-R)

Stereo Microphone Input Left

2 Channel

Stereo Microphone Input

2 Right Channel

Stereo Microphone Input Left

1 Channel

Stereo Microphone Input

1 Right Channel

Analog input/output. Default is input (JACK-F-L)

Analog input/output. Default is input (JACK-F-R)

Analog input/output. Default is input (JACK-B-L)

Analog input/output. Default is input (JACK-B-R)

5.1 Channel High Definition Audio Codec 7 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

Name Type Pin Description Characteristic Definition

Sense A I 13 Jack Detect Pin l Jack resistor network input 1

Sense B I 34 Jack Detect Pin 2 Jack resistor network input 2

Total: 20 Pins

6.3.

Filter/Reference

Table 3. Filter/Reference

Name Ty pe Pin Description Characteristic Definition

VREF - 27 Reference Voltage Typical 2.25V,10µf capacitor to analog ground

MIC1-VREFO-L O 28 Bias Voltage for MIC1 Jack 2.5V/3.2V reference voltage

MIC2-VREFO O 30 Bias Voltage for MIC2 Jack 2.5V/3.2V reference voltage

LINE2-VREFO O 31 Bias Voltage for LINE2 Jack 2.5V/3.2V reference voltage

MIC1-VREFO-R O 32 Bias Voltage for MIC1 Jack 2.5V/3.2V reference voltage

JDREF - 40

Total: 6 Pins

Reference Resistor for Jack Detection

20K, 1% external resistor to analog ground

Datasheet

6.4.

Power/Ground

Table 4. Power/Ground

Name Ty pe Pin Description Characteristic Definition

AVDD1 I 25 Analog VDD Analog power for mixer and amplifier

AVSS1 I 26 Analog GND Analog ground for mixer and amplifier

AVDD2 I 38 Analog VDD Analog power for DACs and ADCs

AVSS2 I 42 Analog GND Analog ground for DACs and ADCs

DVDD I 1 Digital VDD Digital power for core

DVSS I 4 Digital GND Digital ground for core

DVDD-IO I 9 Digital VDD Digital power for HDA link (1.5V~3.3V)

DVSS I 7 Digital GND Digital ground for HDA link

Total: 8 Pins

6.5.

NC (Not Connected) Pins

Table 5. Not Connected Pins

Name Type Pin Description

NC - 29, 33, 37, 45, 46 Not Connected.

Total: 5 Pins

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ALC662 Series

Datasheet

7. High Definition Audio Link Protocol

7.1.

Link Signals

The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent by the HDA controller. The input and output streams, including command and PCM data, are isochronous with a 48kHz frame rate. Figure 3 shows the basic concept of the HDA link protocol.

Figure 3. HDA Link Protocol

5.1 Channel High Definition Audio Codec 9 Track ID: JATR-1076-21 Rev. 1.3

Page 18

7.1.1. Signal Definitions

Table 6. Link RESET#

Item Description

BCLK 24.0MHz bit clock sourced from the HDA controller and connecting to all codecs.

SYNC

SDO

SDI

RESET#

A 48kHz signal used to synchronize input and output streams on the link. It is sourced from the HDA controller and connects to all codecs.

Serial Data Output signal driven by the HDA controller to all codecs. Commands and data streams are carried on SDO. The data rate is double-pumped; the controller drives data onto the SDO, the codec samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To extend outbound bandwidth, multiple SDOs may be supported.

Serial Data Input signal driven by the codec. This is point-to-point serial data from the codec to the HDA controller. The controller must support at least one SDI. Up to a maximum of 15 SDI’s can be supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID.

Active low reset signal. Asserted to reset the codec to default power-on state. RESET# is sourced from the HDA controller and connects to all codecs.

ALC662 Series

Datasheet

Table 7. HDA Signal Definitions

Signal Name Source Type for Controller Description

BCLK Controller Output Global 24.0MHz Bit Clock.

SYNC Controller Output Global 48kHz Frame Sync and Outbound Tag Signal.

SDO Controller Output Serial Data Output from Controller.

SDI Codec/Controller Input/Output

RESET# Controller Output Global Active Low Reset Signal.

Serial data input from codec. Weakly pulled down by the controller.

BCLK

SYNC

SDO

8-Bit Frame SYNC

Start of Frame

7654 0123 999 998 997 996995 994 993 992 991 990

SDI

3210 499

498

497 496 495 494

Codec samples SDO at both rising and falling edge of BCLK

Controller samples SDI at rising edge of BCLK

Figure 4. Bit Timing

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ALC662 Series

Datasheet

7.1.2. Signaling Topology

The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream. RESET#, BCLK, SYNC, SDO0, and SDO1 are driven by the controller to codecs. Each codec drives its own point-to-point SDI signal(s) to the controller.

Figure 5 shows the possible connections between the HDA controller and codecs:

• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission

• Codec 1 has two SDOs for doubled outbound rate, and a single SDI for normal inbound rate

• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate

• Codec N has two SDOs and multiple SDIs

The multiple SDOs and multiple SDIs are used to expand the transmission rate between the controller and codecs. Section 7.2 Frame Composition, page 12, describes the detailed outbound and inbound stream compositions for single and multiple SDOs/SDIs.

The connections shown in Figure 5 can be implemented concurrently in an HDA system. The ALC662 is designed to receive a single SDO stream.

SDI14

. .

HDA

Controller

SDI13

SDI2 SDI1

SDI0 SDO1 SDO0 SYNC

BCLK RST#

RST#

BCLK

SYNC

Codec 0

Single SDO

Single SDI

SDI0

SDO0

RST#

BCLK

SYNC

Codec 1

Two SDOs

Single SDI

SDO0

Figure 5. Signaling Topology

. . .

SDI0

SDO1

RST#

BCLK

SYNC

Codec 2

Single SDO

Two SDIs

SDI0

SDO0

SDI1

. . .

RST#

BCLK

SYNC

Codec N

Two SDOs

Multiple SDIs

SDI0

SDI2

SDO0

SDI1

SDO1

5.1 Channel High Definition Audio Codec 11 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

Datasheet

7.2.

Frame Composition

7.2.1. Outbound Frame – Single SDO

An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry 96kHz samples (Figure 6).

For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 7).

To keep the cadence of converters bound to the same stream, samples for these converters must be placed in the same block.

SYNC

SDO

A 48kHz Frame is composed of Command stream and multiple Data streams

Frame SYNC

Command Stream

Sample Block(s)

Block 1

Sample 1 Sample 2

msb

Block 2

...

BCLK

Stream 'A' Tag Stream 'X' Tag

(Here 'A' = 5) (Here 'X' = 6)

One or multiple blocks in a stream

msb first in a sample

lsb

Figure 6. SDO Outbound Frame

Block Y

Sample Z

Stream Tag

msb lsb

Stream 'X' DataStream 'A' Data

Null Field

For 48kHz rate, only Block1 is included For 96kHz rate, Block1 includes (N) includes (N+1)

Z channels of PCM sample

time of samples

time of samples, Block2

Next FramePrevious Frame

Padded at the

end of Frame

SYNC

SDO

Preamble

(4-Bit) (4-Bit)

7654 0123

Previous Stream

110

Stream=10

Data of Stream 10

msb

Figure 7. SDO Stream Tag is Indicated in SYNC

5.1 Channel High Definition Audio Codec 12 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

Datasheet

7.2.2. Outbound Frame – Multiple SDOs

The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission in less time to get more bandwidth. If software determines that the target codec supports multiple SDO capability, it enables the ‘Stripe Control’ bit in the controller’s Output Stream Control Register to initiate a specific stream (Stream ‘A’ in Figure 8) to be transmitted on multiple SDOs. In this case, the MSB of stream data is always carried on SDO0, the second bit on SDO1 and so forth.

SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to SDO0.

To ensure that all codecs can determine their corresponding stream, the command stream is not striped. It is always transmitted on SDO0, and copied on SDO1.

Figure 8. Striped Stream on Multiple SDOs

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ALC662 Series

Datasheet

7.2.3. Inbound Frame – Single SDI

An Inbound Frame – Single SDI is composed of one 36-bit response stream and multiple data streams. Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 9).

The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the total length of the contiguous sample blocks within a given stream is not of integral byte length (Figure 10).

SYNC

SDI

A 48kHz Frame is Composed of a Response Stream and Multiple Data streams

Frame SYNC

Response Stream

Sample Block(s)Stream Tag

Block 1

Sample 1 Sample 2 ... Sample Z

Block 2

msb ... lsb

... Block Y

msb first in a sample

Figure 9. SDI Inbound Stream

Stream 'A'

Null Pad

For 48kHz rate, only Block1 is included For 96kHz rate, Block{1, 2} includes {(N)

Z channels of PCM sample

Stream 'X'

Null Field

Next FramePrevious Frame

Padded at the end of Frame

(N+1)th} time of samples

BCLK

SDI

Stream Tag

Data Length in Bytes

n-Bit Sample Block

n-1

n-2

(Data Length in Bytes *8)-Bit

A Complete Stream

Figure 10. SDI Stream Tag and Data

Null Pad

Next Stream

5.1 Channel High Definition Audio Codec 14 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

Datasheet

7.2.4. Inbound Frame – Multiple SDIs

A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI signals, each of which operate independently, with different stream numbers at the same frame time. This is similar to having multiple codecs connected to the controller. The controller samples the divided stream into separate memory with multiple DMA descriptors, then software re-combines the divided data into a meaningful stream.

SYNC

Frame SYNC

SDI

Codec drives SDI

Response Stream

and SDI

Tag A

Tag B Data B

Figure 11. Codec Transmits Data Over Multiple SDIs

Stream 'A'

Data A

Stream 'B'

Stream A, B, X, and Y are independent and have separate IDs

Stream 'X'

Stream 'Y'

7.2.5. Variable Sample Rates

The HDA link is designed for sample rates of 48kHz. Variable sample rates are delivered in multiple or sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own sample rate, independent of any other stream.

The HDA controller supports 48kHz and 44.1kHz base rates. Table 8, page 16, shows the recommended sample rates based on multiples or sub-multiples of one of the two base rates.

Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in multiples (n) of 48kHz contain n sample blocks in a frame. Table 9, page 16, shows the delivery cadence of variable rates based on 48kHz.

The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample blocks are transmitted every 160 frames.

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ALC662 Series

The cadence ‘12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)’ interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame AND interleave an empty frame between non-empty frames (see Table 10, page 17).

Table 8. Defined Sample Rate and Transmission Rate

(Sub) Multiple 48kHz Base 44.1kHz Base

1/6 8kHz (1 sample block every 6 frames) -

1/4 12kHz (1 sample block every 4 frames) 11.025kHz (1 sample block every 4 frames)

1/3 16kHz (1 sample block every 3 frames) -

1/2 - 22.05kHz (1 sample block every 2 frames)

2/3 32kHz (2 sample blocks every 3 frames) -

1 48kHz (1 sample block per frame) 44.1kHz (1 sample block per frame)

2 96kHz (2 sample blocks per frame) 88.2kHz (2 sample blocks per frame)

4 192kHz (4 sample blocks per frame) 176.4kHz (4 sample blocks per frame)

Datasheet

Rate Delivery Cadence Description

8kHz YNNNNN (repeat) One sample block is transmitted in every 6 frames

12kHz YNNN (repeat) One sample block is transmitted in every 4 frames

16kHz YNN (repeat) One sample block is transmitted in every 3 frames

32kHz Y2NN (repeat) One sample block is transmitted in every 6 frames

48kHz Y (repeat) One sample block is transmitted in every 6 frames

96kHz Y2 (repeat) Two sample blocks are transmitted in each frame

192kHz Y4 (repeat) Four sample blocks are transmitted in each frame

N: No sample block in a frame Y: One sample block in a frame Yx: X sample blocks in a frame

Table 9. 48kHz Variable Rate of Delivery Timing

5.1 Channel High Definition Audio Codec 16 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

Table 10. 44.1kHz Variable Rate of Delivery Timing

Rate Delivery Cadence

11.025kHz

22.05kHz

44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)

88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)

174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)

{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat)

11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN

{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN

{ - }=NNNN

22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN

Datasheet

{11}=YNYNYNYNYNYNYNYNYNYNYN

{ - }=NN

44.1kHz 12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with no sample block.

88.2kHz 122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with no sample block.

174.4kHz 124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with no sample block.

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ALC662 Series

7.3.

Reset and Initialization

There are two types of reset within an HDA link:

• Link Reset.

Generated by assertion of the RESET# signal. All codecs return to their power-on state

• Codec Reset.

Generated by software directing a command to reset a specific codec back to its default state

An initialization sequence is requested after any of the following three events:

• Link Reset

• Codec Reset

• Codec changes its power state, e.g., hot docking a codec to an HDA system

7.3.1. Link Reset

Datasheet

A link reset may be caused by any of the following three events:

1. The HDA controller asserts RESET# for any reason (power up, or PCI reset)

2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA

controller

3. Software initiates power management sequences. Figure 12, page 19, shows the ‘Link Reset’ timing

including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)

Enter ‘Link Reset’:

n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a link reset

o As the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the end of the frame

p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low

q The controller asserts the RESET# signal to low, and enters the ‘Link Reset’ state

r All link signals driven by controller and codecs should be tri-state by internal pull-low resistors

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ALC662 Series

Exit from ‘Link Reset’:

s If BCLK is re-started for any reason (codec, wake-up event, power management, etc.)

t Software is responsible for de-asserting RESET# after a minimum of 100µs BCLK running time (the

100µsec provides time for the codec PLL to stabilize)

u Minimum of 4 BCLKs after RESET# is de-asserted, the controller starts to signal normal frame SYNC

v The codec drives its SDI to request an initialization sequence (when the SDI is driven high at the last

bit of frame SYNC)

Datasheet

>=100 usec >= 4 BCLK Initialization Sequence

Normal Frame

SYNC

Wake Event

BCLK

SYNC

SDOs

SDIs

RST#

Previous Frame

Normal Frame

SYNC is absent

4 BCLK

Driven Low

4 BCLK

4 53 6 7

Link in Reset

Pulled Low

Figure 12. Link Reset Timing

7.3.2. Codec Reset

A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being reset to the default state. After the target codec completes its reset operation, an initialization sequence is requested.

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ALC662 Series

Datasheet

7.3.3. Codec Initialization Sequence

n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the controller

o The codec stops driving the SDI during this turnaround period

pqrs The controller drives SDI to assign a CAD to the codec

t The controller releases the SDI after the CAD has been assigned

u Normal operating state

Figure 13. Codec Initialization Sequence

7.4.

Verb and Response Format

7.4.1. Command Verb Format

There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with 12-bit identifiers (12-bit verbs) and 8-bits of data. Table 11 shows the 4-bit verb structure of a command stream sent from the controller to operate the codec. Table 12 is the 12-bit verb structure that gets and controls parameters in the codec.

Table 11. 40-Bit Commands in 4-Bit Verb Format

Bit [39:32] Bit [31:28] Bit [27:20] Bit [19:16] Bit [15:0]

Reserved Codec Address Node ID Verb ID Payload

Table 12. 40-Bit Commands in 12-Bit Verb Format

Bit [39:32] Bit [31:28] Bit [27:20] Bit [19:8] Bit [7:0]

Reserved Codec Address Node ID Verb ID Payload

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ALC662 Series

Power Widget

Volume Knob

Datasheet

Beep Generator

Vendor Defined Widget

Table 13. Supported Commands

Supported Verb

Set Verb

Get Verb

Root Node

Audio Function Group

Pin Widget

Sum Widget

Audio In Converter

Audio Out Converter

Vendor Defined Group

HDMI Function Group

Modem Function Group

Selector Widget

Get parameter F00 - Y Y - - - Y Y Y Y Y - Y Y Y

Connection Select F01 701 - - - - - - Y Y - Y - - - -

Get Connection List Entry F02 - - - - - - - Y Y Y Y - - - -

Processing State F03 703 - - - - - - - - - - - - - -

Coefficient Index D-- 5-- - - - - - - - - - - - - - Y

Processing Coefficient C-- 4-- - - - - - - - - - - - - - Y

Amplifier Gain/Mute B-- 3-- - - - - - - Y Y Y - - - - -

Stream Format A-- 2-- - - - - - Y Y - - - - - - -

Digital Converter 1 F0D 70D - - - - - Y Y - - - - - - -

Digital Converter 2 F0D 70E - - - - - Y Y - - - - - - -

Power State F05 705 - Y - - - - - - - - - - - -

Channel / Stream ID F06 706 - - - - - Y Y - - - - - - -

SDI Select F04 704 - - - - - - - - - - - - - -

Pin Widget Control F07 707 - - - - - - - Y - - - - - -

Unsolicited Enable F08 708 - - - - - - - Y - - - Y - -

Pin Sense F09 709 - - - - - - - Y - - - - - -

EAPD / BTL Enable F0C 70C - - - - - - - - - - - - - -

All GPIO Control

F10F1A

710-

71A

- - - - - - - - - - - - - -

Beep Generator Control F0A 70A - - - - - - - - - - - - Y -

Volume Knob Control F0F 70F - - - - - - - - - - - - - -

Subsystem ID, Byte 0 F20 720 - Y - - - - - - - - - - - -

Subsystem ID, Byte 1 F20 721 - Y - - - - - - - - - - - -

Subsystem ID, Byte 2 F20 722 - Y - - - - - - - - - - - -

Subsystem ID, Byte 3 F20 723 - Y - - - - - - - - - - - -

Config Default, Byte 0 F1C 71C - - - - - - - Y - - - - - -

Config Default, Byte 1 F1C 71D - - - - - - - Y - - - - - -

Config Default, Byte 2 F1C 71E - - - - - - - Y - - - - - -

Config Default, Byte 3 F1C 71F - - - - - - - Y - - - - - -

RESET - 7FF - Y - - - - - - - - - - - -

*1: The ALC662 does not support Modem/HDMI/Vendor groups and Power State widgets.

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Supported Parameter

Table 14. Supported Parameters

ALC662 Series

Datasheet

Parameter ID

Root Node

Audio Function Group

Audio Out Converter

Vendor Defined Group

HDMI Function Group

Modem Function Group

Pin Widget

Audio In Converter

Sum Widget

Selector Widget

Power Widget

Volume Knob

Beep Generator

Vendor Defined Widget

Vendor ID 00 Y - - - - - - - - - - - - -

Revision ID 02 Y - - - - - - - - - - - - -

Subordinate Node Count 04 Y Y - - - - - - - - - - - -

Function Group Type 05 - Y - - - - - - - - - - - -

Audio Function Group

08 - Y - - - - - - - - - - - -

Capabilities

Audio Widget Capabilities 09 - - - - - Y Y Y Y Y - Y Y Y

Sample Size, Rate 0A - Y - - - Y Y - - - - - - -

Stream Formats 0B - Y - - - Y Y - - - - - - -

Pin Capabilities 0C - - - - - - - Y - - - - - -

Input Amp Capabilities 0D - - - - - - Y - Y Y - - - -

Output Amp Capabilities 12 - - - - - - - Y Y - - - - -

Connection List Length 0E - - - - - - Y Y Y Y - - - -

Supported Power States 0F - Y - - - Y Y Y Y Y - - - Y

Processing Capabilities 10 - - - - - - - - - - - - - Y

GPI/O Count 11 - - - - - - - - - - - - - -

Volume Knob Capabilities 13 - - - - - - - - - - - - - -

*1: The ALC662 does not support Modem/HDMI/Vendor groups and Power State widgets.

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7.4.2. Response Format

There are two types of response from the codec to the controller. Solicited Responses are returned by the codec in response to a current command verb. The codec will send Solicited Response data in the next frame, without regard to the Set (Write) or Get (Read) command. The 32-bit response is interpreted by software, opaque to the controller.

Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.

Table 15. Solicited Response Format

Bit [35] Bit [34] Bit [33:32] Bit [31:0]

Valid Unsol=0 Reserved Response

Table 16. Unsolicited Response Format

Bit [35] Bit [34] Bit [33:32] Bit [31:28] Bit [27:0]

Valid Unsol=1 Reserved Tag Response

7.5.

Power Management

The ALC662 does not support Wake-Up events when in low-power mode. All power management state changes in widgets are driven by software. Table 17 shows the System Power State Definitions. Table 18 indicates those nodes that support power management. To simplify power control, software can configure whole codec power states through the audio function (NID=01h). Output converters (DACs) and input converters (ADCs) have no individual power control to supply fine-grained power control.

7.5.1. System Power State Definitions

Table 17. System Power State Definitions

Power States Definitions

D0 All power on. Individual DACs and ADCs can be powered up or down as required.

D3 (Hot) Power still supplied. The codec stops the internal clock. State is maintained.

D3 (Cold) All power removed. State lost.

All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog reference stays up.

All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog reference is off (D1 + analog reference off).

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7.5.2. Power Controls in NID 01h

Table 18. Power Controls in NID 01h

Item Description D0 D1 D2 D3 Link Reset

Audio Function

(NID=01h)

Note: PD=Powered Down.

LINK Response Normal Normal Normal PD PD

Front DAC (Node 02h) Normal PD PD PD PD

Surr DAC (Node 03h) Normal PD PD PD PD

Cen/LFE DAC (Node 04h) Normal PD PD PD PD

ADC (Node 08h) Normal PD PD PD PD

ADC (Node 09h) Normal PD PD PD PD

All Headphone Drivers Normal Normal PD PD Normal

All Mixers Normal Normal PD PD Normal

All Reference Normal Normal PD PD Normal

7.5.3. Powered Down Conditions

Table 19. Powered Down Conditions

Condition Description

LINK Response powered down

Front DAC powered down Analog block and digital filter are powered down

Surr DAC powered down Analog block and digital filter are powered down

CEN/LFE DAC powered down Analog block and digital filter are powered down

ADC 08h powered down Analog block and digital filter are powered down. Data on SDATA-IN is quiet

ADC 09h powered down Analog block and digital filter are powered down. Data on SDATA-IN is quiet

Headphone Driver powered down All headphone drivers are powered down

Mixers powered down

References powered down

Internal clock is stopped. SDATA-IN and SPDIF-OUT are floated with pulled low 47K resistors internally. SPDIF-IN is also floated. Detection of ‘Link Reset Entry’ and ‘Link Reset Exit’ sequences are supported. All states are maintained if DVDD is supplied

All internal mixer widgets are powered down. The DC reference and VREFOUTx at individual pin complexes are still alive

All internal references, DC reference, and VREFOUTx at individual pin complexes are off

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ALC662 Series

Datasheet

8. Supported Verbs and Parameters

This section describes the Verbs and Parameters supported by various widgets in the ALC662. If a verb is not supported by the addressed widget, it will respond with 32 bits of ‘0’.

8.1.

Verb – Get Parameters (Verb ID=F00h)

The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget. Some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format, page 20, to get detailed information about supported parameters.

Table 20. Verb – Get Parameters (Verb ID=F00h)

Get Parameter Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=00h Verb ID=F00h Parameter ID[7:0] 32-bit Response

Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.

8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)

Table 21. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)

Codec Response Format

Bit Description

31:16 Vendor ID=10ECh (Realtek’s PCI vendor ID).

15:0 Device ID=0662h.

Note: The Root Node (NID=00h) supports this parameter.

8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)

Table 22. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)

Codec Response Format

Bit Description

31:24 Reserved. Read as 0’s.

23:20 MajRev=1h. The major version number (in decimal) of the HDA Specification.

19:16 MinRev=0h. The minor version number (in decimal) of the HDA Specification.

15:8 Revision ID. The vendor’s revision number.

Note: 01h indicates ALC662 silicon.

7:0 Stepping ID. The vendor’s stepping number within the given Revision ID.

Note: The Root Node (NID=00h) supports this parameter.

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8.1.3. Parameter – Subordinate Node Count

(Verb ID=F00h, Parameter ID=04h)

For the root node, the Subordinate Node Count provides information about audio function group nodes associated with the root node.

For function group nodes, it provides the total number of widgets associated with this function node.

Table 23. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)

Codec Response Format

Bit Description

31:24 Reserved. Read as 0’s.

23:16 Starting Node Number. The starting node number in the sequential widgets.

15:8 Reserved. Read as 0’s.

7:0 Total Number of Nodes. For a root node, this is the total number of function groups in the root node.

For a function group, this is the total number of widget nodes in the function group.

8.1.4. Parameter – Function Group Type

(Verb ID=F00h, Parameter ID=05h)

Table 24. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)

Codec Response Format

Bit Description

31:9 Reserved. Read as 0’s.

7:0

UnSol Capable. 0: Unsolicited response is not supported by this function group

1: Unsolicited response is supported by this function group

Function Group Type. 00h: Reserved 01h: Audio Function 02h: Modem Function

03h~7Fh: Reserved 80h~FFh: Vendor Defined Function

8.1.5. Parameter – Audio Function Capabilities

(Verb ID=F00h, Parameter ID=08h)

Table 25. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)

Codec Response Format

Bit Description

31:17 Reserved. Read as 0’s.

15:12 Reserved. Read as 0’s.

11:8 Input Delay. Number of samples delay from analog input to HDA link.

7:4 Reserved. Read as 0’s.

3:0 Output Delay. Number of samples delay from HDA link to analog output.

Beep Generator. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group.

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8.1.6. Parameter – Audio Widget Capabilities

(Verb ID=F00h, Parameter ID=09h)

Table 26. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)

Codec Response Format

Bit Description

31:24 Reserved. Read as 0’s.

23:20 Widget Type.

0h: Audio Output 1h: Audio Input 2h: Mixer 3h: Selector 4h: Pin Complex 5h: Power Widget 6h: Volume Knob Widget 7h~Eh: Reserved Fh: Vendor defined audio widget

19:16 Delay. Samples delayed between the HDA link and widgets.

15:12 Reserved. Read as 0’s.

11: L-R Swap.

0: Left channel and right channel swapping is not supported 1: Left channel and right channel swapping is supported

10 Power Control.

0: Power control is not supported on this widget 1: Power control is supported on this widget

9 Digital.

0: An analog input or output converter 1: A widget translating digital data between the HDA link and digital I/O (SPDIF, I2S, etc.)

8 ConnList. Connection List.

0: Connected to HDA link. No Connection List Entry will be queried 1: Connection List Entry must be queried

7 UnsolCap. Unsolicited Capable.

0: Unsolicited response is not supported 1: Unsolicited response is supported

6 ProcWidget. Processing Widget.

0: No processing control 1: Processing control is supported

5 Reserved. Read as 0.

4 Format Override.

Note: The ALC662 supports 16/20/24-bit with 44.1kHz, 48kHz, and 96kHz sample rate. The format (parameter ID=0Ah) must be queried

3 AmpParOvr (AMP Param Override).

Override amplifier parameters (Gain Control) in individual output Pin Complexes, ADCs, and Mixer widgets.

2 OutAmpPre (Out AMP Present).

There are amplifiers (Mute Control) in individual output Pin Complexes.

1 InAmpPre (In AMP Present).

There are amplifiers (Gain Control) in individual ADCs and Mixer widgets.

0 Stereo.

0: Mono Widget 1: Stereo Widget

ALC662 Series

Datasheet

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8.1.7. Parameter – Supported PCM Size, Rates

(Verb ID=F00h, Parameter ID=0Ah)

Parameters in audio functions provide default information about formats. Individual converters have their own parameters to provide supported formats if their ‘Format Override’ bit is set.

Table 27. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)

Codec Response Format

Bit Description

31:21 Reserved. Read as 0’s.

20 B32. 32-bit audio format support.

0: Not supported 1: Supported

19 B24. 24-bit audio format support.

0: Not supported 1: Supported (The ALC662 DAC supports this format)

18 B20. 20-bit audio format support.

0: Not supported 1: Supported (The ALC662 DAC supports this format)

17 B16. 16-bit audio format support.

0: Not supported 1: Supported (The ALC662 DAC supports this format)

16 B8. 8-bit audio format support.

0: Not supported 1: Supported

15:12 Reserved. Read as 0’s.

11 R12. 384kHz (=8*48kHz) rate support.

0: Not supported 1: Supported

10 R11. 192kHz (=4*48kHz) rate support.

0: Not supported 1: Supported

9 R10. 176.4Hz (=4*44.1kHz) rate support.

0: Not supported 1: Supported

8 R9. 96kHz (=2*48kHz) rate support.

0: Not supported 1: Supported (The ALC662 DAC and ADC support this sample rate)

7 R8. 88.2kHz (=2*44.1kHz) rate support.

0: Not supported 1: Supported

6 R7. 48kHz rate support.

0: Not supported 1: Supported (The ALC662 DAC and ADC support this sample rate)

5 R6. 44.1kHz rate support.

0: Not supported 1: Supported (The ALC662 DAC and ADC support this sample rate)

4 R5. 32kHz (=2/3*48kHz) rate support.

0: Not supported 1: Supported

3 R4. 22.05kHz (=1/2*44.1kHz) rate support.

0: Not supported 1: Supported

2 R3. 16kHz (=1/3*48kHz) rate support.

0: Not supported 1: Supported

1 R2. 11.025kHz (=1/4*44.1kHz) rate support.

0: Not supported 1: Supported

0 R1. 8kHz (=1/6*48kHz) rate support.

0: Not supported 1: Supported

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8.1.8. Parameter – Supported Stream Formats

(Verb ID=F00h, Parameter ID=0Bh)

Parameters in this node only provide default information for audio function groups. Individual converters have their own parameters to provide supported formats if the ‘Format Override’ bit is set.

Table 28. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)

Codec Response Format

Bit Description

31:3 Reserved. Read as 0’s.

2 AC3.

0: Not supported 1: Supported

1 Float32.

0: Not supported 1: Supported

0 PCM.

0: Not supported 1: Supported (The ALC662 DAC and ADC support this format)

Note: Input converters and output converters support this parameter.

8.1.9. Parameter – Pin Capabilities

(Verb ID=F00h, Parameter ID=0Ch)

The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.

Table 29. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)

Codec Response Format

Bit Description

31:16 Reserved. Read as 0’s.

15:8 VREF Control Capability.

‘1’ in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of AV D D .

7:6 5 4 3 2 1 0

Reserved 100% 80% Reserved Ground 50% Hi-Z

7 Reserved.

6 Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins.

5 Input Capable. ‘1’ indicates this pin complex supports input.

4 Output Capable. ‘1’ indicates this pin complex supports output.

3 Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone.

2 Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is a device plugged in.

1 Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement.

0 Impedance Sense Capable.

‘1’ indicates this pin complex can perform analog sensing on the attached device to determine its type.

Note: Only Pin Complex widgets support this parameter.

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8.1.10. Parameter – Amplifier Capabilities

(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)

Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.

Table 30. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)

Codec Response Format

Bit Description

31 (Input) Mute Capable.

30:23 Reserved. Read as 0.

22:16 Step Size.

Indicates the size of each step in the gain range.

15 Reserved. Read as 0.

14:8 Number of Steps.

Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.

7 Reserved. Read as 0.

6:0 Offset.

Indicates which step is 0dB.

8.1.11. Parameter – Amplifier Capabilities

(Verb ID=F00h, Output Amplifier Parameter ID=12h)

Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.

Table 31. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)

Codec Response Format

Bit Description

31 (Output) Mute Capable.

30:23 Reserved. Read as 0.

22:16 Step Size.

Indicates the size of each step in the gain range. Each individual step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates 0.25dB steps. ‘127’ indicates 32dB steps.

15 Reserved. Read as 0.

14:8 Number of Steps.

Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.

7 Reserved. Read as 0.

6:0 Offset. Indicates which step is 0dB.

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8.1.12. Parameter – Connect List Length

(Verb ID=F00h, Parameter ID=0Eh)

Parameters in this node provide audio function widget connection information.

Table 32. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)

Codec Response Format

Bit Description

31:8 Reserved. Read as 0.

7 Short Form.

0: Short Form 1: Long Form

6:0 Connect List Length.

Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one input, and there is no Connection Select Control (not a MUX widget).

8.1.13. Parameter – Supported Power States

(Verb ID=F00h, Parameter ID=0Fh)

ALC662 Series

Datasheet

Table 33. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)

Codec Response Format

Bit Description

31:4 Reserved. Read as 0’s.

3 D3Sup.

1: Power state D3 is supported

2 D2Sup.

1: Power state D2 is supported

1 D1Sup.

1: Power state D1 is supported

0 D0Sup.

1: Power state D0 is supported

8.1.14. Parameter – Processing Capabilities

(Verb ID=F00h, Parameter ID=10h)

Table 34. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)

Codec Response Format

Bit Description

31:16 Reserved. Read as 0’s.

15:8 NumCoeff. Number of Coefficient.

7:1 Reserved. Read as 0’s.

0 Benign.

0: Processing unit is not linear and time invariant 1: Processing unit is linear and time invariant

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8.1.15. Parameter – GPIO Capabilities

(Verb ID=F00h, Parameter ID=11h)

Table 35. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)

Codec Response Format

Bit Description

31 GPIWake=0. The ALC662 does not support GPIO wake-up function.

30 GPIUnsol=1. The ALC662 supports GPIO unsolicited response.

29:24 Reserved. Read as 0’s.

23:16 NumGPIs=00h. No GPI pin is supported.

15:8 NumGPOs=00h. No GPO pin is supported.

7:0 NumGPIOs=02h. Two GPIO pins are supported.

8.1.16. Parameter – Volume Knob Capabilities

(Verb ID=F00h, Parameter ID=13h)

Table 36. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)

Codec Response Format for NID=21h (Volume Control Knob)

Bit Description

31:8 Reserved. Read as 0’s.

7 Delta.

0: Software cannot modify the Volume Control Knob volume 1: Software can write a base volume to the Volume Control Knob

6:0 NumSteps.

The number of steps in the range of the Volume Control Knob

Note: The ALC662 does not support volume knob and will respond with 0s to this parameter.

ALC662 Series

Datasheet

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ALC662 Series

8.2.

Verb – Get Connection Select Control (Verb ID=F01h)

Table 37. Verb – Get Connection Select Control (Verb ID=F01h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=F01h 0’s Bit[7:0] are Connection Index

Codec Response for NID = 19h (MIC2, PORT-F)

Bit Description

31:8 0’s.

7:0 Connection Index Currently Set (Default value is 00h).

00h: Sum Widget NID=0Ch 01h: Sum Widget NID=0Eh Other: Reserved

Codec Response for NID = 1Bh (LINE2, PORT-E)

Bit Description

31:8 0’s

7:0 Connection Index Currently Set (Default value is 00h).

00h: Sum Widget NID=0Ch 01h: Sum Widget NID=0Eh Other: Reserved

Datasheet

Codec Response for other NID

Bit Description

31:0 Not Supported (returns 00000000h).

8.3.

Verb – Set Connection Select (Verb ID=701h)

Table 38. Verb – Set Connection Select (Verb ID=701h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=701h Select Index [7:0] 0’s for all nodes

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ALC662 Series

8.4.

Verb – Get Connection List Entry (Verb ID=F02h)

Table 39. Verb – Get Connection List Entry (Verb ID=F02h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=F02h Offset Index - N[7:0] 32-bit Response

Codec Response for NID=08h (ADC)

Bit Description

31:8

7:0

Codec Response for NID=09h (ADC)

Bit Description

31:8

7:0

Connection List Entry (N+3), (N+2), (N+1). Returns 000000h.

Connection List Entry (N). Returns 23h (Sum Widget) for N=0~3. Returns 00h for N>3.

Connection List Entry (N+3), (N+2), (N+1). Returns 000000h.

Connection List Entry (N). Returns 22h (Sum Widget) for N=0~3. Returns 00h for N>3.

Datasheet

Codec Response for NID=0Bh (Mixer)

Bit Description

31:24

23:16

15:8

7:0

Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 15h (Pin Complex – SURR) for N=4~7. Returns 00h for N>7.

Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 00h for N>7.

Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7. Returns 00h for N>7.

Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 1Ch (Pin Complex – CD) for N=4~7. Returns 16h (Pin Complex – CEN/LFE) for N=8~11. Returns 00h for N>11.

Codec Response for NID=0Ch (Front Sum)

Bit Description

31:24

23:16

Connection List Entry (N). Returns 00h

Connection List Entry (N+2). Returns 00h.

5.1 Channel High Definition Audio Codec 34 Track ID: JATR-1076-21 Rev. 1.3

Page 43

Codec Response for NID=0Ch (Front Sum)

Bit Description

15:8

7:0

Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3.

Connection List Entry (N). Returns 02h (Front DAC) for N=0~3. Returns 00h for N>3.

Codec Response for NID=0Dh (Surround Sum)

Bit Description

31:24

23:16

15:8

7:0 Connection List Entry (N).

Connection List Entry (N). Returns 00h.

Connection List Entry (N+2). Returns 00h.

Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3.

Returns 03h (Surround DAC) for N=0~3. Returns 00h for N>3.

ALC662 Series

Datasheet

Codec Response for NID=0Eh (Cen/Lfe Sum)

Bit Description

31:24

23:16

15:8

7:0 Connection List Entry (N).

Connection List Entry (N). Returns 00h.

Connection List Entry (N+2). Returns 00h.

Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3.

Returns 04h (Cen/Lfe DAC) for N=0~3. Returns 00h for N>3.

Codec Response for NID=14h (FRONT, Port-D)

Bit Description

31:8

7:0

Connection List Entry (N+3), (N+2), (N+1). Returns 000000h for n>3.

Connection List Entry (N). Returns 0Ch (Sum Widget NID=0Ch) for N=0~3. Returns 00h for N>3.

Codec Response for NID=15h (SURR, Port-D)

Bit Description

31:8

7:0

Connection List Entry (N+3), (N+2), (N+1). Returns 000000h for n>3.

Connection List Entry (N). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3. Returns 00h for N>3.

5.1 Channel High Definition Audio Codec 35 Track ID: JATR-1076-21 Rev. 1.3

Page 44

Codec Response for NID=16h (CEN/LFE, Port-G)

Bit Description

31:8

7:0

Connection List Entry (N+3), (N+2), (N+1). Returns 000000h for n>3.

Connection List Entry (N). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3.

Codec Response for NID=18h (MIC1, Port-B)

Bit Description

31:8

7:0

Connection List Entry (N+3), (N+2), (N+1). Returns 000000h for n>3.

Connection List Entry (N). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3.

Codec Response for NID=19h (MIC2, Port-F)

Bit Description

31:16

15:8

7:0

Connection List Entry (N+3), (N+2). Returns 0000h for n>3.

Connection List Entry (N+1). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3.

Connection List Entry (N). Returns 0Ch (Sum Widget NID=0Ch) for N=0~3. Returns 00h for N>3.

ALC662 Series

Datasheet

Codec Response for NID=1Ah (LINE1, Port-C)

Bit Description

31:8

7:0

Connection List Entry (N+3), (N+2), (N+1). Returns 000000h for n>3.

Connection List Entry (N). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3. Returns 00h for N>3.

Codec Response for NID=1Bh (LINE2, Port-E)

Bit Description

31:16

15:8

7:0

Connection List Entry (N+3), (N+2). Returns 0000h for n>3.

Connection List Entry (N+1). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3.

Connection List Entry (N). Returns 0Ch (Sum Widget NID=0Ch) for N=0~3. Returns 00h for N>3.

5.1 Channel High Definition Audio Codec 36 Track ID: JATR-1076-21 Rev. 1.3

Page 45

Codec Response for NID=1Eh (Pin Widget: SPDIF-OUT)

Bit Description

31:8

7:0

Connection List Entry (N+3), (N+2), (N+1). Returns 000000h.

Connection List Entry (N). Returns 06h (SPDIF-OUT Converter) for N=0~3. Returns 00h for N>3.

Codec Response for NID=22h/23h (Sum Widget)

Bit Description

31:23

23:16

15:8

7:0

Connection List Entry (N+3). Returns 1Bh (Pin Widget LINE2, port-E) for N=0~3. Returns 15h (Pin Widget SURR, port-A) for N=4~7. Returns 00h for n>7.

Connection List Entry (N+2). Returns 1Ah (Pin Widget LINE1, port-C) for N=0~3. Returns 14h (Pin Widget FRONT, port-D) for N=4~7. Returns 00h for N>7.

Connection List Entry (N+1). Returns 19h (Pin Widget MIC2, port-F) for N=0~3. Returns 1Dh (Pin Widget PCBEEP) for N=4~7. Returns 0Bh (Mixer) for N=8~11. Returns 00h for N>11.

Connection List Entry (N). Returns 18h (Pin Widget MIC1, port-B) for N=0~3. Returns 1Ch (Pin Widget CD) for N=4~7. Returns 16h (Pin Widget CEN/LFE, port-G) for N=8~11. Returns 00h for N>11.

ALC662 Series

Datasheet

Codec Response for Other NID

Bit Description

31:0 Not Supported (returns 00000000h).

8.5.

Verb – Get Processing State (Verb ID=F03h)

Table 40. Verb – Get Processing State (Verb ID=F03h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=F03h 0’s 32-bit response

Codec Response for All NID

Bit Description

31:0 Not Supported (returns 00000000h).

5.1 Channel High Definition Audio Codec 37 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

8.6.

Verb – Set Processing State (Verb ID=703h)

Table 41. Verb – Set Processing State (Verb ID=703h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=703h Processing State [7:0] 0’s for all nodes

Codec Response for all NID

Bit Description

31:0 0’s.

8.7.

Verb – Get Coefficient Index (Verb ID=Dh)

Table 42. Verb – Get Coefficient Index (Verb ID=Dh)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]

CAd=X Node ID=20h Verb ID=Dh 0’s Bit [15:0] are Coefficient Index

Datasheet

Codec Response for NID=20h (Realtek Defined Registers)

Bit Description

31:16 Reserved. Read as 0’s.

15:0 Coefficient Index.

Codec Response for Other NID

Bit Description

31:0 Not Supported (returns 00000000h).

8.8.

Verb – Set Coefficient Index (Verb ID=5h)

Table 43. Verb – Set Coefficient Index (Verb ID=5h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]

CAd=X Node ID=20h Verb ID=5h Coefficient Index [15:0] 0’s for all nodes

Codec Response for All NID

Bit Description

31:0 0’s.

5.1 Channel High Definition Audio Codec 38 Track ID: JATR-1076-21 Rev. 1.3

Page 47

ALC662 Series

8.9.

Verb – Get Processing Coefficient (Verb ID=Ch)

Table 44. Verb – Get Processing Coefficient (Verb ID=Ch)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]

CAd=X Node ID=20h Verb ID=Ch 0’s Processing Coefficient [15:0]

Codec Response for NID=20h (Realtek Defined Registers)

Bit Description

31:16 Reserved. Read as 0’s.

15:0 Processing Coefficient.

Codec Response for Other NID

Bit Description

31:0 Not Supported (returns 00000000h).

Datasheet

8.10. Verb – Set Processing Coefficient (Verb ID=4h)

Table 45. Verb – Set Processing Coefficient (Verb ID=4h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]

CAd=X Node ID=20h Verb ID=4h Coefficient [15:0] 0’s for all nodes

Codec Response for All NID

Bit Description

31:0 0’s.

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ALC662 Series

8.11. Verb – Get Amplifier Gain (Verb ID=Bh)

This verb is used to get gain/attenuation settings from each widget.

Table 46. Verb – Get Amplifier Gain (Verb ID=Bh)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=Bh ‘Get’ payload [15:0] Bit[7:0] are responsible for ‘Get’

‘Get’ Payload in Command Bit[15:0]

Bit Description

15 Get Input/Output.

0: Input amplifier gain is requested 1: Output amplifier gain is requested

14 Reserved. Read as 0.

13 Get Left/Right.

0: Right amplifier gain is requested 1: Left amplifier gain is requested

12:4 Reserved. Read as 0’s.

3:0 Index[3:0] for Input Source.

Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.

Datasheet

Codec Response for 02h (FRONT DAC), 03h (SURR DAC), 04h (CEN/LFE DAC)

Bit Description

31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Mute).

Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).

6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).

Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0]. 7-bit step value (0~64) specifying the volume from –64B~0dB in 1dB steps.

Codec Response for 08h (ADC)

Bit Description

31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.

0: Unmute 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).

6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].

7-bit step value (0~31) specifying the volume from –13.5B~+33dB in 1.5dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).

5.1 Channel High Definition Audio Codec 40 Track ID: JATR-1076-21 Rev. 1.3

Page 49

Codec Response for 09h (ADC)

Bit Description

31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.

0: Unmute 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).

6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].

7-bit step value (0~31) specifying the volume from –13.5B~+33dB in 1.5dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).

Codec Response for NID=0Bh (MIXER Sum Widget)

Bit Description

31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.

0: Unmute 1: Mute (Default for all Index) Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).

6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].

7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).

ALC662 Series

Datasheet

Codec Response for NID=0Ch~0Eh (Sum Widget: Front, Surr, Cen/Lfe)

Bit Description

31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.

0: Unmute 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).

6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).

Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).

Codec Response for NID=14h, 15h, 16h and 1Ah (Pin Widget: FRONT/SURR/CEN/LINE1)

Bit Description

31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Mute).

Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute. 0: Unmute 1: Mute (Default=1)

6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).

Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).

5.1 Channel High Definition Audio Codec 41 Track ID: JATR-1076-21 Rev. 1.3

Page 50

Codec Response for NID=18h, 19h and 1Bh (Pin Widget: MIC1/MIC2/LINE2)

Bit Description

31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Mute).

Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute. 0: Unmute 1: Mute (Default=1)

6:0

Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0] specifying the boost from 0dB/10dB/20dB/30dB in 10dB steps (Default=0, 0dB).

Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).

Codec Response for NID=22h (Sum Widget)

Bit Description

31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.

0: Unmute 1: Mute (Default=1 for all index) Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).

6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).

Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).

ALC662 Series

Datasheet

Codec Response for NID=23h (Sum Widget)

Bit Description

31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.

0: Unmute 1: Mute (Default=1 for all index) Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).

6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).

Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).

Codec Response to Other NID

Bit Description

31:0 Not Supported (returns 00000000h).

5.1 Channel High Definition Audio Codec 42 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

8.12. Verb – Set Amplifier Gain (Verb ID=3h)

This verb is used to set amplifier gain/attenuation in each widget.

Table 47. Verb – Set Amplifier Gain (Verb ID=3h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=3h ‘Set’ payload [7:0] 0’s for all nodes

‘Set’ Payload in Command Bit[15:0]

Bit Description

15 Set Output Amp.

1: Indicates output amplifier gain will be set

14 Set Input Amp.

1: Indicates input amplifier gain will be set

13 Set Left Amp.

1: Indicates left amplifier gain will be set

12 Set Right Amp.

1: Indicates right amplifier gain will be set

11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets).

5-bit index offset in connection list is used to select the input gain that will be set on a Sum or a Selector widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is not set.

7 Mute.

0: Unmute 1: Mute (-∞gain)

6:0 Gain[6:0].

A 7-bit step value specifying the amplifier gain.

Datasheet

5.1 Channel High Definition Audio Codec 43 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

8.13. Verb – Get Converter Format (Verb ID=Ah)

Table 48. Verb – Get Converter Format (Verb ID=Ah)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=Ah 0’s Bit[15:0] are converter format

Codec Response for NID=02h~04h, 06h (Output Converters: FRONT, SURR, CEN/LFE DAC, and SPDIF-OUT). Codec Response for NID=08h and 09h (Input Converters: ADC 08h and ADC 09h)

Bit Description

31:16 Reserved. Read as 0.

15 Stream Type (TYPE).

0: PCM 1: Non-PCM

14 Sample Base Rate (BASE).

0: 48kHz 1: 44.1kHz

13:11 Sample Base Rate Multiple (MULT).

000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved

10:8 Sample Base Rate Divisor (DIV).

000b: /1 001b: /2 010b: /3 011b: /4 100b: /5 101b: /6 110b: /7 111b: /8 Not supported. Always read as 000b.

7 Reserved. Read as 0.

6:4 Bits per Sample (BITS).

000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved

3:0 Number of Channels.

0: 1 channel 1: 2 channels 2: 3 channels ……… 15: 16 channels

Datasheet

8.14. Get Converter Format Support

Table 49. Get Converter Format Support

BASE MULT DIV BITS Sample Rate

0 000b, 001b 000b 001, 010b, 011b 48K, 96K NID=02h (Front DAC) 1 000b 000b 001, 010b, 011b 44.1K 0 000b, 001b 000b 001, 010b, 011b 48K, 96K NID=03h (Surr DAC) 1 000b 000b 001, 010b, 011b 44.1K 0 000b, 001b 000b 001, 010b, 011b 48K, 96K NID=04h (Cen/Lfe DAC) 1 000b 000b 001, 010b, 011b 44.1K 0 000b, 001b 000b 001, 010b, 011b 48K, 96K NID=06h (SPDIF-OUT) 1 000b 000b 001, 010b, 011b 44.1K 0 000b, 001b 000b 001b, 010b, 48K, 96K NID=08h (ADC) 1 000b 000b 001b, 010b, 44.1K 0 000b, 001b 000b 001b, 010b, 48K, 96K NID=09h (ADC) 1 000b 000b 001b, 010b, 44.1K

Codec Response for other NID

Bit Description

31:0 Not Supported (returns 00000000h).

5.1 Channel High Definition Audio Codec 44 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

8.15. Verb – Set Converter Format (Verb ID=2h)

Table 50. Verb – Set Converter Format (Verb ID=2h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=2h Set format [15:0] 0’s for all nodes

‘Set’ Payload in Command Bit[15:0]

Bit Description

31:16 Reserved. Read as 0.

15 Stream Type (TYPE).

0: PCM 1: Non-PCM

14 Sample Base Rate (BASE).

0: 48kHz 1: 44.1kHz

13:11 Sample Base Rate Multiple (MULT).

000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved

10:8 Sample Base Rate Divisor (DIV).

000b: /1 001b: /2 010b: /3 011b: /4 100b: /5 101b: /6 110b: /7 111b: /8

7 Reserved. Read as 0.

6:4 Bits per Sample (BITS).

000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved

3:0 Number of Channels.

0: 1 channel 1: 2 channels 2: 3 channels …..… 15: 16 channels

Datasheet

5.1 Channel High Definition Audio Codec 45 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

8.16. Verb – Get Power State (Verb ID=F05h)

Table 51. Verb – Get Power State (Verb ID=F05h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID= F05h 0’s Power State [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit Description

31:6 Reserved. Read as 0’s.

5:4

3:2 Reserved. Read as 0’s.

1:0

PS-Act. Actual Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes (NID=01h), PS-Act is always equal to PS-Set.

PS-Set. Set Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Set controls the current power setting of the referenced node.

Datasheet

Codec Response for other NID

Bit Description

31:0 Not Supported (returns 00000000h).

8.17. Verb – Set Power State (Verb ID=705h)

Table 52. Verb – Set Power State (Verb ID=705h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=705h Power State [7:0] 0’s for all nodes

‘Power State’ in Command Bit[7:0]

Bit Description

7:6 Reserved. Read as 0’s.

5:4

3:2 Reserved. Read as 0’s.

1:0

PS-Act. Actual Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Act indicates the actual power state of the referenced node.

PS-Set. Set Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3

5.1 Channel High Definition Audio Codec 46 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

Datasheet

8.18. Verb – Get Converter Stream, Channel (Verb ID=F06h)

Table 53. Verb – Get Converter Stream, Channel (Verb ID=F06h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=F06h 0’s Stream & Channel [7:0]

Codec Response for NID=02h~04h, 06h (Output Converters: FRONT, SURR, CEN/LFE DAC and SPDIF-OUT) Codec Response for NID=08h and 09h (Input Converters: ADC 08h and ADC 09h)

Bit Description

31:8 Reserved. Read as 0’s.

7:4 Stream[3:0].

The link stream used by the converter. 0000b is unused, 0001b is stream 1, etc.

3:0 Channel[3:0].

The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its left and right channel.

Codec Response for other NID

Bit Description

31:0 Not Supported (returns 00000000h).

8.19. Verb – Set Converter Stream, Channel (Verb ID=706h)

Table 54. Verb – Set Converter Stream, Channel (Verb ID=706h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=706h Stream & Channel [7:0] 0’s for all nodes

‘Stream and Channel’ in Command Bit[7:0]

Bit Description

31:8 Reserved. Read as 0’s.

7:4 Set Stream[3:0].

The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.

1:0 Set Channel[3:0].

The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its left and right channel.

5.1 Channel High Definition Audio Codec 47 Track ID: JATR-1076-21 Rev. 1.3

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ALC662 Series

8.20. Verb – Get Pin Widget Control (Verb ID=F07h)

Table 55. Verb – Get Pin Widget Control (Verb ID=F07h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=F07h 0’s Pin Control [7:0]

Codec Response for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh. (Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, SPDIF-OUT)

Bit Description

31:8 Reserved. Read as 0’s.

7 H-Phn Enable.

0: Disabled 1: Enabled

Note: Only NID=14h (FRONT), 19h (MIC2), and 1Bh (LINE2) support headphone amplifier.

6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit).

0: Disabled 1: Enabled

Note: NID=1Ch (CD-IN) and 1Dh (PCBEEP) do not support output and are always read 0.

5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).

0: Disabled 1: Enabled

Note: NID=1Eh (SPDIF-OUT) does not support output and is always read 0.

4:3 Reserved.

2:0 VrefEn (Vrefout Enable Control).

000b: Hi-Z (Disabled, default for all) 001b: 50% of AVDD (The ALC662 supports 2.5V reference output when AVDD is 5V) 010b: Ground 0V 011b: Reserved 100b: 80% of AVDD (The ALC662 supports 3.2V reference output when AVDD is 5V) 101b: 100% of AVDD 110b~111b: Reserved

Note: Only NID=18h, 19h, and 1Bh support reference output, other nodes will ignore this verb and respond with 0.

Datasheet

Codec Response for other NID

Bit Description

31:0 Not Supported (returns 00000000h).

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8.21. Verb – Set Pin Widget Control (Verb ID=707h)

Table 56. Verb – Set Pin Widget Control (Verb ID=707h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=707h Pin Control [7:0] 0’s for all nodes

‘Pin Control’ in command [7:0]: (NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh) (Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, SPDIF-OUT)

Bit Description

31:8 Reserved. Read as 0’s.

7 H-Phn Enable.

0: Disabled 1: Enabled

Note: Only NID=14h (FRONT), 19h (MIC2), and 1Bh (LINE2) support headphone amplifier.

6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit).

0: Disabled 1: Enabled

Note: NID=1Ch (CD-IN) and 1Dh(PCBEEP) do not support output and always read 0.

5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).

0: Disabled 1: Enabled

Note: NID=1Eh (SPDIF-OUT) does not support output and always read 0.

4:3 Reserved.

2:0 VrefEn (Vrefout Enable Control).

000b: Hi-Z (Disabled, default for all) 001b: 50% of AVDD 010b: Ground 0V 011b: Reserved 100b: 80% of AVDD 101b: 100% of AVDD 110b~111b: Reserved

Note: Only NID=18h, 19h, and 1Bh support reference output. Other nodes will ignore this verb and respond with 0.

Datasheet

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Datasheet

8.22. Verb – Get Unsolicited Response Control (Verb ID=F08h)

Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an unsolicited response to inform software of a real time event.

Table 57. Verb – Get Unsolicited Response Control (Verb ID=F08h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID= F08h 0’s 32-bit Response

Codec Response for NID=01h (GPIO), 14h~16h, 18h~1Bh (Port jack detection)

Bit Description

31:8 Reserved. Read as 0’s.

7 Unsolicited Response is Enabled.

0: Disabled 1: Enabled

6:4 Reserved. Read as 0’s.

3:0 Assigned Tag for Unsolicited Response.

The tag[3:0] is assigned by software to determine which widget generates unsolicited responses.

Codec Response for other NID

Bit Description

31:0 Not Supported (returns 00000000h).

8.23. Verb – Set Unsolicited Response Control (Verb ID=708h)

Enables a widget to generate an unsolicited response.

Table 58. Verb – Set Unsolicited Response Control (Verb ID=708h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID=708h EnableUnsol [7:0] 0’s for all nodes

‘EnableUnsol’ in Command Bit [7:0]

Bit Description

31:8 Reserved. Read as 0’s.

7 Unsolicited Response.

0: Disable 1: Enable

6 Reserved. Read as 0’s.

5:0 Tag for Unsolicited Responses.

Tag[5:0] is defined by software to assign a 6-bit tag for nodes that are enabled to generate unsolicited responses.

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8.24. Verb – Get Pin Sense (Verb ID=F09h)

Returns the Presence Detect status and the impedance of a device attached to the pin.

Table 59. Verb – Get Pin Sense (Verb ID=F09h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID= F09h 0’s 32-bit Response

Codec Response for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh (Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2)

Bit Description

31 Presence Detect Status.

0: No device is attached to the pin 1: Device is attached to the pin

30:0 Measured Impedance.

The ALC662 does not support hardware impedance detect. This field is read as 0s.

Datasheet

Codec Response for other NID

Bit Description

31:0 Not Supported (returns 00000000h).

8.25. Verb – Execute Pin Sense (Verb ID=709h)

Table 60. Verb – Execute Pin Sense (Verb ID=709h)

Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID= 709h Right Channel[0] 0’s for all nodes

‘Payload’ in Command Bit[7:0] (for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh)

Bit Description

7:1 Reserved. Read as 0’s.

0 Right (Ring) Channel Select.

0: Sense Left channel (Tip) 1: Sense Right channel (Ring) The ALC662 does not support hardware impedance detect and will ignore this control bit.

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Datasheet

8.26. Verb – Get Configuration Default

(Verb ID=F1Ch/F1Dh/F1Eh/F1Fh)

Reads the 32-bit sticky register for each Pin Widget configured by software.

Table 61. Verb – Get Configuration Default (Verb ID=F1Ch/F1Dh/F1Eh/F1Fh)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh Verb ID= F1Ch 0’s 32-bit Response

Codec Response for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh (Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, SPDIF-OUT)

Bit Description

31:0 32-bit configuration information for each pin widget.

Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function Reset Verb).

8.27. Verb – Set Configuration Default Bytes 0, 1, 2, 3

(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)

The BIOS can use this verb to figure out the default conditions (e.g., placement and expected default device) for the Pin Widgets NID=0B~0Fh, 10h, 11h, 1Fh, 20h, and 12h.

Table 62. Verb – Set Configuration Default Bytes 0, 1, 2, 3

(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=Xh

Note: Supported by Pin Widget NID=14h~16h, 18h~1Bh, 1Ch, 1Dh, and 1Eh. Other widgets will ignore this verb.

Verb ID=71Ch,

71Dh, 71Eh, 71Fh

Codec Response for All NID

Bit Description

31:0 0’s.

Label [7:0] 0’s for all nodes

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8.28. Verb – Get BEEP Generator (Verb ID=F0Ah)

Table 63. Verb – Get BEEP Generator (Verb ID= F0Ah)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID= F1Bh 0’s Divider [7:0]

‘Response’ for NID=01h

Bit Description

31:8 Reserved.

7:0 Frequency Divider, F[7:0].

The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in F[7:0].

The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.

Codec Response for Other NID

Bit Description

31:0 0’s.

Datasheet

8.29. Verb – Set BEEP Generator (Verb ID=70Ah)

Table 64. Verb – Set BEEP Generator (Verb ID= 70Ah)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=71Bh Divider [7:0] 0’s for all nodes

‘Divider’ in Set Command

Bit Description

31:8 Reserved.

7:0 Frequency Divider, F[7:0].

The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in F[7:0].

The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.

Note: All nodes except BEEP generator (NID=01h) will ignore this verb.

Codec Response for All NID

Bit Description

31:0 0’s.

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8.30. Verb – Get GPIO Data (Verb ID= F15h)

Table 65. Verb – Get GPIO Data (Verb ID= F15h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=F15h 0’s 32-bit Response

Codec Response for NID=01h (Audio Function Group)

Bit Description

31:2 Reserved.

1:0 GPIO[1:0] Data.

The value written (output) or sensed (input) on the corresponding pin if it is enabled.

Codec Response for Other NID

Bit Description

31:0 0’s.

Datasheet

8.31. Verb – Set GPIO Data (Verb ID= 715h)

Table 66. Verb – Set GPIO Data (Verb ID= 715h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=715h Data [7:0] 0’s for all nodes

‘Data’ in Set command for NID=01h (Audio Function Group)

Bit Description

31:2 Reserved.

1:0 GPIO[1:0] Output Data.

The value written determines the value driven on a pin that is configured as an output pin.

Codec Response for All NID

Bit Description

31:0 0’s.

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8.32. Verb – Get GPIO Enable Mask (Verb ID=F16h)

Table 67. Verb – Get GPIO Enable Mask (Verb ID= F16h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=F16h 0’s EnableMask [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit Description

31:2 Reserved.

1:0 GPIO[1:0] Enable Mask.

0: The corresponding GPIO pin is disabled and is in Hi-Z state 1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control

Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit Description

31:0 0’s.

Datasheet

8.33. Verb – Set GPIO Enable Mask (Verb ID=716h)

Table 68. Verb – Set GPIO Enable Mask (Verb ID=716h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=716h Enable Mask [7:0] 0’s for all nodes

Codec Response for NID=01h (Audio Function Group)

Bit Description

31:2 Reserved.

1:0 GPIO[1:0] Enable Mask.

0: The corresponding GPIO pin is disabled and is in Hi-Z state 1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control

Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for All NID

Bit Description

31:0 0’s.

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8.34. Verb – Get GPIO Direction (Verb ID=F17h)

Table 69. Verb – Get GPIO Direction (Verb ID=F17h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=F17h 0’s Direction [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit Description

31:2 Reserved.

1:0 GPIO[1:0] Direction Control.

0: The corresponding GPIO pin is configured as an input 1: The corresponding GPIO pin is configured as an output

Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit Description

31:0 0’s.

Datasheet

8.35. Verb – Set GPIO Direction (Verb ID=717h)

Table 70. Verb – Set GPIO Direction (Verb ID=717h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=717h Direction [7:0] 0’s for all nodes

Codec Response for NID=01h (Audio Function Group)

Bit Description

31:2 Reserved.

1:0 GPIO[1:0] Direction Control.

0: The corresponding GPIO pin is configured as an input 1: The corresponding GPIO pin is configured as an output

Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit Description

31:0 0’s.

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Datasheet

8.36. Verb – Get GPIO Unsolicited Response Enable Mask

(Verb ID=F19h)

Table 71. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=F19h 0’s UnsolEnable [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit Description

31:2 Reserved.

1:0 GPIO[1:0] Unsolicited Enable Mask.

0: Unsolicited response will not be sent on link 1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed

Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit Description

31:0 0’s.

8.37. Verb – Set GPIO Unsolicited Response Enable Mask

(Verb ID=719h)

Table 72. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=719h UnsolEnable [7:0] 0’s for all nodes

Codec Response for NID=01h (Audio Function Group)

Bit Description

31:2 Reserved.

1:0 GPIO[1:0] Unsolicited Enable Mask.

0: Unsolicited response will not be sent on link 1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed

Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’ and Verb-‘Unsolicited

Response’ for NID=01h are enabled.

Codec Response for Other NID

Bit Description

31:0 0’s.

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Datasheet

8.38. Verb – Get Digital Converter Control 1 & Control 2

(Verb ID= F0Dh, F0Eh)

Table 73. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=06h Verb ID=F0Dh/F0Eh 0’s Bit[31:16]=0’s, Bit[15:0] are SIC bit

NID=06h (SPDIF-OUT Converter) Response to ‘Get verb’ – F0Dh (Control for SIC bit[15:0])

Bit Description – SIC (SPDIF IEC Control) Bit[7:0]

31:16 Read as 0’s.

15 Reserved. Read as 0’s.

14:8 CC[6:0] (Category Code).

7 LEVEL (Generation Level).

6 PRO (Professional or Consumer Format).

0: Consumer format 1: Professional format

5 /AUDIO (Non-Audio Data Type).

0: PCM data 1: AC3 or other digital non-audio data

4 COPY (Copyright).

0: Asserted 1: Not asserted

3 PRE (Pre-Emphasis).

0: None 1: Filter pre-emphasis is 50/15 microseconds

2 VCFG for Validity Control (control V bit and data in Sub-Frame).

1 V for Validity Control (control V bit and data in Sub-Frame).

0 Digital Enable. DigEn.

0: OFF 1: ON

Codec Response for Other NID

Bit Description

31:0 0’s.

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8.39. Verb – Set Digital Converter Control 1 & Control 2

(Verb ID=70Dh, 70Eh)

Table 74. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)

Set Command Format (Verb ID=70Dh, Set Control 1) Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=06h Verb ID=70Dh SIC [7:0] 0’s

Set Command Format (Verb ID=70Eh, Set Control 2) Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=06h Verb ID=70Eh SIC [15:8] 0’s

‘Payload’ in Set Control 1 for NID=06h (SPDIF-OUT Converter)

Bit Description – SIC (SPDIF IEC Control) Bit[7:0]

7 LEVEL (Generation Level).

6 PRO (Professional or Consumer Format).

0: Consumer format 1: Professional format

5 /AUDIO (Non-Audio Data Type).

0: PCM data 1: AC3 or other digital non-audio data

4 COPY (Copyright).

0: Asserted 1: Not asserted

3 PRE (Pre-Emphasis).

0: None 1: Filter pre-emphasis is 50/15 microseconds

2 VCFG for Validity Control (control V bit and data in Sub-Frame).

1 V for Validity Control (control V bit and data in Sub-Frame).

0 Digital Enable. DigEn.

0: OFF 1: ON

Datasheet

‘Payload’ in Set Control 2 for NID=06h (SPDIF-OUT Converter)

Bit Description – SIC (SPDIF IEC Control) Bit[7:0]

7 Reserved. Read as 0’s.

6:0 CC[6:0] (Category Code).

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8.40. Verb – Get Subsystem ID [31:0]

(Verb ID=F20h/F21h/D22h/F23h)

32-bit Read/Write register for Audio Function Group (NID=01h)

Table 75. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)

Get Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd = X Node ID=01h Verb ID=F20h 0s 32-bit Response

Codec Response for NID=01h

Bit Description

31:16 Subsystem ID[23:8] (Default=10ECh).

15:8 Subsystem ID[7:0] (Default=06h).

7:0 Assembly ID[7:0] (Default=62h).

Datasheet

8.41. Verb – Set Subsystem ID [31:0] (Verb ID=723h for [31:24],

722h for [23:16], 721h for [15:8], 720h for [7:0])

Table 76. Verb – Set Subsystem ID [31:0]

(Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])

Set Command Format Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd = X Node ID=01h

Codec Response for all NID

Bit Description

31:0 0s.

Verb ID=723h,

722h, 721h, 720h

Label [7:0] 0s for all nodes

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8.42. Verb – Get EAPD Control (Verb ID=F0Ch)

Table 77. Verb – Get EAPD Control (Verb ID=F0Ch)

Get Command Format (NID=14h and 15h) Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X

Node ID

=14h/15h

Codec Response for NID=14h (FRONT, port-D) and 15h (SURR, port-A)

Bit Description

31:3 Reserved.

2 L-R Swap. The ALC662 does not support swapping left and right channels. Read as 0.

1 EAPD Value.

0: EAPD pin state is low 1: EAPD pin state is high

0 BTL Enable. The ALC662 does not support BTL output. Read as 0.

Verb ID=F0Ch 0s Bit[1] is EAPD Control

Datasheet

Codec Response for Other NID

Bit Description

31:0 0’s.

8.43. Verb – Set EAPD Control (Verb ID=70Ch)

Table 78. Verb – Set EAPD Control (Verb ID=70Ch)

Set Command Format (NID=14h and 15h) Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X

Node ID

=14h/15h

Payload in Set command for NID=14h (FRONT, port-D) and 15h (SURR, port-A)

Bit Description

31:3 Reserved.

2 L-R Swap. The ALC662 does not support swapping left and right channels. Read as 0.

1 EAPD Value.

0: EAPD pin state is low 1: EAPD pin state is high.

Note: Only one physical logic for the EAPD signal.

0 BTL Enable. The ALC662 does not support BTL output. Read as 0.

Verb ID=70Ch Bit[1] is EAPD Control 0s

Codec Response

Bit Description

31:0 0’s.

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8.44. Verb – Function Reset (Verb ID=7FFh)

Table 79. Verb – Function Reset (Verb ID=7FFh)

Command Format (NID=01h) Codec Response Format

Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]

CAd=X Node ID=01h Verb ID=7FFh 0’s 0’s

Codec Response

Bit Description

31:0 Reserved. Read as 0’s.

Note: The Function Reset command causes all widgets to return to their power-on default state.

Datasheet

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Datasheet

9. Electrical Characteristics

9.1.

DC Characteristics

9.1.1. Absolute Maximum Ratings

Table 80. Absolute Maximum Ratings

Parameter Symbol Minimum Typica l Maximum Units

Power Supply

Digital Power for Core Digital Power for HDA Link Analog

Ambient Operating Temperature Ta 0 - +70

Storage Temperature Ts - - +125

Susceptibility Voltage

Digital Pins 3500V

Analog Pins 4000V

*: The digital link power DVDD-IO must be lower than the digital core power DVDD. **: The standard testing condition before shipping is AVDD = 5.0V unless specified. Customers designing with a different

AVDD should contact Realtek technical support representatives for special testing support.

DVDD

DVDD-IO*

AV D D * *

ESD (Electrostatic Discharge)

3.0

1.5

3.0

3.3

5.0

3.6

5.5

V V V

°C

9.1.2. Threshold Voltage

DVDD=3.3V±5%, T

Parameter Symbol Minimum Typ ical Maximum Units

Input Voltage Range V

Low Level Input Voltage (HDA Link) V

High Level Input Voltage (HDA Link) V

Low Level Input Voltage (SPDIF-OUT) V

High Level Input Voltage (SPDIF-OUT) V

High Level Output Voltage V

Low Level Output Voltage V

Input Leakage Current - -10 - 10 µA

Output Leakage Current (Hi-Z) - -10 - 10 µA

Output Buffer Drive Current - - 5 - mA

Internal Pull Up Resistance - - 50k 100k

=25°C, with 50pF external load.

ambient

Table 81. Threshold Voltage

-0.30 - DVDD +0.30 V

- - 0.35*DVDDIO V

0.65*DVDDIO - - V

- - 0.44*DVDD (1.45) V

0.56*DVDD (1.85) - - V

0.9*DVDD - - V

- - 0.1*DVDD V

Ω

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Datasheet

9.1.3. Digital Filter Characteristics

Table 82. Digital Filter Characteristics

Filter Symbol Minimum Typica l Maximum Units

ADC Lowpass Filter Passband 0 - 0.45*Fs kHz

Stopband 0.60*Fs - - kHz

Stopband Rejection - -76.0 - dB

Passband Frequency Response -

DAC Lowpass Filter Passband 0 - 0.45*Fs kHz

Stopband 0.60*Fs - - kHz

Stopband Rejection - -78.5 - dB

Passband Frequency Response -

Note: Fs=Sample rate.

±0.05

- dB

9.1.4. SPDIF Output Characteristics

DVDD= 3.3V, T

Parameter Symbol Minimum Typi cal Maximum Units

SPDIF-OUT High Level Output V

SPDIF-OUT Low Level Output V

=25°C, with 75Ω external load.

ambient

Table 83. SPDIF Output Characteristics

3.0 3.3 - V

- 0 0.3 V

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ALC662 Series

Datasheet

9.2.

AC Characteristics

9.2.1. Link Reset and Initialization Timing

Table 84. Link Reset and Initialization Timing

Parameter Symbol Minimum Typica l Maximum Units

RESET# Active Low Pulse Width T

RESET# Inactive to BCLK Startup Delay for PLL Ready Time

SDI Initialization Request T

4 BCLK 4 BCLK

BCLK

RST

PLL

- - 25 Frame Time

FRAME

100.167 - - µs

100 - - µs

Initialization

>= 4 BCLK

Sequence

SYNC

SDO

SDI

RESET#

RST

Figure 14. Link Reset and Initialization Timing

PLL

Normal Frame

Initialization

Request

FRAME

SYNC

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ALC662 Series

Datasheet

9.2.2. Link Timing Parameters at the Codec

Table 85. Link Timing Parameters at the Codec

Parameter Symbol Minimum Typ ical Maximum Units

BCLK Frequency -

BCLK Period T

BCLK Jitter T

BCLK High Pulse Width T

BCLK Low Pulse Width T

SDO Setup Time at Both Rising and Falling Edge of BCLK

SDO Hold Time at Both Rising and Falling Edge of BCLK

SDI Valid Time After Rising Edge of BCLK (1:50pF external load)

SDI Flight Time T

cycle

jitter

high

low

setup

hold

flight

tco

23.9976 24.0 24.0024 MHz

41.163 41.67 42.171 ns

- 150 500 ps

17.5 (42%) - 24.16 (58%) ns (%)

5 - - ns

3 - 11 ns

0 - 7 ns

T_cycle

T_high

BCLK

T_setup

T_hold

T_low

SDO

T_tco

SDI

T_flight

Figure 15. Link Signal Timing

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ALC662 Series

Datasheet

9.2.3. SPDIF Output Timing

Table 86. SPDIF Output Timing

Parameter Symbol Minimum Typica l Maximum Units

SPDIF-OUT Frequency -

SPDIF-OUT Period T

SPDIF-OUT Jitter T

SPDIF-OUT High Level Width T

SPDIF-OUT Low Level Width T

SPDIF-OUT Rising Time T

SPDIF-OUT Falling Time T

cycle

jitter

High

Low

- 2.0 - ns

rise

fall

- 3.072 - MHz

- 325.6 - ns

- - 4 ns

156.2 (48%) 162.8 (50%) 169.2 (52%) ns (%)

- 2.0 - ns

cycle

rise

high

fall

Figure 16. Output Timing

low

9.2.4. Tes t Mo d e

Codec test mode and Automatic Test Equipment (ATE) mode are not supported.

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Page 76

9.3.

Analog Performance

ALC662 Series

Datasheet

Standard Test Conditions

• T

=25°C, DVDD= 3.3V ±5%, AVDD=5.0V±5%

ambient

• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms

• 10KΩ/50pF load; Test bench Characterization BW: 10Hz~22kHz

Table 87. Analog Performance

Parameter Min Ty p Max Units

Full-Scale Input Voltage All Inputs (Gain=0dB)

ADC

Full-Scale Output Voltage DAC

S/N (A Weighted) ADC

DAC Headphone Amplifier

THD+N (-3dB Test Signal) ADC

DAC

Headphone Amplifier (32Ω Load)

THD+N (-1dB Test Signal for ALC662-VCx) ADC

DAC

Magnitude Response ADC (-3dB lower edge, -1dB higher edge)*

DAC (-3dB lower edge, -1dB higher edge)* Passband ripple for DAC and ADC (ALC662) Passband ripple for DAC and ADC (ALC662-VCx)

Power Supply Rejection Ratio - -40 - dB

Total Out-of-Band Noise (28.8kHz~100kHz) - -60 - dB

Crosstalk Between Output Channel (1kHz/20kHz) - - -90/-80 dB

Output Noise Level During System Activity - - 110 dB

Output Inter-Channel Phase Delay - - 0.2 Degree

Input Impedance (Gain=0dB) - 40 -

Output Impedance Line Output

Amplified Output

Power Supply Current (Normal Operation) AVDD=5V/DVDD=3.3V

Power Supply Current (Power Down Mode) AVDD=5V/DVDD=3.3V

VREFOUTx Output Voltage (AVDD=5.0V) - 2.5 3.2 V

VREFOUTx Output Current (AVDD=5.0V) - 5 - mA

*: The higher edge of magnitudes for DAC and ADC are -0.6dB@20,000Hz.

0 0

-0.20

-0.02

1.6

1.4

90 98 98

-85

-92

-75

-83

-90

100

38/23

0.4/1.1

>20,000 >20,000

+0.20 +0.02

Vrms Vrms

Vrms

dB FSA dB FSA dBFS A

dB FS dB FS dB FS

dB FS dB FS

Hz Hz dB dB

KΩ

Ω

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ALC662 Series

Datasheet

10. Application Circuits

The ALC662 series is fully pin to pin compatible with the ALC88x series. Please contact Realtek to get the latest application circuits. To get the best compatibility in hardware design and software driver, any modifications should be confirmed by Realtek. Realtek may update the latest application circuits onto our website (www.realtek.com) without modifying this data sheet.

10.1. Filter Connection

Resistors placed beside onboad front panel header

Front panel header option-1

FRONT-IO-JD

R2 is for SIDE Output not required for ALC662

20K,1%

Front panel header option-2

LINE2-JD

MIC2-JD

FRONT-IO-JD

5.1K,1% (NC)

CEN-JD

C21

10u

10K,1%

+5VA

SURR-L MIC1-R

SURR-R

CEN

LFE

SIDESURR-L

SIDESURR-R

EAPD

S/PDIF-OUT

+3.3VD

GPIO0

GPIO1

C34

10u

FRONT-L

FRONT-R

Sense B

FRONT-L

FRONT-R

AVDD2

SURR-L

JDREF

SURR-R

AVSS2

CENTER

LFE

EAPD

SPDIFO

DVDD

1234567891011

GPIO0

GPIO1

DVSS

ALC662

MIC1-VREFO-R

SDATA-OUT

C17 10u

MIC2-VREFO

LINE2-VREFO

BIT-CLK

C40 22P

DVSS

SDATA-IN

R16 22

R17 22

MIC1-VREFO-L

DVDD-IO

Figure 17. Filter Connection

MIC1-VREFOR

LINE2-VREFO

VREF

AVSS1

SYNC

RESET#

MIC2-VREFO

MIC1-VREFOL

AVDD1

LINE1-R

LINE1-L

MIC1-R

MIC1-L

CD-R

CD-GND

CD-L

MIC2-R

MIC2-L

LINE2-R

LINE2-L

Sense A

PCBEEP

C33 1u

RESET#

SYNC

SDIN

BCLK

SDOUT

+5VA

C18

10u

C36

100P

LINE1-R

LINE1-L

MIC1-L

MIC2-R

MIC2-L

LINE2-R

LINE2-L

R13 10K

R15

R10

CD-IN Header

5.1K,1%

10K,1%

20K,1%

39.2K,1%

Ext. PCBEEP

4 3 2 1

FRONT-JD

LINE1-JD

MIC1-JD

SURR-JD

FRONT-JD

LINE1-JD

MIC1-JD

SURR-JD

C26 1u

C29 1u

C32 1u

AGNDDGND

Tied at one point only under the codec or near the codec

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ALC662 Series

Datasheet

10.2. Onboard Front Panel Header Connection and Front

Panel I/O

Option 1: Follow Intel's HD Audio front panle header design

(Two ports must be in the same jack detect group)

MIC2-VREFO

1N4148

R11

R12

4.7K

MIC2-L

MIC2-R

LINE2-R

LINE2-L

C35 1u

C37 1u

C38 100u

C39 100u

FRONT-IO-JD

6 7 9

CON10A

Onboard front panel header

Key

MIC2-JD

LINE2-JD

39.2K,1%

PRESENCE#

R19

Option 2: A more flexible front panel header

(Each port can be in different jack detect group)

MIC2-VREFO

1N4148

R20

R21

4.7K

MIC2-L

MIC2-R

LINE2-R

LINE2-L

C44 1u

C46 1u

C48 100u

C51 100u

6 7 9

CON10A

Onboard front panel header

Key

PRESENCE#

R25

R26

Figure 18. Onboard Front Panel Header Connection and Front Panel I/O

R14

10K

R23

10K

20K,1%

39.2K,1%

+3.3VD

R18

20K,1%

+3.3VD

MIC2-JD

LINE2-JD

System GPI

Sense B

HD Audio Front Panel I/O Cable

FIO-PORT1-L FIO-PORT1-R FIO-PORT2-R FIO-SENSE FIO-PORT2-L

FIO-PORT2-R

FIO-PORT2-L

FIO-PORT1-R

FIO-PORT1-L

CON10A

L14 FERB

L15 FERB

L16 FERB

L17 FERB

FIO-PRESENCE# PORT1-SENSE-RETURN

KEY

PORT2-SENSE-RETURN

FIO-SENSE

PORT2-SENSE-RETURN

C41

100P

FIO-SENSE

PORT1-SENSE-RETURN

C49

100P

C42

100P

C50

100P

JACK 7

4 3 5

2 1

FIO-PORT2 (Jack-E)

JACK 8

4 3 5

2 1

FIO-PORT1 (Jack-F)

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Page 79

10.3. Analog Input/Output Connection

ALC662 Series

Datasheet

FRONT-R

FRONT-L

LINE1-R

LINE1-L

MIC1-R

MIC1-L

C1 100u

C3 100u L3 FERB

C9 1u

C11 1u

MIC1-VREFO-L

MIC1-VREFO-R

C22 1u

C24 1u

4.7K

L1 FERB

L6 FERB

L8 FERB

4.7K

L10 FERB

L12 FERB

100PC6100P

C15

100P

C27

100P

FRONT-JD

LINE1-JD

C16

100P

MIC1-JD

C28

100P

JACK 1

4 3 5

2 1

FRONT-OUT

JACK 3

4 3 5

2 1

LINE-IN

4 3 5

2 1

JACK 5

MIC-IN

SURR-R

SURR-L

LFE

CEN

C2 1u

C4 1u L4 FERB

C10 1u

Figure 19. Analog Input/Output Connection

L2 FERB

L7 FERB

L9 FERBC14 1u

C19

100P

CEN-JD

C20

100P

SURR-JD

JACK 2

4 3 5

2 1

SURR-OUT

JACK 4

4 3 5

2 1

CEN/LFE-OUT

10.4. Optional SPDIF Output

S/PDIF module option 1: Optical S/PDIF module option 2: Coaxial

TOTX178

C47

0.1u

+5VD

Optical Transmitter

N.CN.C

VCC

GND

S/PDIF-OUT

Figure 20. Optional SPDIF Output

S/PDIF OUTPUT

(Coaxial)

C43

0.01u

S/PDIF-OUT

C45

100P

R22 200

R24

100

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Page 80

11. Mechanical Dimensions

ALC662 Series

Datasheet

See the Mechanical Dimensions notes on the next page.

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Page 81

11.1. Mechanical Dimensions Notes

ALC662 Series

Datasheet

MILLIMETER INCH SYMBOL

MIN. TYP

A - - 1.60 - - 0.063

A1 0.05 - 0.15 0.002 - 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

c 0.09 - 0.20 0.004 - 0.008

D 9.00 BSC 0.354 BSC

D1 7.00 BSC 0.276 BSC

D2 5.50 0.217

E 9.00 BSC 0.354 BSC

E1 7.00BSC 0.276 BSC

E2 5.50 0.217

b 0.17 0.20 0.27 0.007 0.008 0.011

e 0.50 BSC 0.0196 BSC

TH 0o 3.5o 7o 0o 3.5o 7

L 0.45 0.60 0.75 0.018 0.0236 0.030

L1 - 1.00 - - 0.0393 -

MAX. MIN. TYP MAX

TITLE: LQFP-48 (7.0x7.0x1.6mm)

PACKAGE OUTLINE DRAWING,

FOOTPRINT 2.0mm

LEADFRAME MATERIAL

DOC. NO. APPROVE

VERSION 02

DWG NO. PKGC-065 CHECK

DATE

REALTEK SEMICONDUCTOR CORP.

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Page 82

ALC662 Series

Datasheet

12. Ordering Information

Table 88. Ordering Information

Part Number Package Status

ALC662-GR LQFP-48 ‘Green’ Package Production

ALC662-VC0-GR ALC662 Version C Stepping 0 Silicon, LQFP-48 ‘Green’ Package Production

ALC662-VC1-GR ALC662 Version C Stepping 1 Silicon, LQFP-48 ‘Green’ Package Production

Note 1: See page 6 for Green package and version identification. Note 2: Above parts are tested under AVDD=5.0V. If customers have lower AVDD request, please contact Realtek sales

representatives or agents.

Realtek Semiconductor Corp. Headquarters

No. 2, Innovation Road II Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com

5.1 Channel High Definition Audio Codec 74 Track ID: JATR-1076-21 Rev. 1.3

Realtek ALC662-GR, ALC662-VCO-GR, ALC662-VC1-GR, ALC662 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General Description

2. Features

Hardware Features

Software Features

ALC662-VC Series Upgraded Features for Future WLP

3. System Applications

4. Block Diagram

5. Pin Assignments

Package and Version Identification

6. Pin Descriptions

Digital I/O Pins

Analog I/O Pins

Filter/Reference

Power/Ground

NC (Not Connected) Pins

7. High Definition Audio Link Protocol

Link Signals

7.1.1. Signal Definitions

7.1.2. Signaling Topology

Frame Composition

7.2.1. Outbound Frame – Single SDO

7.2.2. Outbound Frame – Multiple SDOs

7.2.3. Inbound Frame – Single SDI

7.2.4. Inbound Frame – Multiple SDIs

7.2.5. Variable Sample Rates

Reset and Initialization

• Link Reset

7.3.2. Codec Reset

7.3.3. Codec Initialization Sequence

Verb and Response Format

7.4.1. Command Verb Format

7.4.2. Response Format

Power Management

7.5.1. System Power State Definitions

7.5.2. Power Controls in NID 01h

7.5.3. Powered Down Conditions

8. Supported Verbs and Parameters

Verb – Get Parameters (Verb ID=F00h)

8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)

8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)

Verb – Get Connection Select Control (Verb ID=F01h)

Verb – Set Connection Select (Verb ID=701h)

Verb – Get Connection List Entry (Verb ID=F02h)

Verb – Get Processing State (Verb ID=F03h)

Verb – Set Processing State (Verb ID=703h)

Verb – Get Coefficient Index (Verb ID=Dh)

Verb – Set Coefficient Index (Verb ID=5h)

Verb – Get Processing Coefficient (Verb ID=Ch)

9. Electrical Characteristics

DC Characteristics

9.1.1. Absolute Maximum Ratings

9.1.2. Threshold Voltage

9.1.3. Digital Filter Characteristics

9.1.4. SPDIF Output Characteristics

AC Characteristics

9.2.1. Link Reset and Initialization Timing

9.2.2. Link Timing Parameters at the Codec

9.2.3. SPDIF Output Timing

9.2.4. Tes t Mo d e

Analog Performance

10. Application Circuits

11. Mechanical Dimensions

12. Ordering Information