RDA 5851S Datasheet

RDA5851S Datasheet V1.01

RDA5851S Bluetooth Multi-Media Single-Chip Terminal

RDA Microelectronics Inc. CONFIDENTIAL 1 / 72

FEATURES

● External Memory Interface

Integrated 8Mbit(or 1MByte) Flash on chip Power efficient using retention technology to avoid floating lines Flexible IO voltage

● Power Management

Power On reset control Internal 32K OSC for standby/ shutoff/ sleep state Battery charger (from USB or AC charger) Integrated all internal voltages from VBAT Provide all LDOs for external components

● User Interface

ADC serial interface Keypad

● Connectivity

USB 1.1 Device UART interface 1 SD controller I2C controller I2S controller General Purpose I/Os 1 GPADC, 10bits, 1 channel

● Audio

1 channel voice ADC, 8kHz, 13 bits/sample for microphone Voice DAC, 8kHz, 13 bits/sample for receiver High fidelity Stereo DAC, up to 48kHz, 16 bits per sample Stereo analog audio line input

● Debug

Host debug interface allowing non intrusive in depth investigation GDB debugger Execution logger and profiling through debug port High level text based debugging using Host debug or USB

● FM

Integrated Broadcast FM tuner which can be tuned world-wide frequency band

● Bluetooth

Integrated Bluetooth SoC complaint with 2.1 + EDR standard

APPLICATIONS

The high level of integration achieved on RDA5851S allows for highly integrated bluetooth music box and stereo headset without increasing the BOM.

RDA5851S Datasheet V1.01

GENERAL DESCRIPTION

A high performance, high integrated multi-media system-on-chip

solution with Bluetooth connectivity.

RDA5851S is a high performance, highly integrated multi-media system-on-chip solution with bluetooth connectivity. This is a newer generation than 5851, which specialized in music and audio applications, such as bluetooth music boom box, bluetooth stereo headset, etc.

Integrating all essential electronic components, including baseband, bluetooth transceiver, power management, FM receiver onto a single system on chip, RDA5851S offers best in class bill of material, space requirement and cost/feature ratio for bluetooth music and audio application.

Built around a cost effective 32-bit XCPU RISC core running at up to 312MHz with 4k of Instruction cache and 4k of Data cache, RDA5851S offers plenty of processing power for multimedia applications. A high performance proprietary 16/32-bit digital signal processing engine can further improve overall performance and user experience when performing complex multimedia tasks.

It is also packed with impressive connectivity for easy scalability of the system, allowing glue less interfaces to SDMMC Memory Cards and USB (slave, full speed).

Additionally, RDA5851S integrates a FM tuner and a Bluetooth module which completely include digital, analogue and RF function. And they can easily work only with a few passive components as filter or matching network.

RDA5851S is available in a small footprint, fine pitch, 6.5 X 6.5, 81 ball TFBGA package.

RDA Microelectronics Inc. CONFIDENTIAL 2 / 72

RDA5851S Datasheet V1.01

Table of Contents

Features ................................................................................................................................................................ 1

Applications ........................................................................................................................................................... 1

General Description ..............................................................................................................................................2

A. Architecture Overview ......................................................................................................................................6

B. Block Description ........................................................................................................................................... 10

B.I System Modules ......................................................................................................................................10

B.I.1 System CPU (XCPU) ....................................................................................................................... 10

B.I.2 Memory Bridge ................................................................................................................................ 19

Operations ........................................................................................................................................... 20

B.I.3 Direct Memory Access (DMA) .......................................................................................................... 21

B.I.4 Page Spy ......................................................................................................................................... 21

B.I.5 System Intelligent Flow Controller (Sys IFC) ....................................................................................21

AHB2APB bridge operation ..................................................................................................................22

DMA Operations .................................................................................................................................. 22

Debug channel operations ................................................................................................................... 23

B.II System Peripherals ................................................................................................................................. 24

B.II.1 System and Clock Control ..............................................................................................................24

B.II.2 Trace (Normal UART) and Host (Debug UART) Port .....................................................................26

B.II.3 I2C .................................................................................................................................................. 32

B.II.4 General Purpose Input Output .......................................................................................................34

B.II.5 Keypad ........................................................................................................................................... 34

B.II.6 Timers ............................................................................................................................................ 34

B.II.7 Debug Port (EXL, PXTS, Signal Spy) .............................................................................................35

B.II.8 General Purpose Analog to Digital Converter (GP ADC) ................................................................ 35

B.II.9 Timing Control Unit and Low Power Synchronizer (TCU+LPS) ....................................................... 36

B.II.10 System AHB Monitor (Sys AHBC Mon) ........................................................................................36

B.II.11 System IRQ Controller (Sys IRQ) ................................................................................................. 37

B.II.12 USB Controller ..............................................................................................................................37

B.II.13 SD/MMC Controller ....................................................................................................................... 38

B.II.14 Audio Interface Analog + I2S (AIF) ...............................................................................................38

B.III Digital Modules ......................................................................................................................................39

B.III.1 Voice Coprocessor (VoC) .............................................................................................................. 39

B.IV Analog Modules ..................................................................................................................................... 39

SPI Interface for Analog IP control ....................................................................................................... 39

Power Management Unit ...................................................................................................................... 40

Analog module (ABB) ..........................................................................................................................45

B.V FM .......................................................................................................................................................... 47

General Description ............................................................................................................................. 47

Features ............................................................................................................................................... 47

Block Description ................................................................................................................................. 47

Receiver Characteristics ......................................................................................................................48

RDA Microelectronics Inc. CONFIDENTIAL 3 / 72

RDA5851S Datasheet V1.01

B.VI Bluetooth ...............................................................................................................................................49

General Description ............................................................................................................................. 49

Features ............................................................................................................................................... 50

Block Description ................................................................................................................................. 50

Performance Characteristics ................................................................................................................51

C. Memory Map .................................................................................................................................................. 54

D. Pins Description ............................................................................................................................................. 56

D.I Pin-out ..................................................................................................................................................... 56

E. Electrical Characteristics ...............................................................................................................................60

E.I Absolute Maximum Rating ....................................................................................................................... 60

E.II Temperature Characteristics ..................................................................................................................60

E.III Audio Characteristics .............................................................................................................................60

E.V DC Characteristics .................................................................................................................................62

E.VI Digital IO DC Characteristics ................................................................................................................. 67

E.VII Digital IO AC Characteristics (SPI Interface Timing) ............................................................................68

F. Packaging ...................................................................................................................................................... 70

G. Ball Out ......................................................................................................................................................... 71

H. Glossary ........................................................................................................................................................ 72

RDA Microelectronics Inc. CONFIDENTIAL 4 / 72

RDA5851S Datasheet V1.01

Figure Index

Figure B.1: XCPU Block Diagram ..............................................................................................................11

Figure B.2: Typical transfer operation ........................................................................................................ 22

Figure B.3: Debug channel block diagram .................................................................................................24

Figure B.4: General Message Format ........................................................................................................28

Figure B.5: Read Return Message Format ................................................................................................ 28

Figure B.6: Event Message Format ........................................................................................................... 28

Figure B.7: Tx Switch STM ........................................................................................................................ 30

Figure B.8: IrDA SIR Data Format ............................................................................................................. 30

Figure B.9: YUV 4:2:2 Subsampling ...........................................................................................................42

Figure B.10: SPI Write & Read Timing .......................................................................................................46

Figure B.11: PMU Power ON ..................................................................................................................... 47

Figure B.12: POR triggered by POWKEY press ........................................................................................48

Figure B.13: Principle schematic for Power-Profiles usage ........................................................................ 49

Figure B.14: Charging I-V Curve ................................................................................................................51

Figure B.15: PLL Clock Path ...................................................................................................................... 52

Figure B.16: USB PHY FS 1.1 .................................................................................................................. 53

Figure B.17: GPADC Timing Diagram ....................................................................................................... 54

Figure B.18: FM Tuner Block Diagram .......................................................................................................55

Figure B.19: Bluetooth Block Diagram ....................................................................................................... 57

Figure E.1: SCLK Timing Diagram ............................................................................................................. 83

Figure E.2: SPI Write Timing Diagram ......................................................................................................83

Figure E.3: SPI Read Timing Diagram .......................................................................................................84

Figure G.1: RDA5851 Ball out diagram ..................................................................................................... 86

RDA Microelectronics Inc. CONFIDENTIAL 5 / 72

RDA5851S Datasheet V1.01

A. ARCHITECTURE OVERVIEW

RDA5851S is a single chip multi-media solution which integrates PMIC, Audio CODEC, FM, and Bluetooth, as well as all the system requirements for a multi-media platform.

1. Analog modules

○ Analog block:

■ PLL generates 624MHz from 26MHz

■ Differential 13 bit Audio ADC and 16 bit stereo DAC

■ Audio line in

■ Full Speed USB PHY 1.1

■ 1 Channel General Purpose ADC

○ PMU

■ Complete integrated power management system

■ Integrated LDO voltage regulators

○ FM Tuner:

■ Support worldwide frequency band 65-108MHz

■ Digital low-IF tuner

■ Fully integrated digital frequency synthesizer

■ Autonomous search tuning

■ Digital auto gain control (AGC)

■ Digital adaptive noise cancellation

■ Programmable de-emphasis (50/75 ms)

■ Receive signal strength indicator (RSSI)

■ Bass boost

■ Volume control

○ Bluetooth:

■ Completely integrates bluetooth radio transceiver and baseband processor

■ Also includes sub-controller software stack

■ Compliant with Bluetooth 2.1 + EDR specification

2. Digital Module

RDA5851S Digital Baseband is based on two processors: the system processor (XCPU) and the multimedia dedicated processor (BCPU). Each of these processor is on an AHB bus (AMBA AHB compliant). Those buses can communicate through an AHB to AHB interface module. Each AHB bus has a dedicated APB bus (AMBA APB compliant).

RDA Microelectronics Inc. CONFIDENTIAL 6 / 72

RDA5851S Datasheet V1.01

● Memory Bridge

○ internal ROM 20kB for critical constants and code, XCPU boot monitor ○ internal SRAM 64kB for critical data and code. Shared communication memory between the 2

CPUs

○ External Bus Controller (EBC)

16 bit data bus, up to 32MB memory space

● System Modules

○ System CPU (XCPU)

RDA RISC Core

32x32 bits Multiplier Accumulator (MAC)

16/32 bit instruction set 4 kByte Instruction Cache 4 kByte Data Cache

○ DSP Co-Processor (VoC)

Bi-MAC, dual operation unit 16-bit instruction set with 32-bit extension 20 kByte + 20 kByte data RAM on 32 bits 32 kByte instruction RAM on 32 bits

○ Direct Memory Access (DMA)

All size, all alignment and all source and destination possible 32-bit word pattern mode

○ Page Spy

Six memory spaces can be spied

○ System Intelligent Flow Controller (Sys IFC) 7 channels

AHB2APB bridge Four 8-bit or 32-bit DMA channels to accelerate data transfer between peripherals and

memory

Dedicated specialized channels for DBG Host

○ Audio Interface (AIF)

Tone generator 4 samples In and Out Fifos I2S / DAI Interface

Serial Input / Output at 8/16 ks/s

Can be used for test purpose in DAI mode Audio Interface

13 bit RX Data from audio ADC

16 bit TX Data to stereo DAC

○ SPI Flash Controller

Up to size 512Mb x 1, or 256Mb x 1, or 128Mb x 2

● System Peripherals

○ System, PLL and Clock Control (Sys & PLL & Clk Ctrl)

Provides general controls over the whole system, including:

Reset controls

Power management controls

Clock selection

RDA Microelectronics Inc. CONFIDENTIAL 7 / 72

RDA5851S Datasheet V1.01

Some debug features

○ Host Port

Software Flow Control (XON/XOFF) Host Port auto-reseted when a break is detected Multiplexed trace mechanism Clock input allowing up to 1840kbps baud rate independent from the system clock Secured protocol with 8 bits CRC (no error correction)

○ Serial Peripheral Interface (SPI)

Master interface with multi-chip selects 16 bytes FIFO

○ I2C Master Peripheral Interface (I2C)

Master interface

○ General Purpose Input Output (GPIO) ○ ADC serial Keypad ○ SD/MMC Card Controller

can support 2 peripherals SD Card specification Version 2.0 SDIO Version 1.10 MMC specification Version 3.1

○ Timers

1 Real Time Clock Timer (Calendar) 1 24 bits general purpose interval Timers at 16384Hz 1 32 bits uptime counter at 16384Hz 1 Watchdog Timer

○ Debug Port

CPU Execution Logger (EXL): Generate strobe and output the selected CPU's program

counter Program Execution Time Stamp (PXTS): Allow to profile running code Hardware Signal Spy, selection of several hardware signal connected to pins. Access to the last PC of the selected CPU when a watchdog reset occurs

○ General Purpose Analog to Digital Converter (GP ADC)

1 channel inputs generate IRQ when programmed threshold is passed

○ Timing Control Unit (TCU)

Quarter bit precision 60 entries event table

○ System AHB Monitor (Sys AHB Monitor)

Measure some bandwidth information from the System AHB bus:

Global Bus usage Master Bus usage and latency Slave Bus usage and access duration Special resource measurement

Write detection to a single word location

○ System IRQ Controller (Sys IRQ)

Several masking levels:

Module level IRQ Control level

RDA Microelectronics Inc. CONFIDENTIAL 8 / 72

RDA5851S Datasheet V1.01

○ BIST

Internal RAMs and ROM test to reduce testing cost in production

○ USB Controller

Fully compliant to USB Specification Version 1.1 Slave Full Speed (12Mbps) Device

RDA Microelectronics Inc. CONFIDENTIAL 9 / 72

RDA5851S Datasheet V1.01

B. BLOCK DESCRIPTION

B.I System Modules

B.I.1 System CPU (XCPU)

The XCPU RISC is a 16/32-bits processor. Using a Reduced Instruction Set Architecture, an efficient 6-stage instruction pipeline and separated Instruction and Data caches, it provides high performance to the system. The Pipeline Stages are as follows:

● PC. Program Counter. Calculate the address of the next instruction and send it to the instruction cache.

● IF. Instruction Fetch. In this stage the instruction cache is being accessed and the instruction

information is retrieved.

● RF. Register File. The register file is being accessed and the instruction is decoded.

● EX. Execution. The instruction is executed

● DC. Data Memory read and write access.

● WB. Write Back. Results are written back to the register file.

Features

● RDA RISC Core.

○ 32x32-bit Multiplier. ○ 32x32-bit -> 64-bit Multiplier Accumulator (MAC) in 2 cycles (pipelined). ○ Read / Write Buffer. ○ 16/32 bit instruction set.

● 32 interrupt sources.

● 4 kByte Instruction Cache.

● 4 kByte Data Cache.

● 16 byte streaming buffer to accelerate uncached instruction accesses.

Block Diagram

RDA Microelectronics Inc. CONFIDENTIAL 10 / 72

RDA5851S Datasheet V1.01

32-bit Instruction Set

Instruction Formats

The RISC processor supports three instruction formats:

R – Register base instruction format

● RD –Target register

● RS – First operand

● RT – Second operand

● SHAMT – Shift amount for shift instructions

● S Code – Instruction code for R type Instructions

0 RS RT RD SHAMT S Code

I – Immediate operand instruction format

● Opcode –Instruction Code

● RS – Source or Base register

● RT – Target Register or Reg-Immediate

RDA Microelectronics Inc. CONFIDENTIAL 11 / 72

AMBA AHB

System Interface

& Rd / Wr Buffer

Instruction Cache

Exception

Co-processor

Data Cache

Address TranslationExceptions

Integer Pipeline

Multiply Instructions and Operands

Multiplier

Divider

Figure B.1: XCPU Block Diagram

Memory

Management

RDA5851S Datasheet V1.01

● Immediate – 16 bit Immediate or Displacement

Opcode RS RT Immediate

J – Jump instruction format

● Opcode –Instruction Code

● Jump Immediate – Immediate 26 bit for jump instruction address

Opcode Jump Immediate

Supported Instructions

Arithmetic Instructions.

Name Type Description Opcode S-Code

ADD R RD = RS + RT 0x00 0x20

ADDU R Unsigned[RD = RS + RT] 0x00 0x21

SUB R RD = RS – RT 0x00 0x22

SUBU R Unsigned[ RD = RS – RT] 0x00 0x23

ADDI I RT = RS + Signed(Immediate) 0x08 n/a

ADDIU I RT = RS + Unsigned(Immediate) 0x09 n/a

Logical Instructions. Logical instructions are all bit wise operations.

Name Type Description Opcode S-Code

AND R RD = RS and RT 0x00 0x24

OR R RD = RS or RT 0x00 0x25

XOR R RD = RS xor RT 0x00 0x26

NOR R RD = not(RS or RT) 0x00 0x27

ANDI I RT = RS and Zero-extend(Immediate) 0x0c n/a

ORI I RT = RS or Zero-extend(Immediate) 0x0d n/a

XORI I RT = RS xor Zero-extend(Immediate) 0x0e n/a

Shift Instructions.

RDA Microelectronics Inc. CONFIDENTIAL 12 / 72

RDA5851S Datasheet V1.01

Name Type Description Opcode S-Code

SLL R RD = RS << SHAMT 0x00 0x00

SRL R RD = RS >> SHAMT 0x00 0x02

SRA R RD = signed(RS) >> SHAMT 0x00 0x03

SLLV R RD = RS << (RT) 0x00 0x04

SRLV R RD = RS >> (RT) 0x00 0x06

SRAV R RD = signed(RS) >> (RT) 0x00 0x07

Conditional Set Instructions. These instructions are used for magnitude conditional test. If the condition is true, the result register is set to 0x1 otherwise it is set to 0x0.

Name Type Description Opcode S-Code

SLT R RD = 0x1 if(RS < RT) 0x00 0x2a

SLTU R RD = 0x1 when unsigned (RS < RT) 0x00 0x2b

SLTI I RD = 0x1 when (RS < signed(Immediate)) 0x0a n/a

SLTIU I RD = 0x1 when unsigned (RS < signed(Immediate)) 0x0b n/a

Branch Instructions. BEQ and BNE test 2 operands for equal and non equal conditions. The rest of the branch instructions test a single operand with 0. BLTZAL and BGEZAL save the address of the instruction following the delay slot in R31.

Name Type Description Opcode S-Code

BEQ I Branch to ((Immediate + 1) << 2) when RS = RT 0x04

BNE I Branch to ((Immediate + 1) << 2) when RS != RT 0x05

BGEZ I Branch to ((Immediate + 1) << 2) when RS >= 0 0x01 0x01

BLEZ I Branch to ((Immediate + 1) << 2) when RS <= 0 0x06 n/a

BGTZ I Branch to ((Immediate + 1) << 2) when RS > 0 0x07 n/a

BLTZ I Branch to ((Immediate + 1) << 2) when RS < 0 0x01 0x00

BLTZAL I Branch to ((Immediate + 1) << 2) when RS < 0 0x01 0x10

BGEZAL I Branch to ((Immediate + 1) << 2) when RS >= 0 0x01 0x11

Jump Instructions. Jump is performed by combining bit (31:28) of PC with the J_IMME field of the instructions and 0b00 to form the target address. Link instructions also save the address of the instruction following the branch delay slot in R31.

Name Type Description Opcode S-Code

J J Jump 0x02 n/a

JAL J Jump and link 0x03 n/a

JR R Jump register 0x00 0x08

JALR R Jump register and link 0x00 0x09

RDA Microelectronics Inc. CONFIDENTIAL 13 / 72

RDA5851S Datasheet V1.01

Move To and From Multiply and Divide registers.

Name Type Description Opcode S-Code

MFHI R Move from High 0x00 0x10

MTHI R Move to High 0x00 0x11

MFLO R Move from Low (RS = Low) 0x00 0x12

MTLO R Move to Low (Low = RS) 0x00 0x13

Multiply and Divide Instructions.

Name Type Description Opcode S-Code

MULT R Multiply (Low, High) = RS x RT 0x00 0x18

MULTU R Multiply unsigned (Low, High) = RS x RT 0x00 0x19

DIV R Divide (Low, High) = RS x RT 0x00 0x1a

DIVU R Divide unsigned (Low, High) = RS x RT 0x00 0x13

Load Upper Immediate.

Name Type Description Opcode S-Code

LUI I RT[31:16] = Immediate 0x0f

Load and Store Instructions. The address for the load or store is calculated by adding the DISP field to the content of RS. The value read from or written to the memory is from RT.

Name Type Description Opcode S-Code

LB I Load Byte (sign extend) 0x20

LH I Load Half (sign extend) 0x21

LW I Load Word 0x23

LBU I Load Byte (unsigned) 0x24

LHU I Load Half (unsigned) 0x25

SB I Store Byte 0x28

SH I Store Half 0x29

SW I Store Word 0x2b

Miscellaneous. In addition to the standard instructions described above, the RISC processor supports the following instructions.

Name Type Description Opcode S-Code

CACHE n/a See the code below. 0x2f

Cache instruction format:

RDA Microelectronics Inc. CONFIDENTIAL 14 / 72

RDA5851S Datasheet V1.01

Opcode OP1 Address Code

Name Description

Code

Bits [2:0]

Command code as follows: "000" invalidate all lines of both caches ('A' is ignored) "001" invalidate all lines of icache ('A' is ignored, dcache is unaffected) "010" invalidate all lines of dcache ('A' is ignored, icache is unaffected)

“011” not specified, do not use.

"100" invalidate an Icache line whos address is specified by register OP1 "101" invalidate a single line specified by 'A' from icache "110" invalidate a single line specified by 'A' from dcache "111" invalidate a Dcache line whos address is specified by register OP1

Address

Bits [13:3]

or bits [11:3]

or bits [9:3]

The cache line byte address to invalidate. The actual bits used are (RAM_HIGH downto TAG_LOW). The XCPU has a 4K of data and instruction cache with 4W line, so the bits used are (11 downto 3). The BCPU has a 1K of data and instruction cache with 4W line, so the bits used are (9 downto 3).

OP1

Bits [25:21]

Opcode

Bits [31:26]

Value: 0x2f.

MAC Instructions. The multiply and accumulate (MAC) option adds supports for the following instructions.

Name Type Description Opcode S-Code

MADD R

Signed multiply and accumulate. {hi, lo} = {hi, lo} + RS * RT

0x00 0x1c

MADDU R

Unsigned multiply and accumulate. {hi, lo} = {hi, lo} + RS * RT

0x00 0x1d

MSUB R

Signed multiply and subtract. {hi, lo} = {hi, lo} - RS * RT

0x00 0x1e

MSUBU R

Unsigned multiply and subtract. {hi, lo} = {hi, lo} - RS * RT

0x00 0x1f

16-bit Instruction Set

The 16 Bit Instruction mode is an option in the configuration file. This chapter assumes that the user chose to enable this mode. The 16 bit instruction set is provided for situations where reducing code size is a priority.

16 Bit and 32 Bit Instruction Modes

The processor determines the Instruction Mode base on bit 0 of the address of the instruction. When bit 0 of the address of the instruction is 0, the processor is in 32 bit mode, and it interprets the instruction as a 32 bit instruction. When bit 0 of the address of the instruction is set, the processor is in 16 bit mode, and it interprets the instruction as a 16 bit instruction.

In this 32 bit mode:

RDA Microelectronics Inc. CONFIDENTIAL 15 / 72

RDA5851S Datasheet V1.01

1. The instruction counter is incremented by 4 from 1 instruction to the next.

2. For Branch and Link instructions, the processor save the address of the instruction + 8 as the return address. This is the instruction after the delay slot.

3. The processor will take an Illegal Instruction Exception, if either bit 0 or bit 1 are set.

In this 16 bit mode:

1. The instruction counter is incremented by 2 from 1 instruction to the next.

2. For Branch and Link instructions, the processor save the address of the instruction + 4 as the return address. This is the instruction after the delay slot.

3. The processor passes bit 1 of the instruction address to the memory subsystem. Bit 0 is always sent as 0 to the memory subsystem.

Switching between 32 Bit and 16 Bit modes.

To switch between the modes, bit 0 of the instruction address must be changed from 1 to 0 and back. There are 2 basic mechanisms to achieve this.

JALX instruction. This instruction exists in both 32 bit and 16 bit modes. In addition to changing the execution path to the target address, it also toggles bit 0 of the instruction and hence the mode.

JR, JALR instructions. These instructions take the 32 bit contents of a register and use it as the target address. Bit 0 of the register can be set to reflect the mode of the instructions at the target address.

The 16 Bit Mode Instructions

The following instructions are supported:

Name 15 .. 11 10 9 8 7 6 5 4 3 2 1 0

ADDIU2 0 1 0 0 1 rx imm8

ADDIU3 0 1 0 0 0 rx ry 0 imm4

ADDIUPC 0 0 0 0 1 rx imm8

ADDIU2SP 0 1 1 0 0 0 1 1 imm8

ADDIU3SP 0 0 0 0 0 rx imm8

ADDU3 1 1 1 0 0 rx ry rz 0 1

AND 1 1 1 0 1 rx ry 0 1 1 0 0

B 0 0 0 1 0 offset

BEQZ 0 0 1 0 0 rx offset

BNEZ 0 0 1 0 1 rx offset

BREAK 1 1 1 0 1 code 0 0 1 0 1

BTEQZ 0 1 1 0 0 0 0 0 offset

BTNEZ 0 1 1 0 0 0 0 1 offset

CMP 1 1 1 0 1 rx ry 0 1 0 1 0

CMPI 0 1 1 1 0 rx imm8

DIV 1 1 1 0 1 rx ry 1 1 0 1 0

DIVU 1 1 1 0 1 rx ry 1 1 0 1 1

EXTEND 1 1 1 1 0 imm(10:5) imm(15:11)

JAL 0 0 0 1 1 0 target(20:16) target(25:21)

JAL 2nd target(15:0)

RDA Microelectronics Inc. CONFIDENTIAL 16 / 72

RDA5851S Datasheet V1.01

Name 15 .. 11 10 9 8 7 6 5 4 3 2 1 0

JALR 1 1 1 0 1 rx 0 1 0 0 0 0 0 0

JALRC 1 1 1 0 1 rx 1 1 0 0 0 0 0 0

JALX 0 0 0 1 1 1 target(20:16) target(25:21)

JALX 2nd target(15:0)

JRRA 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0

JRRAC 1 1 1 0 1 0 0 0 1 0 1 0 0 0 0 0

JRRX 1 1 1 0 1 rx 0 0 0 0 0 0 0 0

JRRXC 1 1 1 0 1 rx 1 0 0 0 0 0 0 0

LI 0 1 1 0 1 rx offset

LB 1 0 0 0 0 rx ry offset

LBU 1 0 1 0 0 rx ry offset

LH 1 0 0 0 1 rx ry offset

LHU 1 0 1 0 1 rx ry offset

LW 1 0 0 1 1 rx ry offset

LWPC 1 0 1 1 0 rx offset

LWSP 1 0 0 1 0 rx offset

MFHI 1 1 1 0 1 rx 0 0 0 1 0 0 0 0

MFLO 1 1 1 0 1 rx 0 0 0 1 0 0 1 0

MOVEmt32 0 1 1 0 0 1 0 1 r32(2:0) r32(4:3) rz

MOVEmf32 0 1 1 0 0 1 1 1 ry r32

MULT 1 1 1 0 1 rx ry 1 1 0 0 0

MULTU 1 1 1 0 1 rx ry 1 1 0 0 1

NEG 1 1 1 0 1 rx ry 0 1 0 1 1

NOT 1 1 1 0 1 rx ry 0 1 1 1 1

OR 1 1 1 0 1 rx ry 0 1 1 0 1

RESTORE 0 1 1 0 0 1 0 0 0 ra s0 s1 frame size

SAVE 0 1 1 0 0 1 0 0 1 ra s0 s1 frame size

SB 1 1 0 0 0 rx ry offset

SDBBP 1 1 1 1 0 code 0 0 0 0 1

SEB 1 1 1 0 1 rx 1 0 0 1 0 0 0 1

SEH 1 1 1 0 1 rx 1 0 1 1 0 0 0 1

SH 1 1 0 0 1 rx ry offset

SLL 0 0 1 1 0 rx ry sa 0 0

SLLV 1 1 1 0 1 rx ry 0 0 1 0 0

SLT 1 1 1 0 1 rx ry 0 0 0 1 0

SLTI 0 1 0 1 0 rx imm8

SLTIU 0 1 0 1 1 rx imm8

SLTU 1 1 1 0 1 rx ry 0 0 0 1 1

RDA Microelectronics Inc. CONFIDENTIAL 17 / 72

RDA5851S Datasheet V1.01

Name 15 .. 11 10 9 8 7 6 5 4 3 2 1 0

SRA 0 0 1 1 0 rx ry sa 1 1

SRAV 1 1 1 0 1 rx ry 0 0 1 1 1

SRL 0 0 1 1 0 rx ry sa 1 0

SRLV 1 1 1 0 1 rx ry 0 0 1 1 0

SUBU 1 1 1 0 1 rx ry rz 1 1

SW 1 1 0 1 1 rx ry offset

SWSPRX 0 1 1 0 0 rx offset

SWSPRA 0 1 1 0 0 0 1 0 offset

XOR 1 1 1 0 1 rx ry 0 1 1 1 0

ZEB 1 1 1 0 1 rx 0 0 0 1 0 0 0 1

ZEH 1 1 1 0 1 rx 0 0 1 1 0 0 0 1

Memory Map

Processor Address Mapping

The addresses are all byte addresses. The Size description is also in byte. The processor offers four different memory spaces.

Segment Name Base Address Size Description

kseg2 0xc000,0000 0x4000,0000 1 GB mapped and cached

kseg1 0xa000,0000 0x2000,0000 0,5 GB unmapped and uncached

kseg0 0x8000,0000 0x2000,0000 0,5 GB unmapped and cached

kuseg 0x0000,0000 0x8000,0000 2 GB mapped and cached

Note that kuseg and kseg2 are available only with the use of a MMU. As there is no MMU in RDA5851S, attempts to access those memory segments will trigger an exception.

Memory Access Types

In case of cache miss, a cached access will occur and a full line of 4 x 32 bits ( = 16 bytes) will be loaded.

An uncached access will be a single access or a streaming buffer fill (16 bytes), in case of a streaming buffer miss, if this feature is enabled. A configuration bit allows to enable / disable the streaming feature.

Multiplier & Divider

The RISC processor’s multiplier unit implements a 2 cycle fall through algorithm.

The divider uses a step divide algorithm, which takes 36 cycles to complete a divide operation.

RDA Microelectronics Inc. CONFIDENTIAL 18 / 72

RDA5851S Datasheet V1.01

B.I.2 Memory Bridge

The memory bridge is the interface to general memory used by the system, including internal rom, internal sram and access to external memory.

Features

● Dual AHB Slave

○ A rom/sram controller ○ An Asynchronous FIFO to external controller

● The bridge is implemented as a crossbar between the 2 AHB and the 2 controller (rom/sram and FIFO)

● The rom/sram controller can insert wait cycle to the AHB Slave (to manage read/write conflicts and to

allow using slower instance if needed).

● The rom/sram controller integrate a BIST engine to test the ROM by computing a CRC and test the rams with the March C algorithm

● All AHB burst size are supported

○ Wrap will be split at wrap address ○ Burst longer than the data buffer size of the FIFO will be split ○ Read INCR will read a fixed data size

● FIFO data buffer can store 2 requests either read or write (each 4x32 bytes) from either AHB slave interface.

● APB slave for configuration

External Bus Controller Features

● The controller handles 16 bits data bus width only, however 8 bit memory chips can still be used; by

groups of 2. 8 bit peripherals must be connected to the 8 LSBs of data and accessed through even addresses only.

● Manage page mode SRAM or FLASH.

● Manage burst mode PseudoSRAM.

● Manage AD-Mux and AD-Mux burst mode PseudoSRAM.

● 1 Control Register Enable (M_CRE) Output pin in same power domain than other memory IO for

PseudoSRAM register control.

● FIFO interface for address/data path

● APB interface for configuration (subset of the mem bridge APB address space)

AHB Master Features

● AHB Compliant master

● except the 1K crossing limit defined by AMBA (additional logic required)

● Memory space divided in 5 spaces with a base address for each (aligned on n Word address, n=FIFO

data buffer size)

● Do not use WRAP (due to FIFO organization)

● use INCR4, SINGLE or INCR (for 2 or 3 data only) burst type

● FIFO interface for address/data path

● APB interface for configuration (subset of the mem bridge APB address space)

● External clock is provided from outside the IP (and synthesized in the outside clock tree)

RDA Microelectronics Inc. CONFIDENTIAL 19 / 72

RDA5851S Datasheet V1.01

Operations

Dual AHB Operation

The Slave allow simultaneous access to rom/sram controller and FIFO from the two slaves. Access to the rom/sram controller are sequenced using WAIT on AHB (HReady low). Access to the FIFO are sequenced using split when the FIFO busy on the other AHB slave (other split conditions are described bellow in FIFO Operation section).

Arbitration in case of simultaneous access to the same controller: Should try to serve each side (BB and Sys) alternatively. Simultaneous access to rom/sram controller: memorize the last accepted burst. when the two arrives exactly simultaneously reply wait to the memorized side and process the other side. Simultaneous access to FIFO: First serve read of data if data are available for this read. Serve the side that did not enter the FIFO on last Burst in priority.

FIFO Operation

The FIFO can store 2 requests either read or write from either AHB Slave interface. But only one at a time. For each request there is an associated Write Data Buffer and a Read Data Buffer.

If the FIFO is full the master is split, this master will be released when one spot is free in the FIFO (all masters split because FIFO was full are released at the same time).

Write

A burst is stored to the Data buffer until the burst is finished. If the Data buffer is full or the Wrap address of a wrap burst is reached, the Split response is send (the master will be released in the same condition as above).

Read

The request is stored (address, length ...) and the master is split. The master will be released when the Data buffer has been filled by the external controller (EBC or AHB Master). When the Master comes back, the Data are provided, if the master end the burst the transfer is complete (even if there is still some data in the buffer, in this case they are lost) if the master request more than the available Data it receive the Split response and will be released in the same conditions as for FIFO full: the request is not stored.

FIFO Flush status: Read in FIFO at special address space does not impact the external controller but returns when the command has reached the end of the FIFO (so the read returns only when previous writes are done, no pooling is required)

If external controller has error (disabled space for EBC or AHB Error response for master) the FIFO data reads as and error code. “0xD15AB1ED”

EBC Operation

FIFO access are translated to external memory access.

Configuration of Chip select are validated only between access (atomic change)

● Flash block address remapping and M_CRE control registers are placed in the FIFO space to keep accesses in sequence and avoid using FIFO Flush each time.

RDA Microelectronics Inc. CONFIDENTIAL 20 / 72

RDA5851S Datasheet V1.01

B.I.3 Direct Memory Access (DMA)

The DMA controller relieve the CPU from doing generic memory transfers. A data FIFO is integrated to allow burst transfers. It can generate an interrupt to the system CPU at transfer completion.

Read and Write transfers are supported from and to any memory mapped location (external memory, internal SRAM, modules FIFO…). The addresses can be word, halfword or byte aligned. The DMA can also be used in pattern mode. In this case, a 32-bit word will be used to fill the destination memory zone.

Features

● Support for linear memory transfers.

● Support for word, halfword and byte aligned addresses.

● Burst transfer mode and internal FIFO for best performances.

● Autonomous transfer up to 64K byte per transfer.

● Interrupt generation at completion of the transaction.

● Can fill a part of the memory with a 32-bit pattern.

B.I.4 Page Spy

This module is a System spy that detects read or write access into predefined ranges of memory addresses and triggers an interrupt in case of selected access.

Features

● Six memory spaces can be spied.

● Memory space described with a start address (inclusive) and an end address (exclusive) and mode

(detect read, write or both).

● For each space a status register gives the master that triggered the spy, the address that caused it and the mode.

B.I.5 System Intelligent Flow Controller (Sys IFC)

The System Intelligent Flow Controller (SYS_IFC) is a bridge between the system bus and the peripheral bus. The IFC also provides DMA capabilities to allow data transfer from or to peripherals. It supports 7 DMA standard channels for 8-bit or 32-bit and a dedicated DMA channel for the RF SPI module.

Features

● 7 independent DMA channels. internal FIFO of four 32-bit words per channel.

● 1 dedicated DMA channel for the debug host

● Burst mode on AHB bus to enhance transfer rate

● Support 2 types of transfer: memory to peripheral and peripheral to memory

● Incremental address for AHB master access and non-incremental address for APB access.

● Dynamic allocation of the 7 DMA channels, request lines among the following peripherals:

a) SCI

RDA Microelectronics Inc. CONFIDENTIAL 21 / 72

RDA5851S Datasheet V1.01

b) SPI1 c) SPI2 d) SPI3 e) TRACE UART (DBG Host) f) UART g) UART2 h) SDMMC

● Hardware semaphore registers which indicate to the CPU which channel must be used and a global status register indicating which channel is free.

● AHB to APB bridge, write buffer for a single write access the master isn't stalled, no wait state inserted

AHB2APB bridge operation

The SYS_IFC include a bridge between the AHB bus and the APB bus. The SYS_IFC bus is the only one master on the APB bus. The APB bus is a low bandwidth and low power bus mainly used to configure peripheral register or transfer data with the IFC DMA.

Arbitration

The IFC includes some DMA capability which can access to APB bus, in case of 2 accesses simultaneously (AHB slave and DMA channel), request from the AHB has the highest priority. But if processor requests an access to the APB, and the DMA already have an access in progress, the processor will be stalled until the DMA access is finished.

DMA Operations

The SYS IFC includes 7 DMA channels. Each channel can perform data movements between devices in the AHB bus and peripheral on the APB bus.

Typical transfer

The DMA feature is used to automatically transfer data from memory to peripheral or from peripheral to memory. A typical transfer is defined by a start address, the number of bytes to transfer (TC), a direction (Rx or Tx) and a peripheral address.

RDA Microelectronics Inc. CONFIDENTIAL 22 / 72

start_addr

memory

Figure B.2: Typical transfer

operation

+ 50 hidden pages

RDA 5851S Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual