RCA VARIOS 24C16 Diagram



25C080/160

8K/16K 5.0V SPI

FEATURES

• SPI modes 0,0 and 1,1

• 3 MHz Clock Rate

• Single 5V supply

• Low Power CMOS Technology

- Max Write Current: 5 mA

- Read Current: 1.0 mA

- Standby Current: 1 µ A typical

• Organization

- 1024 x 8 for 25C080

- 2048 x 8 for 25C160

• 16 Byte Page

• Self-timed ERASE and WRITE Cycles

• Sequential Read

• Block Write Protection

- Protect none, 1/4, 1/2, or all of Array

• Built-in Write Protection

- Power On/Off Data Protection Circuitry

- Write Latch

- Write Protect Pin

• High Reliability

- Endurance: 10M cycles (guaranteed)

- Data Retention: >200 years

- ESD protection: >4000 V

• 8-pin PDIP/SOIC Packages

• Temperature ranges supported

- Commercial (C): 0 ° C to +70 ° C

- Industrial (I): -40 ° C to +85 ° C

- Automotive (E): -40˚C to +125˚C

DESCRIPTION

The Microchip Technology Inc. 25C080/160 are 8K and
16K bit Serial Electrically Erasable PROMs. The mem­ory is accessed via a simple Serial Peripheral Interface
(SPI) compatible serial bus. The bus signals required
are a clock input (SCK) plus separate data in (SI) and
data out (SO) lines. Access to the device is controlled
through a chip select (CS
of devices to share the same bus.

There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also write
operations to the Status Register can be disabled via
the write protect pin (WP

) input, allowing any number

). While the

).



Bus Serial EEPROM

PACKAGE TYPES

PDIP

CS

SOIC

WP

VSS

CS
SO

WP

VSS

SO

1
2

3

4

1
2

3

4

25C080/160

BLOCK DIAGRAM

Status

Register

I/O Control

Logic

WP

SI

SO
CS

SCK

HOLD

Memory

Control

Logic

Vcc
Vss

8
7

6

5

8

25C080/160

7

6

5

X

Dec

V

CC

HOLD

SCK

SI

V

CC

HOLD

SCK

SI

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp.
R/W Control

SPI is a trademark of Motorola.

1996 Microchip Technology Inc.

Preliminary

DS21147F-page 1



25C080/160

≤

µ

µ

µ

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

V

........................................................................7.0V

CC

All inputs and outputs w.r.t. V

Storage temperature.............................-65˚C to 150˚C

Ambient temperature under bias...........-65˚C to 125˚C

Soldering temperature of leads (10 seconds)...+300˚C

ESD protection on all pins...................................... 4kV

*Stresses above those listed under ‘Maximum ratings’ may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at those or any
other conditions above those indicated in the operational list­ings of this specification is not implied. Exposure to maximum
rating conditions for extended period of time ma y affect de vice
reliability

TABLE 1-1: PIN FUNCTION TABLE

Name Function

CS
SO Serial Data Output

SI Serial Data Input

SCK Serial Clock Input

WP

V

SS

V

CC

HOLD

um Ratings*

SS

Chip Select Input

Write Protect Pin
Ground
Supply V oltage
Hold Input

......-0.6V to V

CC

+1.0V

FIGURE 1-1: AC TEST CIRCUIT

Vcc

2.25 K

SO

1.8 K

1.2 A

C Test Conditions

AC Waveform:

= 0.2V

LO

V

HI

V

= Vcc - 0.2V (Note 1)
= 4.0V (Note 2)

HI

V

Timing Measurement Reference Level

Input 0.5 V
Output 0.5 V

Note 1: For V

2: For V

CC

> 4.0V

CC

4.0V

100 pF

CC
CC

TABLE 1-2: DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted.
V

CC

= 4.5V to 5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40˚C to +125˚C

Parameter Symbol Min Max Units Test Conditions

High level input voltage V
Low level input voltage V
Low level output voltage V
High level output voltage V
Input leakage current I
Output leakage current I

Internal Capacitance

IH1
IL1
OL
OH
LI

LO

INT

C

2.0 V

-0.3 0.8 V
— 0.4 V I

CC

V

-0.5 — V I

-10 10

-10 10
— 7 pF Tamb=25˚C, F

(all inputs and outputs)
Operating Current ICC write — 5 mA V

I

CC

READ

ICC

Standby Current I

READ

CCS

—
—

—5

Note: This parameter is periodically sampled and not 100% tested.

CC

+1 V

1

500

=2.1 mA

OL
OH

=-400 µ A
ACS
ACS

mA

A

µ

ACS

=V

=V

CC

V

CC
CC

V
V

CC

=V

, V

=Vss to V

IH

IN

IH

, V

=Vss to V

OUT

CLK

=5.5V (Note)
=5.5V
=5.5V; 3 MHz

=5.5V; 2 MHz

=5.5V; Vin=0V or V

CC

CC

CC

=3.0 MHz,

CC

DS21147F-page 2

Preliminary

1996 Microchip Technology Inc.

FIGURE 1-2: SERIAL INPUT TIMING

CS

t

CSS

SCK

t

SU

t

HD



25C080/160

t

CSD

t

R

t

F

t

CSH

t

CLD

SI

SO

high impedance

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

t

HI

t

LO

SCK

t

V

SO

SI

MSB out

don’t care

FIGURE 1-4: HOLD TIMING

CS

t

t

HS

HH

LSB inMSB in

t

CSH

t

t

HO

DIS

LSB out

t

t

HS

HH

SCK

SO

SI

n+2 n+1 n n-1

n+2 n+1 n

HOLD

1996 Microchip Technology Inc.

t

HZ

high impedance

don’t care

Preliminary

t

HV

n

t

SU

n

n-1

DS21147F-page 3

25C080/160

TABLE 1-3: AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted.
V

CC

= 4.5V to 5.5V
Commercial (C): Tamb = 0 ° to +70 ° C
Industrial (I): Tamb = -40 ° to +85 ° C
Automotive (E): Tamb = -40˚C to +125˚C

Symbol Parameter Min Max Units Test Conditions

SCK

f
t

CSS

t

CSH

t

CSD

t

SU

t

HD

t

R

t

F

t

HI Clock High Time 150 — ns

t

LO Clock Low Time 150 — ns

t

CLD Clock Delay Time 50 — ns

t

V Output Valid from

HO Output Hold Time 0 — ns

t
t

DIS Output Disable Time — 200 ns

t

HS HOLD Setup Time 100 — ns

t

HH HOLD Hold Time 100 — ns

t

HZ HOLD Low to Output High-Z 100 — ns

t

HV HOLD High to Output Valid 100 — ns

t

WC Internal Write Cycle Time — 5 ms

— Endurance 10M — E/W Cycles 25°C, Vcc = 5.0V, Block Mode

Note 1: This parameter is periodically sampled and not 100% tested.

2: t
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

Clock Frequency — 3 MHz
CS Setup Time 100 — ns
CS

Hold Time 100 — ns
Disable Time 250 — ns

CS
Data Setup Time 30 — ns
Data Hold Time 50 — ns
CLK Rise Time — 2
CLK Fall Time — 2

µ s

s

(Note 1)
(Note 1)

— 150 ns

Clock Low

(Note 1)

(Note 1)
(Note 1)
(Note 2)

(Note 3)

WC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write

cycle is complete.
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.



µ

DS21147F-page 4

Preliminary

1996 Microchip Technology Inc.