RCA VARIOS 24C16 Diagram



25C080/160

8K/16K 5.0V SPI

FEATURES

• SPI modes 0,0 and 1,1

• 3 MHz Clock Rate

• Single 5V supply

• Low Power CMOS Technology

- Max Write Current: 5 mA

- Read Current: 1.0 mA

- Standby Current: 1 µ A typical

• Organization

- 1024 x 8 for 25C080

- 2048 x 8 for 25C160

• 16 Byte Page

• Self-timed ERASE and WRITE Cycles

• Sequential Read

• Block Write Protection

- Protect none, 1/4, 1/2, or all of Array

• Built-in Write Protection

- Power On/Off Data Protection Circuitry

- Write Latch

- Write Protect Pin

• High Reliability

- Endurance: 10M cycles (guaranteed)

- Data Retention: >200 years

- ESD protection: >4000 V

• 8-pin PDIP/SOIC Packages

• Temperature ranges supported

- Commercial (C): 0 ° C to +70 ° C

- Industrial (I): -40 ° C to +85 ° C

- Automotive (E): -40˚C to +125˚C

DESCRIPTION

The Microchip Technology Inc. 25C080/160 are 8K and
16K bit Serial Electrically Erasable PROMs. The mem­ory is accessed via a simple Serial Peripheral Interface
(SPI) compatible serial bus. The bus signals required
are a clock input (SCK) plus separate data in (SI) and
data out (SO) lines. Access to the device is controlled
through a chip select (CS
of devices to share the same bus.

There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also write
operations to the Status Register can be disabled via
the write protect pin (WP

) input, allowing any number

). While the

).



Bus Serial EEPROM

PACKAGE TYPES

PDIP

CS

SOIC

WP

VSS

CS
SO

WP

VSS

SO

1
2

3

4

1
2

3

4

25C080/160

BLOCK DIAGRAM

Status

Register

I/O Control

Logic

WP

SI

SO
CS

SCK

HOLD

Memory

Control

Logic

Vcc
Vss

8
7

6

5

8

25C080/160

7

6

5

X

Dec

V

CC

HOLD

SCK

SI

V

CC

HOLD

SCK

SI

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp.
R/W Control

SPI is a trademark of Motorola.

1996 Microchip Technology Inc.

Preliminary

DS21147F-page 1



25C080/160

≤

µ

µ

µ

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

V

........................................................................7.0V

CC

All inputs and outputs w.r.t. V

Storage temperature.............................-65˚C to 150˚C

Ambient temperature under bias...........-65˚C to 125˚C

Soldering temperature of leads (10 seconds)...+300˚C

ESD protection on all pins...................................... 4kV

*Stresses above those listed under ‘Maximum ratings’ may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at those or any
other conditions above those indicated in the operational list­ings of this specification is not implied. Exposure to maximum
rating conditions for extended period of time ma y affect de vice
reliability

TABLE 1-1: PIN FUNCTION TABLE

Name Function

CS
SO Serial Data Output

SI Serial Data Input

SCK Serial Clock Input

WP

V

SS

V

CC

HOLD

um Ratings*

SS

Chip Select Input

Write Protect Pin
Ground
Supply V oltage
Hold Input

......-0.6V to V

CC

+1.0V

FIGURE 1-1: AC TEST CIRCUIT

Vcc

2.25 K

SO

1.8 K

1.2 A

C Test Conditions

AC Waveform:

= 0.2V

LO

V

HI

V

= Vcc - 0.2V (Note 1)
= 4.0V (Note 2)

HI

V

Timing Measurement Reference Level

Input 0.5 V
Output 0.5 V

Note 1: For V

2: For V

CC

> 4.0V

CC

4.0V

100 pF

CC
CC

TABLE 1-2: DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted.
V

CC

= 4.5V to 5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40˚C to +125˚C

Parameter Symbol Min Max Units Test Conditions

High level input voltage V
Low level input voltage V
Low level output voltage V
High level output voltage V
Input leakage current I
Output leakage current I

Internal Capacitance

IH1
IL1
OL
OH
LI

LO

INT

C

2.0 V

-0.3 0.8 V
— 0.4 V I

CC

V

-0.5 — V I

-10 10

-10 10
— 7 pF Tamb=25˚C, F

(all inputs and outputs)
Operating Current ICC write — 5 mA V

I

CC

READ

ICC

Standby Current I

READ

CCS

—
—

—5

Note: This parameter is periodically sampled and not 100% tested.

CC

+1 V

1

500

=2.1 mA

OL
OH

=-400 µ A
ACS
ACS

mA

A

µ

ACS

=V

=V

CC

V

CC
CC

V
V

CC

=V

, V

=Vss to V

IH

IN

IH

, V

=Vss to V

OUT

CLK

=5.5V (Note)
=5.5V
=5.5V; 3 MHz

=5.5V; 2 MHz

=5.5V; Vin=0V or V

CC

CC

CC

=3.0 MHz,

CC

DS21147F-page 2

Preliminary

1996 Microchip Technology Inc.

FIGURE 1-2: SERIAL INPUT TIMING

CS

t

CSS

SCK

t

SU

t

HD



25C080/160

t

CSD

t

R

t

F

t

CSH

t

CLD

SI

SO

high impedance

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

t

HI

t

LO

SCK

t

V

SO

SI

MSB out

don’t care

FIGURE 1-4: HOLD TIMING

CS

t

t

HS

HH

LSB inMSB in

t

CSH

t

t

HO

DIS

LSB out

t

t

HS

HH

SCK

SO

SI

n+2 n+1 n n-1

n+2 n+1 n

HOLD

1996 Microchip Technology Inc.

t

HZ

high impedance

don’t care

Preliminary

t

HV

n

t

SU

n

n-1

DS21147F-page 3

25C080/160

TABLE 1-3: AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted.
V

CC

= 4.5V to 5.5V
Commercial (C): Tamb = 0 ° to +70 ° C
Industrial (I): Tamb = -40 ° to +85 ° C
Automotive (E): Tamb = -40˚C to +125˚C

Symbol Parameter Min Max Units Test Conditions

SCK

f
t

CSS

t

CSH

t

CSD

t

SU

t

HD

t

R

t

F

t

HI Clock High Time 150 — ns

t

LO Clock Low Time 150 — ns

t

CLD Clock Delay Time 50 — ns

t

V Output Valid from

HO Output Hold Time 0 — ns

t
t

DIS Output Disable Time — 200 ns

t

HS HOLD Setup Time 100 — ns

t

HH HOLD Hold Time 100 — ns

t

HZ HOLD Low to Output High-Z 100 — ns

t

HV HOLD High to Output Valid 100 — ns

t

WC Internal Write Cycle Time — 5 ms

— Endurance 10M — E/W Cycles 25°C, Vcc = 5.0V, Block Mode

Note 1: This parameter is periodically sampled and not 100% tested.

2: t
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

Clock Frequency — 3 MHz
CS Setup Time 100 — ns
CS

Hold Time 100 — ns
Disable Time 250 — ns

CS
Data Setup Time 30 — ns
Data Hold Time 50 — ns
CLK Rise Time — 2
CLK Fall Time — 2

µ s

s

(Note 1)
(Note 1)

— 150 ns

Clock Low

(Note 1)

(Note 1)
(Note 1)
(Note 2)

(Note 3)

WC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write

cycle is complete.
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.



µ

DS21147F-page 4

Preliminary

1996 Microchip Technology Inc.

25C080/160

2.0 PRINCIPLES OF OPERATION

The 25C080/160 is an 1024/2048 byte EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro­controller families, including Microchip’s midrange
PIC16CXX microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly with soft­ware.

The 25C080/160 contains an 8-bit instruction register.
The part is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS
be low and the HOLD
operation. If the WPEN bit in the status register is set,
the WP

pin must be held high to allow writing to the non-

volatile bits in the status register.
T ab le 2-1 contains a list of the possible instruction bytes

and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.

Data is sampled on the first rising edge of SCK after CS
goes low . If the clock line is shared with other peripheral
devices on the SPI bus, the user can assert the HOLD
input and place the 25C080/160 in ‘HOLD’ mode. After
releasing the HOLD
point when the HOLD

pin must be high for the entire

pin, operation will resume from the

was asserted.

2.1 Write Enable (WREN) and Write Disable (WRDI)

The 25C080/160 contains a write enable latch. This
latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch. The following is
a list of conditions under which the write enable latch
will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

pin must

the WREN or WRDI commands regardless of the state
of write protection on the status register. This bit is read
only .

The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.

The Write Protect Enable (WPEN) bit is a non-volatile
bit that is available as an enable bit for the WP
Write Protect (WP
(WPEN) bit in the status register control the program­mable hardware write protect feature. Hardware write
protection is enabled when WP
WPEN bit is high. Hardw are write protection is disabled
when either the WP
When the chip is hardware write protected, only writes
to non-volatile bits in the status register are disabled.
See Table 2-2 for matrix of functionality on the WPEN
bit and Figure 2-1 for a flowchart of Table 2-2. See
Figure 3-5 for RDSR timing sequence.

) pin and the Write Protect Enable

pin is low and the

pin is high or the WPEN bit is low.

pin. The

TABLE 2-1: INSTRUCTION SET

Instruction

Name

WREN 0000 0110 Set the write enable latch

WRDI 0000 0100 Reset the write enable

RDSR 0000 0101 Read status register

WRSR 0000 0001 Write status register (write

READ 0000 0011 Read data from memory

WRITE 0000 0010 Write data to memory

Instruction

Format

Description

(enable write operations)
latch (disable write opera-

tions)

protect enable and block
write protection bits)

array beginning at
selected address

array beginning at
selected address

2.2 Read Status Register (RDSR)

The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format­ted as follows:

7 654 3 2 1 0

WPEN X X X BP1 BP0 WEL WIP

The Write-In-Process (WIP) bit indicates whether the
25C080/160 is busy with a write operation. When set to
a ‘1’ a write is in progress, when set to a ‘0’ no write is
in progress. This bit is read only.

The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array and status register, when set
to a ‘0’ the latch prohibits writes to the array and status
register. The state of this bit can always be updated via

 1996 Microchip Technology Inc. Preliminary DS21147F-page 5

25C080/160

TABLE 2-2: WRITE PROTECT FUNCTIONALITY MATRIX

WPEN WP WEL Protected Blocks Unprotected Blocks Status Register

0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable

FIGURE 2-1: WRITE TO STATUS REGISTER AND/OR ARRAY FLOWCHART

CS Returns High

No

No

Write to

Status Register

Write

to Status

Reg?

WEL = 1?

WP is low?

Yes

WPEN = 1?

Yes

Do not write to

Status Register

No

No

Write

to array?

YesYes

WEL = 1?

YesYes

Write to the

Unprotected Block

Do not write to

No

No

To other
Commands

Array

From other
Commands

Continue

DS21147F-page 6 Preliminary  1996 Microchip Technology Inc.

25C080/160

2.3 Write Status Register (WRSR)

The WRSR instruction allows the user to select one of
four protection options for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg­ments of the array. The partitioning is controlled as illus­trated in table below. See Figure 3-6 for WRSR timing
sequence.

TABLE 2-3: ARRAY PROTECTION

BP1 BP0

0 0 none
0 1 upper 1/4

1 0 upper 1/2

1 1 all

Array Addresses

Write Protected

300h-3FFh for 25C080
600h-7FFh for 25C160

200h-3FFh for 25C080
400h-7FFh for 25C160

000h-3FFh for 25C080
000h-7FFh for 25C160

3.0 DEVICE OPERATION

3.1 Clock and Data Timing

Data input on the SI pin is latched on the rising edge of
SCK. Data is output on the SO pin after the f alling edge
of SCK.

3.2 Read Sequence

The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the 25C080/160 followed by
the 16-bit address, with the five (25C160) or six
(25C080) MSBs of the address being don’t care bits.
After the correct read instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. The data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
address pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($3FF for
25C080, $7FF for 25C160) the address counter rolls
over to address $000 allowing the read cycle to be con­tinued indefinitely. The read operation is terminated by
setting CS

3.3 Write Sequence

Prior to any attempt to write data to the 25C080/160,
the write enable latch must be set by issuing the WREN
instruction (Figure 3-2). This is done by setting CS
and then clocking the proper instruction into the
25C080/160. After all eight bits of the instruction are
transmitted, the CS
write enable latch. If the write operation is initiated

high (see Figure 3-1).

low

must be brought high to set the

immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not hav e been
properly set.

Once the write enable latch is set, the user may pro­ceed by setting the CS
followed b y the 16-bit address, with the five (25C160) or
six (25C080) MSBs of the address being don’t care bits,
and then the data to be written. Up to 16 bytes of data
can be sent to the 25C080/160 before a write cycle is
necessary. The only restriction is that all of the bytes
must reside in the same page. A page address begins
with XXXX XXXX XXXX 0000 and ends with XXXX
XXXX XXXX 1111. If the internal address counter
reaches XXXX XXXX XXXX 1111 and the clock contin­ues, the counter will roll back to the first address of the
page and overwrite any data in the page that may ha ve
been written.

For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)

th

of the n
high at any other time, the write operation will not be
completed. See Figure 3-3 and Figure 3-4 for more
detailed illustrations on the byte write sequence and the
page write sequence, respectively.

While the write is in progress, the status register may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits. A read attempt of a memory array
location will not be possible during a write cycle. When
a write cycle is completed, the write enable latch is
reset

data byte has been clocked in. If CS is brought

low, issuing a write instruction,

3.4 Data Protection

The following protection has been implemented to pre­vent inadvertent writes to the array:

• The write enable latch is reset on power-up.

• A write enable instruction must be issued to set
the write enable latch.

• After a successful byte write, page write, or status
register write, the write enable latch is reset.

•CS

must be set high after the proper number of

clock cycles to start an internal write cycle.

• Access to the array during an internal write cycle
is ignored and programming is continued.

3.5 Power On State

The 25C080/160 powers on in the following state:

• The device is in low power standby mode (CS

• The write enable latch is reset.

• SO is in high impedance state.

• A low level on CS

is required to enter active state.

=1).

 1996 Microchip Technology Inc. Preliminary DS21147F-page 7

25C080/160

FIGURE 3-1: READ SEQUENCE

CS

0 234567891011 21222324252627282930311

SCK

instruction 16 bit address

SI

0100000 1 15 14 13 12 210

high impedance

SO

FIGURE 3-2: WRITE ENABLE SEQUENCE

CS

0 2345671

SCK

SI

SO

010000 01

FIGURE 3-3: WRITE SEQUENCE

CS

8

91011 2122232425262728293031

SCK

SI

0 2345671

instruction 16 bit address data byte

0000000 1 15 14 13 12

high impedance

21076543210

data out

76543210

T

wc

high impedance

SO

DS21147F-page 8 Preliminary  1996 Microchip Technology Inc.

FIGURE 3-4: PAGE WRITE SEQUENCE

CS

8

91011 2122232425262728293031

SCK

SI

CS

0 2345671

instruction 16 bit address data byte 1

0000000 1 15 14 13 12

25C080/160

21076543210

41 42 43 46 47

40

76543210

44 45

data byte 3

SCK

SI

32 34 35 36 37 38 3933

data byte 2

76543210

FIGURE 3-5: READ STATUS REGISTER SEQUENCE

CS

8

9 101112131415

data from status register

7654 210

SCK

SI

SO

0 2345671

instruction

11000000

high impedance

FIGURE 3-6: WRITE STATUS REGISTER SEQUENCE

CS

data byte n (16 max)

76543210

3

8

0 2345671

SCK

instruction data to status register

SI

SO

 1996 Microchip Technology Inc. Preliminary DS21147F-page 9

01000000

high impedance

9 101112131415

7654

210

3

25C080/160

4.0 PIN DESCRIPTIONS

4.1 Chip Select (CS)

A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already in
progress will be completed, regardless of the CS
signal. If CS
device will go into standby mode as soon as the pro­gramming cycle is complete. As soon as the device is
deselected, SO goes to the high impedance state,
allowing multiple parts to share the same SPI bus. A
low to high transition on CS
is what initiates an internal write cycle. After power-up,
a low level on CS
being initiated.

is brought high during a program cycle, the

after a valid write sequence

is required prior to any sequence

4.2 Serial Input (SI)

The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data to be written
to the memory. Input is latched on the rising edge of the
serial clock.

It is possible for the SI pin and the SO pin to be tied
together. With SI and SO tied together, two way com­munication of data can occur using only one microcon­troller I/O line.

4.3 Serial Output (SO)

The SO pin is used to transfer data serially out of the
25C080/160. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.

It is possible for the SI pin and the SO pin to be tied
together. With SI and SO tied together, two way com­munication of data can occur using only one microcon­troller I/O line.

4.4 Serial Clock (SCK)

input

4.5 Write Protect (WP)

This pin is used in conjunction with the WPEN bit in the
status register to prohibit writes to the non-volatile bits
in the status register. When WP
high, writing to the non-volatile bits in the status register
is disabled. All other operations function normally.
When WP
non-volatile bits in the status register operate normally.
If the WPEN bit is set WP
write sequence will disable writing to the status register.
If an internal write cycle has already begun, WP
low will have no effect on the write.

The WP
the status register is low. This allows the user to install
the 25C080/160 in a system with WP
still be able to write to the status register. The WP
functions will be enabled when the WPEN bit is set
high.

is high, all functions, including writes to the

pin function is blocked when the WPEN bit in

is low and WPEN is

low during a status register

going

pin grounded and

pin

4.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the
25C080/160 while in the middle of a serial sequence
without having to re-transmit the entire sequence over
at a later time. It should be held high any time this func­tion is not being used. Once the device is selected and
a serial sequence is underway, the HOLD
pulled low to pause further serial communication with­out resetting the serial sequence. The HOLD
be brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high to
low transition. The 25C080/160 must remain selected
during this sequence. The SI, SCK, and SO pins are in
a high impedance state during the time the part is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD
high while the SCK pin is low , otherwise serial commu­nication will not resume.

pin may be

pin must

must be brought

The SCK is used to synchronize the communication
between a master and the 25C080/160. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.

DS21147F-page 10 Preliminary  1996 Microchip Technology Inc.

25C080/160

25C080/160 Product Identification System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.

25C080/160–E/P

Package: P = Plastic DIP (300 mil body), 8 lead

SN = Plastic SOIC (150 mil body), 8 lead

Temperature Blank = 0°C to +70°C
Range: I = -40°C to +85°C

E = -40°C to +125°C

Device:

25C080/160

SPI Bus Serial EEPROM

25C080T/160T SPI Bus Serial EEPROM (Tape and Reel)

Sales and Support

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

Your local Microchip sales office (see next page)

1.
The Microchip Corporate Literature Center U.S. FAX: [phone]

2.
The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

3.

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

 1996 Microchip Technology Inc. Preliminary DS21147F-page 11

WORLDWIDE SALES & SERVICE

AMERICAS

Corporate Office

Microchip T echnology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone] Fax: [phone]

Technical Support:
Web:

http://www.microchip.com

Atlanta

Microchip T echnology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: [phone] Fax: [phone]

Boston

Microchip T echnology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: [phone] Fax: [phone]

Chicago

Microchip T echnology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: [phone] Fax: [phone]

Dallas

Microchip T echnology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: [phone] Fax: [phone]

Dayton

Microchip T echnology Inc.
Suite 150
Two Prestige Place
Miamisburg, OH 45342
Tel: [phone] Fax: [phone]

Los Angeles

Microchip T echnology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: [phone] Fax: [phone]

New Y ork

Microchip T echnology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: [phone] Fax: [phone]

San Jose

Microchip T echnology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: [phone] Fax: [phone]

Toronto

Microchip T echnology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: [phone] Fax: [phone]

602 786-7627

ASIA/PACIFIC

Hong Kong

Microchip T echnology
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: [phone] Fax: [phone]

India

Microchip T echnology
No. 6, Legacy, Convent Road
Bangalore 560 025 India
Tel: [phone] Fax: [phone]

Korea

Microchip T echnology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: [phone] Fax: [phone]

Shanghai

Microchip T echnology
Unit 406 of Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, Peoples Republic of China
Tel: [phone]
Fax: [phone]

Singapore

Microchip T echnology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: [phone] Fax: [phone]

Taiwan, R.O.C

Microchip T echnology
10F-1C 207
Tung Hua North Road
T aipei, Taiwan, ROC
Tel: [phone] Fax: [phone]

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: [phone] Fax: [phone]

France

Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: [phone] Fax: [phone]

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: [phone] Fax: [phone]

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: [phone] Fax: [phone]

JAPAN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: [phone] Fax: [phone]

11/7/96

All rights reserved.  1996, Microchip Technology Incorporated, USA. 11/96

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre­sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho­rized except with express written approval by Microchip. No licenses are conv e y ed, implicitly or otherwise, under an y intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21147F-page 12 Preliminary  1996 Microchip Technology Inc.

This datasheet has been downloaded from:

www.DatasheetCatalog.com

Datasheets for electronic components.