RCA RDR3600V Service Manual
Communications Systems
RDR3600V
Service Manual
RCA Communications Systems
Circuit Description
、 、 Frequencies constitute
一
The receiver uses secondary frequency conversion. The first IF is 49.95 MHz and the second IF is
450 kHz. The first local oscillation signal is provided by the PLL circuit.
The PLL circuit generates the required transmit frequency
as picture 1 Frequency structu
、 Receiving department
二、
Frequency structure of receiving department as picture 2
re
As picture 2 receiving department
1. The front-end (RF amplifier)
From the antenna signal into the transmit/receive switch diode circuits（D501，D503and D504）to
amplify.This signal passes through BPF (L508) and then enters mixing.These BPFs are adjusted by the
variable capacitors (D505, D506 and D512).The voltage of the input variable capacitor is adjusted by the
voltage output of the microprocessor (U301).
2. First
The signal of the front end is mixed with the first local oscillator signal generated by the PLL
circuit at Q1 to generate a firs
resulting signal is filtered by XF501
mixer
t intermediate frequency signal at a frequency of 49.95 MHz,and the
3. If amplifier circuit
The first intermediate frequency signal eliminates the signal of adjacent channel by crystal filter
(XF501) and amplifi
enters the intermediate frequency system chip (U501).The IF system chip provides a second mixer, a second
local oscillator signal, a limiting amplifier, a quadrature detector, and an RSSI (Received Signal Strength
Indicator).The second mixer mixes the first intermediate frequency signal with a second local oscillation
signal output of 50.8 MHz and generates a second intermediate frequency signal of 400 MHz.
The second intermediate frequency signal continues to cancel the signal of the adjacent channel through
the ceramic filter (CF501).The filtered second intermediate frequency signal is amplified by a limiting
amplifier and demodulated by a quadrature detector with a ceramic discriminator (FD501). The demodulated
signal enters the audio power circuit.
es the first frequency signal by the first intermediate frequency amplifier (Q507) and
4. wide / narrow switching circuit
t the width and width of each channel by turning on the wide and narrow card switch.
Se
When receiving WIDE (low level) data, Q511 connected.
When receiving NARROW (high) data, Q511 is disconnected.
Q511 is turned on / off with wide / narrow data, the U501 detector output level changes
frequently, with a constant output level that maintains a wide or narrow signal process.
as
picture 3 Wide / narrow switching ci
5. Audio amplifier circuit
rcuit
The demodulated signal from U501 is sent to the audio amplifier via U102.The signal is output by AF
volume control and amplified by audio power am
6. Sque
modified by the filter and amplifier to generate the DC voltage corresponding to the noise level.The DC
signal is sent to the analog port (U301) of the microprocessor via the U261. U301 determines whether to
output sound from the speaker by detecting whether the input voltage is higher or lower than the preset
value.When the sound is output from the speaker, U301 sends a high level signal to the SP MUTE line and
turns on the U561.（as picture 4）
lch
part of the AF signal output by the U601 enters the IC, and the noise component is amplified and
A
plifier (U204) to loudspeaker
As picture 4 AFamplifier and squelch
7. Receive signaling
1) QT/DQT
The
signal output by U601 enters microprocess (U301) through U201. U301 Determines whether QT or DQT
matches the set value, and controls the SP MUTE and speaker output sound based on this result
2) MSK（Fleet Sync）
The MSK input signal from the FM IC is sent to U201. The signal is mediated in the MSK mediator on
U201. The mediated data is sent to the CPU for processing.
3) DTMF
U601 DTMF output signal to U201. The decoded data has CPU processing.
三、 、 PLL frequency synthesis
The PLL circuit generates the first oscillation signal for reception and the RF signal for emission.
1. PLL
The frequency step of the circuit 5 or 6.25KHz.The output signal of the reference oscillator (VCO) of 16.8MHz is
amplified by Q605 buffer, and then divided by a programmable dual module counter in U601.The frequency division
signals are compared in the corresponding comparators of the U601.The generated signal is filtered through a low-pass
filter and transmitted to the VCO to control the oscillator frequency. (as picture 5)
2. VCO
The frequency used is generated by the Q601 in the transmit mode and is generated by Q603 in the receiving mode.
The oscillation frequency is controlled by feeding the VCO control voltage obtained from the phase comparator to the
shell diode (D607 and D608 in the mode of transmission, D602 and D605 in the reception mode).When receiving, the RX
pin is set to high, so that the Q602 is connected. At launch, the TX pin is set to high, amplifying the Q602 and
transmitting it to the RF amplifier.
as picture 5 PLL Circuit
3. Lo
and D601 lowers the input voltage of the microprocessor. The microprocessor detects this condition
after the launch is disabled, ignoring the PTT switch input signal.
ss of lock detector
If the pulse signal appears on the PLD pin, a lockout occurs,The DC voltage obtained from C671, R623
4. Tra
nsmitter system
1) Microphone amplifier
he signal from the microphone passes through the U201. When the encoder is DTMF, the input signal of
T
the microphone is closed by U201. The signal is modulated by audio processing (U204), and then sent to VCO
modulation input.
as picture 6 Microphone amplifier
2) Drive and terminal amplifier
T
he signal from the VCO is amplified by the pre-driver amplifier (Q503) and the driver amplifier (Q502)
to 50mW.The output of the driver amplifier is amplified by the RF power amplifier (Q501) to 4.0W (1W at
low power). The RF power amplifier is composed of two MOSFETs. The output of the RF power amplifier is
connected by a harmonic filter (LPF) and an antenna switch ( D501) and sent to the antenna terminal.
3) Automatic power control (APC) circuit
APC circuit monitors the current through the RF power amplifier (Q501) and keeps the current
The
stable. Changes in the current through the RF power amplifier cause the voltage drop of the R559, R560
and R561 to be sent to the differential amplifier U502A.U502B compares the output voltage of U502A from
the reference voltage of U301.U502B output voltage control RF power amplifier, drive amplifier, pre-drive
amplifier VG, so that the voltage remains the same.
High / low power changes are achieved by changing the reference voltage
502
301
as picture 7 Driver, terminal amplifier and APC ci
5. Po
wer Supply
The machine is powered by 3 5V power supplies to the microprocessor:5C,5R and 5T,At the same
time, when the power is switched on, a 3.3V keeps the output, although the 3.3V is often output,
but when the power is turned off, it is also turned off to prevent the microprocessor from
failure.
5C for the public 5V, in the non-power state to keep the output.
5R is the 5V used for reception and maintains output during reception.
5T is the 5V used for launch and remains output during launch.
rcuit
6. control circuit
Th
e control circuit is composed of microprocessor (U301) and external circuit. The main
functions of U301 are as follows:
a) a) According to the PTT input signal to convert and receive the state.
b) b) Read the system, group, frequency, and programming data from the memory circuit.
c) c) Send the frequency data to the PLL.
d) d) According to the squelch circuit output DC voltage to control the audio mute.
e) e) Control audio mute based on decoded data.
f) f) Launch Tone and programming data.
1) Frequency offset circuit
The microprocessor (U301) operates under the 8MHz clock. The oscillator has a circuit that can be converted
to U308 frequency.
If the "Beat Shift" is set to ON, the beat tone can be avoided.
302
as picture 8 Frequency offset circuit
2) Battery low voltage warning
The battery voltage is monitored by the microprocessor and a warning
tone is issued when the warning voltage is lower than the warning
voltage
a) The warning light flashes when the battery voltage is below 6.8V.
b) In the launch, when the battery voltage is below 5.8V, the handset
is forbidden to launch.
c) When the battery voltage drops to less than 5.3V, the hand held
machine.
7. Control system
Key and Channel Selector Circuit:
The keys and channel selector signals are input directly to the microprocessor.
Pin definition
Each pin is assigned as shown in chart 1.
chart 1---CPU pin definition:
Pin Type Name
pin definition Description
1 O PE2 FLASH_CS
FLASH_SCLK/
2 O PE3
LCD_DB6
3 I PE4 FLASH_SDO
FLASH_SDI/
4 O PE5
LCD_DB7
5 O PE6 DMR_SLEEP
6 S VBAT VBAT
7 O PC13 TX_LED
8 O PC14 RX_LED
9 O PC15 LAMP
10 S VSS_5 VSS_5
11 S VDD_5 VDD_5
12 I OSC_IN OSC_IN
13 O OSC_OUT OSC_OUT
14 I RESET RESET
15 I PC0/EXTI0 TIME_SLOT_INTER
Connect the serial FLASH to the first foot CS
Connect serial FLASH sixth pin SCK, multiplexing
to
LCD_DB6
Connect serial FLASH second pin SO
Connect serial FLASH fifth foot SI, multiplexing
o LCD_DB7
t
Connect HR_C5000 forty-seventh pin POWERDOWN; high level effective.
Connect VDD with 0Ω resistor.
TX_LED control; active high.
RRX LED control; active high.
Key backlight control, active high
Connect VSSA.
Connect 3.3V.
Connect 8MHz crystal, 20pF capacitor ground.
With 0Ω resistor, connect 8MHz crystal, 20pF capacitor ground
Connect reset chip; active low. Reserved JTAG RESET
Connect to HR_C5000 at 48 feet TIME_SLOT_INTER
16 I PC1/EXTI1 SYS_INTER
17 I PC2/EXTI2 RF_TX_INTER
PC3/EXTI3/
18 I
RF_RX_INTER
AD123_IN13
19 S VDD VDD
20 S VSS VSS
21 S VREF+ VREF+
22 S VDDA VDDA
PA0/
23 I
MANDOWN
ADC123_IN0
PA1/
24 I
BATT
ADC123_IN1
PA2/
25 I
QT/DQT_IN
ADC123_IN2
PA3/
26 I
VOX
ADC123_IN3
27 S VSS_4 VSS_4
cess to HR_C5000 pin 49 SYS_INTER
Ac
C
onnect to HR_C5000 at 50 feet RF_TX_INTER
onnect HR_C5000 fifty-first foot RF_RX_INTER.
C
onnect 3.3V.
C
onnect VSSA
C
onnect 3.3V.
C
onnect 3.3V.
C
ANDOWN input;
M
attery voltage detection.
B
T/DQT input;
Q
VOX detection input
onnect VSSA
C
28 S VDD_4 VDD_4
29 O PA4/ APC/TV
onnect 3.3V.
C
Transmit power control and receive tuned D / A outputs
DAC_OUT1
30 O
MOD2_BIAS
DAC_OUT2
PA6/
PA5/
31 I
POWER_DET
ADC12_IN6
32 O PA7 POWER_C
33 O PC4 RF_APC_SW
34 O PC5 5TC
PB0/
35 I
RSSI
ADC12_IN8
PB1/
36 I
BUSY
ADC12_IN9
BOOT1/
37 I/O PB2/BOOT1
FM_SW
38 O PE7 FM_MUTE
39 O PE8 VCOVCC_SW
40 O PE9 DMR_SW
41 O PE10 VOL_MAX
42 O PE11 MIC_SW
Co
ntrols the TCXO reference frequency D / A
output
wer switch input.
Po
wer on control; active high.
Po
RF amplifier switch control; active high.
power control, active high.
5T
SI detection input.
RS
USY detection
B
T
he default 10K resistor is grounded.
F
M receive channel mute control.
RXVCO / TXVCO power control.
MR receive IF path switch control
D
aximum volume control, active high.
M
I
nternal MIC mute control, high level INT_MIC.
43 I PE12 PTT_KEY
44 I PE13 ALARM_KEY
45 I PE14 ENCODE_IN0
46 I PE15 ENCODE_IN1
47 I PB10 ENCODE_IN2
48 I PB11 ENCODE_IN3
49 S VCAP_1 VCAP_1
50 S VDD_1 VDD_1
PB12/
51 O
DMR_CS
SPI2_NSS
PB13/
52 O
DMR_SCLK
SPI2_SCK
PB14/
53 I
DMR_SDO
SPI2_MISO
PB15/
54 O
DMR_SDI
SPI2_MOSI
55 I PD8 PLL_LD
56 O PD9 PLL_CS
57 O PD10 PLL_DAT
TT key input
P
larm key input
A
hannel coding input 0
C
hannel coding input 1
C
hannel coding input 2
C
hannel coding input 3
C
E
xternal capacitor to ground.
onnect 3.3V.
C
onnect to HR_C5000 at pin 58 U_CS.
C
C
onnect to HR_C5000 at pin 57 U_SCLK
onnect to HR_C5000 at pin 55 U_SDO
C
onnect to HR_C5000 at pin 56 U_SDI
C
LL lock detection, high when locked.
P
LL enable control
P
P
PLL_DAT output control
58 O PD11 PLL_CLK
LL_CLK clock pin
P
59 O PD12 LCD_RES LCD_RES
60 O PD13 LCD_A0 LCD_A0
61 O PD14 LCD_CS1 LCD_CS1
62 O PD15 FL_C
Fast lock voltage output control, active high
63 O PC6/TIM8_CH1 FAST_LOCK
64 O PC7/TIM8_CH2 CTC/DCS_OUT
65 O PC8/TIM8_CH3 BEEP
66 O PC9 5RC
67 O PA8 SAVE
PA9/
串口TXD/
68 I/O
USART1_TX
PA10/
SELC
串口RXD/
69 I
USART1_RX
EXT_PTT
70 I/O PA11/USBDM USBD-
71 I/O PA12/USBDP USBD+
JTMS-SWDIO/
SWDIO/
72 I/O
PA13
WORN_SW
73 S VCAP_2 VCAP_2
74 S VSS_2 VSS_2
75 S VDD_2 VDD_2
Fast lock voltage output control, active high.
/ DCS PWM output to TCXO
CTC
/ ALARM / DTMF PWM output
BEEP
5R power control, active high.
5C power supply power control; active high.
Reserved Bootloader TX; Alternate external access control
input, then the first part of the external accessories.
Reserved Bootloader RX; multiplexed external
PTT input, external accessory pin 9.
USB data cable DM, then the external accessories 5 feet
USB data cable DP, access to external accessories 4 feet.
served JTAG interface.
Re
ternal capacitor to ground.
Ex
ound
Gr
nnect 3.3V.
Co
JTCK-SWCLK/
SWCLK/
76 I/O
PA14
MANDOWN_SW
PA15/
77 O
I2S_FS
I2S3_WS
PC10/
78 O
I2S_CK
I2S3_CK
PC11/
79 O
I2S_RX
I2S3ext_SD
PC12/
80 I
I2S_TX
I2S3_SD
81 I/O PD0 K2
82 I/O PD1 K3
83 I/O PD2 K4
84 I/O PD3 K5
85 I/O PD4 K6
86 I/O PD5 K7
87 I/O PD6 K8
88 O PD7 V_CS
served JTAG interface; multiplexed access
Re
to external accessories 12 feet.
Co
nnect to HR_C5000 pin 37 I2S_FS
C
nnect the HR_C5000 to the 36th foot I2S_CK
o
nnect HR_C5000 pin 34 I2S_RX
Co
nnect HR_C5000 to pin 35 I2S_TX
Co
Pr
ess key K2 to enter
ess key K3 to enter
Pr
ess key K4 to enter
Pr
Pr
ess key K5 to enter
Press key K6 to enter
Pr
ess key K7 to enter
Pr
ess key K8 to enter
Connect HR_C5000 to pin 44 V_CS
89 O
PB3/
SPI3_SCK
V_SCLK
Co
nnect the HR_C5000 to the 43rd pin V_SCLK
90 I
PB4/
SPI3_MISO
V_SDO
nect HR_C5000 to pin 42 V_SDO
Con
91 O
V_SDI
SPI3_MOSI
92 O PB6 SELECT
93 O PB7 MODE
94 I BOOT0 BOOT0
PB8/
PB5/
95 O
SCL
I2C1_SCL
PB9/
96 O
SDA
I2C1_SDA
97 O PE0 K0
98 O PE1 K1
99 S VSS_3 VSS_3
100 S VDD_3 VDD_3
nect HR_C5000 to pin 41 V_SDI
Con
Internal external audio output selection, high level external.
Audio amplifier control, high level open.
The default 10K pull-down resistor is grounded.
nnect the chip to the third pin, an external
Co
pull-up resistor to 3.3V.
Connect the encryption chip pin 4, external
pull-up resistor to 3.3V.
Pre
ss key K0 to enter
ess key K1 to enter
Pr
round
G
onnect 3.3V.
C
chart 2--- CPU pin Port definition:
Pin
Pin Type Name
definition
Exp
lain
23 I
MANDOWN
ADC123_IN0
PA1/
PA0/
24 I
BATT
ADC123_IN1
PA2/
25 I
QT/DQT_IN
ADC123_IN2
PA3/
26 I
VOX
ADC123_IN3
PA4/
29 O
APC/TV
DAC_OUT1
PA5/
30 O
MOD2_BIAS
DAC_OUT2
PA6/
31 I
POWER_DET
ADC12_IN6
32 O PA7 POWER_C
67 O PA8 SAVE
PA9/
串口TXD/
68 I/O
USART1_TX
PA10/
SELC
串口RXD/
69 I
USART1_RX
EXT_PTT
70 I/O PA11/USBDM USBD-
served) MANDOWN input;
(Re
Batt
ery voltage detection; the maximum input
voltage of 2.8v.
DQT input
QT/
VOX detection input
ansmit power control and receive tuned
Tr
D / A outputs
ontrols the TCXO reference frequency D /
C
A output
ower switch input, high level indicates
P
that the power is turned on.
ower on control; active high.
P
5
C power supply power control; active high.
Reserved Bootloader TX; Alternate external access control
input, then the first part of the external accessories.
Reserved Bootloader RX; multiplexed external PTT input,
external accessory pin 9.
SB data cable DM, then the external
U
accessories 5 feet.
71 I/O PA12/USBDP USBD+
JTMS-SWDIO/
SWDIO/
72 I/O
PA13
JTCK-SWCLK/
WORN_SW
SWCLK/
76 I/O
PA14
MANDOWN_SW
PA15/
77 O
I2S_FS
I2S3_WS
PB0/
35 I
RSSI
ADC12_IN8
PB1/
36 I
BUSY
ADC12_IN9
BOOT1/
37 I/O PB2/BOOT1
FM_SW
PB3/
89 O
V_SCLK
SPI3_SCK
USB data cable DP, access to external accessories 4
feet.
Reserved JTAG interface; multiplexed with external accessories
pin 2. Reserved wide and narrowband to receive volume switching,
Reserved JTAG interface; multiplexed access to external
accessories 12 feet. Reserved MANDOWN power switch, active
The default 10K resistor is grounded. Used as output port,
the default working state is 0, reduce power consumption.
Multiplexed for FM reception IF channel switch control;
C
onnect the HR_C5000 to the 43rd pin V_SCLK
high level for broadband.
high.
C
onnect to HR_C5000 pin 37 I2S_FS
SSI detection input
R
USY detection
B
active high.
90 I
PB4/
SPI3_MISO
V_SDO
Connect HR_C5000 to pin 42 V_SDO
91 O
V_SDI
SPI3_MOSI
92 O PB6 SELECT
93 O PB7 MODE
PB8/
PB5/
95 O
SCL
I2C1_SCL
PB9/
96 O
SDA
I2C1_SDA
47 I PB10 ENCODE_IN2
48 I PB11 ENCODE_IN3
PB12/
51 O
DMR_CS
SPI2_NSS
PB13/
52 O
DMR_SCLK
SPI2_SCK
PB14/
53 I
DMR_SDO
SPI2_MISO
PB15/
54 O
DMR_SDI
SPI2_MOSI
15 I PC0/EXTI0 TIME_SLOT_INTER
Connect HR_C5000 to pin 41 V_SDI
Internal external audio output selection, high level external.
Audio amplifier control, high level open
Conn
ect the chip to the third pin, an external
pull-up resistor to 3.3V.
n
ect the encryption chip pin 4, external
Con
pull-up resistor to 3.3V.
Channel code input 2
Channel code input 3
ect the HR_C5000 58th U_CS, an external
Conn
pull-up resistor to 3.3V.
nect to HR_C5000 at pin 57 U_SCLK
Con
Co
nnect to HR_C5000 at pin 55 U_SDO
Co
nnect to HR_C5000 at pin 56 U_SDI
Connect to HR_C5000 at 48 feet TIME_SLOT_INTER
16 I PC1/EXTI1 SYS_INTER
17 I PC2/EXTI2 RF_TX_INTER
PC3/EXTI3/
18 I
RF_RX_INTER
AD123_IN13
33 O PC4 RF_APC_SW
34 O PC5 5TC
63 O PC6/TIM8_CH1 FAST_LOCK
64 O PC7/TIM8_CH2 CTC/DCS_OUT
65 O PC8/TIM8_CH3 BEEP
66 O PC9 5RC
PC10/
78 O
I2S_CK
I2S3_CK
PC11/
79 O
I2S_RX
I2S3ext_SD
PC12/
80 I
I2S_TX
I2S3_SD
7 O PC13 TX_LED
nnect to HR_C5000 pin 49 SYS_INTER
Co
Co
nnect to HR_C5000 at 50 feet RF_TX_INTER
Connect HR_C5000 pin 51 RF_RX_INTER. Reserved
fo
r 2T / 5T / DTMF input detection.
RF
amplifier switch control; active high.
5T
power control, active high.
st lock voltage PWM output
Fa
C / DCS PWM output to TCXO
CT
EP / ALARM / DTMF PWM output
BE
power control, active high.
5R
Co
nnect the HR_C5000 to the 36th foot I2S_CK
C
onnect HR_C5000 pin 34 I2S_RX
C
onnect HR_C5000 to pin 35 I2S_TX
X_LED control; active high.
T
8 O PC14 RX_LED
9 O PC15 LAMP
X LED control; active high.
R
ey backlight control, active high
K
81 I/O PD0 K2
82 I/O PD1 K3
83 I/O PD2 K4
84 I/O PD3 K5
ss key K2 to enter
Pre
Pre
ss key K3 to enter
Pre
ss key K4 to enter
ss key K5 to enter
Pre
85 I/O PD4 K6
86 I/O PD5 K7
87 I/O PD6 K8
88 O PD7 V_CS
55 I PD8 PLL_LD
56 O PD9 PLL_CS
57 O PD10 PLL_DAT
58 O PD11 PLL_CLK
Pre
ss key K6 to enter
ss key K7 to enter
Pre
ss key K8 to enter
Pre
nect HR_C5000 to pin 44 V_CS
Con
PLL lock detection, high when locked.
PLL enable control
PLL_DAT output control
_CLK clock pin
PLL
59 O PD12 LCD_RES LCD_RES
60 O PD13 LCD_A0 LCD_A0
61 O PD14 LCD_CS1 LCD_CS1
62 O PD15 FL_C
97 O PE0 K0
98 O PE1 K1
1 O PE2 FLASH_CS
FLASH_SCLK/
2 O PE3
LCD_DB6
Fast lock voltage output control, active high.
ss key K0 to enter
Pre
ss key K1 to enter
Pre
Con
nect the serial FLASH to the first foot CS
nect the serial FLASH 6th SCK, multiplexed
Con
with LCD_DB6
3 I PE4 FLASH_SDO
FLASH_SDI/
4 O PE5
LCD_DB7
5 O PE6 DMR_SLEEP
38 O PE7 FM_MUTE
39 O PE8 VCOVCC_SW
40 O PE9 DMR_SW
41 O PE10 VOL_MAX
42 O PE11 MIC_SW
43 I PE12 PTT_KEY
44 I PE13 ALARM_KEY
45 I PE14 ENCODE_IN0
46 I PE15 ENCODE_IN1
Con
nect Serial Flash 2nd Foot SO
Connect the serial FLASH pin 5, multiplexed to
LCD_DB7
Connect HR_C5000 47th POWERDOWN; active
h
igh. External pull-up resistor to 3.3V.
FM receive channel mute control; active high.
RXVCO / TXVCO power control.
DMR receive IF channel switch control, active high.
Ma
ximum volume control, active high.
I
ternal MIC mute control, active high.
n
T key input
PT
arm key input
Al
annel code input 0
Ch
annel code input 1
Ch
BOM
parameter
16.8MHz
1XTV16800CFA
3225
1
X601
1SR154-400
D1210
1
D402
1SS372
1SS372
3
D101 D114-115
29.4912MHz
1XTW29491CAA
3225
1
X201
2SA1586
2SA1586
1
Q105
2SC3356
SOT-23
4
Q503-504 Q601 Q603
PBR951
SOT-23
2
Q507 Q509
2SC4116 2SC4116 1 Q103
KTC4075
2SJ243
2SJ243
2
Q101 Q607
2SK1824
SOT-523
1
Q104
ELFY450H 450KHZ 1 CF501
LTWC450H
8MHz
1C208000BB0B
3225
1
X301
AD2736
SOT23-6
1
U401
SKY72310
SKY72310-S62LF
QFN-24
1
U601
SKRTLAE010
SKRTLAE010
ALARM-PX780
1
SW301
HR_V3000S/ALPU-MP
HR_V3000S/ALPU-MP
SOT23-6
1
U307
AT41511
AT41511
1
Q505
BATTERY-CON
CBC47S13D
CBC47S13D
1
J401
BLM21PG221S BLM21PG221S L0805 3 L201 L522 L545
PB201209-221
0P5
402
2
C608-609
100P 402 19
C152-159 C161 C525 C527 C580 C654 C656-659 C678
C681
102 402 19
C105-106 C108 C125 C233 C248 C256 C287 C314-315
C404 C410 C523 C555 C584 C594 C639 C649 C711
specification
Package
Quantity
Element bit number Additional information
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