Port options can be specified independently for each bit.
The programmable pull-up resistors are provided depending on whether CMOS or Nch-OD (Nch open
drain ) is selected as the port 1 option.
3. Refer to Table 3 about Functions and Data of the IC’s Each Pin.
I/O
1-bit input port
(P83 is set only in CH04T1002)
I
4-bit input/output port(P84-P87)
Each bit can be independently programmable
Other function:
AD converter input port
P83
B
P84-P87
X
10
SERVICE MANUAL
EEPROM AT24C04 (N002)
1. Features
Data EEPROM internally organized as 512
bytes and 32 pages×16 bytes
Low power CMOS
Vcc=2.7 to 5.5V operation
Two wire serial interface bus I
compatible
Filtered inputs for noise suppression with
Schmitt trigger
Clock frequency up to 400 kHz
High programming flexibility
-Internal programming voltage
-Self timed programming cycle including erase
-Byte-write and page-write programming
between 1 and 16 bytes
-Typical programming time 6 ms(<10ms) for up
to 16 bytes
High reliability
-Endurance 10
-Data retention 40 years
6
cycles
1)
1)
-ESD protection 4000 V on all pins
8 pin DIP/DSO packages
Available for extended temperature ranges
-Industrial -40 to +85
-Automotive -40 to +125
3. Block Diagram
2
C-Bus
2. Pin Configuration
Fig. 6
Fig. 7
4. Refer to Table 4 about Functions and Data of the IC’s Each Pin
11
SERVICE MANUAL
OM8839PS (N301)
I2C-bus Controlled PAL/NTSC/SECAM TV Processors
1. Features
The following features are available in all IC’s:
·Multi-standard vision IF circuit with an
alignment-free PLL demodulator without external
components
·Alignment-free multi-standard FM sound
demodulator (4.5 MHz to 6.5 MHz)
·Audio switch
·Flexible source selection with CVBS switch and
Y(CVBS)/C input so that a comb filter can be
applied
·Integrated chrominance trap circuit
·Integrated luminance delay line
·Asymmetrical peaking in the luminance channel
with a (defeatable) noise coring function
·Black stretching of non-standard CVBS or lumina-
nce signals
·Integrated chroma band-pass filter with switchable
centre frequency
·Dynamic skin tone control circuit
·Blue stretch circuit which offsets colours near
white towards blue
·RGB control circuit with “Continuous Cathode
Calibration” and white point adjustment
·Possibility to insert a“blue back” option when no
video signal is available
·Horizontal synchronization with two control loops
and alignment-free horizontal oscillator
·Vertical count-down circuit
·Vertical driver optimised for DC-coupled vertical
output stages
2
·I
C-bus control of various functions
2. General Description
The various versions of the TDA 884X/5X
series are I
2
processors which are intended to be applied in
PAL, NTSC, PAL/NTSC and multi-standard
television receivers. The N2 version is pin and
application compatible with the N1 version,
however, a new feature has been added which
makes the N2 more attractive. The IF PLL
demodulator has been replaced by an
alignment-free IF PLL demodulator with
internal VCO (no tuned circuit required). The
setting of the various frequencies (33.4, 33.9,
38, 38.9, 45.75 and 58.75 MHz) can be made
via the I
2
C-bus.
Because of this difference the N2 version is
compatible with the N1, however, N1 devices
cannot be used in an optimised N2 application.
Functionally the IC series is split up in 3
categories, viz:
·Versions intended to be used in economy TV
receivers with all basic functions (envelope:
S-DIP 56 and QFP 64)
·Versions with additional features like E-W
geometry control, H-V zoom function and
YUV interface which are intended for TV
receivers with 110° picture tubes (envelope:
S-DIP 56)
·Versions which have in addition a second
RGB input with saturation control and a
second CVBS output (envelope: QFP 64)
The various type numbers are given in the
table below.
C-bus controlled single chip TV
3. Survey of IC Types
EnvelopeS-DIP 56 QFP 64
TV receiver category EconomyMid/High end EconomyMid/High end