Raytheon RMLA3565A-58 Datasheet
RMLA3565A-58
Wideband Low Noise MMIC Amplifier
PRODUCT INFORMATION
Description
Features
Absolute
Maximum
Ratings
The Raytheon RMLA3565A-58 is a single bias wideband low noise MMIC amplifier designed for the 3.5 - 6.5 GHz
frequency range. The MMIC requires no external matching circuits or external gate bias supply. This device uses
Raytheon’s advanced 0.25 µm PHEMT process to provide low noise, high linearity, and low current.
19.0 dB Gain typical
1.2 dB Noise Figure Typical 5.0 - 6.5 GHz
Single Positive Bias
Small Outline Metal Base Quad Plastic Package
Internal 50Ω Matching
1
Parameter Symbol Value Unit
Positive Drain DC Voltage (No RF) Vdd 6.5 V
RF Input Power (from 50
Drain Current Idd 130 mA
Case Operating Temperature Tc -35 to 85 °C
Storage Temperature Range Tstg -40 to 110 °C
Soldering Temperature Tsolder
Ω source) Pin(CW) 0 dBm
220 °C
(Photo TBS)
Electrical
Characteristics
2
Parameter Min Typ Max Unit
Frequency Range 3.5 6.5 GHz
Gain (Small Signal)
Gain Variation vs Temp -0.008 dB/°C
Noise Figure
3.5 - 5 GHz 1.4 1.9 dB
5 - 6.5 GHz 1.2 1.4 dB
Power Out, P1dB @ 5.5 GHz 8.0 10.0 dBm
Notes:
1. No permanent damage with only one parameter set at maximum limit and all other parameters at typical conditions.
2. All parameters met at Tc = +25 °C, Vdd = 4.0V.
3. Pin = -20 dBm, Vdd = 4.0 V, Frequency 3.5 - 6.5 GHz
4. Data de-embedded from fixture loss
Characteristic performance data and specifications are subject to change without notice.
3,4
4
17.0 19.0 dB
Parameter Min Typ Max Unit
OIP3 @ 5.5 GHz, +3 dBm
Pout total 17 21.0 dBm
Idd 70.0 85.0 mA
Vdd 3.0 4.0 6.0 V
Input Return Loss -15.0 dB
Output Return Loss -10.0 dB
Thermal Resistance Rjc 135 °C/W
(Channel to Case)
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Revised March 28, 2002
Page 1
Raytheon RF Components
362 Lowell Street
Andover, MA 01810
RMLA3565A-58
Wideband Low Noise MMIC Amplifier
PRODUCT INFORMATION
Application
Information
Figure 1
Package Outline and
Pin Designations
CAUTION: THIS IS AN ESD SENSITIVE DEVICE
The following briefly describes a procedure for evaluating the high efficiency PHEMT amplifier packaged in a
surface mount package. It may be noted that the chip is a fully monolithic single ended two stage amplifier for 3.5
to 6.5 GHz applications.
Test Fixture
Figure 1 shows the outline and pin-out descriptions for the packaged device. Figure 2 shows the functional block
diagram of the packaged product. A typical test fixture schematic showing external bias components is shown in
Figure 3. Figure 4 shows typical layout of an evaluation board corresponding to the schematic diagram. Typical
performance of the test fixture is shown in the performance data section. The following should be noted:
(1) Package pin designations are shown in figure 1.
(2) Vd is the drain voltage (positive) applied at the pins of the package.
(3) Vdd is the positive supply voltage at the evaluation board terminal.
Dimensions in inches
TOP VIEWTOP VIEW
0.200 SQ.
54
6
BOTTOM VIEW
546
Pin# Description
1N/C
2 RF Out
3 GND
4 N/C
5 GND
6 N/C
7 GND
8 RF In
9 N/C
10 N/C
11 N/C
12 Vd
13 GND
(Package Base)
0.030
0.008
0.015
7
8
9
10 12
11
PLASTIC LID
0.282
0.015
3
2
1
0.011
0.075 MAX.
3
2
0.020
SIDE SECTION
1
7
8
9
0.041
11
12
10
Functional Block
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Figure 2
Diagram
Ground
Pins# 3,5,7,13
Ground
Pin# 7
RF IN
Pin# 8
Characteristic performance data and specifications are subject to change without notice.
Revised March 28, 2002
Page 2
Ground
Pin# 5
Vd
Pin# 12
N/C
1,4,6,9,10,11
(Recommend grounding
externally to PC board)
RF OUT
Pin# 2
Raytheon RF Components
362 Lowell Street
Andover, MA 01810
Figure 3
Schematic for a Typical
Test Evaluation Board
(RMLA3565A-58-TB)
RMLA3565A-58
Wideband Low Noise MMIC Amplifier
PRODUCT INFORMATION
RF in
J1
Ray
LA3565
RF out
J2
Figure 4
Layout and Assembly of
Test Evaluation Board
(RMLA3565A-58-TB)
C1
C2
RF In
J1
GND
P2
Ground
(GND) P2
C1
(Opt)
Vdd P1
C2
(OPT)
C3
Vdd
P1
U1
RF Out
J2
Test Procedure
for the evaluation board
(RMLA3565A-58-TB)
Parts List
for test evaluation board
RMLA3565A-58-TB
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The following sequence of procedure must be followed to properly test the power amplifier:
Step 1: Turn off RF input power.
Step 2: Use GND terminal of the evaluation board to
connect DC supply grounds.
Step 3: Apply drain supply voltage of +4.0 V to
evaluation board terminal Vdd.
Part Value EIA Size Vendor(s)
C1 330 pF .04” x .02” AVX, Murata, Novacap,
C2 4.75 uF .14”x .11” Sprague, ATC, AVX, Murata
U1 RMLA3565A-58 .28” x .28” x .07” Raytheon
P1, P2 Terminal Samtec
J1, J2 SMA Connectors E.F. Johnson
Board RO4003(Rogers) 1.99x1.50x.032 Raytheon
Characteristic performance data and specifications are subject to change without notice.
Revised March 28, 2002
Page 3
Step 4: After the bias condition is established, RF input
signal may now be applied.
Step 5: Follow turn-off sequence of:
(i) Turn off RF input power.
(ii) Turn down and off Vdd.
Raytheon RF Components
362 Lowell Street
Andover, MA 01810
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