Raytheon RMLA3565-53 Datasheet

Raytheon RF Components
362 Lowell Street
Andover, MA 01810
Revised September 24, 2001
Page 1
www.raytheon.com/micro
Characteristic performance data and specifications are subject to change without notice.
PRELIMINARY INFORMATION
Description
Absolute
Maximum
Ratings
Electrical
Characteristics
1
18.0 dB Gain1.35 dB Noise FigureSingle Positive BiasSmall Outline Metal Base Quad Plastic Package
Features
Notes:
1. Operated at 25 °C and Vdd=4.0V, 50 system
2. Pin = -20 dBm, Freq 2.5 - 6.5 GHz
3. Data de-embedded from fixture loss
Parameter Symbol Value Unit
Positive Drain DC Voltage V
dd
6.5 V
RF Input Power (from 50W source) P
IN
(CW) 0 dBm
Drain Current I
dd
110 mA
Case Operating Temperature T
case
-40 to 100 °C
Storage Temperature Range T
storage
-40 to 110 °C
Soldering Temperature T
solder
220 °C
Thermal Resistance 77.5 °C/W
RMLA3565-58
Wideband Low Noise MMIC Amplifier
Parameter Min Typ Max Unit
Frequency Range 3.5 6.5 GHz Gain (Small Signal)
2
17.0 18.0 dB Gain Variation vs Temp -0.013 dB/°C Noise Figure
3
3.5 - 5 GHz 1.7 1.9 dB 5 - 6.5 GHz 1.3 1.4 dB
Parameter Min Typ Max Unit
Input/Output Return Loss -10.0 -5.0 dB Power Out, P-1dB 8.0 9.0 dBm IP3 @ 5.5GHz,-8dBm Out 21.0 dBm Idd 70.0 90.0 mA Vdd 3.0 4.0 6.0 V
Raytheon RF Components
362 Lowell Street
Andover, MA 01810
Revised September 24, 2001
Page 2
www.raytheon.com/micro
Characteristic performance data and specifications are subject to change without notice.
PRELIMINARY INFORMATION
CAUTION: THIS IS AN ESD SENSITIVE DEVICE
The following briefly describes a procedure for evaluating the high efficiency PHEMT amplifier packaged in a surface mount package. It may be noted that the chip is a fully monolithic single ended two stage amplifier for
3.5 to 6.5 GHz applications. Figure 1 shows the functional block diagram of the packaged product.
Test Fixture
Figure 2 shows the outline and pin-out descriptions for the packaged device. A typical test fixture schematic showing external bias components is shown in figure 3. Figure 4 shows typical layout of an evaluation board corresponding to the schematic diagram. A typical performance obtained from the test fixture is shown in figure
5. The following should be noted: (1) Package pin designations are as shown in figure 2. (2) Vd is the Drain Voltage (positive) applied at the pins of the package (3) Vdd is the positive supply voltage at the evaluation board terminal
Application
Information
Figure 1
Functional Block
Diagram
RF IN Pin# 8
RF OUT Pin# 2
Ground Pin# 1,3,4,6,9,10,11,13
Vd Pin# 12
Ground Pin# 7
Ground Pin# 5
RMLA3565-58
Wideband Low Noise MMIC Amplifier
Figure 2
Outline
Dimensions
Dimensions in inches
Pin# Description
1GND
2 RF Out
3 GND
4 GND 5 GND 6 GND
7 GND 8 RF In 9 GND 10 GND 11 GND 12 Vd 13 GND
(Package Base)
PLASTIC LID
SIDE SECTION
0.069 MAX.
0.010
0.230
0.246
0.282
1
2
3
546
7
9
8
10
12
11
0.041
1
2
3
0.015
0.200 SQ.
TOP VIEWTOP VIEW
BOTTOM VIEW
54
6
7
9
8
10 12
11
0.030
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