RAMTRON VRS51C540-40-L, VRS51L540-25-L, VRS51C540-40-Q, VRS51L540-25-Q, VRS51C540-40-P DATA SHEET
...
VRS51x540
Datasheet Rev 1.2
Versa 8051 MCU with 4KB Flash
Overview
The VRS51x540 is a low cost 8-bit microcontroller
based on the standard 80C51 microcontroller family
architecture. It is pin compatible and is a drop-in
replacement for standard 8051 MCUs
Aimed at cost effective applications requiring small
amounts of program/data memory coupled with
streamlined peripheral support, the VRS51x540 includes
4KB of Flash memory, 128 bytes of RAM a UART, three
16-bit timers, a Watchdog timer and power down
features.
The VRS51x540 is available in 5 (VRS51C540) and 3.3
(VRS51L540) volt versions in PLCC-44, QFP-44 and
DIP-40 packages. The VRS51x540 devices operate
over the entire industrial temperature range. The Flash
memory can be programmed using programmers
available from Ramtron or other 3rd party commercial
programmers.
FIGURE 1: VRS51X540 FUNCTIONAL DIAGRAM
4KB
FLASH
128 Bytes of
RAM
UART
8051
PROCESSOR
ADDRESS/
DATA BUS
PORT 0
PORT 1
PORT 2
8
8
8
Feature Set
• 80C51/80C52 pin compatible
• 12 clock periods per machine cycle
• 4KB on-chip Flash memory
• 128 bytes on-chip data RAM
• 32 I/O lines: P0-P3 = 8-bit
• Full duplex serial port (UART)
• 3, 16-bit Timers/Counters
• Watchdog Timer
• 8-bit Unsigned Division / Multiply
• BCD arithmetic
• Direct and Indirect Addressing
• Two levels of interrupt priority and nested interrupts
• Power saving modes
• Code protection function
• Operates at a clock frequency of up to 40MHz
• Low EMI (inhibit ALE)
• Programming voltage: 12V
• Industrial Temperature range (-40°C to +85°C)
• 5V and 3V versions available (see ordering information.)
FIGURE 2: VRS51X540 PLCC AND QFP PINOUT DIAGRAMS
3
1
D
D
A
A
/
/
3
1
.
.
0
NC
T2/P1.0
1
S
C
S
N
V
0
P0.0/AD0
VDD
P0.2/AD2
P
P
40
39
P0.4 /AD4
P0.5 /AD5
P0.6 /AD6
P0.7 /AD7
#EA
NC
ALE
#PSEN
P2.7 /A15
P2.6 /A14
P2.5 /A13
29
28
1
2
1
1
A
A
/
/
3
4
.
.
2
2
P2.1/A9
P2.0/A8
P
P2.2/A10
P
P1.5
P1.6
P1.7
RESET
RXD/P3.0
TXD/P3.1
#INT0/P 3.2
#INT1/P 3.3
T0/P 3.4
T1/P 3.5
3
2
.
.
1
1
P
P1.4
T2EX/P1.1
P
6
7
17
18
6
.
3
P
/
R
W
#RD/P3.7
#
VRS51x540
PLCC-44
1
2
L
L
A
A
T
T
X
X
NC
2 INTERRUPT
INPUTS
TIMER 0
TIMER 1
TIMER 2
RESET
POWER
CONTROL
WATCHDOG
TIMER
PORT 3
8
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
NC
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P0.7/AD7
#EA
P0.5/AD5
P0.6/AD6
P0.4/AD4
3
3
3
4
VRS51x540
QFP-44
4
4 1
1
P1.6
P1.5
P1.7
RESET
RXD/P3.0
P2.6/A14
P2.5/A13
#PSEN
P2.7/A15NCALE
2
2
3
P2.4/A12
2
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
NC
VSS
XTAL1
XTAL2
#RD/P3.7
1
#WR/P3.6
2
1
NC
T0/P3.4
T1/P3.5
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
Ramtron International Corporation
1850 Ramtron Drive Colorado Springs
Colorado, USA, 80921
http://www.ramtron.com
?
MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208
?
1-800-545-FRAM, 1-719-481-7000
?
page 1 of 40
VRS51x540
Pin Descriptions for QFP-44
TABLE 1: PIN DESCRIPTIONS FOR QFP-44/
QFP
Name I/O Function
- 44
1 P1.5 I/O Bit 5 of Port 1
2 P1.6 I/O Bit 6 of Port 1
3 P1.7 I/O Bit 7 of Port 1
4 RES I Reset
RXD I Receive Data
5
P3.0 I/O Bit 0 of Port 3
6 NC - No Connect
TXD O Transmit Data &
7
P3.1 I/O Bit 1 of Port 3
#INT0 I External Interrupt 0
8
P3.2 I/O Bit 2 of Port 3
#INT1 I External Interrupt 1
9
P3.3 I/O Bit 3 of Port 3
T0 I Timer 0
10
P3.4 I/O Bit 4 of Port 3
T1 I Timer 1 & 3
11
P3.5 I/O Bit 5 of Port
#WR O Ext. Memory Write
12
P3.6 I/O Bit 6 of Port 3
#RD O Ext. Memory Read
13
P3.7 I/O Bit 7 of Port 3
14 XTAL2 O Oscillator/Crystal Output
15 XTAL1 I Oscillator/Crystal In
16 VSS - Ground
17 NC - No Connect
P2.0 I/O Bit 0 of Port 2
18
A8 O Bit 8 of External Memory Address
P2.1 I/O Bit 1 of Port 2
19
A9 O Bit 9 of External Memory Address
P2.2 I/O Bit 2 of Port 2
20
A10 O Bit 10 of External Memory Address
P2.3 I/O Bit 3 of Port 2 &
21
A11 O Bit 11 of External Memory Address
P2.4 I/O Bit 4 of Port 2
22
A12 O Bit 12 of External Memory Address
P2.5 I/O Bit 5 of Port 2
23
A13 O Bit 13 of External Memory Address
QFP
Name I/O Function
- 44
P2.6 I/O Bit 6 of Port 2
24
A14 O Bit 14 of External Memory Address
P2.7 I/O Bit 7 of Port 2
25
A15 O Bit 15 of External Memory Address
26 #PSEN O Program Store Enable
27 ALE O Address Latch Enable
28 NC - No Connect
29 #EA I External Access
P0.7 I/O Bit 7 Of Port 0
30
AD7 I/O Data/Address Bit 7 of External Memory
P0.6 I/O Bit 6 of Port 0
31
AD6 I/O Data/Address Bit 6 of External Memory
P0.5 I/O Bit 5 of Port 0
32
AD5 I/O Data/Address Bit 5 of External Memory
P0.4 I/O Bit 4 of Port 0
33
AD4 I/O Data/Address Bit 4 of External Memory
P0.3 I/O Bit 3 Of Port 0
34
AD3 I/O Data/Address Bit 3 of External Memory
P0.2 I/O Bit 2 of Port 0
35
AD2 I/O Data/Address Bit 2 of External Memory
P0. 1 I/O Bit 1 of Port 0 & Data
36
AD1 I/O Address Bit 1 of External Memory
P0.0 I/O Bit 0 Of Port 0 & Data
37
AD0 I/O Address Bit 0 of External Memory
38 VDD - VCC
39 NC - No Connect
T2 I Timer 2 Clock Out
40
P1.0 I/O Bit 0 of Port 1
T2EX I Timer 2 Control
41
P1.1 I/O Bit 1 of Port 1
42 P1.2 I/O Bit 2 of Port 1
43 P1.3 I/O Bit 3 of Port 1
44 P1.4 I/O Bit 4 of Port 1
P2.6/A14
P2.5/A13
#PSEN
P2.7/A15NCALE
2
2
3
2
1
1
2
1
P0.3/AD 3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P0.7/AD7
#EA
P0.5/AD5
P0.6/AD6
P0.4/AD4
3
3
3
4
VRS51x540
NC
4
4
QFP-44
1
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
NC
VSS
XTAL1
XTAL2
#RD/P3.7
#WR /P3.6
P1.6
P1.5
NC
P1.7
RESET
RXD/P3.0
T0/P3.4
TXD/P3.1
T1/P3.5
#INT0/P3.2
#INT1/P3.3
________________________________________________________________________________________________
www.ramtron.com page 2 of 40
VRS51x540
Pin Descriptions for PLCC-44
TABLE 2: PIN DESCRIPTIONS FOR PLCC-44
PLCC
- 44
Name I/O Function
1 NC - No Connect
T2 I Timer 2 Clock Out
2
P1.0 I/O Bit 0 of Port 1
T2EX I Timer 2 Control
3
P1.1 I/O Bit 1 of Port 1
4 P1.2 I/O Bit 2 of Port 1
5 P1.3 I/O Bit 3 of Port 1
6 P1.4 I/O Bit 4 of Port 1
7 P1.5 I/O Bit 5 of Port 1
8 P1.6 I/O Bit 6 of Port 1
9 P1.7 I/O Bit 7 of Port 1
10 RES I Reset
RXD I Receive Data
11
P3.0 I/O Bit 0 of Port 3
12 NC - No Connect
TXD O Transmit Data &
13
P3.1 I/O Bit 1 of Port 3
#INT0 I External Interrupt 0
14
P3.2 I/O Bit 2 of Port 3
#INT1 I External Interrupt 1
15
P3.3 I/O Bit 3 of Port 3
T0 I Timer 0
16
P3.4 I/O Bit 4 of Port 3
T1 I Timer 1 & 3
17
P3.5 I/O Bit 5 of Port
#WR O Ext. Memory Write
18
P3.6 I/O Bit 6 of Port 3
#RD O Ext. Memory Read
19
P3.7 I/O Bit 7 of Port 3
20 XTAL2 O Oscillator/Crystal Output
21 XTAL1 I Oscillator/Crystal In
22 VSS - Ground
23 NC - No Connect
PLCC
- 44
Name I/O Function
P2.0 I/O Bit 0 of Port 2
24
A8 O Bit 8 of External Memory Address
P2.1 I/O Bit 1 of Port 2
25
A9 O Bit 9 of External Memory Address
P2.2 I/O Bit 2 of Port 2
26
A10 O Bit 10 of External Memory Address
P2.3 I/O Bit 3 of Port 2 &
27
A11 O Bit 11 of External Memory Address
P2.4 I/O Bit 4 of Port 2
28
A12 O Bit 12 of External Memory Address
P2.5 I/O Bit 5 of Port 2
29
A13 O Bit 13 of External Memory Address
P2.6 I/O Bit 6 of Port 2
30
A14 O Bit 14 of External Memory Address
P2.7 I/O Bit 7 of Port 2
31
A15 O Bit 15 of External Memory Address
32 #PSEN O Program Store Enable
33 ALE O Address Latch Enable
34 NC - No Connect
35 #EA I External Access
P0.7 I/O Bit 7 Of Port 0
36
AD7 I/O
Data/Address Bit 7 of External
Memory
P0.6 I/O Bit 6 of Port 0
37
AD6 I/O
Data/Address Bit 6 of External
Memory
P0.5 I/O Bit 5 of Port 0
38
AD5 I/O
Data/Address Bit 5 of External
Memory
P0.4 I/O Bit 4 of Port 0
39
AD4 I/O
Data/Address Bit 4 of External
Memory
P0.3 I/O Bit 3 Of Port 0
40
AD3 I/O
Data/Address Bit 3 of External
Memory
P0.2 I/O Bit 2 of Port 0
41
AD2 I/O
P0. 1 I/O Bit 1 of Port 0 & Data
42
AD1 I/O Address Bit 1 of External Memory
P0.0 I/O Bit 0 Of Port 0 & Data
43
AD0 I/O Address Bit 0 of External Memory
Data/Address Bit 2 of External
Memory
44 VDD - VCC
3
1
D
D
A
A
/
3
2
.
.
1
1
P
P1.4
T2EX/P1.1
P
T2/P1.0
6
7
P1. 5
P1. 6
P1. 7
RESET
RXD/P3. 0
NC
TXD/P3 .1
#INT0/P3 .2
#INT1/P3 .3
T0/P 3.4
T1/P 3.5
________________________________________________________________________________________________
17
18
6
.
3
P
/
R
W
#RD/P3.7
#
VRS51x540
PLCC-44
1
2
S
L
L
S
A
A
V
T
T
X
X
/
3
1
.
.
0
0
NC
1
C
N
P
P0.0/AD0
VDD
P0.2/AD2
P
40
39
P0.4 /AD4
P0.5 /AD5
P0.6 /AD6
P0.7 /AD7
#EA
NC
ALE
#PSEN
P2.7 /A15
P2.6 /A14
P2.5 /A13
29
28
1
2
1
1
A
A
/
/
3
4
.
.
2
2
P2.1/A9
P2.0/A8
P
P2.2/A10
P
www.ramtron.com page 3 of 40
VRS51x540
VRS51x540 DIP-40 Pin Descriptions
TABLE 3: VRS51X540 IN DESCRIPTIONS FOR DIP-40 PACKAGE
DIP40 Name I/O Function
T2 I Timer 2 Clock Out
1
P1.0 I/O Bit 0 of Port 1
T2EX I Timer 2 Control
2
P1.1 I/O Bit 1 of Port 1
3 P1.2 I/O Bit 2 of Port 1
4 P1.3 I/O Bit 3 of Port 1
5 P1.4 I/O Bit 4 of Port 1
6 P1.5 I/O Bit 5 of Port 1
7 P1.6 I/O Bit 6 of Port 1
8 P1.7 I/O Bit 7 of Port 1
9 RESET I Reset
RXD I Receive Data
10
P3.0 I/O Bit 0 of Port 3
TXD O Transmit Data &
11
P3.1 I/O Bit 1 of Port 3
#INT0 I External Interrupt 0
12
P3.2 I/O Bit 2 of Port 3
#INT1 I External Interrupt 1
13
P3.3 I/O Bit 3 of Port 3
T0 I Timer 0
14
P3.4 I/O Bit 4 of Port 3
T1 I Timer 1 & 3
15
P3.5 I/O Bit 5 of Port
#WR O Ext. Memory Write
16
P3.6 I/O Bit 6 of Port 3
#RD O Ext. Memory Read
17
P3.7 I/O Bit 7 of Port 3
18 XTAL2 O Oscillator/Crystal Output
19 XTAL1 I Oscillator/Crystal In
20 VSS - Ground
T2 / P1.0
T2EX / P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
RXD / P3.0
TXD / P3.1
#INT0 / P3.2
#INT1 / P3.3
T0 / P3.4
T1 / P3.5
#WR / P3.6
#RD / P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VRS51x540
DIP-40
40
VDD
39
P0.0 / AD0
38
P0.1 / AD1
37
P0.2 / AD2
36
P0.3 / AD3
35
P0.4 / AD4
34
P0.5 / AD5
33
P0.6 / AD6
32
P0.7 / AD7
31
#EA / VPP
30
ALE
29
PSEN
28
P2.7 / A15
27
P2.6 / A14
26
P2.5 / A13
25
P2.4 / A12
24
P2.3 / A11
23
P2.2 / A10
22
P2.1 / A9
21
P2.0 / A8
DIP40
21
22
23
24
25
26
27
28
29 #PSEN O Program Store Enable
30 ALE O Address Latch Enable
31
32
33
34
35
36
37
38
39
40 VDD - Supply input
Name I/O Function
P2.0 I/O Bit 0 of Port 2
A8 O Bit 8 of External Memory Address
P2.1 I/O Bit 1 of Port 2
A9 O Bit 9 of External Memory Address
P2.2 I/O Bit 2 of Port 2
A10 O Bit 10 of External Memory Address
P2.3 I/O Bit 3 of Port 2 &
A11 O Bit 11 of External Memory Address
P2.4 I/O Bit 4 of Port 2
A12 O Bit 12 of External Memory Address
P2.5 I/O Bit 5 of Port 2
A13 O Bit 13 of External Memory Address
P2.6 I/O Bit 6 of Port 2
A14 O Bit 14 of External Memory Address
P2.7 I/O Bit 7 of Port 2
A15 O Bit 15 of External Memory Address
#EA /
VPP
External Access
I
Flash programming voltage input
P0.7 I/O Bit 7 Of Port 0
AD7 I/O
Data/Address Bit 7 of External
Memory
P0.6 I/O Bit 6 of Port 0
AD6 I/O
Data/Address Bit 6 of External
Memory
P0.5 I/O Bit 5 of Port 0
AD5 I/O
Data/Address Bit 5 of External
Memory
P0.4 I/O Bit 4 of Port 0
AD4 I/O
Data/Address Bit 4 of External
Memory
P0.3 I/O Bit 3 Of Port 0
AD3 I/O
Data/Address Bit 3 of External
Memory
P0.2 I/O Bit 2 of Port 0
AD2 I/O
Data/Address Bit 2 of External
Memory
P0. 1 I/O Bit 1 of Port 0 & Data
AD1 I/O Address Bit 1 of External Memory
P0.0 I/O Bit 0 Of Port 0 & Data
AD0 I/O Address Bit 0 of External Memory
______________________________________________________________________________________________
www.ramtron.com page 4 of 40
VRS51x540
Instruction Set
The following tables describe the instruction set of the
VRS51x540. The instructions are functional and binary
code compatible with industry standard 8051s.
TABLE 4: LEGEND FOR INSTRUCTION SET TABLE
Symbol Function
A
Rn
Direct
@Ri
Rel
Bit
#data
#data 16
addr 16
addr 11
TABLE 5: VRS51X540 INSTRUCTION SET
Mnemonic Description
Arithmetic instructions
ADD A, Rn Add register to A
ADD A, direct Add direct byte to A
ADD A, @Ri Add data memory to A
ADD A, #data Add immediate to A
ADDC A, Rn Add register to A with carry
ADDC A, direct Add direct byte to A with carry
ADDC A, @Ri Add data memory to A with carry
ADDC A, #data Add immediate to A with carry
SUBB A, Rn Subtract register from A with borrow
SUBB A, direct Subtract direct byte from A with borrow
SUBB A, @Ri Subtract data mem from A with borrow
SUBB A, #data Subtract immediate from A with borrow
INC A Increment A
INC Rn Increment register
INC direct Increment direct byte
INC @Ri Increment data memory
DEC A Decrement A
DEC Rn Decrement register
DEC direct Decrement direct byte
DEC @Ri Decrement data memory
INC DPTR Increment data pointer
MUL AB Multiply A by B
DIV AB Divide A by B
DA A Decimal adjust A
Logical Instructions
ANL A, Rn AND register to A
ANL A, direct AND direct byte to A
ANL A, @Ri AND data memory to A
ANL A, #data AND immediate to A
ANL direct, A AND A to direct byte
ANL direct, #data AND immediate data to direct byte
ORL A, Rn OR register to A
ORL A, direct OR direct byte to A
ORL A, @Ri OR data memory to A
ORL A, #data OR immediate to A
ORL direct, A OR A to direct byte
ORL direct, #data OR immediate data to direct byte
XRL A, Rn Exclusive-OR register to A
XRL A, direct Exclusive-OR direct byte to A
XRL A, @Ri Exclusive-OR data memory to A
XRL A, #data Exclusive-OR immediate to A
XRL direct, A Exclusive-OR A to direct byte
XRL direct, #data Exclusive-OR immediate to direct byte
CLR A Clear A
CPL A Compliment A
SWAP A Swap nibbles of A
RL A Rotate A left
RLC A Rotate A left through carry
RR A Rotate A right
RRC A Rotate A right through carry
Accumulator
Register R0-R7
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
Size
(bytes)
Instr. Cycles
1 1
2 1
1 1
2 1
1 1
2 1
1 1
2 1
1 1
2 1
1 1
2 1
1 1
1 1
2 1
1 1
1 1
1 1
2 1
1 1
1 2
1 4
1 4
1 1
1 1
2 1
1 1
2 1
2 1
3 2
1 1
2 1
1 1
2 1
2 1
3 2
1 1
2 1
1 1
2 1
2 1
3 2
1 1
1 1
1 1
1 1
1 1
1 1
1 1
Mnemonic Description
Boolean Instruction
CLR C Clear Carry bit
CLR bit Clear bit
SETB C Set Carry bit to 1
SETB bit Set bit to 1
CPL C Complement Carry bit
CPL bit Complement bit
ANL C,bit Logical AND between Carry and bit
ANL C,#bit Logical AND between Carry and not bit
ORL C,bit Logical ORL between Carry and bit
ORL C,#bit Logical ORL between Carry and not bit
MOV C,bit Copy bit value into Carry
MOV bit,C Copy Carry value into Bit
Data Transfer Instructions
MOV A, Rn Move register to A
MOV A, direct Move direct byte to A
MOV A, @Ri Move data memory to A
MOV A, #data Move immediate to A
MOV Rn, A Move A to register
MOV Rn, direct Move direct byte to register
MOV Rn, #data Move immediate to register
MOV direct, A Move A to direct byte
MOV direct, Rn Move register to direct byte
MOV direct, direct
MOV direct, @Ri Move data memory to direct byte
MOV direct, #data
MOV @Ri, A Move A to data memory
MOV @Ri, direct Move direct byte to data memory
MOV @Ri, #data Move immediate to data memory
MOV DPTR, #data
MOVC A, @A+DPTR
MOVC A, @A+PC Move code byte relative PC to A
MOVX A, @Ri Move external data (A8) to A
MOVX A, @DPTR Move external data (A16) to A
MOVX @Ri, A Move A to external data (A8)
MOVX @DPTR, A Move A to external data (A16)
PUSH direct Push direct byte onto stack
POP direct Pop direct byte from stack
XCH A, Rn Exchange A and register
XCH A, direct Exchange A and direct byte
XCH A, @Ri Exchange A and data memory
XCHD A, @Ri Exchange A and data memory nibble
Branching Instructions
ACALL addr 11 Absolute call to subroutine
LCALL addr 16 Long call to subroutine
RET Return from subroutine
RETI Return from interrupt
AJMP addr 11 Absolute jump unconditional
LJMP addr 16 Long jump unconditional
SJMP rel Short jump (relative address)
JC rel Jump on carry = 1
JNC rel Jump on carry = 0
JB bit, rel Jump on direct bit = 1
JNB bit, rel Jump on direct bit = 0
JBC bit, rel Jump on direct bit = 1 and clear
JMP @A+DPTR Jump indirect relative DPTR
JZ rel Jump on accumulator = 0
JNZ rel Jump on accumulator 1= 0
CJNE A, direct, rel Compare A, direct JNE relative
CJNE A, #d, rel Compare A, immediate JNE relative
CJNE Rn, #d, rel Compare reg, immediate JNE relative
CJNE @Ri, #d, rel
DJNZ Rn, rel Decrement register, JNZ relative
DJNZ direct, rel Decrement direct byte, JNZ relative
Miscellaneous Instruction
NOP No operation
Rn: Any of the register R0 to R7
@Ri: Indirect addressing using Register R0 or R1
#data: immediate Data provided with Instruction
#data16: Immediate data included with instruction
bit: address at the bit level
rel: relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d: Immediate Data supplied with instruction
Move direct byte to direct byte
Move immediate to direct byte
Move immediate to data pointer
Move code byte relative DPTR to A
Compare ind, immediate JNE relative
Size
(bytes)
1 1
2 1
1 1
2 1
1 1
2 1
2 2
2 2
2 2
2 2
2 1
2 2
1 1
2 1
1 1
2 1
1 1
2 2
2 1
2 1
2 2
3 2
2 2
3 2
1 1
2 2
2 1
3 2
1 2
1 2
1 2
1 2
1 2
1 2
2 2
2 2
1 1
2 1
1 1
1 1
2 2
3 2
1 2
1 2
2 2
3 2
2 2
2 2
2 2
3 2
3 2
3 2
1 2
2 2
2 2
3 2
3 2
3 2
3 2
2 2
3 2
1 1
Instr. Cycles
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VRS51x540
Special Function Registers (SFR)
Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table
lists the VRS51x540 Special Function Registers.
TABLE 6: SPECIAL FUNCTION REGISTERS (SFR)
SFR
Register
P0 80h - - - - - - - -
SP 81h - - - - - - - -
DPL 82h - - - - - - - -
DPH 83h - - - - - - - -
Reserved 84h - - - - - - - -
PCON 87h SMOD - - - GF1 GF0 PDOWN IDLE 00000000b
TCON 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000b
TMOD 89h GATE1 C/T1 M1.1 M0.1 GATE0 C/T0 M1.0 M0.0 00000000b
TL0 8Ah - - - - - - - -
TL1 8Bh - - - - - - - -
TH0 8Ch - - - - - - - -
TH1 8Dh - - - - - - - -
P1 90h - - - - - - - -
SCON 98h SM0 SM1 SM2 REN TB8 RB8 TI RI 00000000b
SBUF 99h - - - - - - - -
WDTCON 9Fh WDTE - WDCLR - - WDPS2 WDPS1 WDPS0 0*0**000b
P2 A0h - - - - - - - -
IE A8h EA - ET2 ES ET1 EX1 ET0 EX0 00000000b
P3 B0h - - - - - - - -
IP B8h - - PT2 PS PT1 PX1 PT0 PX0 00000000b
SYSCON BFh WDRESET - - - - ALEI 0*****00b
T2CON C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00000000b
RCAP2L CAh - - - - - - - - 00000000b
RCAP2H CBh - - - - - - - - 00000000b
TL2 CCh - - - - - - - - 00000000b
TH2 CDh 00000000b
PSW D0h CY AC F0 RS1 RS0 OV - P 00000000b
ACC E0h - - - - - - - -
B F0h - - - - - - - -
SFR
Adrs
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Value
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VRS51x540
Program Memory Structure
Program Memory
The VRS51x540 includes 4k of on-chip Program Flash
memory.
FIGURE 3: VRS51X540 INTERNAL PROGRAM MEMORY
FFFh
VRS51x540
Flash Memory
(4K Bytes)
0000h
Program Status Word Register
The PSW register is a bit addressable register that
contains the status flags (CY, AC, OV, P), user flag
(F0) and register bank select bits (RS1, RS0) of the
8051 processor.
TABLE 7: PROGRAM STATUS WORD REGISTER (PSW) - SFR DOH
7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV - P
Bit Mnemonic Description
7 CY Carry Bit
6 AC Auxiliary Carry Bit from bit 3 to 4.
5 F0 User flag
4 RS1 R0-R7 Registers bank select bit 0
3 RS0 R0-R7 Registers bank select bit 1
2 OV Overflow flag
1 - 0 P Parity flag
RS1 RS0 Active Bank Address
0 0 0 00h-07h
0 1 1 08h-0Fh
1 0 2 10h-17h
1 1 3 18-1Fh
Data Pointer
The VRS51x540 has one 16-bit data pointer. The
DPTR is accessed through two SFR addresses: DPL
located at address 82h and DPH located at address
83h.
Data Memory
The VRS51x540 has a total of 128 Bytes of RAM
memory configured as the internal memory structure of
a standard 8051.
FIGURE 4: VRS51X540 DATA MEMORY
FFh
80h
7Fh
00h
128 bytes RAM
(indirect addressing only)
128 bytes RAM
(Can be accessed in indirect and
direct addressing mode)
(Direct addressing mode only)
Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1)
The lower 128 bytes of data memory (from 00h to 7Fh)
is summarized as follows:
• Address range 00h to 7Fh can be accessed in
direct and indirect addressing modes.
• Address range 00h to 1Fh includes R0-R7
registers area.
• Address range 20h to 2Fh is bit addressable.
• Address range 30h to 7Fh is not bit addressable
and can be used as general-purpose storage.
.
FIGURE 5: VRS51X540 INTERNAL RAM STRUCTURE
SFR Area
Direct or Bit Access Only
DPH
DPL
SP
P0
7Fh
30h
2Fh
20h
18h
10h
08h
00h
80 Bytes of
General Purpose RAM
7F 7E 7D 7C 7B 7A 79 78
77 76 75 74 73 72 71 70
0F 0E 0D 0C 0B 0A 09 08
07 06 05 04 03 02 01 00
R7
-
Registers Bank 3
R0
R7
-
Registers Bank 2
R0
R7
Registers Bank 1
-
R0
R7
Registers Bank 0
-
R0
85 84 83 82 81 80
87 86
SFR
FFh
80h
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VRS51x540
Description of Peripherals
System Control Register
The SYSCON Register is used for system control and
is described in the following table. The WDRESET bit
(7) indicates whether the system has been reset due to
the overflow of the Watchdog Timer.
Bit 0 of the SYSCON register is the ALE output inhibit
bit. Setting this bit to a 1 will inhibit the Fosc/6 clock
signal output to the ALE pin.
TABLE 8: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH
7 6 5 4 3 2 1 0
WDRESET
Unused
Bit Mnemonic Description
7
6 Unused 5 Unused 4 Unused 3 Unused 2 Unused 1 Unused 0 ALEI ALE output inhibit bit, which is used to
WDRESET
This is the Watchdog Timer reset bit. It
will be set to 1 when the reset signal
generated by WDT overflows.
reduce EMI.
XRAME
ALEI
These power saving modes are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
TABLE 9: POWER CONTROL REGISTER (PCON) - SFR 87H
7 6 5 4 3 2 1 0
Unused RAM1 RAM0
Bit Mnemonic Description
7 SMOD 1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
6
5
4
3 GF1 General Purpose Flag
2 GF0 General Purpose Flag
1 PDOWN Power down mode control bit
0 IDLE Idle mode control bit
Power Control Register
The VRS51x540 provides two power saving modes:
Idle and Power Down. These two modes serve to
reduce the power consumption of the device.
In Idle mode, the processor is stopped but the oscillator
continues to run. The content of the RAM, I/O state
and SFR registers are maintained and the Timer and
external interrupts are left operational. The processor
will be woken up when an external event, triggering an
interrupt, occurs.
In Power Down mode, the oscillator and peripherals of
the VRS51x540 are disabled. The contents of the
RAM and the SFR registers, however, are maintained.
The minimum VCC in Power Down mode is 2V.
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VRS51x540
Input/Output Ports
The VRS51x540 has a total of 32 bi-directional I/O
lines grouped into four 8-bit I/O ports. These I/Os can
be individually configured as inputs or outputs.
With the exception of the P0 I/Os, which are of the
open drain type, each I/O is made of a transistor
connected to ground and a weak pull-up resistor.
Writing a 0 in a given I/O port bit register will activate
the transistor connected to Vss, this will bring the I/O to
a LOW level.
Writing a 1 into a given I/O port bit register de-activates
the transistor between the pin and ground. In this case
the pull-up resistor will bring the corresponding pin to a
HIGH level.
To use a given I/O as an input, a 1 must be written into
its associated port register bit. By default, upon reset
all I/Os are configured as inputs.
General Structure of an I/O Port
The following elements establish the link between the
core unit and the pins of the microcontroller:
• Special Function Register (same name as port)
• Output Stage Amplifier (the structure of this
element varies with its auxiliary function)
From the next figure, one can see that the D flip-flop
stores the value received from the internal bus after
receiving a write signal from the core. Also, note that
the Q output of the flip-flop can be linked to the internal
bus by executing a read instruction.
This is how one would read the content of the register.
It is also possible to link the value of the pin to the
internal bus. This is done by the “read pin” instruction.
In short, the user may read the value of the register or
the pin.
FIGURE 6: INTERNAL STRUCTURE OF ONE OF THE FOUR I/O PORT LINES
Read Register
D Flip-Flop
Q
Output
Q
Stage
IC Pin
Internal Bus
Write to
Register
Read Pin
Structure of the P1, P2, P3
The following figure gives a general idea of the
structure P1, P2 and P3 ports. Note that the figure
below does not show the intermediary logic that
connects the output of the register and the output stage
together because this logic varies with the auxiliary
function of each port.
FIGURE 7: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2 AND P3
Read Register
Vcc
Pull-up
Network
D Flip-Flop
Q
Q
X1
IC Pin
Internal Bus
Write to
Register
Read Pin
Each line may be used independently as a logical
input or output. When used as an input, as mentioned
earlier, the corresponding port register bit must be
high.
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VRS51x540
Structure of Port 0
The internal structure of P0 is shown below. The
auxiliary function of this port requires a particular logic.
As opposed to the other ports, P0 is truly bi-directional.
In other words, when used as an input, it is considered
to be in a floating logical state (high impedance state).
This arises from the absence of the internal pull-up
resistance. The pull-up resistance is actually replaced
by a transistor that is only used when the port is
configured to access the external memory/data bus
(EA=0).
When used as an I/O port, P0 acts as an open drain
port and the use of an external pull-up resistor is likely
to be required for most applications.
FIGURE 8: PORT P0’S PARTICULAR STRUCTURE
Internal Bus
Write to
Register
Read Register
D Flip-Flop
Read Pin
Q
Q
Address A0/A7
Control
Vcc
IC Pin
X1
When P0 is used as an external memory bus input (for
a MOVX instruction, for example), the outputs of the
register are automatically forced to 1.
Port P0 and P2 as Address and Data Bus
The output stage may receive data from two sources
• The outputs of register P0 or the bus address
itself, multiplexed with the data bus for P0.
• The outputs of the P2 register or the high byte
(A8 through A15) of the bus address for the P2
port.
FIGURE 9: P2 PORT STRUCTURE
Read Register
Vcc
Pull-up
Network
IC Pin
X1
Internal Bus
Write to
Register
Read Pin
D Flip-Flop
Address
Q
Q
Control
When the ports are used as an address or data bus,
the special function registers P0 and P2 are
disconnected from the output stage. The 8-bits of the
P0 register are forced to 1 and the content of the P2
register remains constant.
Auxiliary Port 1 Functions
The port 1 I/O pins are shared with the Timer 2 EX and
T2 inputs as shown below:
Pin Mnemonic Function
P1.0 T2 Timer 2 counter input
P1.1 T2EX Timer2 Auxiliary input
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
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VRS51x540
Auxiliary P3 Port Functions
The Port 3 I/O pins are shared with the UART
interface, INT0 and INT1 interrupts, Timer 0 and Timer
1 inputs and finally the #WR and #RD lines when
external memory access is performed.
FIGURE 10: P3 PORT STRUCTURE
Read Register
Internal Bus
Write to
Register
Read Pin
D Flip-Flop
The following table describes the auxiliary function of
the port 3 I/O pins.
TABLE 10: P3 AUXILIARY FUNCTION TABLE
Pin Mnemonic Function
P3.0 RXD Serial Port:
P3.1 TXD Serial Port:
P3.2
P3.3
INT0
INT1
P3.4 T0 Timer 0 Counter Input
P3.5 T1 Timer 1 Counter Input
P3.6
P3.7
WR
RD
Auxiliary
Function: Output
Vcc
IC Pin
Q
Q
Auxiliary
Function: Input
X1
Receive data in asynchronous
mode. Input and output data in
synchronous mode.
Transmit data in asynchronous
mode. Output clock value in
synchronous mode.
External Interrupt 0
Timer 0 Control Input
External Interrupt 1
Timer 1 Control Input
Write signal for external memory
Read signal for external memory
Software Particularities Concerning the Ports
Some instructions allow the user to read the logic state
of the output pin, while others allow the user to read
the content of the associated port register. These
instructions are called read-modify-write instructions. A
list of these instructions may be found in the table
below.
Upon execution of these instructions, the content of the
port register (at least 1-bit) is modified. The other read
instructions take the present state of the input into
account. For example, the instruction ANL P3, #01h
obtains the value in the P3 register; performs the
desired logic operation with the constant 01h; and recopies the result into the P3 register. When users want
to take the present state of the inputs into account,
they must first read these states and perform an AND
operation between the reading and the constant.
MOV A, P3; State of the inputs in the accumulator
ANL A, #01; AND operation between P3 and 01h
When the port is used as an output, the register
contains information on the state of the output pins.
Measuring the state of an output directly on the pin is
inaccurate because the electrical level depends mostly
on the type of charge that is applied to it. The functions
shown below take the value of the register rather than
that of the pin.
TABLE 11: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER
VALUES
Instruction Function
ANL Logical AND ex: ANL P0, A
ORL Logical OR ex: ORL P2, #01110000B
XRL Exclusive OR ex: XRL P1, A
JBC Jump if the bit of the port is set to 0
CPL Complement one bit of the port
INC Increment the port register by 1
DEC Decrement the port register by 1
DJNZ Decrement by 1 and jump if the result
is not equal to 0
MOV P., C Copy the held bit C to the port
CLR P.x Set the port bit to 0
SETB P.x Set the port bit to 1
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VRS51x540
Port Operation Timing
Writing to a Port (Output)
When an operation results in a modification of the
content in a port register, the new value is placed at the
output of the D flip-flop during the T12 period of the last
machine cycle that the instruction needed to execute.
It is important to note, however, that the output stage
only samples the output of the registers on the P1
phase of each period. It follows the new value
appearing at the output after the T12 period of the
following machine cycle.
Reading a Port (Input)
The reading of an I/O pin takes place:
• During T9 cycle for P0, P1
• During T10 cycle for P2, P3
• When the ports are configured as I/Os
•
In order to be sampled, the signal duration present on
the I/O inputs must be longer than Fosc/12.
I/O Ports Driving Capability
The maximum allowable continuous current that the
device can sink on an I/O port is defined by the
following:
Maximum sink current on one given I/O 10mA
Maximum total sink current for P0 26mA
Maximum total sink current for P1, 2, 3 15mA
Maximum total sink current on all I/O 71mA
It is not recommended to exceed the sink current
outlined in the above table. Doing so is likely to make
the low-level output voltage exceed the device’s
specification and it is likely to affect device reliability.
The VRS51x540 I/O ports are not designed to source
current.
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