RAMTRON FM574-S, FM574-P, FM573-S, FM573-P Datasheet

Preliminary

Other package types may be available. Contact

FM573/574

Nonvolatile Octal Latch/Register

Features

8-bit Nonvolatile Latch

• Logic state is preserved in the absence of power

• Over 10 Billion (1010) nonvolatile state changes

• Advanced high-reliability ferroelectric process

Op erates like conventional CMOS logic

• Transparent (573) or D-Flip-flop (574) operation

• FM573 transparent for C high, latched for C low

• FM574 data is clocked on the rising edge of C

• 33/80 ns data propagation delay (5V/3V)

• 30 MHz/12 MHz Maximum frequency (5V/3 V)

Description

The FM573 and FM574 are innovative circuits that
store inputs like conventional logic families, and then
retain the stored state in the absence of power. These
products solve three basic problems in an elegant
fashion. First, they provide continuous access to
nonvolatile system settings without performing a
memory read operation or using dedicated processor
I/O pins. Second, they allow the storage of signals or
data that may change frequently and possibly without
notice. Third, they allow the nonvolatile storage of a
few bits of data or system settings without the system
overhead and extra pins of a serial memory. The
FM573 is a transparent latch. The inputs are passed
to the outputs when the clock is high; the state is
latched when the clock goes low. The FM574 is a D­type register. Inputs are stored and passed to the
outputs on the rising edge of the clock. The
nonvolatile latch is a unique product that serves a
variety of applications. A few ideas as follows:

ü Controls relays and valves with automatic setting

on power -up without processor intervention.

ü Interface to soft/momentary front-panel switches

and indicator lamps. Capture switch settings and
light LED’s without processor intervention.

ü Replaces jumpers & control signal routing
ü Initialize state of I/O card signals.
ü Save system errors or status codes when power

fails with a fast, no overhead write and automatic
restore on power up.

ü Eliminate the overhead of serial memory for

systems needing only a few bits of data.

The FM573 and FM574 are provided in a 20-pin DIP
or SOP. They are rated from –40C to +85C.

This data sheet contains specifications for a product under development. Ramtron International Corporation
Characterization is not complete; specifications may change without notice. 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, [phone], Fax [phone]

27 March 2001 www.ramtron.com
1/10

Automatic Nonvolatile Operation

• Latched state is stored automatically

• State is automatically restored on power -up

• Power supply monitor prevents low -VDD writes

Low Power Operation

• Supply voltage of 2.7V to 5.5V

• 125 µA standby current

Industry Stand ard Configuration

• Industrial temperature -40° C to +85° C

• 20-pin SOP or DIP

Pin Configuration

20
19
18
17
16
15
14
13
12
11

VDD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C

D0
D1
D2
D3
D4
D5
D6
D7

1
2
3
4
5
6
7
8
9
10

OE

VSS

Pin Names Function

D0-D7 Data in
Q0-Q7 Data Out
C Clock/Latch Enable
/OE Output enable
VSS Ground
VDD Supply Voltage

Ordering Information

FM573-P Transparent latch, 20-pin plastic DIP
FM573-S Transparent latch, 20-pin SOP
FM574-P Register, 20-pin plastic DIP
FM574-S Register, 20-pin SOP

the factory for more information.

Ramtron FM573/574

Mux

Figure 1. Block Diagram

Dn

C

Nonvolatile

section

VDD

Reference

S

1

S

2

S

1

S

2

Power-up Restore

Power

Monitor

Pin Description

Pin Name Pin Number I/O Pin Description

D

Mux

D

Nonvolatile Latch

State Change

Q D

Q

L

QD

Q

Detect

OE

Qn

/OE 1 I Output enable. When low, the outputs are driven. When high, the outputs

are tri-stated.
C 11 I Controls the latching of data according to the truth tables below.
D0-D7 2-9 I Data in.
Q0-Q7 12-19 O Data out.
VSS 10 I Ground
VDD 20 I Supply Voltage

Functional Tables

FM573 Table

/OE

1 X X X Hi-Z Tri-state outputs
0 0 X Qn Qn Outputs enabled, hold state
0 1 Dn Dn Dn Transparent
1 1 Dn Dn Hi-Z Load data, outputs tri-state

FM574 Table

/OE

1 X X X Hi-Z Tri-state outputs
0 X X Qn Qn Outputs enabled, hold state
0
1

↑
↑

C

C

Dn

Dn

Internal

Qn

Internal

Qn

Output

Qn

Output

Qn

Description

Description

Dn Dn Dn Load data, outputs enabled
Dn Dn Hi-Z Load data, outputs tri-state

27 March 2001 2/10

Ramtron FM573/574

Overview

Nonvolatile logic is a revolutionary product family
that simplifies the design of system control functions.
The FM573 is a transparent octal latch; the FM574 is
an octal D-type register. These products are unique
because the stored values also are retained in the
absence of power. They are pin and functionally
compatible with their industry standard CMOS
equivalents. Any change in the latched state
automatically is written into a nonvolatile
ferroelectric latch. This function is possible due to the
fast write time and extremely high write endurance of
the underlying ferroelectric memory technology. A

This power up sequence occurs as follows. On
detection of a power-up, the internal nonvolatile latch
is read. This value is then placed on an internal
version of the Dn input. A single internal clock is
generated to cause the user latch to accept the
restored data. After this process is complete, the latch
provides normal user-controlled operation. Users
should not attempt to latch externally supplied data
prior to t

after VDD reaches V

PUH

. The following

MIN

diagram illustrates the power-up and down
sequences.

Figure 2. Power Cycle Flow Chart

new state becomes nonvolatile no more than 500 ns
(VDD=5V) after the write begins.

Users interface to a conventional latch rather than

System VDD rises,

bandgap begins to function

directly to the nonvolatile latch. Equivalent
ferroelectric nonvolatile latches shadow the user’s
latches. They offer a very high but not unlimited

No

number of write-cycles. Therefore, the internal state
machine writes to the nonvolatile latch only if the
latched state has changed in order to minimize the

VDD > VMIN?

VDD < VMIN

actual number of nonvolatile write-cycles. This
determination is made independently for each bit.

Yes

Yes

Due to the short write-time and realistic power slew
rates, it is virtually impossible for the system to lose
power before the nonvolatile state is acquired.

Read nonvolatile

store

Complete NV-

writes in progress

No

Power Down Sequence

An internal power monitor blocks updates to the
nonvolatile latch when VDD is below V

(internal

MIN

voltage reference). The power supply monitor also
blocks write access to the user latch when VDD is
below V
of the last value, state changes should cease t
before VDD reaches V

. To guarantee a proper nonvolatile write

MIN

MIN

. The V

threshold is low

MIN

PDS

enough that no special action may be needed in
systems with slow slew rates. For fast power supply
slew-rates or for systems that run down to relatively
low supply voltages, the user should employ some
form of low -VDD reset that trips above V

MIN

.

Power Up

The V

threshold is a critical parameter for several

MIN

aspects of product operations. On power-up, the
FM573/574 automatically restores the Qn outputs
(and internal latches) to the previously stored state.
This process begins as VDD rises to V
completed t

afterward. Thus for all practical

RES

MIN

and is

purposes, the nonvolatile values have been restored
as soon as the system logic is functional on power­up. After the restore process, the latch is
indistinguishable from its last state prior to power
down and operates normally.

No

Read

complete?

Yes

Restore data to

user latch, drive

pins

Restore

complete?

Yes

Allow user access

to latch, normal

operation

No

Block new writes to

NV-Latch, user latch

27 March 2001 3/10