RAMTRON FM25640-S, FM25640-P Datasheet

This data sheet contains design specifications for product development. Ramtron International Corporation
These specifications may change in any manner without not ice 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, [phone], Fax [phone]
www.ramtron.com

23 October 2000 1/14

FM25640

64Kb FRAM Serial Memory

Features

64K bit Ferroelectric Nonvolatile RAM

• Organized as 8,192 x 8 bits

• High endurance 10 Billion (1010) read/writes

• 10 year data retention at 85° C

• NoDelay™ write

• Advanced high-reliability ferroelectric process

Very Fast Serial Peripheral Interface - SPI

• Up to 5 MHz maximum bus frequency

• Direct hardware replacement for EEPROM

• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)

Sophisticated Write Protection Scheme

• Hardware protection

• Software protection

Low Power Consumption

• 10 µA standby current

Industry Standard Configuration

• Industrial temperature -40° C to +85° C

• 8-pin SOP or DIP

Description

The FM25640 is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for 10 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.

Unlike serial EEPROMs, the FM25640 performs
write operations at bus speed. No write delays are
incurred. Data is written to the memory array mere
hundreds of nanoseconds after it has been
successfully transferred to the device. The next bus
cycle may commence immediately. In addition, the
product offers substantial write endurance compared
with other nonvolatile memories. The FM25640 is
capable of supporting up to 1E10-read/write cycles -­far more than most systems will require from a serial
memory.

These capabilities make the FM25640 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.

The FM25640 provides substantial benefits to users
of serial EEPROM, in a hardware drop-in
replacement. The FM25640 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. It is guaranteed over an
industrial temperature range of -40°C to +85°C.

Pin Configuration

CS

SO

WP

VSS

VDD
HOLD

SCK

SI

Pin Names Function

/CS Chip Select
SO Serial Data Output
/WP Write Protect
VSS Ground
SI Serial Data Input
SCK Serial Clock
/HOLD Hold
VDD 5V

Ordering Information

FM25640-P 8-pin plastic DIP
FM25640-S 8-pin SOP

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Figure 1. Block Diagram

Instruction Decode

Clock Generator

Control Logic
Write Protect

Instruction Register

Address Register

Counter

`

2,048 x 32

FRAM Array

13

Data I/O Register

8

Nonvolatile Status

Register

3

WP

CS

HOLD

SCK

SO

Pin Description

Pin Name Pin Number I/O Pin Description

/CS 1 I Chip Select. Activates the device. When high, all outputs are tri-state and

the device ignores other inputs. The part remains in a low-power standby
mode. When low, the part recognizes activity on the SCK signal. A
falling edge on /C S must occur prior to every op-code.

SO 2 O Serial Output. SO is the data output pin. It is driven actively during a

read and remains tri-state at all other times including when HOLD\ is
low. Data transitions are driven on the falling edge of the serial clock.
* SO can be connected to SI for a single pin data interface since the part
communicates in half-duplex.

/WP 3 I Write Protect. This pin prevents write operations to the status register.

This is critical since other write protection features are controlled through
the status register. A complete explanation of write protection is provided
below. *Note that the function of /WP is different from the FM25040

where it prevents all writes to the part.
VSS 4 I Ground
SI 5 I Serial Input. All data is input to the device on this pin. The pin is

sampled on the rising edge of SCK and is ignored at other times. It

should always be driven to a valid logic level to meet IDD specifications.

* SI may be connected to SO for a single pin data interface.
SCK 6 I Serial Clock. All I/O activity is synchronized to the serial clock. Inputs

are latched on the rising edge and outputs occur on the falling edge. The

part is static so the clock frequency may be any value between 0 and 5

MHz and may be interrupted at any time.
/HOLD 7 I Hold. The /HOLD signal is used when the host CPU must interrupt a

memory operation for another task. Taking the /HOLD signal to a low

state pauses the current operation. The part ignores any transition on

SCK or /CS. All transitions on /HOLD must occur while SCK is low.
VDD 8 I Supply Voltage. 5V

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Overview

The FM25640 is a serial FRAM memory. The
memory array is logically organized as 8,192 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the FRAM is similar to serial EEPROMs. The
major difference between the FM25640 and a serial
EEPROM with the same pin-out relates to its
superior write performance.

Memory Architecture

When accessing the FM25640, the user addresses
8,192 lo cations each with 8 data bits. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code and a
two-byte address. The upper 3 bits of the address
range are ‘don’t care’ values. The complete address
of 13-bits specifies each byte address uniquely.

Most functions of the FM25640 either are controlled
by the SPI interface or are handled automatically by
on-board circuitry. The access time for memory
operation essentially is zero, beyond the time needed
for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike an
EEPROM, it is not necessary to poll the device for a
ready condition since writes occur at bus speed. That
is, by the time a new bus transaction can be shifted
into the part, a write operation will be complete. This
is explained in more detail in the interface section
below.

Users expect several obvious system benefits from
the FM25640 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.

Note that the FM25640 contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that VDD is within data sheet tolerances to
prevent incorrect operation.

Serial Peripheral Interface – SPI Bus

The FM25640 employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to 5
MHz. This high-speed serial bus provides high
performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25640 operates in SPI Mode 0 and 3.

The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. It is possible to
connect the two data lines together. Figure 2
illustrates a typical system configuration using the
FM25640 with a microcontroller that offers an SPI
port. Figure 3 shows a similar configuration for a
microcontroller that has no hardware support for the
SPI bus.

Protocol Overview

The SPI interface is a synchronous serial interface
using clock and data lines. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25640 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25640 supports modes 0 and 3. Figure 4 shows
the required signal relationships for mo des 0 and 3.
For both modes, data is clocked into the FM25640 on
the rising edge of SCK and data is expected on the
first rising edge after /CS goes active. If the clock
begins from a high state, it will fall prior to beginning
data transfer in order to create the first rising edge.

The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the part. After /CS
is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.

Certain op-codes are commands with no subsequent
data transfer. The /CS must go inactive after an
operation is complete and before a new op-code can
be issued. There is one valid op-code only per active
chip select.

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Figure 2. System Configuration with SPI port

SPI

Micro controller

FM25640

MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select

FM25640

Figure 3. System Configuration without SPI port

Microcontroller

P1.0

P1.1

P1.2

FM25640

Figure 4. SPI Modes 0 & 3

SPI Mode 0: CPOL=0, CPHA=0

01234567

SPI Mode 3: CPOL=1, CPHA=1

01234567

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Data Transfer

All data transfers to and from the FM25640 occur in
8-bit groups. They are synchronized to the clock
signal (SCK) and they transfer most significant bit
(MSB) first. Serial inputs are clocked in on the rising
edge of SCK. Outputs are driven on the falling edge
of SCK.

Command Structure

There are six commands called op-codes that can be
issued by the bus master to the FM25640. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, are commands
that have no subsequent operations. They perform a
single function such as to enable a write operation.
Second are commands followed by one byte, either in
or out. They operate on the status register. La st are
commands for memory transactions followed by
address and one or more bytes of data.

Table 1. Op -code Commands

Name Description Op-code value
WREN Set Write Enable Latch

00000110b

WRDI Write Disable

00000100b

RDSR Read Status Register

00000101b

WRSR Write Status Register

00000001b

READ Read Memory Data

00000011b

WRITE Write Memory Data

00000010b

WREN - Set Write Enable Latch

The FM25640 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.

Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 4 below illustrates the
WREN command bus configuration.

WRDI - Write Disable

The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are dis abled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
5 below illustrates the WRDI command bus
configuration.

Figure 5. WREN Bus Configuration

Figure 6. WRDI Bus Configuration