RAMTRON FM24C256-SE Datasheet

Preliminary Data Sheet

FM24C256

256Kb FRAM Serial Memory

Features

256Kbit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits

• High Endurance 100 Billion (10

• 10 year Data Retention

• NoDelay™ Writes

• Advanced High-Reliability Ferroelectric Process

Fast Two-wire Serial Interface

• Up to 1 MHz M aximum Bus Frequency

• Supports Legacy Timing for 100 kHz & 400 kHz

Description

The FM24C256 is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.

The FM24C256 performs write operations at bus
speed. No write delays are incurred. The next bus
cycle may commence immediately without the need
for data polling. In addition, the product offers
virtually unlimited write endurance, orders of
magnitude more endurance than EEPROM. Also,
FRAM exhibits much lower power during writes than
EEPROM since write operations do not require an
internally elevated power supply voltage for write
circuits.

These capabilities make the FM24C256 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.

The FM24C256 is provided in a 8-pin EIAJ SOP
package using a familiar two-wire protocol. It is
guaranteed over an industrial temperature range of

-40°C to +85°C.

11

) Read/Writes

Low Power Operation

• True 5V Operation

• 200 µA Active Current (100 kHz)

• 100 µA Standby Current

Industry Standard Configurat ion

• Industrial Temperature -40° C to +85° C

• 8-pin EIAJ SOP

Pin Configuration

A0
A1
A2

VSS

1
2
3
4

Pin Names Function

A0-A2 Device Select Address
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
VSS Ground
VDD Supply Voltage 5V

8
7
6
5

VDD
WP
SCL
SDA

Ordering Information

FM24C256-SE 8-pin SOP EIAJ

This is a product in sampling or pre-produ ction phase of develop-
ment. Characteristic data and other specifications are subject to 1850 Ramtron Drive, Colorado Springs, CO 80921
change without notice. (800) 545-FRAM, [phone], Fax [phone]

Ramtron International Corporation

www.ramtron.com

Rev 1.1
Sept 2001 Page 1of 13

FM24C256

A0-A2

SDA

SCL

WP

Counter

Address

Latch

4,096 x 64

FRAM Array

8

`

Serial to Parallel

Converter

Data Latch

Control Logic

Figure 1. Block Diagram

Pin Description

Pin Name Type Pin Description

A0-A2 Input Address 0-2. These pins are used to select one of up to 8 devices of the same type on

the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.

WP Input Write Protect. When tied to VDD, the entire array will be write-protected. When WP is

connected to ground, all addresses may be written. This pin is pulled down internally.

SDA I/O Serial Data Address. This is a bi-directional line for the two-wire interface. It is open-

drain and is intended to be wire-ORed with other devices on the two-wire bus. The
input buffer incorporates a schmitt trigger for noise immunity and the output driver
includes slope control for falling edges. A pull-up resistor is required.

SCL Input Serial Clock. The serial clock line for the two-wire interface. Data is clocked out of the

part on the falling edge, and in on the rising edge. The SCL input also incorporates a

schmit trigger input for noise immunity.
VDD Supply Supply Voltage. 5V
VSS Supply Ground

Rev 1.1
Sept 2001 Page 2 of 13

FM24C256

Overview

The FM24C256 is a serial FRAM memory. The
memory array is logically organized as 32,768 x 8 bit
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24C256 and a serial
EEPROM relates to its superior write performance.

Two-wire Interface

The FM24C256 employs a bi-directional two-wire
bus protocol using few. Figure 2 illustrates a typical
system configuration using the FM24C256 in a
microcontroller-based system. The industry standard
two-wire bus is familiar to many users but is
described in this section.

By convention, any device that is se nding data onto

Memory Architecture

When accessing the FM24C256, the user addresses
32,768 locations each with 8 data bits. These data bits
are shifted serially. The 32,768 addresses are
accessed using the two-wire protocol, which includes
a slave address (to distinguish other non-memory
devices), and an extended 16-bit address. Only the
lower 15 bits are used by the decoder for accessing
the memory. The upper address bit should be set to 0
for compatibility with larger devices in the future.

The memory is read or written at the speed of the
two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the time a

the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24C256 always is a slave device.

The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including Start, Stop, Data bit, and Acknowledge.
Figure 3 illustrates the signal conditions that specify
the four states. Detailed timing diagrams are shown
in the electrical specifications.

VDD

new bus transaction can be shifted into the part, a
write operation is complete. This is explained in more
detail in the interface section below.

Microcontroller

Rmin = 1.8 K

Rmax = tR/Cbus

Ω

Users expect several obvious system benefits from
the FM24C256 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM

SDA SCL

FM24C256

A0 A1 A2

SDA SCL

FM24C64

A0 A1 A2

since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.

Note that the FM24C256 contains no power
management circuits other than a simple internal

Figure 2. Typical System Configuration

power-on reset. It is the user’s responsibility to
ensure that V

is maintained within data sheet

DD

tolerances to prevent incorrect operation.

Rev 1.1
Sept 2001 Page 3 of 13

FM24C256

7

Stop

(Master)

Start

(Master)

Data bits

(Transmitter)

Figure 3. Data Transfer Protocol

Stop Condition

A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24C256 must end
with a Stop condition. If an operation is pending
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a Stop condition.

Start Condition

A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM24C256 for a new operation.

If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation.

Data/Address Transfer

All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.

Acknowledge

The Acknowledge takes place after the 8

th

data bit
has been transferred in any transaction. During this
state the transmitter should release the SDA bus to
allow the receiver to drive it. The receiver drives the
SDA signal low to acknowledge receipt of the byte.
If the receiver does not drive SDA low, the condition
is a No-Acknowledge and the operation is aborted.

The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge ends the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.

6

0

Data bit

(Transmitter)

Acknowledge

(Receiver)

Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24C256
will continue to place data onto the bus as long as
the receiver sends Acknowledges (and clocks).
When a read operation is complete and no more data
is needed, the receiver must not acknowledge the
last byte. If the receiver acknowledges the last byte,
this will cause the FM24C256 to attempt to drive
the bus on the next clock while the master is sending
a new command such as Stop.

Slave Address

The first byte that the FM24C256 expects after a
Start condition is the slave address. As shown in
Figure 4, the slave address contains the Slave ID
(device type), the device select address bits, and a
bit that specifies if the transaction is a read or a
write.

Bits 7-4 are the device type and should be set to
1010b for the FM24C256. These bits allow other
types of function types to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
address select bits. They must match the
corresponding value on the external address pins to
select the device. Up to eight FM24C256 devices
can reside on the same two-wire bus by assigning a
different address to each. Bit 0 is the read/write bit.
A 0 indicates a write operation.

Slave

ID

1010A2A1A0R/W

7654321 0

Device

Select

Figure 4. Slave Address

Rev 1.1
Sept 2001 Page 4 of 13