RAMTRON FM24C16A Technical data

FM24C16A

16Kb FRAM Serial Memory

Features

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2,048 x 8 bits

• High Endurance (10

• 45 year Data Retention

• NoDelay™ Writes

• Advanced High-Reliability Ferroelectric Process

Fast Two-wire Serial Interface

• Up to 1MHz maximum bus freq uency

• Direct hardware replacement for EEPROM

Description

The FM24C16A is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for over 45
years while eliminating the complexities, overhead,
and system level reliability problems caused by
EEPROM and other nonvolatile memories.

Unlike serial EEPROMs, the FM24C16A performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
FM24C16A is capable of supporting 10
cycles, or a million times more write cycles than
EEPROM.

These capabilities make the FM24C16A ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows the system to write
data more frequently, with less system overhead.

The FM24C16A provides substantial benefits to users
of serial EEPROM, and these benefits are available as
a hardware drop-in replacement. The FM24C16A is
available in an industry standard 8-pin SOIC and uses
a two-wire protocol. The specifications are
guaranteed over the industrial temperature range from

-40°C to +85°C.

12

) Read/Write Cycles

12

read/write

Low Power Operation

• 5V operation

• 150 µA Active Current (100 kHz)

• 10 µA Standby Current

Industry Standard Configurat ion

• Industrial Temperature -40° C to +85° C

• 8-pin SOIC (-S)

• “Green” 8-pin SOIC (-G)

Pin Configuration

NC
NC

NC

VSS

1
2
3
4

Pin Names Function

SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
VDD Supply Voltage 5V
VSS Ground

8
7
6
5

VDD
WP
SCL
SDA

Ordering Information

FM24C16A-S 8-pin SOIC
FM24C16A-G “Green” 8-pin SOIC

This product conforms to specifications per the terms of the Ramtron Ramtron International Corporation
standard warranty. The product has completed Ramtron’s internal 1850 Ramtron Drive, Colorado Springs, CO 80921
qualification testing and has reached production status. (800) 545-FRAM, [phone]

Rev. 3.0
Mar. 2005 Page 1 of 12

www.ramtron.com

FM24C16A

Counter

SDA

SCL

WP

Pin Description

Pin Name Type Pin Description

SDA I/O Serial Data Address: This is a bi-directional data pin for the two-wire interface. It

SCL Input Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on

WP Input Write Protect: W hen WP is high, the entire array is write-protected. When WP is low,

VDD Supply Supply Voltage (5V)
VSS Supply Ground
NC - No connect

`

Serial to Parallel

Converter

Control Logic

Figure 1. Block Diagram

employs an open-drain output and is intended to be wire-OR’d with other devices on the
two-wire bus. The input buffer incorpo rates a Schmitt trigger for noise immunity and the
output driver includes slope control for falling edges. A pull-up resistor is required.

the falling edge and clocked-in on the rising edge.

all addresses may be written. This pin is internally pulled down.

Address

Latch

256 x 64

FRAM Array

8

Data Latch

Rev 3.0
Mar. 2005 Page 2 of 12

FM24C16A

Overview

The FM24C16A is a serial FRAM memory. The
memory array is logically organized as a 2,048 x 8
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24C16A and a serial
EEPROM with the same pinout relates to its superior
write performance.

Memory Architecture

When accessing the FM24C16A, the user addresses
2,048 locations each with 8 data bits. These data bits
are shifted serially. The 2,048 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish from other non-memory
devices), a row address, and a segment address. The
row address consists of 8-bits that specify one of 256
rows. The 3-bit segment address specifies one of 8
segments within each row. The complete 11-bit
address specifies each byte uniquely.

Most functions of the FM24C16A either are
controlled by the two-wire interface or handled
automatically by on-board circuitry. The memory is
read or written at the speed of the two-wire bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready cond ition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation is complete.
This is explained in more detail in the interface
section below.

Note that the FM24C16A contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to ensure
that VDD is within data sheet tolerances to prevent
incorrect operation.

Two-wire Interface

The FM24C16A employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24C16A in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.

By convention, any device tha t is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24C16A is always a slave device.

The bus protocol is contr olled by transition states in
the SDA and SCL signals. There are four conditions
including Start, Stop, Data bit, and Acknowledge.
Figure 3 illustrates the signal conditions that define
the four states. Detailed timing diagrams are shown in
the Electrical Specifications section.

VDD

Rmin = 1.8 K?

Rmax = tR/Cbus

Microcontroller

SDA SCL

FM24C16A

Figure 2. Typical System Configuration

SDA SCL

Other Slave Dev ice

Rev 3.0
Mar. 2005 Page 3 of 12

FM24C16A

SCL

SDA

Stop

(Master)

Start

(Master)

Figure 3. Data Transfer Protocol

Stop Condition

A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24 C16A must end
with a Stop condition. If an operation is pending
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a Stop co ndition.

Start Condition

A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
prepare the FM24C16A for a new operation.

If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation.

Data/Address Transfer

All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high. For system design
considerations, keeping SCL in a lo w state while idle
improves robustness.

Acknowledge

The Acknowledge takes place after the 8

th

data bit has
been transferred in any transaction. During this state,
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
No-Acknowledge and the operation is aborted.

7

Data bits

(Transmitter)

6

0

Data bit

(Transmitter)

Acknowledge

(Receiver)

The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge ends the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.

Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24C16A
will continue to place data onto the bus as long as the
receiver sends Acknowledges (and clocks). When a
read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24C16A to attempt to drive the bus
on the next clock while the master is sending a new
command such as a Stop.

Slave Address

The first byte that the FM24C16A expects after a
Start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the page of memory to be accessed, and a bit that
specifies if the transaction is a read or a write.

Bits 7-4 are the device type and should be set to
1010b for the FM24C16A. The device type allows
other types of functions to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
page select. They specify the 256-byte block of
memory that is targeted for the current operation. Bit
0 is the read/write bit. A 0 indicates a write operation.

Rev 3.0
Mar. 2005 Page 4 of 12