Rainbow Electronics АDC0805 User Manual

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
8-Bit mP Compatible A/D Converters

December 1994

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

8-Bit mP Compatible A/D Converters

General Description

The ADC0801, ADC0802, ADC0803, ADC0804 and
ADC0805 are CMOS 8-bit successive approximation A/D
converters that use a differential potentiometric ladderÐ
similar to the 256R products. These converters are de­signed to allow operation with the NSC800 and INS8080A
derivative control bus with TRI-STATE

output latches di-

É

rectly driving the data bus. These A/Ds appear like memory
locations or I/O ports to the microprocessor and no inter­facing logic is needed.

Differential analog voltage inputs allow increasing the com­mon-mode rejection and offsetting the analog zero input
voltage value. In addition, the voltage reference input can
be adjusted to allow encoding any smaller analog voltage
span to the full 8 bits of resolution.

Features

Y

Compatible with 8080 mP derivativesÐno interfacing
logic needed - access time - 135 ns

Y

Easy interface to all microprocessors, or operates
‘‘stand alone’’

Typical Applications

Y

Differential analog voltage inputs

Y

Logic inputs and outputs meet both MOS and TTL volt­age level specifications

Y

Works with 2.5V (LM336) voltage reference

Y

On-chip clock generator

Y

0V to 5V analog input voltage range with single 5V
supply

Y

No zero adjust required

Y

0.3×standard width 20-pin DIP package

Y

20-pin molded chip carrier or small outline package

Y

Operates ratiometrically or with 5 VDC, 2.5 VDC, or ana­log span adjusted voltage reference

Key Specifications

Y

Resolution 8 bits

Y

Total error

Y

Conversion time 100 ms

g

(/4 LSB,g(/2 LSB andg1 LSB

TL/H/5671– 1

8080 Interface

Error Specification (Includes Full-Scale,

Zero Error, and Non-Linearity)

Part

Number

Full-

Scale

Adjusted

V

/2e2.500 VDCV

REF

(No Adjustments) (No Adjustments)

/2eNo Connection

REF

ADC0801g(/4 LSB

ADC0802

g

(/2 LSB

ADC0803g(/2 LSB

ADC0804

TL/H/5671– 31

TRI-STATEÉis a registered trademark of National Semiconductor Corp.
Z-80

is a registered trademark of Zilog Corp.

É

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/H/5671

ADC0805

g

1 LSB

g

1 LSB

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V
Voltage

Logic Control Inputs
At Other Input and Outputs

Lead Temp. (Soldering, 10 seconds)

) (Note 3) 6.5V

CC

b

0.3V toa18V

b

0.3V to (V

CC

a

0.3V)

Dual-In-Line Package (plastic) 260
Dual-In-Line Package (ceramic) 300

Surface Mount Package

Vapor Phase (60 seconds) 215
Infrared (15 seconds) 220

Storage Temperature Range

Package Dissipation at T

e

25§C 875 mW

A

ESD Susceptibility (Note 10) 800V

Operating Ratings (Notes1&2)

Temperature Range T

ADC0801/02LJ, ADC0802LJ/883b55§CsT

C

§

C

§

C

§

C

§

ADC0801/02/03/04LCJ
ADC0801/02/03/05LCN
ADC0804LCN 0
ADC0802/03/04LCV 0
ADC0802/03/04LCWM 0

Range of V

CC

b

65§Ctoa150§C

s

T

MIN

s

A

b

40§CsT

b

A

40§CsT

A

CsT

§

A

CsT

§

A

CsT

§

A

4.5 VDCto 6.3 V

A

s
s
s
s
s

s

a

a
a
a
a
a

T

MAX

125§C

85§C
85§C
70§C
70§C
70§C

DC

Electrical Characteristics

s

The following specifications apply for V

CC

e

5VDC,T

MIN

s

T

T

A

MAX

and f

e

640 kHz unless otherwise specified.

CLK

Parameter Conditions Min Typ Max Units

ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj.

ADC0802: Total Unadjusted Error (Note 8) V

ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj.

ADC0804: Total Unadjusted Error (Note 8) V

ADC0805: Total Unadjusted Error (Note 8) V

V

/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kX

REF

(See Section 2.5.2)

/2e2.500 V

REF

DC

(See Section 2.5.2)

/2e2.500 V

REF

/2-No Connection

REF

DC

ADC0804 (Note 9) 0.75 1.1 kX

Analog Input Voltage Range (Note 4) V(a)orV(b) Gnd–0.05 V

DC Common-Mode Error Over Analog Input Voltage

Power Supply Sensitivity V

Range

e

g

5V

DC

10% Over

CC

Allowed VIN(a) and VIN(b)
Voltage Range (Note 4)

g

(/16

g

(/16

g

(/4 LSB

g

(/2 LSB

g

(/2 LSB

g

1 LSB

g

1 LSB

a

0.05 V

CC

g

(/8 LSB

g

(/8 LSB

DC

AC Electrical Characteristics

The following specifications apply for V

e

5VDCand T

CC

Symbol Parameter Conditions Min Typ Max Units

T

C

T

C

f

CLK

CR Conversion Rate in Free-Running INTR tied to WR with 8770 9708 conv/s

t

W(WR)L

t

ACC

t1H,t

tWI,t

C

IN

C

OUT

Conversion Time f

Conversion Time (Note 5, 6) 66 73 1/f

Clock Frequency V
Clock Duty Cycle (Note 5) 40 60 %

Mode CS

Width of WR Input (Start Pulse Width) CSe0VDC(Note 7) 100 ns

Access Time (Delay from Falling C
Edge of RD

TRI-STATE Control (Delay C

0H

from Rising Edge of RD
Hi-Z State) Circuits)

Delay from Falling Edge 300 450 ns

RI

of WR or RD to Reset of INTR

Input Capacitance of Logic 5 7.5 pF
Control Inputs

TRI-STATE Output 5 7.5 pF
Capacitance (Data Buffers)

to Output Data Valid)

to (See TRI-STATE Test

CONTROL INPUTS[Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately

VIN(1) Logical ‘‘1’’ Input Voltage V

(Except Pin 4 CLK IN)

e

25§C unless otherwise specified.

A

e

640 kHz (Note 6) 103 114 ms

CLK

e

5V, (Note 5) 100 640 1460 kHz

CC

e

0VDC,f

e

100 pF 135 200 ns

L

e

10 pF, R

L

e

5.25 V

CC

e

640 kHz

CLK

e

10k 125 200 ns

L

DC

2.0 15 V

CLK

]

DC

2

AC Electrical Characteristics (Continued)

s

5V

DC

DC

DC

DC

DC

s

T

T

A

, unless otherwise specified.

MAX

0.005 1 mA

b

e

4.75 V

CC

CC

CC

CC

e

e

e

4.75 V

4.75 V

4.75 V

DC

DC

2.4 V

DC

4.5 V

DC

b

e

25§C 4.5 6 mA

A

e

25§C 9.0 16 mA

A

e

25§C

A

supply. Be careful, during testing at low VCClevels (4.5V),

CC

does not exceed the supply voltage by more than 50 mV, the output

IN

pulse (see timing diagrams).

b

1

0.005 mA

3 mA

]

0.8 V

0.4 V

0.4 V

3 mA

Figure 5

.

DC

DC

DC

DC

DC

DC

DC

DC

DC

DC

DC

DC

DC

DC

DC

DC

e

The following specifications apply for V

CC

5VDCand T

MIN

Symbol Parameter Conditions Min Typ Max Units

CONTROL INPUTS[Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately

VIN(0) Logical ‘‘0’’ Input Voltage V

(Except Pin 4 CLK IN)

IIN(1) Logical ‘‘1’’ Input Current V

(All Inputs)

IIN(0) Logical ‘‘0’’ Input Current V

(All Inputs)

CC

IN

IN

e

e

e

4.75 V

5V

0V

DC

DC

CLOCK IN AND CLOCK R

a

V

T

b

V

T

V

H

V

OUT

V

OUT

CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 V
Threshold Voltage

CLK IN (Pin 4) Negative 1.5 1.8 2.1 V
Going Threshold Voltage

CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 V

a)b

(V

T

(0) Logical ‘‘0’’ CLK R Output I

Voltage V

(1) Logical ‘‘1’’ CLK R Output I

Voltage V

b

(V

)

T

e

360 mA 0.4 V

O

e

4.75 V

CC

eb

360 mA 2.4 V

O

e

4.75 V

CC

DATA OUTPUTS AND INTR

V

(0) Logical ‘‘0’’ Output Voltage

OUT

Data Outputs I
INTR Output I

V

(1) Logical ‘‘1’’ Output Voltage I

OUT

V

(1) Logical ‘‘1’’ Output Voltage I

OUT

I

OUT

I

SOURCE

I

SINK

TRI-STATE Disabled Output V
Leakage (All Data Buffers) V

e

OUT

e

OUT

eb

360 mA, V

O

eb

O

e

OUT

e

OUT

V

Short to Gnd, T

OUT

V

Short to VCC,T

OUT

1.6 mA, V

1.0 mA, V

10 mA, V

0V
5V

POWER SUPPLY

I

CC

Supply Current (Includes f
Ladder Current) V

e

CLK

REF

and CS

640 kHz,

/2eNC, T

e

ADC0801/02/03/04LCJ/05 1.1 1.8 mA
ADC0804LCN/LCV/LCWM 1.9 2.5 mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.

Note 3: A zener diode exists, internally, from V

Note 4: For V

conduct for analog input voltages one diode drop below ground or one diode drop greater than the V
as high level analog inputs (5V) can cause this input diode to conduct – especially at elevated temperatures, and cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog V
code will be correct. To achieve an absolute 0 V
variations, initial tolerance and loading.

Note 5: Accuracy is guaranteed at f
extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.

Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see

Note 7: The CS
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR

Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and

Note 9: The V

ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kX. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kX.

Note 10: Human body model, 100 pF discharged through a 1.5 kX resistor.

(b)tVIN(a) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward

IN

CLK

input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold

/2 pin is the center point of a two-resistor divider connected from VCCto ground. In all versions of the ADC0801, ADC0802, ADC0803, and

REF

Figure 2

to Gnd and has a typical breakdown voltage of 7 VDC.

CC

to5VDCinput voltage range will therefore require a minimum supply voltage of 4.950 VDCover temperature

DC

e

640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be

and section 2.0.

3

Typical Performance Characteristics

Delay From Falling Edge of
Logic Input Threshold Voltage
vs. Supply Voltage

RD

to Output Data Valid

vs. Load Capacitance

CLK IN Schmitt Trip Levels
vs. Supply Voltage

f

vs. Clock Capacitor

CLK

Output Current vs
Temperature

Full-Scale Error vs

Conversion Time

Power Supply Current

vs Temperature (Note 9)

Effect of Unadjusted Offset Error
vs. V

/2 Voltage

REF

Linearity Error at Low

/2 Voltages

V

REF

TL/H/5671– 2

4

TRI-STATE Test Circuits and Waveforms

t

1H

e

t

20 ns

r

t1H,C

e

10 pF

L

t

Timing Diagrams (All timing is measured from the 50% voltage points)

e

t0H,C

0H

e

t

20 ns

r

L

10 pF

TL/H/5671– 3

Output Enable and Reset INTR

Note: Read strobe must occur 8 clock periods (8/f

) after assertion of interrupt to guarantee reset of INTR.

CLK

5

TL/H/5671– 4

Typical Applications (Continued)

6800 Interface Ratiometric with Full-Scale Adjust

Absolute with a 2.500V Reference

*For low power, see also LM385-2.5

Zero-Shift and Span Adjust: 2V

Note: before using caps at VINor V

see section 2.3.2 Input Bypass Capacitors.

Absolute with a 5V Reference

s

s

V

5V Span Adjust: 0VsV

IN

REF

/2,

s

3V

IN

TL/H/5671– 5

6

Typical Applications (Continued)

Directly Converting a Low-Level Signal

1 mV Resolution with mP Controlled Range

V

/2e128 mV

REF

e

1 LSB

1mV

s

s

V

DAC

a

V

(V

DAC

256 mV)

IN

V

REF

/2e256 mV

A mP Interfaced Comparator

For: VIN(a)lVIN(b)

e

Output

FF

Output

HEX

e

00

HEX

For: VIN(a)kVIN(b)

Digitizing a Current Flow

7

TL/H/5671– 6

Typical Applications (Continued)

Self-Clocking Multiple A/Ds

External Clocking

*Use a large R value

to reduce loading
at CLK R output.

Self-Clocking in Free-Running Mode

*After power-up, a momentary grounding

input is needed to guarantee operation.

of the WR

Operating with ‘‘Automotive’’ Ratiometric Transducers

CLK

s

1460 kHz

100 kHzsf

mP Interface for Free-Running A/D

Ratiometric with V

/2 Forced

REF

*VIN(b)e0.15 V

15% of V

s

CC

CC

s

V

85% of V

XDR

CC

TL/H/5671– 7

8

Typical Applications (Continued)

mP Compatible Differential-Input Comparator with Pre-Set V

*See

Figure 5

to select R value

e

DB7

‘‘1’’ for VIN(a)lVIN(b)a(V

Omit circuitry within the dotted area if

hysteresis is not needed

Handlingg10V Analog Inputs

/2)

REF

Low-Cost, mP Interfaced, Temperature-to-Digital Converter

(with or without Hysteresis)

OS

*Beckman InstrumentsÝ694-3-R10K resistor array

mP Interfaced Temperature-to-Digital Converter

s

*Circuit values shown are for 0§CsT

**Can calibrate each sensor to allow easy replacement, then

A/D can be calibrated with a pre-set input voltage.

a

128§C

A

TL/H/5671– 8

9

Typical Applications (Continued)

Handling

g

5V Analog Inputs

Read-Only Interface

*Beckman InstrumentsÝ694-3-R10K resistor array

TL/H/5671– 33

mP Interfaced Comparator with Hysteresis

TL/H/5671– 35

Analog Self-Test for a System

TL/H/5671– 34

Protecting the Input

Diodes are 1N914

TL/H/5671– 9

A Low-Cost, 3-Decade Logarithmic Converter

TL/H/5671– 36

*LM389 transistors

e

A, B, C, D

10

TL/H/5671– 37

LM324A quad op amp

Typical Applications (Continued)

3-Decade Logarithmic A/D Converter

Noise Filtering the Analog Input

e

f

20 Hz

C

Uses Chebyshev implementation for steeper roll-off
unity-gain, 2nd order, low-pass filter
Adding a separate filter for each channel increases
system response time if an analog multiplexer
is used

Output Buffers with A/D Data Enabled

Multiplexing Differential Inputs

Increasing Bus Drive and/or Reducing Time on Bus

*A/D output data is updated 1 CLK period
prior to assertion of INTR

TL/H/5671– 10

*Allows output data to set-up at falling edge of CS

11