Rainbow Electronics W9864G6GB User Manual

W9864G6GB

1M × 4 BANKS × 16 BITS SDRAM

Table of Contents-

1. GENERAL DESCRIPTION.............................................................................................................3

2. FEATURES .................................................................................................................................... 3

3. AVAILABLE PART NUMBER......................................................................................................... 3

4. PIN CONFIGURATION .................................................................................................................. 4

5. PIN DESCRIPTION........................................................................................................................ 5

6. BLOCK DIAGRAM ......................................................................................................................... 6

7. FUNCTIONAL DESCRIPTION....................................................................................................... 7

7.1 Power Up and Initialization.................................................................................................. 7

7.2 Programming Mode Register .............................................................................................. 7

7.3 Bank Activate Command..................................................................................................... 7

7.4 Read and Write Access Modes........................................................................................... 7

7.5 Burst Read Command......................................................................................................... 8

7.6 Burst Command...................................................................................................................8

7.7 Read Interrupted by a Read................................................................................................ 8

7.8 Read Interrupted by a Write ................................................................................................ 8

7.9 Write Interrupted by a Write ................................................................................................ 8

7.10 Write Interrupted by a Read ................................................................................................ 8

7.11 Burst Stop Command .......................................................................................................... 9

7.12 Addressing Sequence of Sequential Mode ......................................................................... 9

7.13 Addressing Sequence of Interleave Mode .......................................................................... 9

7.14 Auto-precharge Command ................................................................................................ 10

7.15 Precharge Command ........................................................................................................ 10

7.16 Self Refresh Command ..................................................................................................... 10

7.17 Power Down Mode ............................................................................................................ 11

7.18 No Operation Command ................................................................................................... 11

7.19 Deselect Command........................................................................................................... 11

7.20 Clock Suspend Mode ........................................................................................................ 11

8. TABLE OF OPERATING MODES ............................................................................................... 12

8.1 Simplified State Diagram................................................................................................... 13

9. ABSOLUTE MAXIMUM RATING ................................................................................................. 14

10. RECOMMENDED DC OPERATING CONDITIONS .................................................................... 14

Publication Release Date: August 14, 2006

- 1 - Revision A01

W9864G6GB

CAPACITANCE ............................................................................................................................ 14

11.

12. DC CHARACTERISTICS ............................................................................................................. 15

13. AC CHARACTERISTICS ............................................................................................................. 16

14. TIMING WAVEFORMS ................................................................................................................19

14.1 Command Input Timing ..................................................................................................... 19

14.2 Read Timing ...................................................................................................................... 20

14.3 Control Timing of Input Data ............................................................................................. 21

14.4 Control Timing of Output Data........................................................................................... 22

14.5 Mode Register Set Cycle................................................................................................... 23

15. OPERATING TIMING EXAMPLE................................................................................................. 24

15.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) .......................................... 24

15.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)................. 25

15.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) .......................................... 26

15.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)................. 27

15.5 Interleaved Bank Write (Burst Length = 8) ........................................................................ 28

15.6 Interleaved Bank Write (Burst Length = 8, Autoprecharge) .............................................. 29

15.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ................................................... 30

15.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3).......................................... 31

15.9 Autoprecharge Read (Burst Length = 4, CAS Latency = 3).............................................. 32

15.10 Autoprecharge Write (Burst Length = 4) ........................................................................... 33

15.11 Autorefresh Cycle .............................................................................................................. 34

15.12 Self-refresh Cycle ..............................................................................................................35

15.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)................................... 36

15.14 Power-down Mode............................................................................................................. 37

15.15 Auto-precharge Timing (Write Cycle) ................................................................................ 38

15.16 Auto-precharge Timing (Read Cycle)................................................................................ 39

15.17 Timing Chart of Read to Write Cycle................................................................................. 40

15.18 Timing Chart of Write to Read Cycle................................................................................. 41

15.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) ................................................ 42

15.20 CKE/DQM Input Timing (Write Cycle) ............................................................................... 43

15.21 CKE/DQM Input Timing (Read Cycle)............................................................................... 44

15.22 Self Refresh/Power Down Mode Exit Timing .................................................................... 45

16. PACKAGE DIMENSIONS ............................................................................................................ 46

17. VERSION HISTORY .................................................................................................................... 47

- 2 -

W9864G6GB

1. GENERAL DESCRIPTION

W9864G6GB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words × 4 banks × 16 bits. Using pipelined architecture and 110nm process technology,
W9864G6GB delivers a data bandwidth of up to 286MHz bytes per second (-7). The -7 parts can run
up to 143MHz/CL3.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance.

2. FEATURES

• The -7 grade can support 2.7V〜3.6V power supply

• 1048576 words × 4 banks × 16 bits organization

• Self Refresh Current: Standard and Low Power

• CAS latency: 3

• Burst Length: 1, 2, 4, 8, and full page

• Sequential and Interleave burst

• Burst read, single write operation

• Byte data controlled by DQM

• Power-down Mode

• Auto-precharge and controlled precharge

• 4K refresh cycles/64 mS

• Interface: LVTTL

• Package: VFBGA 60 balls pitch=0.65

• W9864G6GB

is using lead free materials with RoHS

3. AVAILABLE PART NUMBER

PART

NUMBER

W9864G6GB-7 143 MHz 2mA

SPEED (CL = 3)

SELF REFRESH CURRENT

(MAX.)

OPERATING

TEMPERATURE

0°C ~ 70°C

Publication Release Date: August 14, 2006

- 3 - Revision A01

4. PIN CONFIGURATION

A

A

A

A

A

A

A

A

A10A

A

A

A

A11A8A

A

A

A

A

A10A

A

A0A

W9864G6GB

VSS

DQ14

DQ13

DQ12

DQ10

DQ9

DQ8

NC

NC

NC

CKE

11

8

6

VSS

B

C

D

E

F

G

H

J

K

L

M

N

P

R

Top View

1

DQ15

VSSQ

VDDQ

DQ11

VSSQ

VDDQ

NC

VSS

UDQM

CLK

NC

9

7

5

4

762

DQ0

VDDQ

VSSQ

DQ4

VDDQ

VSSQ

NC

VDD

LDQM

RAS#

NC

BS1

0

2

3

VDD

DQ1

DQ2

DQ3

DQ5

DQ6

DQ7

NC

WE#

CAS#

CS#

BS0

1

VDD

VDD

DQ1

DQ2

DQ3

DQ5

DQ6

DQ7

NC

WE#

CAS#

CS#

BS0

1

VDD

Bottom View

7 6 2 1

DQ0

VDDQ

VSSQ

DQ4

VDDQ

VSSQ

NC

VDD

LDQM

RAS#

NC

BS1

DQ15

VSSQ

VDDQ

DQ11

VSSQ

VDDQ

NC

VSS

UDQM

CLK

NC

9

7

2

3

5

4

VSS

DQ14

DQ13

DQ12

DQ10

DQ9

DQ8

NC

NC

NC

CKE

6

VSS

- 4 -

5. PIN DESCRIPTION

BALL LOCATION PIN NAME FUNCTION DESCRIPTION

Multiplexed pins for row and column address.
M1,M2,N1,N2,N6,
N7,P1,P2,P6,P7,

R6,

M6,M7

A2,A6,B1,B7,C1,C7
,D1,D2,D6,D7,E1,E
7,F1,F7,G1,G7

L7

K6

K7

J7

J2,J6

K2 CLK Clock Inputs

L1 CKE Clock Enable

A7,H6,R7 VDD

A1,H2,R1 VSS Ground

B6,C2,E6,F2 VDDQ

B2,C6,E2,F6 VSSQ

G2,G6,H1,H7,J1,K1
,L2,L6

A0−A11

BS0, BS1 Bank Select

DQ0−DQ15

CS

RAS

CAS

WE

UDQM
LDQM

NC

Address

Data Input/
Output

Chip Select

Row Address
Strobe

Column
Address
Strobe

Write Enable

Input/output
mask

Power
(+3.3V)

Power
(+3.3V) for I/O
buffer

Ground for I/O
buffer

No
Connection

Row address: A0−A11. Column address: A0−A7.

A10 is sampled during a precharge command to

determine if all banks are to be precharged or

bank selected by BS0, BS1.

Select bank to activate during row address latch

time, or bank to read/write during address latch

time.

Multiplexed pins for data output and input.

Disable or enable the command decoder. When

command decoder is disabled, new command is

ignored and previous operation continues.

Command input. When sampled at the rising edge

of the clock

operation to be executed.

Referred to

Referred to

The output buffer is placed at Hi-Z (with latency of

2) when DQM is sampled high in read cycle. In

write cycle, sampling DQM high will block the

write operation with zero latency.

System clock used to sample inputs on the rising

edge of clock.

CKE controls the clock activation and

deactivation. When CKE is low, Power Down

mode, Suspend mode, or Self Refresh mode is

entered.

Power for input buffers and logic circuit inside

DRAM.

Ground for input buffers and logic circuit inside

DRAM.

Separated power from VDD, to improve DQ noise

immunity.

Separated ground from V

immunity.

No connection

RAS, CAS

RAS

RAS

and WE define the

SS, to improve DQ noise

W9864G6GB

Publication Release Date: August 14, 2006

- 5 - Revision A01

6. BLOCK DIAGRAM

W9864G6GB

CKE

RAS

CLK

CAS

WE

A10

A11
BS0
BS1

CLOCK

BUFFER

CS

COMMAND

DECODER

A0

ADDRESS

A9

REFRESH

COUNTER

BUFFER

CONTROL

GENERATOR

MODE
REGISTER

COLUMN

COUNTER

SIGNAL

COLUMN DECODER

CELL ARRAY

BANK #0

ROW DECODER

SENSE AMPLIFIER

COLUMN DECODER

DATA CONTROL

CIRCUIT

COLUMN DECODER

CELL ARRAY

BANK #1

ROW DECODERROW DECODER

SENSE AMPLIFIER

COLUMN DECODER

DQ
BUFFER

DQ0

DQ15

UDQM
LDQM

CELL ARRAY

BANK #2

ROW DECODER

SENSE AMPLIFIER

NOTE:

The cell array configuration is 4096 * 256 * 16

- 6 -

CELL ARRAY

BANK #3

SENSE AMPLIFIER

W9864G6GB

7. FUNCTIONAL DESCRIPTION

7.1 Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.

During power up, all V
when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.3V
on any of the input pins or V
followed by a precharge of all banks using the precharge command. To prevent data contention on the
DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required
before or after programming the Mode Register to ensure proper subsequent operation.

7.2 Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low

signals of
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to t
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

RAS , CAS , CS and WE at the positive edge of the clock. The address input data

CC and VCCQ pins must be ramp up simultaneously to the specified voltage

CC supplies. After power up, an initial pause of 200 µS is required

RSC has

7.3 Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t

RCD). Once a bank has been activated it must be precharged before another Bank

Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t

RC).

The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (t
specified as T

RAS (max.).

RRD). The maximum time that each bank can be held active is

7.4 Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting

RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level

defines whether the access cycle is a read operation (
address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.

WE high), or a write operation ( WE low). The

Publication Release Date: August 14, 2006

- 7 - Revision A01

W9864G6GB

7.5 Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding

RAS

and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.

7.6 Burst Command

The Burst Write command is initiated by applying logic low level to CS , CAS and WE while

RAS

holding
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.

7.7 Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.

high at the rising edge of the clock. The address inputs determine the starting column

7.8 Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.

7.9 Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.

7.10 Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.

- 8 -

W9864G6GB

7.11 Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop

Command is defined by having
the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS
Latency in a burst read cycle, interrupted by Burst Stop.

7.12 Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA ACCESS ADDRESS BURST LENGTH

Data 0 n BL = 2 (disturb address is A0)

Data 1 n + 1 No address carry from A0 to A1

Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)

Data 3 n + 3 No address carry from A1 to A2

Data 4 n + 4

Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)

Data 6 n + 6 No address carry from A2 to A3

Data 7 n + 7

RAS and CAS high with CS and WE low at the rising edge of

7.13 Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA ACCESS ADDRESS BUST LENGTH

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

A8 A7 A6 A5 A4 A3 A2 A1

A8 A7 A6 A5 A4 A3 A2

A8 A7 A6 A5 A4 A3 A2

A8 A7 A6 A5 A4 A3

A8 A7 A6 A5 A4 A3

A8 A7 A6 A5 A4 A3

A8 A7 A6 A5 A4 A3

Publication Release Date: August 14, 2006

A2

A2 A1 A0

A2 A1 A0

A2 A1 A0

- 9 - Revision A01

A0

A1 A0

A1 A0

A1 A0

BL = 4

BL = 8

W9864G6GB

7.14 Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto-precharge cannot be interrupted before the entire burst
operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is
prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started,
the bank cannot be reactivated until the Precharge time (t
Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write
Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically
enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred
to as write t
satisfied. This is referred to as t

DPL. The bank undergoing auto-precharge cannot be reactivated until tWR and tRP are

DAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-

precharge Command, the interval between the Bank Activate Command and the beginning of the
internal precharge operation must satisfy t

RAS (min).

7.15 Precharge Command

RP) has been satisfied. Issue of Auto-

The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when

CS , RAS and WE are low and CAS is high at the rising

edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(t

RP).

7.16 Self Refresh Command

The Self Refresh Command is defined by having CS , RAS, CAS and CKE held low with WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal
to the t

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.

AC cycle time plus the Self Refresh exit time.

- 10 -

W9864G6GB

7.17 Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (t
device.

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t
enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.).

CK. The input buffers need to be

7.18 No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when
the clock. A No Operation Command will not terminate a previous operation that is still executing,
such as a burst read or write cycle.

CS is low with RAS, CAS , and WE held high at the rising edge of

7.19 Deselect Command

REF) of the

The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when

cares.

CS is brought high, the RAS , CAS , and WE signals become don't

7.20 Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.

Publication Release Date: August 14, 2006

- 11 - Revision A01

W9864G6GB

8. TABLE OF OPERATING MODES

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.

TABLE 1 TRUTH TABLE (NOTE (1), (2))

COMMAND

Bank Active Idle H x x v v V L L H H

Bank Precharge Any H x x v L x L L H L

Precharge All Any H x x x H x L L H L

Write Active (3) H x x v L v L H L L

Write with
Autoprecharge

Read Active (3) H x x v L v L H L H

Read with
Autoprecharge

Mode Register Set Idle H x x v v v L L L L

No-Operation Any H x x x x x L H H H

Burst Stop Active (4) H x x x x x L H H L

Device Deselect Any H x x x x x H x x x

Auto-Refresh Idle H H x x x x L L L H

Self-Refresh Entry Idle H L x x x x L L L H

Self Refresh Exit

Clock suspend Mode
Entry

Power Down Mode
Entry

Clock Suspend Mode
Exit

Power Down Mode Exit

Data write/Output
Enable

Data Write/Output
Disable

Notes:

(1) v = valid, x = Don't care, L = Low Level, H = High Level

(2) CKEn signal is input leve l when commands are provided.

(3) These are state of bank designated by BS0, BS1 signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

DEVICE

STATE

Active (3) H x x v H v L H L L

Active (3) H x x v H v L H L H

Idle

(S.R)

Active H L x x x x x x x x

Idle

Active (5)

Active L H x x x x x x x X

Any

(power

down)

Active H x L x x x x x x x

Active H x H x x x x x x x

CKEN-1 CKEN DQM BS0, 1 A10 A0-A9

L
L

H
H

L
L

H H x

L
L

H H x

x

x

x

x

x
x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

RAS CAS WE

CS

H

L

H

L

H

L

H

H

H

x

x

x

x H x

x

x H X

H

x H X

H

- 12 -

8.1 Simplified State Diagram

Mode

Register

Set

F

L

E

S

e

F

L

E

ACT

S

C

K

E

C

K

E

MRS REF

IDLE

t

i

x

Self

Refresh

Power

Down

CBR

Refresh

W9864G6GB

Write

POWER

ON

CKE

CKE

CKE

CKE

WRITE

SUSPEND

WRITEA

SUSPEND

Notes:

MRS = Mode Register Set
REF = Refresh
ACT = Active
PRE = Precharge
WRITEA = Write with Auto precharge
READA = Read with Auto precharge

S

B

WRITE

WRITEA

Precharge

CKE

ROW

ACTIVE

T

e

t

i

r

W

P

R

E

(

p

r

e

h

t

i

w

e

t

i

r

t

u

W

A

Read

c
h

a

r

g

e

t

e

r

m

Precharge

A

R

e

u

g

r

t

o

a

R

h

p

e

c

r

a

e

e

d

r

c

p

h

w

a

o

i

n

i

t

r

h

g

e

Write

t

a

PRE

n

i

m

r

e

t

e

g

r

a
h
c

e

r
p

(

a

t

E

i

o

R

n

P

)

CKE

e

a

)

n

o

i

d

B

S

T

READ

READA

Active
Power

Down

Read

CKE

CKE

CKE

CKE

READ

SUSPEND

READA

SUSPEND

Automatic sequence

Manual input

Publication Release Date: August 14, 2006

- 13 - Revision A01

W9864G6GB

9. ABSOLUTE MAXIMUM RATING

PARAMETER SYM. RATING UNIT NOTES

Input, Column Output Voltage(-7) VIN, VOUT 2.7V~3.6V V 1

Power Supply Voltage VCC, VCCQ

Operating Temperature(-7) TOPR

Storage Temperature TSTG

-0.3 − 4.6

0 − 70

-55 − 150

Soldering Temperature (10s) TSOLDER 260

V 1

°C

°C

°C

1

1

1

Power Dissipation PD 1 W 1

Short Circuit Output Current IOUT 50 mA 1

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

10. RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to 70°C for -7)

PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES

Power Supply Voltage(-7) VCC 2.7 3.3 3.6 V 2

Power Supply Voltage for I/O Buffer(-7) VCCQ 2.7 3.3 3.6 V 2

Input High Voltage VIH 2.0 - VCC +0.3 V 2

Input Low Voltage VIL -0.3 - 0.8 V 2

Note: VIH (max.) = VCC/VCCQ+1.2V for pulse width < 5 nS, VIL (min.) = VSS/VSSQ-1.2V for pulse width < 5 nS

11. CAPACITANCE

(VCC

= 2.7V~3.6V, T

Input Capacitance

(A0 to A11, BS0, BS1,

Input Capacitance (CLK) CCLK 2.5 4 pf

Input/Output Capacitance (DQ0−DQ15)

Input Capacitance DQM Ci2 3.0 5.5 pf

Note: These parameters are periodically sampled and not 100% tested

A = 25 °C, f = 1 MHz)

PARAMETER SYM. MIN. MAX. UNIT

CS, RAS, CAS

, WE , , CKE)

- 14 -

C

i1 2.5 4 pf

o 4 6.5 pf

C

12. DC CHARACTERISTICS

(VCC=2.7V~3.6V, TA = 0 to 70°C )

PARAMETER SYM. -7 ( MAX.) UNIT NOTES

Operating Current
tCK = min., tRC = min.
Active precharge command

cycling without burst
operation

Standby Current
tCK = min., CS = VIH

VIH/L = VIH (min.)/VIL
(max.)

Bank: Inactive State

Standby Current

CLK = VIL,
VIH/L=VIH (min.)/VIL (max.)

BANK: Inactive State

No Operating Current
tCK = min., CS= VIH (min.)

BANK: Active State (4
banks)

Burst Operating Current (tCK = min.)
Read/Write command cycling

Auto Refresh Current (tCK = min.)
Auto refresh command cycling

Self Refresh Current
Self refresh mode

(CKE = 0.2V)

CS = VIH

1 bank operation

CKE = VIH

CKE = VIL
(Power Down
mode)

CKE = VIH

CKE = VIL
(Power Down
mode)

CKE = VIH ICC3 55

CKE = VIL
(Power Down
mode)

Standard(-7) ICC6 2

W9864G6GB

ICC1 80 3

ICC2 30 3

ICC2P 2 3

ICC2S 15

mA

ICC2PS 2

ICC3P 15

ICC4 145 3, 4

ICC5 120 3

PARAMETER SYMBOL MIN. MAX. UNIT NOTES

Input Leakage Current

(0V ≤ VIN ≤ VCC, all other pins not under test = 0V)

Output Leakage Current

(Output disable, 0V ≤ VOUT ≤ VCCQ)

LVTTL Output ″H″ Level Voltage

(IOUT = -2 mA)

LVTTL Output

(IOUT = 2 mA)

"

L″ Level Voltage

Publication Release Date: August 14, 2006

II(L) -5 5

IO(L) -5 5

VOH 2.4 - V

VOL - 0.4 V

µA

µA

- 15 - Revision A01