W9864G2GH
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. AVAILABLE OPTIONS................................................................................................................ 4
4. PIN ASSIGNMENT ..................................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION.................................................................................................... 7
7.1 Power Up and Initialization ............................................................................................. 7
7.2 Programming Mode Register.......................................................................................... 7
7.3 Bank Activate Command ................................................................................................ 7
7.4 Read and Write Access Modes ...................................................................................... 7
7.5 Burst Read Command .................................................................................................... 8
7.6 Burst Command.............................................................................................................. 8
7.7 Read Interrupted by a Read ........................................................................................... 8
7.8 Read Interrupted by a Write............................................................................................ 8
7.9 Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode .................................................................... 9
7.13 Addressing Sequence of Interleave Mode...................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode ....................................................................................................... 11
7.18 No Operation Command............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
8. TABLE OF OPERATING MODES ............................................................................................ 12
9. DC CHARACTERISTICS.......................................................................................................... 14
9.1 Absolute Maximum Rating............................................................................................ 14
10. RECOMMENDED DC OPERATING CONDITIONS................................................................. 14
11. CAPACITANCE......................................................................................................................... 15
11.1 DC CHARACTERISTICS.............................................................................................. 15
Publication Release Date: August 16 ,2006
- 1 - Revision A01
W9864G2GH
12.
AC CHARACTERISTICS .......................................................................................................... 16
13. TIMING WAVEFORMS............................................................................................................. 19
13.1 Command Input Timing ................................................................................................ 19
13.2 Read Timing.................................................................................................................. 20
13.3 Control Timing of Input Data......................................................................................... 21
13.4 Control Timing of Output Data ...................................................................................... 22
13.5 Mode Register Set Cycle .............................................................................................. 23
14. OPERATING TIMING EXAMPLE ............................................................................................. 24
14.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 24
14.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) ............ 25
14.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 26
14.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) ............ 27
14.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 28
14.6 Interleaved Bank Write (Burst Length = 8, Autoprecharge).......................................... 29
14.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 30
14.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 31
14.9 Autoprecharge Read (Burst Length = 4, CAS Latency = 3) ......................................... 32
14.10 Autoprecharge Write (Burst Length = 4) ..................................................................... 33
14.11 Autorefresh Cycle........................................................................................................ 34
14.12 Self-refresh Cycle........................................................................................................ 35
14.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)............................. 36
14.14 Power-down Mode ...................................................................................................... 37
14.15 Auto-precharge Timing (Write Cycle).......................................................................... 38
14.16 Auto-precharge Timing (Read Cycle).......................................................................... 39
14.17 Timing Chart of Read to Write Cycle........................................................................... 40
14.18 Timing Chart of Write to Read Cycle........................................................................... 41
14.19 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 42
14.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 43
14.21 CKE/DQM Input Timing (Write Cycle)......................................................................... 44
14.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 45
14.23 Self Refresh/Power Down Mode Exit Timing .............................................................. 46
15. PACKAGE DIMENSIONS......................................................................................................... 47
15.1 86L TSOP (II)-400 mil................................................................................................... 47
16. REVISION HISTORY ................................................................................................................48
- 2 -
W9864G2GH
1. GENERAL DESCRIPTION
W9864G2GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words × 4 banks × 32 bits. Using pipelined architecture and 0.11 µm process technology,
W9864G2GH delivers a data bandwidth of up to 800M bytes per second. For different application,
W9864G2GH is sorted into the following speed grades:-5,-6,-7.The -5 parts can run up to
200MHz/CL3.The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9864G2GH is ideal for main memory in
high performance applications.
2. FEATURES
• 3.3V± 0.3V for -5/-6 grade power supply and 2.7V〜3.6V for -7/ -7S grade power supply.
• Interface : LVTTL.
• Four banks operation.
• CAS latency 3.
• Burst length (1, 2, 4, 8 & Full page).
• Burst type (Sequential & Interleave).
• Burst read single-bit write operation.
• DQM for masking.
• Auto & self refresh.
• 64ms refresh period (4K cycle).
• W9864G2GH is using Lead free materials
• All inputs are sampled at the positive going edge of the system clock .
Publication Release Date: August 16 ,2006
- 3 - Revision A01
3. AVAILABLE OPTIONS
W9864G2GH
PART NUMBER SPEED (CL = 3) SELF REFRESH CURRENT (MAX.)
W9864G2GH-5 200 MHz 2mA
W9864G2GH-6 166 MHz 2mA
W9864G2GH-7 143 MHz 2mA
4. PIN ASSIGNMENT
VCC
DQ0
V
CC
DQ1
DQ2
V
SS
DQ3
DQ4
V
CC
DQ5
DQ6
VSSQ
DQ7
VCC
DQM0
CAS
RAS
BS0
BS1
A10/AP
DQM2
V
DQ16
V
SS
DQ17
DQ18
V
CC
DQ19
DQ20
V
SS
DQ21
DQ22
V
CC
DQ23
V
1
2
3
Q
4
5
6
Q
7
8
9
Q
10
11
12
13
14
NC
15
16
17
WE
18
19
20
CS
21
NC
22
23
24
25
A0
26
A1
27
A2
28
CC
29
NC
30
31
Q
32
33
34
Q
35
36
37
38
Q
39
40
41
Q
42
43
CC
86
V
ss
DQ15
85
84
V
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
SS
DQ14
DQ13
V
CC
DQ12
DQ11
V
SS
DQ10
DQ9
V
CC
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
CC
DQ30
DQ29
V
SS
DQ28
DQ27
V
CC
DQ26
DQ25
V
SS
DQ24
V
SS
OPERATING
TEMPERATURE
0°C ~ 70°C
0°C ~ 70°C
0°C ~ 70°C
Q
Q
Q
Q
Q
Q
Q
Q
- 4 -
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION DESCRIPTION
24, 25, 26, 27, 60, 61, 62, 63,
64, 65, 66
22, 23 BS0, BS1 Bank Select
2, 4, 5, 7, 8, 10, 11, 13, 31, 33,
34, 36, 37, 39, 40, 42, 45, 47,
48, 50, 51, 53, 54, 56, 74, 76,
77, 79, 80, 82, 83, 85
20
19
18
A0−A10
DQ0−
DQ31
CS
RAS
CAS
Address
Data Input/
Output
Chip Select
Row Address
Strobe
Column Address
Strobe
W9864G2GH
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or
bank selected by BS0, BS1.
Select bank to activate during row address latch
time, or bank to read/write during address latch
time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising
edge of the clock
define the operation to be executed.
Referred to RAS
RAS , CAS and WE
17
16, 28, 59, 71
68 CLK Clock Inputs
67 CKE Clock Enable
1, 15, 29, 43 VCC Power
44, 58, 72, 86 VSS Ground
3, 9, 35, 41, 49, 55, 75, 81 VCCQ
6, 12, 32, 38, 46, 52, 78, 84 VSSQ
14, 21, 30, 57, 69, 70, 73 NC No Connection
WE
DQM0−
DQM3
Write Enable
Input/Output
Mask
Power for I/O
Buffer
Ground for I/O
Buffer
Referred to RAS
The output buffer is placed at Hi-Z (with latency
of 2) when DQM is sampled high in read cycle.
In write cycle, sampling DQM high will block the
write operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and
deactivation. When CKE is low, Power Down
mode, Suspend mode, or Self Refresh mode is
entered.
Power for input buffers and logic circuit inside
DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Separated power from VCC, to improve DQ
noise immunity.
Separated ground from VSS, to improve DQ
noise immunity.
No connection.(The NC pin must connect to
ground or floating.)
Publication Release Date: August 16 ,2006
- 5 - Revision A01
6. BLOCK DIAGRAM
W9864G2GH
CLK
CKE
RAS
CAS
A10
BS0
BS1
CLOCK
BUFFER
CS
COMMAND
DECODER
WE
A0
ADDRESS
A9
REFRESH
COUNTER
BUFFER
CONTROL
GENERATOR
MODE
REGISTER
COLUMN
COUNTER
SIGNAL
COLUMN DECODER
CELL ARRAY
BANK #0
ROW DECODER
SENSE AMPLIFIER
COLUMN DECODER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #1
ROW DECODERROW DECODER
SENSE AMPLIFIER
COLUMN DECODER
DQ
BUFFER
DQ0
DQ31
DQM0~3
CELL ARRAY
BANK #2
ROW DECODER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 2048 * 256 * 32
- 6 -
CELL ARRAY
BANK #3
SENSE AMPLIFIER
W9864G2GH
7. FUNCTIONAL DESCRIPTION
7.1 Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all
when the input signals are held in the “NOP” state. The power up voltage must not exceed
on any of the input pins or
by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been precharged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.
7.2 Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to t
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
RAS , CAS , CS and WE at the positive edge of the clock. The address input data
VCC and VCCQ pins must be ramp up simultaneously to the specified voltage
VCC +0.3V
VCC supplies. After power up, an initial pause of 200 µS is required followed
RSC has
7.3 Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t
RCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t
RC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (t
specified as T
RAS (max.).
RRD). The maximum time that each bank can be held active is
7.4 Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS
high and
defines whether the access cycle is a read operation (
address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.
CAS
low at the clock rising edge after minimum of tRCD delay.
WE high), or a write operation ( WE low). The
Publication Release Date: August 16 ,2006
- 7 - Revision A01
WE
pin voltage level
7.5 Burst Read Command
W9864G2GH
The Burst Read command is initiated by applying logic low level to CS and
RAS and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
CAS
while holding
7.6 Burst Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
RAS high at the rising edge of the clock. The address inputs determine the starting column
7.7 Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
7.8 Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
7.9 Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
7.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
- 8 -
W9864G2GH
7.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having
the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS
Latency in a burst read cycle, interrupted by Burst Stop.
RAS
7.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 n BL = 2 (disturb address is A0)
Data 1 n + 1 No address carry from A0 to A1
Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)
Data 3 n + 3 No address carry from A1 to A2
Data 4 n + 4
Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)
Data 6 n + 6 No address carry from A2 to A3
Data 7 n + 7
and
CAS
high with CS and WE low at the rising edge of
7.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA ACCESS ADDRESS BUST LENGTH
Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
A8 A7 A6 A5 A4 A3 A2 A1
A8 A7 A6 A5 A4 A3 A2
A8 A7 A6 A5 A4 A3 A2
A8 A7 A6 A5 A4 A3
A8 A7 A6 A5 A4 A3
A8 A7 A6 A5 A4 A3
A8 A7 A6 A5 A4 A3
A2 A1 A0
A2 A1 A0
A2 A1 A0
A2 A1 A0
- 9 - Revision A01
A0
A1
A0
A1 A0
Publication Release Date: August 16 ,2006
BL = 4
BL = 8
W9864G2GH
7.14 Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto-precharge cannot be interrupted before the entire burst
operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is
prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started,
the bank cannot be reactivated until the Precharge time (t
Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write
Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically
enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred
to as write t
satisfied. This is referred to as t
DPL. The bank undergoing auto-precharge cannot be reactivated until tDPL and tRP are
DAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-
precharge Command, the interval between the Bank Activate Command and the beginning of the
internal precharge operation must satisfy t
RAS (min).
7.15 Precharge Command
RP) has been satisfied. Issue of Auto-
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when
CS , RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(t
RP).
7.16 Self Refresh Command
The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal
to the t
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
AC cycle time plus the Self Refresh exit time.
- 10 -
W9864G2GH
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (t
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t
enabled with CKE held high for a period equal to tCES (min.) + tCK (min.).
CK. The input buffers need to be
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
CS
is low with
RAS, CAS
, and
WE
held high at the rising edge of
7.19 Deselect Command
REF) of the
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when
CS
is brought high, the
RAS, CAS
, and
WE
signals become don’t cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
Publication Release Date: August 16 ,2006
- 11 - Revision A01
W9864G2GH
8. TABLE OF OPERATING MODES
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
TABLE 1 TRUTH TABLE (NOTE (1), (2))
COMMAND DEVICE
STATE
Bank Active Idle H x x v v V L L H H
Bank Precharge Any H x x v L x L L H L
Precharge All Any H x x x H x L L H L
Write Active (3) H x x v L v L H L L
Write with Autoprecharge Active (3) H x x v H v L H L L
Read Active (3) H x x v L v L H L H
Read with Autoprecharge Active (3) H x x v H v L H L H
Mode Register Set Idle H x x v v v L L L L
No-Operation Any H x x x x x L H H H
Burst Stop Active (4) H x x x x x L H H L
Device Deselect Any H x x x x x H x x x
Auto-Refresh Idle H H x x x x L L L H
Self-Refresh Entry Idle H L x x x x L L L H
Self Refresh Exit idle
(S.R)
Clock suspend Mode Entry Active H L x x x x x x x x
Power Down Mode Entry Idle
Active (5) H H
Clock Suspend Mode Exit Active L H x x x x x x x X
Power Down Mode Exit Any
(power
down)
Data write/Output Enable Active H x L x x x x x x x
Data Write/Output Disable Active H x H x x x x x x x
Notes:
(1) v = valid, x = Don’t care, L = Low Level, H = High Level
(2) CKEn signal is input leve l when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
CKEN-1 CKEN DQM BS0, 1 A10 A0-A9
L
L
L
L
H
H
L
L
H
H
x
x
x
x
x
x
x
x
x
x
x
x
x
x x H L x H x Hx
x
x
x x H L x H x HX
x
x
x x H L x H x HX
x
CS
RAS CAS
WE
x
H
H
- 12 -
SIMPLIFIED STATE DIAGRAM
Mode
Register
Set
F
L
E
S
e
F
L
E
MRS REF
IDLE
S
C
K
E
C
K
E
ACT
t
i
x
Self
Refresh
Power
Down
CBR
Refresh
W9864G2GH
Write
POWER
ON
CKE
CKE
CKE
CKE
WRITE
SUSPEND
WRITEA
SUSPEND
MRS = Mode Register Set
REF = Refresh
ACT = Active
PRE = Precharge
WRITEA = Write with Auto precharge
READA = Read with Auto precharge
B
WRITE
WRITEA
Precharge
CKE
ROW
ACTIVE
T
S
e
t
i
r
W
P
R
E
(
p
r
e
c
h
t
i
w
e
t
i
r
o
t
u
W
A
Read
h
a
r
g
e
t
e
r
m
Precharge
A
R
e
u
PRE
t
o
p
Write
R
P
e
R
e
r
a
e
d
c
h
w
a
i
t
r
h
g
e
i
t
a
n
i
m
r
e
t
e
g
r
a
h
c
e
r
p
(
E
g
r
a
h
c
e
r
p
i
n
a
t
i
o
n
)
CKE
a
)
n
o
d
B
S
T
READ
READA
Active
Power
Down
Read
CKE
CKE
CKE
CKE
READ
SUSPEND
READA
SUSPEND
Automatic sequence
Manual input
Publication Release Date: August 16 ,2006
- 13 - Revision A01
W9864G2GH
9. DC CHARACTERISTICS
9.1 Absolute Maximum Rating
PARAMETER SYM. RATING UNIT NOTES
Input, Column Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
IN, VOUT
V
VCC, VCCQ
OPR
T
STG
T
SOLDER
T
D
P
OUT
I
10. RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to 70°C)
-0.3~
VCC+0.3V V 1
-0.3~4.6V V 1
0 − 70
-55 − 150
260
°C
°C
°C
1
1
1
1 W 1
50 mA 1
PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Power Supply Voltage(-7)
Power Supply Voltage
VCC
VCCQ
VCC
VCCQ
3.0 3.3 3.6 V
3.0 3.3 3.6 V
2.7 3.3 3.6 V
2.7 3.3 3.6 V
(for I/O Buffer)(-7)
Input High Voltage VIH 2 - VCC +0.3 V 1
Input Low Voltage VIL -0.3 - +0.8 V 2
Output logic high voltage
Output logic low voltage
Input leakage current
Note: 1. VIH (max.) = VCC/VCCQ+1.2V for pulse width < 5 nS
2. VIL (min.) = VSS/VSSQ-1.2V for pulse width
3. Any input 0V
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
<VIN<VCCQ.
VOH 2.4V - - V
VOL - - 0.4 V
ILI -10 - 10 uA 3
< 5 nS
IOH=2mA
IOL= 2mA
- 14 -
11. CAPACITANCE
(VCC
3.3V±0.3V, TA = 25 °C, f = 1 MHz)
=
W9864G2GH
PARAMETER SYM. MIN. MAX. UNIT
Input Capacitance
C
(A0 to A10, BS0, BS1,
CS, RAS, CAS
, WE , DQM, CKE)
i 2.5 4 pf
Input Capacitance (CLK) CCLK 2.5 4 pf
o 4 6.5 pf
Input/Output capacitance (DQ0−DQ31)
Note: These parameters are periodically sampled and not 100% tested
C
11.1 DC CHARACTERISTICS
(VCC = 3.3V±0.3V, TA = 0°~70°C for -5/-6/-7)
PARAMETER SYM.
Operating Current
tCK = min., tRC = min.
Active precharge command
cycling without burst operation
Standby Current
tCK = min., CS = VIH
VIH/L = VIH (min.)/VIL (max.)
Bank: Inactive State
Standby Current
CLK = VIL, CS = VIH
VIH/L=VIH (min.)/VIL (max.)
BANK: Inactive State
No Operating Current
tCK = min.,
BANK: Active State (4 banks)
Burst Operating Current (tCK = min.)
Read/Write command cycling
Auto Refresh Current (tCK = min.)
Auto refresh command cycling
Self Refresh Current
Self refresh mode
(CKE = 0.2V)
CS = VIH (min.)
1 bank operation ICC1 150 140 130 3
CKE = VIH ICC2 40 35 30 3
CKE = VIL
(Power Down
mode)
CKE = VIH ICC2S 15 15 15
CKE = VIL
(Power Down
mode)
CKE = VIH ICC3 70 65 60
CKE = VIL
(Power Down
mode)
Standard(-5/-6/-7) ICC6 2 2 2
ICC2P 3 3 3 3
ICC2P
S
ICC3P 15 15 15
ICC4 180 170 160 3, 4
ICC5 240 220 200 3
-5 -6 -7
UNIT NOTES
MAX. MAX. MAX.
3 3 3
mA
Publication Release Date: August 16 ,2006
- 15 - Revision A01
12. AC CHARACTERISTICS
(V
= 3.3V±0.3V, V
CC
PARAMETER SYM.
Ref/Active to Ref/Active
Command Period
Active to precharge
Command Period
Active to Read/Write
Command Delay Time
Read/Write(a) to Read/
Write(b) Command
Period
Precharge to Active(b)
Command Period
Active(a) to Active(b)
Command Period
Write Recovery Time
CL* = 2
CL* = 3
CLK Cycle Time
CL* = 2
CL* = 3
CLK High Level
CLK Low Level
Access Time from CLK
CL* = 2
CL* = 3
Output Data Hold Time
Output Data High
Impedance Time
Output Data Low
Impedance Time
Power Down Mode
Entry Time
Transition Time of CLK
(Rise and Fall)
Data-in-Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode Register Set
Cycle Time
= 0V, Ta = 0 to 70 °C for -5/-6/-7) (Notes: 5, 6.)
SS
MIN. MAX. MIN. MAX. MIN. MAX.
tRC 55 60 65
tRAS 40 100000 42 100000 45 100000
tRCD 15 18 20
tCCD 1 1 1 tCK
tRP 15 18 20
tRRD 10 12 14
tWR 2 2 2 tCK
tCK 10 1000 10 1000 10 1000
5 1000 6 1000 7 1000
tCH 2 2 2
tCL 2 2 2
tAC
4.5 5 5.5
tOH 2 2 2
tHZ 2 5 2 6 2 7
tLZ 0 0 0
tSB 0 5 0 6 0 7
tT 0.5 5 0.5 5 0.5 5
tDS 1.5 1.5 1.5
tDH 1 1 1
tAS 1.5 1.5 1.5
tAH 1 1 1
tCKS 1.5 1.5 1.5
tCKH 1 1 1
tCMS 1.5 1.5 1.5
tCMH 1 1 1
tREF 64 64 64 mS
tRSC 10 12 14 nS
W9864G2GH
-5 -6 -7
－
6 6
UNIT NOTE
nS
nS
nS
- 16 -
W9864G2GH
A
Notes:
1.Operation exceeds “ABSOLUTE MAXIMUM RATING” may cause permanent damage to the
devices.
2. All voltages are referenced to V
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of t
CK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up Sequence
(1)Power up must be performed in the following sequence.
(2) Power must be applied to V
signals must be started at the same time.
(3) After power-up a pause of at least 200 µseconds is required. It is required that DQM and CKE signals then be held ‘
high‘ (V
CC levels) to ensure that the DQ output is impedance.
(4) All banks must be precharged.
(5) The Mode Register Set command must be asserted to initialize the Mode Register.
(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device
CC and VCCQ (simultaneously) while all input signals are held in the “NOP” state. The CLK
6. AC Testing Conditions
PARAMETER CONDITIONS
OUTPUT REFERENCE LEVEL
OUTPUT LOAD
Input Signal Levels (VIH/VIL)
Transition Time (Rise and Fall) of Input Signal
Input Reference Level
SS
1.4V
See diagram below
2.4V/0.4V
1 nS
1.4V
Z = 50 ohmsoutput
C TEST LOAD
1. Transition times are measured between VIH and VIL.
HZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
2. t
3. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as
follows the number of clock cycles = specified value of timing/ clock period
(count fractions as whole number)
CH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).
(1) t
1.4 V
50 ohms
30pF
Publication Release Date: August 16 ,2006
- 17 - Revision A01
W9864G2GH
tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).
(2) A.C Latency Characteristics
CKE to clock disable (CKE Latency) 1 tCK
DQM to output to HI-Z (Read DQM Latency) 2
DQM to output to HI-Z (Write DQM Latency) 0
Write command to input data (Write Data Latency) 0
CS to Command input ( CS Latency)
Precharge to DQ Hi-Z Lead time
Precharge to Last Valid data out
Bust Stop Command to DQ Hi-Z Lead time
Bust Stop Command to Last Valid Data out
Read with Auto-precharge Command to Active/Ref
Command
Write with Auto-precharge Command to Active/Ref Command
CL = 2 2
CL = 3 3
CL = 2 1
CL = 3 2
CL = 2 2
CL = 3 3
CL = 2 1
CL = 3 2
CL = 2 BL + tRP tCK + nS
CL = 3 BL + tRP
CL = 2 (BL+1)+ tRP
CL = 3 (BL+1)+ tRP
7.
Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
( The tT maximum can’t be more than 10nS for low frequency application. )
0
- 18 -
13. TIMING WAVEFORMS
13.1 Command Input Timing
K
t
C
IH
V
CLK
V
IL
t
CMStCMH
CS
t
CMStCMH
RAS
t
CMStCMH
CAS
t
CMH
W9864G2GH
t
t
CL
CH
t
T
t
T
t
CMS
t
CMStCMH
WE
t
AS
t
AH
A0-A10
BS0, 1
t
CKS
t
CKH
t
CKH
t
CKS
t
CKS
t
CKH
CKE
Publication Release Date: August 16 ,2006
- 19 - Revision A01
Timing Waveforms, continued
13.2 Read Timing
CLK
CS
RAS
CAS
W9864G2GH
Read CAS Latency
WE
A0-A10
BS0, 1
t
t
OH
Valid
Data-Out
AC
Burst Length
t
OH
Valid
Data-Out
t
HZ
DQ
Read Command
t
AC
t
LZ
- 20 -
Timing Waveforms, continued
13.3 Control Timing of Input Data
(Word Mask)
CLK
DQM0
DQM1
DQ0 -DQ7
DQ8-DQ15
DQ16 -DQ23
DQ24-DQ31
t
CMH
t
DS
t
DH
Valid
Data-in
t
DH
t
DS
Valid
Data-in
t
DH
t
DS
Valid
Data-in
t
DH
t
DS
Valid
Data-in
t
CMStCMH
t
DS
Valid
Data-in
t
DS
Valid
Data-in
t
DS
Valid
Data-in
t
DH
t
DH
t
DH
t
CMS
t
DStDH
t
DStDH
Data-in
t
DS
Data-in
t
DS
Data-in
Valid
Data-in
Valid
Valid
Valid
W9864G2GH
t
t
CMH
t
DH
t
DH
CMStCMH
t
DStDH
Valid
Data-in
t
DS
Valid
Data-in
t
DS
Valid
Data-in
t
DH
t
DH
t
CMS
t
DStDH
t
DStDH
t
DS
t
DS
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
DH
t
DH
*DQM2,3="L"
(Clock Mask)
CLK
t
CKH
t
CKStCKH
t
CKS
CKE
t
DQ0 -DQ7
DQ8 -DQ15
DQ16 -DQ23
DQ24 -DQ31
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
t
DH
t
DS
Valid
Data-in
t
DH
t
DS
Valid
Data-in
t
DH
t
DS
Valid
Data-in
t
DH
t
DS
Valid
Data-in
t
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
t
DStDH
Valid
Data-in
Publication Release Date: August 16 ,2006
- 21 - Revision A01
Timing Waveforms, continued
13.4 Control Timing of Output Data
(Output Enable)
CLK
t
DQM0
DQM1
DQ0 -DQ7
DQ8 -DQ15
DQ16 -DQ23
DQ24 -DQ31
CMH
t
OH
t
OH
t
OH
t
OH
t
AC
t
AC
t
AC
t
AC
t
CMStCMH
Valid
Data-Out
Valid
Data-Out
Data-Out
Data-Out
t
Valid
Valid
CMH
t
OH
t
OH
t
OH
t
OH
W9864G2GH
t
CMS
t
t
CMStCMH
t
AC
t
AC
t
AC
t
AC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
t
t
OH
t
t
OH
t
OH
t
OH
CMS
HZ
AC
t
HZ
t
HZ
OPEN
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
t
AC
t
LZ
t
HZ
t
OH
Valid
Data-Out
t
AC
t
OH
t
AC
t
LZ
OPEN
t
Valid
Data-Out
Valid
Data-Out
AC
t
OH
t
AC
t
OH
t
AC
t
LZ
t
AC
t
OH
*DQM2,3="L"
(Clock Mask)
CLK
CKE
DQ0 -DQ7
DQ8 -DQ15
DQ16 -DQ23
DQ24 -DQ31
t
CKH
t
OH
t
OH
t
OH
t
OH
t
CKStCKH
t
AC
t
AC
t
AC
t
AC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
t
OH
t
OH
t
OH
t
OH
t
CKS
t
t
AC
Valid
t
AC
t
AC
t
AC
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
AC
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
- 22 -
Timing Waveforms, continued
13.5 Mode Register Set Cycle
CLK
t
CMH
t
CMS
CS
t
CMH
t
CMS
RAS
t
CMStCMH
CAS
t
CMH
t
CMS
WE
W9864G2GH
t
RSC
A0-A10
BS0,1
t
AS
t
AH
Register
set data
A0
A1
Burst Length
A2
A3
Addressing Mode
A4
A5
CAS Latency
A6
A0
A7
A8 Reserved
A0
A9
A10
A0A11
BS0
A0BS1
(Test Mode)
"0"
"0"
Write Mode
"0"
"0"
Reserved
"0"
"0"
A0
A0
command
A0
A0A2 A1 A0
A00 0 0
A0
0 0 1
A00 1 0
A00 1 1
A0Burst Length
A0Sequential A0Interleave
1 A01
A0
2
A04 A04
A08 A08
A01 0 0
A0
1 0 1
A0
1 1 0
A01 1 1
A0
A3
A0
Reserved
A0Full Page
Addressing Mode
Reserved
A0
A00 A0Sequential
A01 A0Interleave
A0A6 A5 A4
A00 0 0
A00 0 1
A0
0 1 0
A00 1 1
A01 0 0
A0CAS Latency
A0Reserved
A0Reserved
2
A03
Reserved
A0A9 Single Write Mode
A00 A0Burst read and Burst write
A01 A0Burst read and single write
next
A0
2
A0
Publication Release Date: August 16 ,2006
- 23 - Revision A01
W9864G2GH
14. OPERATING TIMING EXAMPLE
14.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
1 2 3 4 5
0
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9
DQM
CKE
DQ
t
RC
t
RC
t
RAS
t
RCD
RAa RBb RAc RBd
RAa
CAw
t
RRD
t
AC
RBb
aw0
aw1
t
RCD
t
RP
t
RAS
CBx
aw2 aw3 bx0
t
RRD
RAc CAy
t
AC
t
RCD
bx1
t
RRD
bx2
bx3
t
t
RAS
t
RP
RBd CBz
t
AC
RC
t
RC
t
RP
t
RAS
t
RCD
RAe
RAe
t
AC
cy2
cy0
cy1
t
cy3
RRD
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
Read
Precharge
Active Read
Active
Precharge
Read
Active
Precharge
Read
Active
- 24 -
W9864G2GH
Operating Timing Example, continued
14.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
1 2 3 4 5 6 7 8 9 10
0
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9
DQM
CKE
DQ
t
RC
t
RC
t
RAS
t
RCD
RAa RAc
RAa CAw
RBb
RBb
t
RRD
t
RCD
t
AC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2
t
RRD
t
RP
t
RAS
CBx
RAc
t
AC
t
RC
t
RC
t
RAS
t
RP
t
RCD
CAy
t
AC
t
RRD
RBd
RBd
t
RCD
t
RP
t
RAS
RAe
CBz
t
RRD
RAe
t
AC
cy3
dz0
AP*
Read
Active
AP*
Active
Read
Bank #0
Bank #1
Bank #2
Bank #3
Idle
Active
Read
Active
* AP is the internal precharge start timing
AP*
Active
Read
Publication Release Date: August 16 ,2006
- 25 - Revision A01
W9864G2GH
Operating Timing Example, continued
14.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
8 9 10 11 12 13 14 15 16 17 18
t
RC
CLK
CS
1 2 3 4 5 6 7
0
19 20 21 22 23
RAS
CAS
WE
BS0
BS1
A10
A0-A9
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
t
RCD
RAa
RAa CAx
Active
Idle
t
RRD
Read
Precharge
t
RAS
t
RP
t
RCD
RBb
RBb CBy
t
AC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0
t
RRD
Active
Read
t
RP
t
RAS
RAc
RAc
t
AC
Precharge Active
t
RAS
t
RCD
CAz
t
AC
Read
Precharge
- 26 -
W9864G2GH
Operating Timing Example, continued
14.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
t
RC
21 22 23
CLK
CS
1 2 3 4 5
0
RAS
t
RAS
t
RP
t
RAS
CAS
WE
BS0
BS1
t
A10
A0-A9
RAa
RAa
RCD
CAx
t
RCD
RBb
RBb CBy
RAc
RAc
t
RCD
CAz
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
Read
t
CAC
ax0
ax1
t
RRD
ax3 ax4
ax2
Active
* AP is the internal precharge start timing
ax5 ax6 ax7 by0 by1 by4 by5 by6
t
RRD
AP*
Read
t
CAC
Active
Read
AP*
t
CAC
CZ0
Publication Release Date: August 16 ,2006
- 27 - Revision A01
Operating Timing Example, continued
14.5 Interleaved Bank Write (Burst Length = 8)
(CLK = 100 MHz)
CLK
CS
RAS
CAS
WE
BS0
BS1
1 2 3 4 5
0
t
RCD
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t
RC
t
RAS
t
RCD
W9864G2GH
t
RP
t
RAS
t
RCD
A10
A0-A9
RAa
RAa
CAx
RBb
RBb CBy
RAc
RAc CAz
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
ax0 ax1 by4 by5 by6 by7 CZ0 CZ1 CZ2
t
Active Write
Idle
RRD
ax4 ax5 ax6 ax7 by0 by1 by2 by3
t
RRD
Precharge
Active Write
Active
Write
Precharge
- 28 -
Operating Timing Example, continued
A
A
A
A
A
A
A
14.6 Interleaved Bank Write (Burst Length = 8, Autoprecharge)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RC
t
RAS
RP
t
RAS
t
RAb
CAS
WE
BS0
BS1
10
RAS
t
RCD
t
RAa
RBb
RCD
t
W9864G2GH
RCD
t
0-A9
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
RAa
CAx
RBb
CBy
RAc
ax4
ax1
ctive
ax0
Write
RRD
t
Idle
ax5 ax6 ax7 by0 by1
ctive
* AP is the internal precharge start timing
Write
by2
by3 by4
RRD
t
P*
by5
ctive
by6
CAz
by7 CZ0 CZ1 CZ2
Write
P*
Publication Release Date: August 16 ,2006
- 29 - Revision A01
Operating Timing Example, continued
14.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
t
CS
RAS
CAS
WE
BS0
BS1
CCD
t
RAS
t
CCD
t
RAS
t
CCD
W9864G2GH
t
A10
A0-A9
RAa
RAa
RCD
CAI
t
RCD
RBb
RBb CBx CAy CAm CBz
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
t
RRD
Read
Active Read
t
AC
t
a0 a1
a3 bx0
a2
Read Read
* AP is the internal precharge start timing
t
AC
AC
Ay0 Ay1 Ay2 am0
bx1
t
AC
Read
t
AC
am1 am2 bz0 bz1 bz2 bz3
Precharge
AP*
- 30 -
Operating Timing Example, continued
14.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
W9864G2GH
CLK
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9,
A11
DQM
1 2 3 4 5
0
t
RCD
RAa
RAa
CAx
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
(CLK = 100 MHz)
t
RAS
CAy
t
RP
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
Active Read
Idle
t
AC
ax0 ax1
ax2
QQ Q Q Q Q
t
WR
ax3
ax5 ay1
ax4
ay0 ay2 ay4
D
D
Write
ay3
DDD
Precharge
Publication Release Date: August 16 ,2006
- 31 - Revision A01
Operating Timing Example, continued
14.9 Autoprecharge Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
CLK
0
1 2 3
6 7 8
5
4
9 10
11 12 13
14 15
16 17 18
W9864G2GH
19
21
20
22 23
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9
DQM
CKE
DQ
t
RCD
RAa
RAa CAw
t
RC
t
RAS
t
AC
aw0 aw1 aw2 aw3
t
RP
t
RCD
RAb
RAb
CAx
t
RAS
t
AC
bx2bx1
bx0
bx3
Bank #0
Active
Read
AP*
Active Read
AP*
Bank #1
Bank #2
Bank #3
Idle
* AP is the internal precharge start timing
- 32 -
Operating Timing Example, continued
A
A
A
A
A
A
A
14.10 Autoprecharge Write (Burst Length = 4)
(CLK = 100 MHz)
CLK
CS
RAS
0
1 2 3
4
5
6 7 8
9 10
t
RC
11 12 13
14 15
16 17 18
t
RC
W9864G2GH
19
21
20
22 23
CAS
WE
BS0
BS1
10
0-A9
DQM
CKE
DQ
Bank #0
Bank #1
Bank #2
Bank #3
t
RAS
t
RP
t
RAS
t
RP
t
t
RCD
RAa
RAa
ctive
CAw
aw0 aw1 aw2 aw3
Write
P*
RCD
RAb
RAb CA x
bx0
ctive Write
bx1
bx2
bx3
RAc
RAc
P*
ctive
Idle
* AP is the internal precharge start
Publication Release Date: August 16 ,2006
- 33 - Revision A01
Operating Timing Example, continued
14.11 Autorefresh Cycle
CLK
CS
RAS
CAS
WE
0
1 2 3
t
RP
5
4
6 7 8
t
W9864G2GH
(CLK = 100 MHz)
9 10
RC
11 12 13
14 15
16 17 18
t
19
RC
21
20
22 23
BS0,1
A10
A0-A9
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
- 34 -
Operating Timing Example, continued
14.12 Self-refresh Cycle
W9864G2GH
CLK
CS
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
0
1 2 3
6 7 8
5
4
t
RP
9 10
11 12 13
14 15
16 17 18
19
21
20
22 23
(CLK = 100 MHz)
t
t
t
SB
CKS
CKS
CKE
t
CKS
DQ
t
RC
Arbitrary Cycle
All Banks
Precharge
Self Refresh
Entry
Self Refresh Cycle
No Operation Cycle
Publication Release Date: August 16 ,2006
- 35 - Revision A01
W9864G2GH
Operating Timing Example, continued
14.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
CLK
CS
RAS
CAS
WE
BS0
0
1 2 3
t
RCD
6 7 8
5
4
9 10
11 12 13
14 15
16 17 18
19
20
21
22 23
BS1
A10
RBa
A0-A9
RBa
CBv CBw CBx CBy
CBz
DQM
CKE
t
DQ
Bank #0
Bank #1
Bank #2
Bank #3
Idle
Read
AC
av0 av1
QQ Q Q D DDQQQQ
av3 aw0 ax0 ay0
av2
Single WriteActive
Read
t
AC
az0
az1 az2 az3
- 36 -
Operating Timing Example, continued
14.14 Power-down Mode
CLK
CS
RAS
CAS
WE
0
1 2 3
5
4
6 7 8
(CLK = 100 MHz)
9 10
11 12 13
14 15
16 17 18
W9864G2GH
19
21
20
22 23
BS
A10
A0-A9
DQM
CKE
DQ
RAa RAa
RAa CAa RAa CAx
t
t
CKS
Active
SB
t
CKS
NOP
Active Standby
Power Down mode
Read
ax0
ax1
ax2 ax3
t
SB
t
t
CKS
Precharge NOP Active
CKS
Precharge Standby
Power Down mode
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Publication Release Date: August 16 ,2006
- 37 - Revision A01
Operating Timing Example, continued
14.15 Auto-precharge Timing (Write Cycle)
W9864G2GH
(1) CAS Latency = 2
(a) burst length = 1
Command
(b) burst length = 2
Command
(c) burst length = 4
Command
(d) burst length = 8
Command
(2) CAS Latency = 3
(a) burst length = 1
Command
(b) burst length = 2
Command
(c) burst length = 4
Command
(d) burst length = 8
Command
CLK
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
01 32
Write
D0
Write
D0
Write
D0
Write
D0
Write
D0
Write
D0
Write
D0
Write
D0
tWR
D1
D1
D1
tWR
D1
D1
D1
45 76891110
ActAP
tRP
ActAP
tWR
D2 D3
D2 D3 D4 D5 D6 D7
tWR
D2 D3
D2 D3 D4 D5 D6 D7
tRP
ActAP
tWR
tRP
tRP
tWR
tRP
ActAP
ActAP
tRP
12
ActAP
AP
tRP
Act
tRP
Act
tWR
ActAP
tWR
Note )
Write
AP
Act
Act
When the /auto precharge command is asserted,the period from Bank Activate
command to the start of intermal precgarging must be at least tRAS (min).
represents the Write with Auto precharge command.
represents the start of internal precharing.
represents the Bank Active command.
- 38 -
Operating Timing Example, continued
14.16 Auto-precharge Timing (Read Cycle)
W9864G2GH
(1) CAS
Latency=2
( a ) burst length = 1
Command
DQ
( b ) burst length = 2
Command
DQ
( c ) burst length = 4
Command
DQ
( d ) burst length = 8
Command
DQ
(2) CAS
Latency=3
( a ) burst length = 1
Command
DQ
( b ) burst length = 2
Command
DQ
( c ) burst length = 4
Command
DQ
( d ) burst length = 8
Command
DQ
0 1110987654321
Read AP
Read AP Act
Read AP Act
Read AP Act
Read AP Act
Read AP Act
Read AP Act
Act
t
RP
Q0
t
RP
Q0
Q1
t
RP
Q0
Q1 Q2
Q3
AP ActRead
Q0 Q1
t
RP
Q2 Q3 Q4 Q5 Q6 Q7
Q0
t
RP
Q0
Q0
Q1
t
RP
Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
t
RP
t
RP
Note:
Read
AP
Act
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t
RAS
(min).
Publication Release Date: August 16 ,2006
- 39 - Revision A01
Operating Timing Example, continued
14.17 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
W9864G2GH
(1) CAS Latency=2
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
(2) CAS Latency=3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
0
Read Write
Read Write
Read
Read
1110987654321
D0 D1 D2 D3
D0 D1 D2 D3
Write
D0 D1 D2 D3
Write
D0 D1 D2 D3
Note: The Output data must be masked by DQM to avoid I/O conflict.
- 40 -
Operating Timing Example, continued
14.18 Timing Chart of Write to Read Cycle
In the case of Burst Length = 4
W9864G2GH
(1) CAS Latency = 2
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
(2) CAS Latency = 3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
0
D0
Write
D0 D1
Write
Write
D0 D1
ReadWrite
Read
Read
Read
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3D0
Q0
Q1
1110987654321
Q2 Q3
Publication Release Date: August 16 ,2006
- 41 - Revision A01
W9864G2GH
Operating Timing Example, continued
14.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0 1110987654321
(1) Read cycle
( a ) CAS latency =2
Command
Read BST
( b )CAS latency = 3
Command
(2) Write cycle
Command
DQ
Q0 Q1 Q2 Q3
Read
DQ
Write
DQ
Q0 Q1 Q2 Q3 Q4
Note: represents the Burst stop command
BST
Q4
BST
Q0 Q1 Q2 Q3 Q4
BST
- 42 -
14.20 Timing Chart of Burst Stop Cycle (Precharge Command)
01 111098765432
(1) Read cycle
W9864G2GH
(2) Write cycle
(a) CAS latency =2
Command
DQ
(b) CAS latency =3
Command
DQ
(a) CAS latency =2
Command
DQM
DQ
(b) CAS latency =3
Command
DQM
DQ
Q0 Q1 Q2 Q3 Q4
Q0 Q1 Q2 Q3 Q4
Write
Q0 Q1 Q2 Q3 Q4
Write
Q0 Q1 Q2 Q3 Q4
PRCGRead
PRCGRead
PRCG
tWR
PRCG
tWR
Publication Release Date: August 16 ,2006
- 43 - Revision A01
Operating Timing Example, continued
14.21 CKE/DQM Input Timing (Write Cycle)
W9864G2GH
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
1
D1 D6D5D3D2
1
D1
5432
DQM MASK
( 1 )
5432
D3D2
6
CKE MASK
6
D5
7
7
D6
CLK cycle No.
External
CLK
Internal
DQM
CKE
DQ
1
D1
DQM MASK
( 2 )
D3D2
CKE MASK
( 3 )
CKE MASK
5432
76
D6D5D4
- 44 -
Operating Timing Example, continued
14.22 CKE/DQM Input Timing (Read Cycle)
W9864G2GH
CLK cycle No.
External
CLK
Internal
CKE
DQM
CLK cycle No.
External
CLK
Internal
DQ
CKE
DQM
DQ
1
Q1
1
Q1
Q2
Q3
Q4Q3Q2
( 1 )
( 2 )
5432
5432
Q4
6
Open Open
6
Open
7
Q6
7
Q6
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
1
Q1
Q2
Q3
( 3 )
765432
Q5Q4
Q6
Publication Release Date: August 16 ,2006
- 45 - Revision A01
Operating Timing Example, continued
14.23 Self Refresh/Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time (Power down mode exit time) is specified by
t (min.) + t
CKS
A ) tCK < t CKS
CLK
(min.) + t
CK
(min.)
CK (min.)
tCK
W9864G2GH
CKE
Comm and
B) tCK
CLK
CKE
Command
>= t
CKS (min.) + t
tCKS(min)+tCK(min)
NOP
(min.)
CK
t CK
tCKS(min)+tCK(min)
Command
Input Buffer Enable
Comm and
Input Buffer Enable
Note:
All Input Buffer (Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
NOP
Command
Represents the No-Operation command
Represents one command
- 46 -
15. PACKAGE DIMENSIONS
15.1 86L TSOP (II)-400 mil
86 44
1 43
W9864G2GH
H
E
E
e
D
b
C
q
A2
A
ZD
Y
SEATING PLANE
A1
L
L1
Controlling Dimension: Millimeters
DIMENSION
SYM.
A
A1
A2
b
c
D
E
H
e
L
L1
Y
ZD
E
(MM)
MAX.MIN.
NOM.
1.20
0.05
0.17
0.12 0.005
10.06 10.16 10.26 0.400 0.404
0.40 0.50
0.15
1.00
0.27
0.21
22.2222.12 22.62 0.875 0.905
0.50
0.60
0.80 0.032
0.10
0.61
DIMENSION
(INCH)
MAX.MIN.
NOM.
0.047
0.039
0.020
0.020
0.024
0.006
0.011
0.008
0.024
0.004
0.002
0.007
0.871
0.396
0.45511.7611.56 11.96 0.463 0.471
0.016
Publication Release Date: August 16 ,2006
- 47 - Revision A01
W9864G2GH
16. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A01 8/16/2006 all CREAT NEW DATASHEET
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
- 48 -
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