Rainbow Electronics W9864G2GH User Manual

W9864G2GH

Table of Contents-

1. GENERAL DESCRIPTION ......................................................................................................... 3

2. FEATURES ................................................................................................................................. 3

3. AVAILABLE OPTIONS................................................................................................................ 4

4. PIN ASSIGNMENT ..................................................................................................................... 4

5. PIN DESCRIPTION..................................................................................................................... 5

6. BLOCK DIAGRAM ...................................................................................................................... 6

7. FUNCTIONAL DESCRIPTION.................................................................................................... 7

7.1 Power Up and Initialization ............................................................................................. 7

7.2 Programming Mode Register.......................................................................................... 7

7.3 Bank Activate Command ................................................................................................ 7

7.4 Read and Write Access Modes ...................................................................................... 7

7.5 Burst Read Command .................................................................................................... 8

7.6 Burst Command.............................................................................................................. 8

7.7 Read Interrupted by a Read ........................................................................................... 8

7.8 Read Interrupted by a Write............................................................................................ 8

7.9 Write Interrupted by a Write............................................................................................ 8

7.10 Write Interrupted by a Read............................................................................................ 8

7.11 Burst Stop Command ..................................................................................................... 9

7.12 Addressing Sequence of Sequential Mode .................................................................... 9

7.13 Addressing Sequence of Interleave Mode...................................................................... 9

7.14 Auto-precharge Command ........................................................................................... 10

7.15 Precharge Command.................................................................................................... 10

7.16 Self Refresh Command ................................................................................................ 10

7.17 Power Down Mode ....................................................................................................... 11

7.18 No Operation Command............................................................................................... 11

7.19 Deselect Command ...................................................................................................... 11

7.20 Clock Suspend Mode.................................................................................................... 11

8. TABLE OF OPERATING MODES ............................................................................................ 12

9. DC CHARACTERISTICS.......................................................................................................... 14

9.1 Absolute Maximum Rating............................................................................................ 14

10. RECOMMENDED DC OPERATING CONDITIONS................................................................. 14

11. CAPACITANCE......................................................................................................................... 15

11.1 DC CHARACTERISTICS.............................................................................................. 15

Publication Release Date: August 16 ,2006

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W9864G2GH

12.

AC CHARACTERISTICS .......................................................................................................... 16

13. TIMING WAVEFORMS............................................................................................................. 19

13.1 Command Input Timing ................................................................................................ 19

13.2 Read Timing.................................................................................................................. 20

13.3 Control Timing of Input Data......................................................................................... 21

13.4 Control Timing of Output Data ...................................................................................... 22

13.5 Mode Register Set Cycle .............................................................................................. 23

14. OPERATING TIMING EXAMPLE ............................................................................................. 24

14.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 24

14.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) ............ 25

14.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 26

14.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) ............ 27

14.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 28

14.6 Interleaved Bank Write (Burst Length = 8, Autoprecharge).......................................... 29

14.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 30

14.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 31

14.9 Autoprecharge Read (Burst Length = 4, CAS Latency = 3) ......................................... 32

14.10 Autoprecharge Write (Burst Length = 4) ..................................................................... 33

14.11 Autorefresh Cycle........................................................................................................ 34

14.12 Self-refresh Cycle........................................................................................................ 35

14.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)............................. 36

14.14 Power-down Mode ...................................................................................................... 37

14.15 Auto-precharge Timing (Write Cycle).......................................................................... 38

14.16 Auto-precharge Timing (Read Cycle).......................................................................... 39

14.17 Timing Chart of Read to Write Cycle........................................................................... 40

14.18 Timing Chart of Write to Read Cycle........................................................................... 41

14.19 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 42

14.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 43

14.21 CKE/DQM Input Timing (Write Cycle)......................................................................... 44

14.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 45

14.23 Self Refresh/Power Down Mode Exit Timing .............................................................. 46

15. PACKAGE DIMENSIONS......................................................................................................... 47

15.1 86L TSOP (II)-400 mil................................................................................................... 47

16. REVISION HISTORY ................................................................................................................48

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W9864G2GH

1. GENERAL DESCRIPTION

W9864G2GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.11 µm process technology, W9864G2GH delivers a data bandwidth of up to 800M bytes per second. For different application, W9864G2GH is sorted into the following speed grades:-5,-6,-7.The -5 parts can run up to 200MHz/CL3.The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9864G2GH is ideal for main memory in high performance applications.

2. FEATURES

• 3.3V± 0.3V for -5/-6 grade power supply and 2.7V〜3.6V for -7/ -7S grade power supply.

• Interface : LVTTL.

• Four banks operation.

• CAS latency 3.

• Burst length (1, 2, 4, 8 & Full page).

• Burst type (Sequential & Interleave).

• Burst read single-bit write operation.

• DQM for masking.

• Auto & self refresh.

• 64ms refresh period (4K cycle).

• W9864G2GH is using Lead free materials

• All inputs are sampled at the positive going edge of the system clock .

Publication Release Date: August 16 ,2006

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3. AVAILABLE OPTIONS

W9864G2GH

PART NUMBER SPEED (CL = 3) SELF REFRESH CURRENT (MAX.)

W9864G2GH-5 200 MHz 2mA

W9864G2GH-6 166 MHz 2mA

W9864G2GH-7 143 MHz 2mA

4. PIN ASSIGNMENT

VCC

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

VSSQ

DQ7

VCC

DQM0

CAS

RAS

BS0

BS1

A10/AP

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQM1

CLK

CKE

DQM3

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

OPERATING

TEMPERATURE

0°C ~ 70°C

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5. PIN DESCRIPTION

PIN NUMBER PIN NAME FUNCTION DESCRIPTION

24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66

22, 23 BS0, BS1 Bank Select

2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85

A0−A10

DQ0−

DQ31

RAS

CAS

Address

Data Input/ Output

Chip Select

Row Address Strobe

Column Address Strobe

W9864G2GH

Multiplexed pins for row and column address. Row address: A0−A10. Column address: A0−A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1.

Select bank to activate during row address latch time, or bank to read/write during address latch time.

Multiplexed pins for data output and input.

Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues.

Command input. When sampled at the rising

edge of the clock define the operation to be executed.

Referred to RAS

RAS , CAS and WE

16, 28, 59, 71

68 CLK Clock Inputs

67 CKE Clock Enable

1, 15, 29, 43 VCC Power

44, 58, 72, 86 VSS Ground

3, 9, 35, 41, 49, 55, 75, 81 VCCQ

6, 12, 32, 38, 46, 52, 78, 84 VSSQ

14, 21, 30, 57, 69, 70, 73 NC No Connection

DQM0−

DQM3

Write Enable

Input/Output Mask

Power for I/O Buffer

Ground for I/O Buffer

Referred to RAS

The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency.

System clock used to sample inputs on the rising edge of clock.

CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered.

Power for input buffers and logic circuit inside DRAM.

Ground for input buffers and logic circuit inside DRAM.

Separated power from VCC, to improve DQ noise immunity.

Separated ground from VSS, to improve DQ noise immunity.

No connection.(The NC pin must connect to ground or floating.)

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6. BLOCK DIAGRAM

W9864G2GH

CLK

CKE

RAS

CAS

A10

BS0

BS1

CLOCK

BUFFER

COMMAND

DECODER

ADDRESS

REFRESH

COUNTER

BUFFER

CONTROL

GENERATOR

MODE REGISTER

COLUMN

COUNTER

SIGNAL

COLUMN DECODER

CELL ARRAY

BANK #0

ROW DECODER

SENSE AMPLIFIER

COLUMN DECODER

DATA CONTROL

CIRCUIT

COLUMN DECODER

CELL ARRAY

BANK #1

ROW DECODERROW DECODER

SENSE AMPLIFIER

COLUMN DECODER

DQ BUFFER

DQ0

DQ31

DQM0~3

CELL ARRAY

BANK #2

ROW DECODER

SENSE AMPLIFIER

NOTE:

The cell array configuration is 2048 * 256 * 32

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CELL ARRAY

BANK #3

SENSE AMPLIFIER

W9864G2GH

7. FUNCTIONAL DESCRIPTION

7.1 Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs.

During power up, all when the input signals are held in the “NOP” state. The power up voltage must not exceed on any of the input pins or by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.

7.2 Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low

signals of during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

RAS , CAS , CS and WE at the positive edge of the clock. The address input data

VCC and VCCQ pins must be ramp up simultaneously to the specified voltage

VCC +0.3V

VCC supplies. After power up, an initial pause of 200 µS is required followed

RSC has

7.3 Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t

RCD). Once a bank has been activated it must be precharged before another Bank

Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t

RC).

The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t specified as T

RAS (max.).

RRD). The maximum time that each bank can be held active is

7.4 Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting

RAS

high and

defines whether the access cycle is a read operation ( address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.

CAS

low at the clock rising edge after minimum of tRCD delay.

WE high), or a write operation ( WE low). The

Publication Release Date: August 16 ,2006

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pin voltage level

7.5 Burst Read Command

W9864G2GH

The Burst Read command is initiated by applying logic low level to CS and

RAS and WE high at the rising edge of the clock. The address inputs determine the starting column

address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode.

CAS

while holding

7.6 Burst Command

The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding

address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.

RAS high at the rising edge of the clock. The address inputs determine the starting column

7.7 Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied.

7.8 Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.

7.9 Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.

7.10 Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.

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W9864G2GH

7.11 Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop

Command is defined by having the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in a burst read cycle, interrupted by Burst Stop.

RAS

7.12 Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA ACCESS ADDRESS BURST LENGTH

Data 0 n BL = 2 (disturb address is A0)

Data 1 n + 1 No address carry from A0 to A1

Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)

Data 3 n + 3 No address carry from A1 to A2

Data 4 n + 4

Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)

Data 6 n + 6 No address carry from A2 to A3

Data 7 n + 7

and

CAS

high with CS and WE low at the rising edge of

7.13 Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA ACCESS ADDRESS BUST LENGTH

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

A8 A7 A6 A5 A4 A3 A2 A1

A8 A7 A6 A5 A4 A3 A2

A8 A7 A6 A5 A4 A3

A2 A1 A0

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A1 A0

Publication Release Date: August 16 ,2006

BL = 4

BL = 8

W9864G2GH

7.14 Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto-precharge cannot be interrupted before the entire burst operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (t Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred to as write t satisfied. This is referred to as t

DPL. The bank undergoing auto-precharge cannot be reactivated until tDPL and tRP are

DAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-

precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t

RAS (min).

7.15 Precharge Command

RP) has been satisfied. Issue of Auto-

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when

CS , RAS and WE are low and CAS is high at the rising

edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (t

RP).

7.16 Self Refresh Command

The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the t

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode.

AC cycle time plus the Self Refresh exit time.

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W9864G2GH

7.17 Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t device.

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on t enabled with CKE held high for a period equal to tCES (min.) + tCK (min.).

CK. The input buffers need to be

7.18 No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.

is low with

RAS, CAS

, and

held high at the rising edge of

7.19 Deselect Command

REF) of the

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when

is brought high, the

RAS, CAS

, and

signals become don’t cares.

7.20 Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.

Publication Release Date: August 16 ,2006

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W9864G2GH

8. TABLE OF OPERATING MODES

Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.

TABLE 1 TRUTH TABLE (NOTE (1), (2))

COMMAND DEVICE

STATE

Bank Active Idle H x x v v V L L H H

Bank Precharge Any H x x v L x L L H L

Precharge All Any H x x x H x L L H L

Write Active (3) H x x v L v L H L L

Write with Autoprecharge Active (3) H x x v H v L H L L

Read Active (3) H x x v L v L H L H

Read with Autoprecharge Active (3) H x x v H v L H L H

Mode Register Set Idle H x x v v v L L L L

No-Operation Any H x x x x x L H H H

Burst Stop Active (4) H x x x x x L H H L

Device Deselect Any H x x x x x H x x x

Auto-Refresh Idle H H x x x x L L L H

Self-Refresh Entry Idle H L x x x x L L L H

Self Refresh Exit idle

(S.R)

Clock suspend Mode Entry Active H L x x x x x x x x

Power Down Mode Entry Idle

Active (5) H H

Clock Suspend Mode Exit Active L H x x x x x x x X

Power Down Mode Exit Any

(power

down)

Data write/Output Enable Active H x L x x x x x x x

Data Write/Output Disable Active H x H x x x x x x x

Notes:

(1) v = valid, x = Don’t care, L = Low Level, H = High Level

(2) CKEn signal is input leve l when commands are provided.

(3) These are state of bank designated by BS0, BS1 signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

CKEN-1 CKEN DQM BS0, 1 A10 A0-A9

x x H L x H x Hx

x x H L x H x HX

RAS CAS

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SIMPLIFIED STATE DIAGRAM

Mode

Set

MRS REF

IDLE

ACT

Self

Refresh

Power

Down

CBR

Refresh

W9864G2GH

Write

POWER

CKE

WRITE

SUSPEND

WRITEA

SUSPEND

MRS = Mode Register Set REF = Refresh ACT = Active PRE = Precharge WRITEA = Write with Auto precharge READA = Read with Auto precharge

WRITE

WRITEA

Precharge

CKE

ROW

ACTIVE

(

Read

Precharge

PRE

Write

r a

r p

(

a h c

)

CKE

)

READ

READA

Active Power

Down

Read

CKE

READ

SUSPEND

READA

SUSPEND

Automatic sequence

Manual input

Publication Release Date: August 16 ,2006

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W9864G2GH

9. DC CHARACTERISTICS

9.1 Absolute Maximum Rating

PARAMETER SYM. RATING UNIT NOTES

Input, Column Output Voltage

Power Supply Voltage

Operating Temperature

Storage Temperature

Soldering Temperature (10s)

Power Dissipation

Short Circuit Output Current

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

IN, VOUT

VCC, VCCQ

OPR

STG

SOLDER

OUT

10. RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to 70°C)

-0.3~

VCC+0.3V V 1

-0.3~4.6V V 1

0 − 70

-55 − 150

260

°C

1 W 1

50 mA 1

PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES

Power Supply Voltage

Power Supply Voltage (for I/O Buffer)

Power Supply Voltage(-7)

Power Supply Voltage

VCC

VCCQ

VCC

VCCQ

3.0 3.3 3.6 V

2.7 3.3 3.6 V

(for I/O Buffer)(-7)

Input High Voltage VIH 2 - VCC +0.3 V 1

Input Low Voltage VIL -0.3 - +0.8 V 2

Output logic high voltage

Output logic low voltage

Input leakage current

Note: 1. VIH (max.) = VCC/VCCQ+1.2V for pulse width < 5 nS

2. VIL (min.) = VSS/VSSQ-1.2V for pulse width

3. Any input 0V Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

<VIN<VCCQ.

VOH 2.4V - - V

VOL - - 0.4 V

ILI -10 - 10 uA 3

< 5 nS

IOH=2mA

IOL= 2mA

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11. CAPACITANCE

(VCC

3.3V±0.3V, TA = 25 °C, f = 1 MHz)

W9864G2GH

PARAMETER SYM. MIN. MAX. UNIT

Input Capacitance

(A0 to A10, BS0, BS1,

CS, RAS, CAS

, WE , DQM, CKE)

i 2.5 4 pf

Input Capacitance (CLK) CCLK 2.5 4 pf

o 4 6.5 pf

Input/Output capacitance (DQ0−DQ31)

Note: These parameters are periodically sampled and not 100% tested

11.1 DC CHARACTERISTICS

(VCC = 3.3V±0.3V, TA = 0°~70°C for -5/-6/-7)

PARAMETER SYM.

Operating Current tCK = min., tRC = min. Active precharge command

cycling without burst operation

Standby Current tCK = min., CS = VIH

VIH/L = VIH (min.)/VIL (max.)

Bank: Inactive State

Standby Current

CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.)

BANK: Inactive State

No Operating Current tCK = min.,

BANK: Active State (4 banks)

Burst Operating Current (tCK = min.) Read/Write command cycling

Auto Refresh Current (tCK = min.) Auto refresh command cycling

Self Refresh Current Self refresh mode

(CKE = 0.2V)

CS = VIH (min.)

1 bank operation ICC1 150 140 130 3

CKE = VIH ICC2 40 35 30 3

CKE = VIL (Power Down mode)

CKE = VIH ICC2S 15 15 15

CKE = VIL (Power Down mode)

CKE = VIH ICC3 70 65 60

CKE = VIL (Power Down mode)

Standard(-5/-6/-7) ICC6 2 2 2

ICC2P 3 3 3 3

ICC2P

ICC3P 15 15 15

ICC4 180 170 160 3, 4

ICC5 240 220 200 3

-5 -6 -7 UNIT NOTES

MAX. MAX. MAX.

3 3 3

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