Rainbow Electronics W9825G6CH User Manual

W9825G6CH
4M ×× 4 BANKS ×× 16 BIT SDRAM
GENERAL DESCRIPTION
W9825G6CH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 4M words × 4 banks × 16 bits. Using pipelined architecture and 0.13 µm process technology,
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9825G6CH is ideal for main memory in high performance applications.
FEATURES
3.3V ± 0.3V Power Supply
Up to 166 MHz Clock Frequency
4,194,304 Words × 4 Banks × 16 Bits Organization
Self Refresh Mode: Standard and Low Power
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and Full Page
Burst Read, Single Writes Mode
Byte Data Controlled by LDQM, UDQM
Power-down Mode
Auto-precharge and Controlled Precharge
8K Refresh Cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil - 0.80, using PB free material.
AVAILABLE PART NUMBER
Part Number Speed Grade Self Refresh Current (Max) Operating Temperature
W9825G6CH- 6 PC166/CL3 3mA 0°C - 70°C W9825G6CH- 7 PC133/CL2 3mA 0°C - 70°C W9825G6CH-75 PC133/CL3 3mA 0°C - 70°C W9825G6CH75L PC133/CL3 1mA 0°C - 70°C W9825G6CH75I PC133/CL3 1mA -40°C - 85°C
Publication Release Date: Oct 2004
- 1 - Revision A2
PIN CONFIGURATION
W9825G6CH
VCC
DQ0
VCCQ
DQ1 DQ2
VSSQ
DQ3 DQ4
VCCQ
DQ5 DQ6
VSSQ
DQ7
VCC
LDQM
WE CAS
RAS
CS BS0 BS1
A10/AP
A0
A1
A2
A3
VCC
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ
DQ10 DQ9 VCCQ
DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
- 2 -
PIN DESCRIPTION
, or
WE
define the operation
WE
cycle, sampling DQM high will block the write operation
edge
When CKE is low, Power Down mode, Suspend mode,
PIN NO. PIN NAME FUNCTION DESCRIPTION
W9825G6CH
2326, 22,
2936 20, 21 BS0, BS1 Bank Select
2, 4, 5, 7, 8, 10,
11, 13, 42, 44, 45, 47, 48, 50,
51, 53
19
18
17
16
15, 39
38 CLK Clock Inputs
37 CKE Clock Enable
1, 14, 27 VCC Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
A0A12
DQ0DQ16
CS
RAS
CAS
LDQM, UDQM
Address
Data
Input/Output
Chip Select
Row Address
Strobe
Column
Address
Strobe
Write Enable
Input/Output
Mask
Multiplexed pins for row and column address. Row address: A0A12. Column address: A0−A8.
Select bank to activate during row address latch time bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues.
Command input. When sampled at the rising edge of the clock, RAS, CAS and
to be executed.
Referred to RAS
Referred to RAS The output buffer is placed at Hi-Z(with latency of 2)
when DQM is sampled high in read cycle. In write with zero latency.
System clock used to sample inputs on the rising of clock.
CKE controls the clock activation and deactivation. or Self Refresh mode is entered.
28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V)
3, 9, 43, 49 VCCQ
6, 12, 46, 52 VSSQ
40 NC No Connection No connection
Publication Release Date: Oct. 2004
- 3 - Revision A2
for I/O Buffer
Ground
for I/O Buffer
Separated power from VCC, to improve DQ noise immunity.
Separated ground from VSS, to improve DQ noise immunity.
BLOCK DIAGRAM
W9825G6CH
A10
A11 A12 BS0 BS1
CLK
CKE
CS
RAS
CAS
WE
A0
A9
CLOCK
BUFFER
COMMAND DECODER
ADDRESS
BUFFER
REFRESH COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
ROW DECODER
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #1
ROW DECODERROW DECODER
SENSE AMPLIFIER
DQ
BUFFER
DQ0
DQ15
LDQM
UDQM
COLUMN DECODER
CELL ARRAY
BANK #2
ROW DECODER
SENSE AMPLIFIER
Note: The cell array configuration is 8192 * 512 * 16.
- 4 -
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
WE
PARAMETER SYMBOL RATING UNIT NOTES
W9825G6CH
Input, Output Voltage VIN, VOUT
Supply Voltage VCC, VCCQ Operating Temperature(-6/-7/-75/75L) TOPR Operating Temperature(75I) TOPR Storage Temperature TSTG Soldering Temperature (10s) TSOLDER 260 Power Dissipation PD 1 W 1 Short Circuit Output Current IOUT 50 mA 1
Note 1: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
-0.3 VCC +
0.3
-0.3 4.6 0 70
-40 85
-55 150
V 1
V 1
°C °C °C °C
1 1 1 1
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Supply Voltage VCC 3.0 3.3 3.6 V 2 Supply Voltage (for I/O Buffer) VCCQ 3.0 3.3 3.6 V 2 Input High Voltage VIH 2.0 - VCC +0.3 V 2 Input Low Voltage VIL -0.3 - 0.8 V 2
Note 2: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 nS
CAPACITANCE
(VCC = 3.3V, f = 1 MHz, TA = 25°C)
PARAMETER SYMBOL MIN. MAX. UNIT
Input Capacitance (A0 to A12, BS0, BS1, CS, RAS , CAS,
UDQM, CKE) Input Capacitance (CLK) CCLK - 3.5 pf Input/Output Capacitance CIO - 6.5 pf
Note: These parameters are periodically sampled and not 100% tested.
Publication Release Date: Oct. 2004
- 5 - Revision A2
, LDQM,
CI - 3.8 pf
W9825G6CH
AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I ; Notes: 5, 6, 7, 8)
PARAMETER SYM.
MIN. MAX. MIN. MAX.
Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b) Command
Period Precharge to Active Command Period
Active(a) to Active(b) Command Period Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 CL* = 3 7 1000 7.5 1000 nS CLK High Level Width CLK Low Level Width Access Time from CLK CL* = 2
Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK
(Rise and Fall) Data-in Set-up Time
Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time
*CL = CAS Latency
CL* = 3 5.4 5.4 nS
tRC
t
RAS
t
RCD
t
CCD
tRP
t
RRD
tWR
tCK
tCH 2.5 2.5 tCL 2.5 2.5 tAC
tOH
tHZ
tLZ
tSB
tT
tDS tDH tAS tAH
t
CKS
t
CKH
t
CMS
t
CMH
t
REF
t
RSC
-7
(PC133, CL2)
56 65 nS 40 100000 45 100000 nS 15 20 nS
1 1 tCK
15 20 nS 15 15 nS
2 2 tCK 2 2 tCK
7.5 1000 10 1000 nS
5.4 6 nS
3 3 nS 3 7 3 7.5 nS 0 0 nS 0 7 0 7.5 nS
0.5 10 0.5 10 nS
1.5 1.5 nS
0.8 0.8 nS
1.5 1.5 nS
0.8 0.8 nS
1.5 1.5 nS
0.8 0.8 nS
1.5 1.5 nS
0.8 0.8 nS 64 64 mS
14 15 nS
-75/75L/75I
(PC133, CL3)
UNIT
nS nS
- 6 -
PARAMETER SYM.
-6
MIN. MAX.
Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b) Command
Period Precharge to Active Command Period Active(a) to Active(b) Command Period
Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 CL* = 3 6 1000 nS CLK High Level Width CLK Low Level Width Access Time from CLK CL* = 2
Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK
(Rise and Fall) Data-in Set-up Time
Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time
CL* = 3 5.4 nS
tRC
t
RAS
t
RCD
t
CCD
tRP
t
RRD
tWR
tCK
tCH 2.5 tCL 2.5 tAC
tOH
tHZ
tLZ
tSB
tT
tDS tDH tAS tAH
t
CKS
t
CKH
t
CMS
t
CMS
t
REF
t
RSC
60 nS 42 100000 nS 18 nS
1 tCK
18 nS 12 nS
2 tCK 2 tCK
7.5 1000 nS
5.4 nS
3 nS 3 7 nS 0 nS 0 7 nS
0.5 10 nS
1.5 nS
0.8 nS
1.5 nS
0.8 nS
1.5 nS
0.8 nS
1.5 nS
0.8 nS 64 mS
12 nS
UNIT
W9825G6CH
nS nS
Publication Release Date: Oct. 2004
- 7 - Revision A2
W9825G6CH
DC CHARACTERISTICS
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I)
PARAMETER SYM. -6
MAX. MAX.
Operating Current
t
= min., tRC = min.
CK
Active precharge command cycling without burst operation
Standby Current
t
= min, CS = VIH
CK
VIH/L = VIH (min.)/VIL (max.) Bank: Inactive state
Standby Current
CLK = VIL, CS= VIH VIH/L = VIH (min.)/VIL (max.)
BANK: Inactive state
No Operating Current
t
= min., CS = VIH (min.)
CK
BANK: Active state (4 banks)
Burst Operating Current
t
= min.
CK
Read/ Write command cycling
Auto Refresh Current
t
= min.
CK
Auto refresh command cycling
Self Refresh Current
Self Refresh Mode CKE = 0.2V
1 Bank Operation ICC1 90 80 75 3
CKE = VIH ICC2 50 40 35 3
CKE = VIL (Power
down mode)
CKE = VIH ICC2S 10 10 10
CKE = VIL (Power
down mode)
CKE = VIH ICC3 70 60 55
CKE = VIL (Power
down mode)
Standard(-6/-7/-75) 3 3 3 Low Power(75L/75I)
ICC2P 2 2 2 3
ICC2PS 2 2 2 mA
ICC3P 10 10 10
ICC4 110 100 95 3, 4
ICC5 180 170 160 3
ICC6L
- 1
-7 -75/75L/75I
UNIT
NOTES
PARAMETER SYMBOL MIN. MAX. UNIT NOTES
Input Leakage Current
(0V VIN VCC, all other pins not under test = 0V)
Output Leakage Current
(Output disable, 0V VOUT VCCQ)
LVTTL Output ″H″ Level Voltage
(IOUT = -2 mA )
LVTTL Output ″L″ Level Voltage
(IOUT = 2 mA )
II(L) -5 5
IO(L) -5 5
VOH 2.4 - V
VOL - 0.4 V
µA
µA
- 8 -
W9825G6CH
Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open.
5. Power up sequence is further described in the "Functional Description" section.
6. AC Testing Conditions
Output Reference Level 1.4V/1.4V Output Load See diagram below Input Signal Levels 2.4V/0.4V Transition Time (Rise and Fall) of Input Signal 2 nS Input Reference Level 1.4V
1.4 V
50 ohms
Z = 50 ohmsoutput
50pF
AC TEST LOAD
7. Transition times are measured between VIH and VIL.
8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
Publication Release Date: Oct. 2004
- 9 - Revision A2
W9825G6CH
OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1) , (2))
COMMAND DEVICE
Bank Active Idle H x x v v v L L H H Bank Precharge Any H x x v L x L L H L Precharge All Any H x x x H x L L H L Write Active (3) H x x v L v L H L L Write with Autoprecharge Active (3) H x x v H v L H L L Read Active (3) H x x v L v L H L H Read with Autoprecharge Active (3) H x x v H v L H L H Mode Register Set Idle H x x v v v L L L L No-operation Any H x x x x x L H H H Burst Stop Active (4) H x x x x x L H H L Device Deselect Any H x x x x x H x x x Auto-refresh Idle H H x x x x L L L H Self-refresh Entry Idle H L x x x x L L L H Self-refresh Exit Idle
Clock Suspend Mode Entry
Power Down Mode Entry Idle
Clock Suspend Mode Exit Active L H x x x x x x x x Power Down Mode Exit
Data Write/Output Enable Active H x L x x x x x x x Data Write/Output Disable Active H x H x x x x x x x
STATE
(S.R.) Active H L x x x x x x x x
Active (5)
Any
(Power
down)
CKEN-1 CKEN DQM BS0, 1 A10
L L
H H
L L
H H
L L
H H
x x
x x
x x
x x
x x
x x
x x
x x
x x
A0−−A9
A11, A12
x x
x x
x x
CS RAS CAS
H L x
H
H L x
H
H L x
H
x
H
x
H
x
H
WE
x x
x x
x x
Notes: (1) v = valid x = Don't care L = Low Level H = High Level (2) CKEn signal is input level when commands are provided. CKEn-1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode.
- 10 -
W9825G6CH
RAS
FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs.
During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed Vcc +0.3V on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
RSC
has
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to
command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t specified as t
(max).
RAS
). Once a bank has been activated it must be precharged before another Bank
RCD
activate in EDO DRAM. The delay from when the Bank Activate
). The maximum time that each bank can be held active is
RRD
Read and Write Access Modes
After a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of t level defines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.
delay. WE pin voltage
RCD
Publication Release Date: Oct. 2004
- 11 - Revision A2
W9825G6CH
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.
Burst Write Command
The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.
- 12 -
W9825G6CH
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 n BL = 2 (disturb address is A0) Data 1 n + 1 No address carry from A0 to A1 Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1) Data 3 n + 3 No address carry from A1 to A2
Data 4 n + 4 Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2) Data 6 n + 6 No address carry from A2 to A3 Data 7 n + 7
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA ACCESS ADDRESS BUST LENGTH
Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 Data 1
Data 2 Data 3 Data 4 Data 5 Data 6 Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 4
BL = 8
Publication Release Date: Oct. 2004
- 13 - Revision A2
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