Rainbow Electronics W982516CH User Manual

W982516CH

4M × 4 BANKS × 16 BIT SDRAM

GENERAL DESCRIPTION

W982516CH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
4M words × 4 banks × 16 bits. Using pipelined architecture and 0.13 µm process technology,
W982516CH delivers a data bandwidth of up to 166M words per second (-6). To fully comply with the

personal computer industrial standard, W982516CH is sorted into two speed grades: -6, -7 and -75.
The -6 is compliant to the 166 MHz/CL3 specification, the -7 is compliant to the 143 MHz/CL3 or

PC133/CL2 specification, the -75 is compliant to the PC133/CL3 specification, for handheld device
application, we also provide a low power option, the 75L grade, with Self Refresh Current under 1mA.,
and an industrial temperature option, the grade of 75I, which is guranteed to support -40° C – 85°C.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W982516CH is ideal for main memory in

high performance applications.

FEATURES

• 3.3V ± 0.3V Power Supply

• Up to 166 MHz Clock Frequency

• 4,194,304 Words × 4 Banks × 16 Bits Organization

• Self Refresh Mode: Standard and Low Power

• CAS Latency: 2 and 3

• Burst Length: 1, 2, 4, 8, and Full Page

• Burst Read, Single Writes Mode

• Byte Data Controlled by LDQM, UDQM

• Power-down Mode

• Auto-precharge and Controlled Precharge

• 8K Refresh Cycles/64 mS

• Interface: LVTTL

• Packaged in TSOP II 54 -pin, 400 mil - 0.80

AVAILABLE PART NUMBER

Part Number Speed Grade Self Refresh Current (Max) Operating Temperature

W982516CH- 6 PC166/CL3 3mA 0°C - 70°C
W982516CH- 7 PC133/CL2 3mA 0°C - 70°C
W982516CH-75 PC133/CL3 3mA 0°C - 70°C
W982516CH75L PC133/CL3 1mA 0°C - 70°C
W982516CH75I PC133/CL3 1mA -40°C - 85°C

Publication Release Date: Mar 2003

- 1 - Revision A1

PIN CONFIGURATION

DQ0

VCCQ

DQ1
DQ2

VSSQ

DQ3

DQ4

VCCQ

DQ5
DQ6

VSSQ

DQ7

LDQM

CAS
RAS

BS0
BS1

A10/AP

VCC

VCC

WE

CS

A0
A1
A2
A3

VCC

W982516CH

V SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54

DQ15

53

V SSQ

52

DQ14

51

DQ13

50

V CCQ

49

DQ12

48

DQ11

47

V SSQ

46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

DQ10
DQ9
V CCQ

DQ8
V SS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6

A5
A4
V SS

- 2 -

PIN DESCRIPTION

define the operation

cycle, sampling DQM high will block the write operation

When CKE is low, Power Down mode, Suspend mode,

PIN NO. PIN NAME FUNCTION DESCRIPTION

23−26, 22,

29−36
20, 21 BS0, BS1 Bank Select

2, 4, 5, 7, 8, 10,

11, 13, 42, 44,
45, 47, 48, 50,

51, 53

19

18

17

A0−A12

DQ0−DQ16

CS

RAS

CAS

Input/Output

Chip Select

Row Address

Address

Data

Strobe

Column

Address

Strobe

Multiplexed pins for row and column address.
Row address: A0−A12. Column address: A0−A8.

Select bank to activate during row address latch time, or
bank to read/write during address latch time.

Multiplexed pins for data output and input.

Disable or enable the command decoder. When
command decoder is disabled, new command is

ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock, RAS, CAS and WE

to be executed.

Referred to RAS

W982516CH

16

15, 39

38 CLK Clock Inputs

37 CKE Clock Enable

1, 14, 27 VCC Power (+3.3V) Power for input buffers and logic circuit inside DRAM.

28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM.

3, 9, 43, 49 VCCQ

6, 12, 46, 52 VSSQ

40 NC No Connection No connection

WE

LDQM,

UDQM

Write Enable

Input/Output

Power (+3.3V)

for I/O Buffer

for I/O Buffer

Mask

Ground

Referred to
The output buffer is placed at Hi -Z(with latency of 2)

when DQM is sampled high in read cycle. In write
with zero latency.

System clock used to sample inputs on the rising edge
of clock.

CKE controls the clock activation and deactivation.
or Self Refresh mode is entered.

Separated power from VCC, to improve DQ noise
immunity.

Separated ground from V SS, to improve DQ noise
immunity.

RAS

Publication Release Date: Mar 2003

- 3 - Revision A1

BLOCK DIAGRAM

W982516CH

A10

A11
A12
BS0
BS1

CLK

CKE

RAS

CAS

WE

A0

A9

CLOCK

BUFFER

CS

COMMAND

DECODER

ADDRESS

BUFFER

REFRESH
COUNTER

CONTROL

GENERATOR

MODE

REGISTER

COLUMN

COUNTER

SIGNAL

COLUMN DECODER

CELL ARRAY

BANK #0

ROW DECODER

SENSE AMPLIFIER

DATA CONTROL

CIRCUIT

COLUMN DECODER

CELL ARRAY

BANK #1

ROW DECODERROW DECODER

SENSE AMPLIFIER

DQ

BUFFER

DQ0

DQ15

LDQM
UDQM

COLUMN DECODER

CELL ARRAY

BANK #2

ROW DECODER

SENSE AMPLIFIER

Note: The cell array configuration is 8192 * 512 * 16.

- 4 -

COLUMN DECODER

CELL ARRAY

BANK #3

SENSE AMPLIFIER

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT NOTES

W982516CH

Input, Output Voltage VIN, VOUT

Supply Voltage VCC , VCCQ
Operating Temperat ure(-6/-7/-75/75L) TOPR
Operating Temperature(75I) TOPR
Storage Temperature TSTG

Soldering Temperature (10s) TSOLDER 260 °C 1
Power Dissipation PD 1 W 1

Short Circuit Output Current IOUT 50 mA 1

Note 1: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

-0.3 − VCC +

0.3

-0.3 − 4.6
0 − 70

-40 − 85

-55 − 150

V 1

V 1

°C 1
°C 1
°C 1

RECOMMENDED DC OPERA TING CONDITIONS

(Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Supply Voltage VCC 3.0 3.3 3.6 V 2
Supply Voltage (for I/O Buffer) VCCQ 3.0 3.3 3.6 V 2
Input High Voltage VIH 2.0 - VCC +0.3

V 2

Input Low Voltage VIL -0.3 - 0.8 V 2

Note 2: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS
VIL(min) = VSS/ VSS Q-1.2V for pulse width < 5 nS

CAPACITANCE

(VCC = 3.3V, f = 1 MHz, T A = 25°C)

PARAMETER SYMBOL MIN. MAX. UNIT

Input Capacitance
(A0 to A12, BS0, BS1, CS , RAS, CAS, WE, LDQM,

UDQM, CKE)
Input Capacitance (CLK) CCLK - 3.5 pf
Input/Output Capacitance CIO - 6.5 pf

Note: These parameters are periodically sampled and not 100% tested.

Publication Release Date: Mar 2003

- 5 - Revision A1

CI - 3.8 pf

W982516CH

AC CHARACTERISTICS A ND OPERATING CONDITION

(Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I ; Notes: 5, 6, 7, 8)

PARAMETER SYM.

MIN. MAX. MIN. MAX.

Ref/Active to Ref/Active Command Period
Active to precharge Command Period

Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b) Command

Period
Precharge to Active Command Period

Active(a) to Active(b) Command Period
Write Recovery Time CL* = 2
CL* = 3

CLK Cycle Time CL* = 2
CL* = 3 7 1000 7.5 1000 nS
CLK High Level Width
CLK Low Level Width
Access Time from CLK CL* = 2

Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK

(Rise and Fall)
Data-in Set-up Time

Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set -up Time
CKE Hold Time

Command Set -up Time
Command Hold Time
Refresh Time

Mode register Set Cycle Time

*CL = CAS Latency

CL* = 3 5.4 5.4 nS

tRC

t

RAS

t

RCD

t

CCD

tRP

t

RRD

tWR

tCK

tCH 2.5 2.5

tCL 2.5 2.5

tAC

tOH

tHZ
tLZ
tSB

tT

tDS
tDH

tAS

tAH

t

CKS

t

CKH

t

CMS

t

CMS

t

REF

t

RSC

-7

(PC133, CL2)

56 65 nS
40 100000

15 20 nS

1 1 tCK

15 20 nS
15 15 nS

2 2 tCK
2 2 tCK

7.5 1000 10 1000 nS

5.4 6 nS

3 3 nS
3 7 3 7.5 nS
0 0 nS
0 7 0 7.5 nS

0.5 10 0.5 10 nS

1.5 1.5 nS

0.8 0.8 nS

1.5 1.5 nS

0.8 0.8 nS

1.5 1.5 nS

0.8 0.8 nS

1.5 1.5 nS

0.8 0.8 nS
64 64 mS

14 15 nS

-75/75L/75I

(PC133, CL3)

45 100000

UNIT

nS

nS
nS

- 6 -

PARAMETER SYM. -6

MIN. MAX.

Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b) Command

Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period

Write Recovery Time CL* = 2
CL* = 3
CLK Cycle Time CL* = 2

CL* = 3 6 1000 nS
CLK High Level Width

CLK Low Level Width t
Access Time from CLK CL* = 2

Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK

(Rise and Fall)
Data-in Set-up Time

Data-in Hold Time
Address Set-up Time

Address Hold Time
CKE Set -up Time
CKE Hold Time
Command Set -up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time

CL* = 3 5.4 nS

tRC

t

RAS

t

RCD

t

CCD

tRP

t

RRD

tWR

tCK

tCH 2.5

2.5 nS

CL

tAC

tOH

tHZ
tLZ
tSB

tT

tDS
tDH

tAS

tAH

t

CKS

t

CKH

t

CMS

t

CMS

t

REF

t

RSC

60 nS
42 100000
18 nS

1 tCK

18 nS
12 nS

2 tCK
2 tCK

7.5 1000 nS

5.4 nS

3 nS
3 7 nS
0 nS
0 7 nS

0.5 10 nS

1.5 nS

0.8 nS

1.5 nS

0.8 nS

1.5 nS

0.8 nS

1.5 nS

0.8 nS
64 mS

12 nS

W982516CH

UNIT

nS

nS

Publication Release Date: Mar 2003

- 7 - Revision A1

DC CHARACTERISTICS

(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I)

PARAMETER SYM.

Operating Current

t

= min., tRC = min.

CK

Active precharge command
cycling without burst

operation

Standby Current

t

= min, CS = VIH

CK

VIH/L = VIH (min.)/VIL (max.)
Bank: Inactive state

Standby Current

CLK = VIL, CS= VIH
VIH/L = VIH (min.)/VIL (max.)

BANK: Inactive state

No Operating Current

t

= min., CS = VIH (min.)

CK

BANK: Active state
(4 banks)

Burst Operating Current

t

= min.

CK

Read/ Write command cycling

Auto Refresh Current

t

= min.

CK

Auto refresh command cycling

Self Refresh Current

Self Refresh Mode
CKE = 0.2V

1 Bank Operation ICC1 90 80 75 3

CKE = VIH ICC2 50 40 35 3

CKE = VIL (Power

down mode)

CKE = VIH ICC2S 10 10 10

CKE = VIL (Power

down mode)

CKE = VIH ICC3 70 60 55

CKE = VIL (Power

down mode)

Standard(-6/-7/-75) 3 3 3
Low Power(75L/75I)

ICC2P 2 2 2 3

ICC2PS 2 2 2 mA

ICC3P 10 10 10

ICC4 110 100 95 3, 4

ICC5 180 170 160 3

ICC6L

-6

MAX. MAX.

- 1

-7

W982516CH

-75/75L/75I

UNIT

NOTES

PARAMETER SYMBOL

Input Leakage Current

(0V ≤ VIN ≤ VCC, all other pins not under test = 0V)

Output Leakage Current

(Output disable, 0V ≤ VOUT ≤ VCCQ)

LVTTL Output ″H″ Level Voltage

(IOUT = -2 mA )

LVTTL Output ″L″ Level Voltage

(IOUT = 2 mA )

II(L) -5 5

IO(L) -5 5

VOH 2.4 - V

VOL - 0.4 V

MIN. MAX. UNIT NOTES

µ A

µ A

- 8 -

W982516CH

Notes:

1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the
devices.

2. All voltages are referenced to VSS

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.

4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.

5. Power up sequence is further described in the "Functional Description" section.

6. AC Testing Conditions

Output Reference Level 1.4V/1.4V
Output Load See diagram below
Input Signal Levels 2.4V/0.4V
Transition Time (Rise and Fall) of Input Signal 2 nS
Input Reference Level 1.4V

1.4 V

50 ohms

Z = 50 ohmsoutput

AC TEST LOAD

7. Transition times are measured between VIH and V IL.

8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.

50pF

Publication Release Date: Mar 2003

- 9 - Revision A1

W982516CH

CS

WE

OPERATION MODE

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.

Table 1 Truth Table (Note (1) , (2))

COMMAND DEVICE

Bank Active Idle H x x v v v L L H H
Bank Precharge Any H x x v L x L L H L

Precharge All Any H x x x H x L L H L
Write Active (3) H x x v L v L H L L
Write with Autoprecharge Active (3) H x x v H v L H L L

Read Active (3) H x x v L v L H L H
Read with Autoprecharge Active (3) H x x v H v L H L H
Mode Register Set Idle H x x v v v L L L L
No- operation Any H x x x x x L H H H
Burst Stop Active (4) H x x x x x L H H L
Device Deselect Any H x x x x x H x x x
Auto-refresh Idle H H x x x x L L L H
Self-refresh Entry Idle H L x x x x L L L H
Self-refresh Exit Idle

Clock Suspend Mode
Entry

Power Down Mode Entry Idle

Clock Suspend Mode Exit Active L H x x x x x x x x
Power Down Mode Exit

Data Write/Output Enable Active H x L x x x x x x x
Data Write/Output Disable

STATE

(S.R.)

Active H L x x x x x x x x

Active (5)

Any

(Power

down)

Active H x H x x x x x x x

CKEN-1 CKEN DQM BS0, 1 A10

L
L

H
H

L
L

H
H

L
L

H
H

x
x

x
x

x
x

A0−A9

A11, A12

x
x

x
x

x
x

x
x

x
x

x
x

x
x

x
x

x
x

H

L

H

L

H

L

RAS CAS

x
H

x
H

x
H

x
H

x
H

x
H

x
x

x
x

x
x

Notes:
(1) v = valid x = Don't care L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn -1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.

- 10 -

W982516CH

FUNCTIONAL DESCRIPTION

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.

During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the "NOP" state. The power up voltage must not exceed Vcc +0.3V
on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µS is required followed
by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been precharged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode

Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this
cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to t
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

RSC

has

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (t
specified as t

RAS

(max).

). Once a bank has been activated it must be precharged before another Bank

RCD

). The maximum time that each bank can be held active is

RRD

Read and Write Access Modes

After a bank has been activated , a read or write cycle can be followed. This is accomplished by
setting RAS high and CAS low at the clock rising edge after minimum of t
level defines whether the access cycle is a read operation (WE high), or a write operation (WE low).
The address inputs determine the starting column address.

Reading or writing to a different row within an activated bank requires the bank be precharged and a
new Bank Activate command be issued. When more than one bank is activated, interleaved bank

Read or Write operations are possible. By using the programmed burst length and alternating the
access and precharge operations between multiple banks, seamless data access operation among

many different pages can be realized. Read or Write Commands can also be issued to the same bank
or between active banks on every clock cycle.

Publication Release Date: Mar 2003

- 11 - Revision A1

delay. WE pin voltage

RCD

W982516CH

Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS
and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequential mode.

Burst Write Command

The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding
RAS high at the rising edge of the clock. The address inputs determine the starting column address.

Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the
Write Command is issued. The remaining data inputs must be supplied on each subsequent rising
clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data

from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full page.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.
The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst
read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write
operation, then any residual data from the burst write cycle will be ignored.

- 12 -

W982516CH

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA ACCESS ADDRESS

Data 0 n BL = 2 (disturb address is A0)
Data 1 n + 1 No address carry from A0 to A1

Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)
Data 3 n + 3 No address carry from A1 to A2

Data 4 n + 4
Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)
Data 6 n + 6 No address carry from A2 to A3

Data 7 n + 7

BURST LENGTH

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA ACCESS ADDRESS BUST LENGTH

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2
Data 1

Data 2
Data 3
Data 4
Data 5
Data 6
Data 7

A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 4

BL = 8

Publication Release Date: Mar 2003

- 13 - Revision A1