Rainbow Electronics W982516CH User Manual

W982516CH

4M × 4 BANKS × 16 BIT SDRAM

GENERAL DESCRIPTION

W982516CH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 4M words × 4 banks × 16 bits. Using pipelined architecture and 0.13 µm process technology, W982516CH delivers a data bandwidth of up to 166M words per second (-6). To fully comply with the

personal computer industrial standard, W982516CH is sorted into two speed grades: -6, -7 and -75. The -6 is compliant to the 166 MHz/CL3 specification, the -7 is compliant to the 143 MHz/CL3 or

PC133/CL2 specification, the -75 is compliant to the PC133/CL3 specification, for handheld device application, we also provide a low power option, the 75L grade, with Self Refresh Current under 1mA., and an industrial temperature option, the grade of 75I, which is guranteed to support -40° C – 85°C.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W982516CH is ideal for main memory in

high performance applications.

FEATURES

• 3.3V ± 0.3V Power Supply

• Up to 166 MHz Clock Frequency

• 4,194,304 Words × 4 Banks × 16 Bits Organization

• Self Refresh Mode: Standard and Low Power

• CAS Latency: 2 and 3

• Burst Length: 1, 2, 4, 8, and Full Page

• Burst Read, Single Writes Mode

• Byte Data Controlled by LDQM, UDQM

• Power-down Mode

• Auto-precharge and Controlled Precharge

• 8K Refresh Cycles/64 mS

• Interface: LVTTL

• Packaged in TSOP II 54 -pin, 400 mil - 0.80

AVAILABLE PART NUMBER

Part Number Speed Grade Self Refresh Current (Max) Operating Temperature

W982516CH- 6 PC166/CL3 3mA 0°C - 70°C W982516CH- 7 PC133/CL2 3mA 0°C - 70°C W982516CH-75 PC133/CL3 3mA 0°C - 70°C W982516CH75L PC133/CL3 1mA 0°C - 70°C W982516CH75I PC133/CL3 1mA -40°C - 85°C

Publication Release Date: Mar 2003

- 1 - Revision A1

PIN CONFIGURATION

DQ0

VCCQ

DQ1 DQ2

VSSQ

DQ3

DQ4

VCCQ

DQ5 DQ6

VSSQ

DQ7

LDQM

CAS RAS

BS0 BS1

A10/AP

VCC

WE

CS

A0 A1 A2 A3

VCC

W982516CH

V SS

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

54

DQ15

53

V SSQ

52

DQ14

51

DQ13

50

V CCQ

49

DQ12

48

DQ11

47

V SSQ

46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28

DQ10 DQ9 V CCQ

DQ8 V SS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6

A5 A4 V SS

- 2 -

PIN DESCRIPTION

define the operation

cycle, sampling DQM high will block the write operation

When CKE is low, Power Down mode, Suspend mode,

PIN NO. PIN NAME FUNCTION DESCRIPTION

23−26, 22,

29−36 20, 21 BS0, BS1 Bank Select

2, 4, 5, 7, 8, 10,

11, 13, 42, 44, 45, 47, 48, 50,

51, 53

19

18

17

A0−A12

DQ0−DQ16

CS

RAS

CAS

Input/Output

Chip Select

Row Address

Address

Data

Strobe

Column

Address

Strobe

Multiplexed pins for row and column address. Row address: A0−A12. Column address: A0−A8.

Select bank to activate during row address latch time, or bank to read/write during address latch time.

Multiplexed pins for data output and input.

Disable or enable the command decoder. When command decoder is disabled, new command is

ignored and previous operation continues. Command input. When sampled at the rising edge of the clock, RAS, CAS and WE

to be executed.

Referred to RAS

W982516CH

16

15, 39

38 CLK Clock Inputs

37 CKE Clock Enable

1, 14, 27 VCC Power (+3.3V) Power for input buffers and logic circuit inside DRAM.

28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM.

3, 9, 43, 49 VCCQ

6, 12, 46, 52 VSSQ

40 NC No Connection No connection

WE

LDQM,

UDQM

Write Enable

Input/Output

Power (+3.3V)

for I/O Buffer

Mask

Ground

Referred to The output buffer is placed at Hi -Z(with latency of 2)

when DQM is sampled high in read cycle. In write with zero latency.

System clock used to sample inputs on the rising edge of clock.

CKE controls the clock activation and deactivation. or Self Refresh mode is entered.

Separated power from VCC, to improve DQ noise immunity.

Separated ground from V SS, to improve DQ noise immunity.

RAS

Publication Release Date: Mar 2003

- 3 - Revision A1

BLOCK DIAGRAM

W982516CH

A10

A11 A12 BS0 BS1

CLK

CKE

RAS

CAS

WE

A0

A9

CLOCK

BUFFER

CS

COMMAND

DECODER

ADDRESS

BUFFER

REFRESH COUNTER

CONTROL

GENERATOR

MODE

REGISTER

COLUMN

COUNTER

SIGNAL

COLUMN DECODER

CELL ARRAY

BANK #0

ROW DECODER

SENSE AMPLIFIER

DATA CONTROL

CIRCUIT

COLUMN DECODER

CELL ARRAY

BANK #1

ROW DECODERROW DECODER

SENSE AMPLIFIER

DQ

BUFFER

DQ0

DQ15

LDQM UDQM

COLUMN DECODER

CELL ARRAY

BANK #2

ROW DECODER

SENSE AMPLIFIER

Note: The cell array configuration is 8192 * 512 * 16.

- 4 -

COLUMN DECODER

CELL ARRAY

BANK #3

SENSE AMPLIFIER

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT NOTES

W982516CH

Input, Output Voltage VIN, VOUT

Supply Voltage VCC , VCCQ Operating Temperat ure(-6/-7/-75/75L) TOPR Operating Temperature(75I) TOPR Storage Temperature TSTG

Soldering Temperature (10s) TSOLDER 260 °C 1 Power Dissipation PD 1 W 1

Short Circuit Output Current IOUT 50 mA 1

Note 1: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

-0.3 − VCC +

0.3

-0.3 − 4.6 0 − 70

-40 − 85

-55 − 150

V 1

°C 1 °C 1 °C 1

RECOMMENDED DC OPERA TING CONDITIONS

(Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Supply Voltage VCC 3.0 3.3 3.6 V 2 Supply Voltage (for I/O Buffer) VCCQ 3.0 3.3 3.6 V 2 Input High Voltage VIH 2.0 - VCC +0.3

V 2

Input Low Voltage VIL -0.3 - 0.8 V 2

Note 2: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS VIL(min) = VSS/ VSS Q-1.2V for pulse width < 5 nS

CAPACITANCE

(VCC = 3.3V, f = 1 MHz, T A = 25°C)

PARAMETER SYMBOL MIN. MAX. UNIT

Input Capacitance (A0 to A12, BS0, BS1, CS , RAS, CAS, WE, LDQM,

UDQM, CKE) Input Capacitance (CLK) CCLK - 3.5 pf Input/Output Capacitance CIO - 6.5 pf

Note: These parameters are periodically sampled and not 100% tested.

Publication Release Date: Mar 2003

- 5 - Revision A1

CI - 3.8 pf

W982516CH

AC CHARACTERISTICS A ND OPERATING CONDITION

(Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I ; Notes: 5, 6, 7, 8)

PARAMETER SYM.

MIN. MAX. MIN. MAX.

Ref/Active to Ref/Active Command Period Active to precharge Command Period

Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b) Command

Period Precharge to Active Command Period

Active(a) to Active(b) Command Period Write Recovery Time CL* = 2 CL* = 3

CLK Cycle Time CL* = 2 CL* = 3 7 1000 7.5 1000 nS CLK High Level Width CLK Low Level Width Access Time from CLK CL* = 2

Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK

(Rise and Fall) Data-in Set-up Time

Data-in Hold Time Address Set-up Time Address Hold Time CKE Set -up Time CKE Hold Time

Command Set -up Time Command Hold Time Refresh Time

Mode register Set Cycle Time

*CL = CAS Latency

CL* = 3 5.4 5.4 nS

tRC

t

RAS

t

RCD

t

CCD

tRP

t

RRD

tWR

tCK

tCH 2.5 2.5

tCL 2.5 2.5

tAC

tOH

tHZ tLZ tSB

tT

tDS tDH

tAS

tAH

t

CKS

t

CKH

t

CMS

t

CMS

t

REF

t

RSC

-7

(PC133, CL2)

56 65 nS 40 100000

15 20 nS

1 1 tCK

15 20 nS 15 15 nS

2 2 tCK 2 2 tCK

7.5 1000 10 1000 nS

5.4 6 nS

3 3 nS 3 7 3 7.5 nS 0 0 nS 0 7 0 7.5 nS

0.5 10 0.5 10 nS

1.5 1.5 nS

0.8 0.8 nS

1.5 1.5 nS

0.8 0.8 nS

1.5 1.5 nS

0.8 0.8 nS

1.5 1.5 nS

0.8 0.8 nS 64 64 mS

14 15 nS

-75/75L/75I

(PC133, CL3)

45 100000

UNIT

nS

nS nS

- 6 -

PARAMETER SYM. -6

MIN. MAX.

Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b) Command

Period Precharge to Active Command Period Active(a) to Active(b) Command Period

Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2

CL* = 3 6 1000 nS CLK High Level Width

CLK Low Level Width t Access Time from CLK CL* = 2

Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK

(Rise and Fall) Data-in Set-up Time

Data-in Hold Time Address Set-up Time

Address Hold Time CKE Set -up Time CKE Hold Time Command Set -up Time Command Hold Time Refresh Time Mode register Set Cycle Time

CL* = 3 5.4 nS

tRC

t

RAS

t

RCD

t

CCD

tRP

t

RRD

tWR

tCK

tCH 2.5

2.5 nS

CL

tAC

tOH

tHZ tLZ tSB

tT

tDS tDH

tAS

tAH

t

CKS

t

CKH

t

CMS

t

CMS

t

REF

t

RSC

60 nS 42 100000 18 nS

1 tCK

18 nS 12 nS

2 tCK 2 tCK

7.5 1000 nS

5.4 nS

3 nS 3 7 nS 0 nS 0 7 nS

0.5 10 nS

1.5 nS

0.8 nS

1.5 nS

0.8 nS

1.5 nS

0.8 nS

1.5 nS

0.8 nS 64 mS

12 nS

W982516CH

UNIT

nS

Publication Release Date: Mar 2003

- 7 - Revision A1

DC CHARACTERISTICS

(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I)

PARAMETER SYM.

Operating Current

t

= min., tRC = min.

CK

Active precharge command cycling without burst

operation

Standby Current

t

= min, CS = VIH

CK

VIH/L = VIH (min.)/VIL (max.) Bank: Inactive state

Standby Current

CLK = VIL, CS= VIH VIH/L = VIH (min.)/VIL (max.)

BANK: Inactive state

No Operating Current

t

= min., CS = VIH (min.)

CK

BANK: Active state (4 banks)

Burst Operating Current

t

= min.

CK

Read/ Write command cycling

Auto Refresh Current

t

= min.

CK

Auto refresh command cycling

Self Refresh Current

Self Refresh Mode CKE = 0.2V

1 Bank Operation ICC1 90 80 75 3

CKE = VIH ICC2 50 40 35 3

CKE = VIL (Power

down mode)

CKE = VIH ICC2S 10 10 10

CKE = VIL (Power

down mode)

CKE = VIH ICC3 70 60 55

CKE = VIL (Power

down mode)

Standard(-6/-7/-75) 3 3 3 Low Power(75L/75I)

ICC2P 2 2 2 3

ICC2PS 2 2 2 mA

ICC3P 10 10 10

ICC4 110 100 95 3, 4

ICC5 180 170 160 3

ICC6L

-6

MAX. MAX.

- 1

-7

W982516CH

-75/75L/75I

UNIT

NOTES

PARAMETER SYMBOL

Input Leakage Current

(0V ≤ VIN ≤ VCC, all other pins not under test = 0V)

Output Leakage Current

(Output disable, 0V ≤ VOUT ≤ VCCQ)

LVTTL Output ″H″ Level Voltage

(IOUT = -2 mA )

LVTTL Output ″L″ Level Voltage

(IOUT = 2 mA )

II(L) -5 5

IO(L) -5 5

VOH 2.4 - V

VOL - 0.4 V

MIN. MAX. UNIT NOTES

µ A

- 8 -

W982516CH

Notes:

1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.

2. All voltages are referenced to VSS

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC.

4. These parameters depend on the output loading conditions. Specified values are obtained with output open.

5. Power up sequence is further described in the "Functional Description" section.

6. AC Testing Conditions

Output Reference Level 1.4V/1.4V Output Load See diagram below Input Signal Levels 2.4V/0.4V Transition Time (Rise and Fall) of Input Signal 2 nS Input Reference Level 1.4V

1.4 V

50 ohms

Z = 50 ohmsoutput

AC TEST LOAD

7. Transition times are measured between VIH and V IL.

8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.

50pF

Publication Release Date: Mar 2003

- 9 - Revision A1

W982516CH

CS

WE

OPERATION MODE

Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.

Table 1 Truth Table (Note (1) , (2))

COMMAND DEVICE

Bank Active Idle H x x v v v L L H H Bank Precharge Any H x x v L x L L H L

Precharge All Any H x x x H x L L H L Write Active (3) H x x v L v L H L L Write with Autoprecharge Active (3) H x x v H v L H L L

Read Active (3) H x x v L v L H L H Read with Autoprecharge Active (3) H x x v H v L H L H Mode Register Set Idle H x x v v v L L L L No- operation Any H x x x x x L H H H Burst Stop Active (4) H x x x x x L H H L Device Deselect Any H x x x x x H x x x Auto-refresh Idle H H x x x x L L L H Self-refresh Entry Idle H L x x x x L L L H Self-refresh Exit Idle

Clock Suspend Mode Entry

Power Down Mode Entry Idle

Clock Suspend Mode Exit Active L H x x x x x x x x Power Down Mode Exit

Data Write/Output Enable Active H x L x x x x x x x Data Write/Output Disable

STATE

(S.R.)

Active H L x x x x x x x x

Active (5)

Any

(Power

down)

Active H x H x x x x x x x

CKEN-1 CKEN DQM BS0, 1 A10

L L

H H

L L

H H

L L

H H

x x

A0−A9

A11, A12

x x

H

L

H

L

H

L

RAS CAS

x H

x x

Notes: (1) v = valid x = Don't care L = Low Level H = High Level (2) CKEn signal is input level when commands are provided. CKEn -1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode.

- 10 -

W982516CH

FUNCTIONAL DESCRIPTION

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs.

During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed Vcc +0.3V on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode

Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

RSC

has

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t specified as t

RAS

(max).

). Once a bank has been activated it must be precharged before another Bank

RCD

). The maximum time that each bank can be held active is

RRD

Read and Write Access Modes

After a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of t level defines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address.

Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank

Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among

many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.

Publication Release Date: Mar 2003

- 11 - Revision A1

delay. WE pin voltage

RCD

W982516CH

Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.

Burst Write Command

The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address.

Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data

from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.

- 12 -

W982516CH

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA ACCESS ADDRESS

Data 0 n BL = 2 (disturb address is A0) Data 1 n + 1 No address carry from A0 to A1

Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1) Data 3 n + 3 No address carry from A1 to A2

Data 4 n + 4 Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2) Data 6 n + 6 No address carry from A2 to A3

Data 7 n + 7

BURST LENGTH

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA ACCESS ADDRESS BUST LENGTH

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 Data 1

Data 2 Data 3 Data 4 Data 5 Data 6 Data 7

A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 4

BL = 8

Publication Release Date: Mar 2003

- 13 - Revision A1

W982516CH

Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execut e as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during

a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-pecharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-pecharge function is initiated. The SDRAM automatically enters the precharge operation two clock delay from the last burst write cycle. This delay is referred to as Write tWR. The bank undergoing auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as t to Active delay (t Bank Activate Command and the beginning of the internal precharge operation must satisfy t

= tWR + tRP). When using the Auto-precharge Command, the interval between the

DAL

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of

the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP).

, Data-in

DAL

RAS

(min).

Self Refresh Command

The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time.

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 8,192 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode.

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations,

therefore the device can not remain in Power Down mode longer than the Refresh period (t device.

- 14 -

REF

) of the

W982516CH

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to t

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares.

Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is ac tive, Clock Suspend Mode is entered. The Clock Suspend mode

deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.

(min) + tCK (min).

CKS

Publication Release Date: Mar 2003

- 15 - Revision A1

TIMING WAVEFORMS

Command Input Timing

VIH

CLK

VIL

CS

RAS

t

CK

t

CMStCMH

t

CMStCMH

t

CMH

W982516CH

t

CH

CL

t

T

t

T

t

CMS

t

CMStCMH

CAS

t

CMStCMH

WE

t

AS

t

AH

A0-A12

BS0, 1

t

CKH

t

CKStCKH

CKS

t

CKS

t

CKH

CKE

- 16 -

Timing Waveforms, continued

Read Timing

CLK

CS

RAS

W982516CH

Read CAS Latency

A0 - A12

BS0, 1

CAS

WE

DQ

Read Command

t

AC

t

LZ

t

OH

Valid

Data-Out

t

AC

Burst Length

t

OH

Valid

Data-Out

t

HZ

Publication Release Date: Mar 2003

- 17 - Revision A1

Timing Waveforms, continued

Control Timing of Input/Output Data

Input Data

(Word Mask)

CLK

t

CMStCMH

t

CKStCKH

DQM

DQ0 -15

(Clock Mask)

CLK

CKE

t

DStDH

Valid

Data-in

t

CMH

t

CKH

t

CMS

t

DStDH

Valid

Data-in

t

CKS

tDSt

Data-in

Valid

W982516CH

DH

t

DStDH

Valid

Data-in

DQ0 -15

Output Data

(Output Enable)

CLK

DQM

DQ0 -15

(Clock Mask)

CLK

CKE

DQ0 -15

t

DStDH

Valid

Data-in

t

DStDH

Valid

Data-in

t

CMH

t

CKH

t

CMStCMH

t

AC

OH

t

AC

OH

Data-Out

t

CKStCKH

Data-Out

Valid

t

OH

t

OH

CMS

t

Valid

Data-Out

HZ

t

OH

Valid

Data-Out

t

AC

t

CKS

t

AC

t

DS

Valid

Data-in

OPEN

t

DH

t

LZ

t

OH

t

DStDH

Valid

Data-in

t

AC

t

AC

t

Valid

Data-Out

Valid

Data-Out

t

AC

OH

t

AC

t

OH

- 18 -

Timing Waveforms, continued

Mode Register Set Cycle

CLK

t

CMStCMH

CS

t

CMStCMH

RAS

t

CMStCMH

CAS

t

CMStCMH

WE

t

A0-A12

BS0,1

AStAH

Register set data

W982516CH

t

RSC

A0 A1

Burst Length A2 A3

Addressing Mode A4 A5

CAS Latency

A6

"0"

(Test Mode)

A0A7 A8 Reserved A0A9 A0Write Mode

A10

"0" A0A11

"0"

A12

A0BS0

"0"

A0

Reserved

A0BS1 "0"

A0 A0A2 A1 A0 A00 0 0 A00 0 1 A00 1 0 A00 1 1

A0Burst Length

A0Sequential A0Interleave

1 A01 A02 A02 A04 A04 A08 A08

A01 0 0 A0

1 0 1

A0Reserved A01 1 0 A01 1 1

A0

A3

A0Full Page

A0

Addressing Mode A00 A0Sequential A01 A0Interleave

A0A6 A5 A4 A00 0 0 A00 0 1 A00 1 0 A00 1 1 A01 0 0

A0CAS Latency A0Reserved A0Reserved

2

A03

Reserved

A0A9 Single Write Mode A00 A0Burst read and Burst write A01 A0Burst read and single write

A0Reserved

Publication Release Date: Mar 2003

- 19 - Revision A1

OPERATING TIMING EXAMPLE

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

0

CLK

W982516CH

CS

RAS

CAS

WE

BS0

BS1

A10

A0-A9,

A11,12

DQM

CKE

DQ

t

RC

t

RC

t

RAS

t

RCD

RAa RBb RAc RBd RAe

RAa

CAw

t

RRD

t

AC

t

RCD

RBb CBx RAc CAy

aw0 aw1 aw2 aw3 bx0

t

RP

t

RAS

t

RCD

t

AC

bx1

t

RRD

t

RRD

bx2

bx3

t

RC

t

RAS

t

RP

RBd CBz

t

AC

t

RC

t

RAS

t

RCD

cy0 cy1 cy2 cy3

t

RRD

t

RP

RAe

t

AC

Active Read

Bank #0 Bank #1 Bank #2

Idle

Precharge

Active Read

Active

Read

Active

Precharge

ReadPrecharge

Active

Bank #3

- 20 -

W982516CH

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)

(CLK = 100 MHz)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

0

CS

RAS

CAS

WE

BS0

BS1

A10

A0-A9,

A11,12

DQM

CKE

DQ

t

RC

t

RC

t

RAS

t

RCD

RAa RBb RAc

RAa CAw

RBb CBx RAc

t

RRD

t

RCD

t

AC

aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0

t

RRD

t

RP

t

RAS

t

RC

t

RC

t

RAS

t

RP

t

RCD

CAy

t

AC

t

RRD

RBd

t

RCD

t

RP

t

RAS

RAe

RAeCBz

t

AC

t

RRD

Bank #0 Bank #1

Bank #2 Bank #3

Idle

Active

Read

AP*

Active Read

Active

Read

AP*

Active

AP*

Active

Read

* AP is the internal precharge start timing

Publication Release Date: Mar 2003

- 21 - Revision A1

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)

(CLK = 100 MHz)

0 1 2 3 4 5

CLK

CS

RAS

CAS

WE

BS0

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

t

RC

t

RAS

t

RP

t

RP

t

RAS

W982516CH

t

RC

t

RC

t

RAS

t

RP

BS1

t

A10

A0-A9,

A11,12

RCD

RAa

RAa CAx

t

RCD

RBb

RBb CBy

RAc

t

RCD

CAz

DQM

CKE

t

DQ

Bank #0 Bank #1 Bank #2 Bank #3

Active

Idle

t

RRD

Read

Precharge

AC

ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7

Active

Read

t

AC

t

RRD

Precharge Active

Read

Precharge

t

AC

CZ0

- 22 -

W982516CH

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)

(CLK = 100 MHz)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

0

CLK

CS

RAS

CAS

WE

BS0

t

RC

t

RC

t

RAS

t

RP

t

RAS

t

RAS

t

RP

BS1

A10

A0-A9,

A11,12

DQM

CKE

DQ

Bank #0 Bank #1 Bank #2 Bank #3

t

RCD

RAa

CAx

Active Read

Idle

t

RCD

RBb

RBb CBy

t

CAC

ax0 ax1 ax2

t

RRD

ax3 ax4

ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0

t

RRD

t

AP*

Active

Read

* AP is the internal precharge start timing

RCD

RAc

RAc CAz

CAC

Active Read

AP*

t

CAC

Publication Release Date: Mar 2003

- 23 - Revision A1

Operating Timing Example, continued

Interleaved Bank Write (Burst Length = 8)

(CLK = 100 MHz)

CLK

CS

RAS

CAS

WE

0 1 2 3 4 5

t

RCD

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

t

RC

t

RAS

t

RCD

W982516CH

t

RP

t

RAS

t

RP

t

RCD

BS0

BS1

A10

A0-A9,

A11,12

DQM

CKE

DQ

Bank #0 Bank #1 Bank #2

Bank #3

RAa

RAa CAx

Idle

RBb

RBb CBy

ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2

t

RRD

Active Write

t

RRD

PrechargeActive Write

RAc

RAc CAz

Active

Write

Precharge

- 24 -

Operating Timing Example, continued

Interleaved Bank Write (Burst Length = 8, Autoprecharge)

(CLK = 100 MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CS

t

RC

RAS

t

RAS

CAS

WE

W982516CH

t

RP

t

RAS

t

RAS

t

RP

BS0

BS1

A10

A0-A9,

A11,12

DQM

CKE

DQ

Bank #0 Bank #1 Bank #2 Bank #3

t

RCD

RAa

CAx

ax0 ax1

Active Write

Idle

t

RCD

RBb

ax4

ax5 ax6 ax7 by0 by1

t

RRD

CBy

by2

by3 by4

t

RRD

AP*

Active

Write

RCD

RAb

RAc

by5

by6 by7 CZ0 CZ1 CZ2

Active

CAz

Write

AP*

* AP is the internal precharge start timing

Publication Release Date: Mar 2003

- 25 - Revision A1

Operating Timing Example, continued

Page Mode Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

t

CS

RAS

CAS

WE

CCD

t

RAS

t

CCD

t

RAS

t

CCD

W982516CH

t

RP

t

RP

BS0

BS1

A10

A0-A9, A11,12

DQM

CKE

DQ

Bank #0 Bank #1 Bank #2 Bank #3

t

RCD

RAa

CAI

t

RRD

Active Read

Idle

t

RCD

RBb

RBb CBx CAy CAm CBz

t

AC

a0 a1

t

AC

a3 bx0

a2

AC

Ay0 Ay1 Ay2 am0

bx1

t

AC

Read Read

Active Read

* AP is the internal precharge start timing

t

AC

am1 am2 bz0 bz1 bz2 bz3

Precharge

Read

AP*

- 26 -

Operating Timing Example, continued

Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)

W982516CH

CLK

CS

RAS

CAS

WE

BS0

BS1

A10

A0-A9, A11,12

DQM

0 1 2 3 4 5

t

RCD

RAa

CAx CAy

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

(CLK = 100 MHz)

t

RAS

t

RP

CKE

Bank #0 Bank #1 Bank #2 Bank #3

DQ

Active Read

Idle

t

AC

ax0 ax1

ax2

Q Q Q Q Q Q

t

WR

ax3

ax5 ay1ay0 ay2 ay4

ax4

D

Write

ay3

D DD

Precharge

Publication Release Date: Mar 2003

- 27 - Revision A1

Operating Timing Example, continued

Auto Precharge Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

W982516CH

CS

RAS

CAS

WE

BS0

BS1

A10

A0-A9,

A11,12

DQM

CKE

DQ

t

RC

t

RAS

t

RCD

RAa

RAa CAw RAb

t

AC

aw0 aw1 aw2 aw3

t

RP

RAb

t

RC

t

RAS

t

RCD

CAx

t

AC

bx0 bx1 bx2 bx3

t

RP

Bank #0 Bank #1

Bank #2 Bank #3

Active

Idle

Read

AP*

* AP is the internal precharge start timing

Active Read AP*

- 28 -

Operating Timing Example, continued

Auto Precharge Write (Burst Length = 4)

(CLK = 100 MHz)

CLK

CS

RAS

CAS

WE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

t

RC

t

RAS

t

RP

W982516CH

t

RC

t

RAS

t

RP

BS0

BS1

A10

A0-A9,

A11,12

DQM

CKE

DQ

Bank #0 Bank #1 Bank #2 Bank #3

t

RCD

RAa

RAa CAw RAb CAx

aw1 aw2

Active

Idle

aw0

Write

aw3

AP*

* AP is the internal precharge start timing

RCD

RAb RAc

Active Write AP*

bx0 bx1

bx2

RAc

bx3

Active

Publication Release Date: Mar 2003

- 29 - Revision A1

Operating Timing Example, continued

Auto Refresh Cycle

CLK

RAS

CAS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

t

CS

WE

RP

W982516CH

(CLK = 100 MHz)

t

RC

t

RC

BS0,1

A10

A0-A9,

A11,12

DQM

CKE

DQ

All Banks Prechage

Auto

Refresh

Auto Refresh (Arbitrary Cycle)

- 30 -

Operating Timing Example, continued

Self Refresh Cycle

W982516CH

CLK

CS

RAS

CAS

WE

BS0,1

A10

A0-A9,

A11,12

DQM

CKE

DQ

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

t

RP

t

SB

t

CKS

(CLK = 100 MHz)

t

CKS

t

CKS

t

RC

Arbitrary Cycle

All Banks

Precharge

Self Refresh

Entry

Self Refresh Cycle

No Operation Cycle

Publication Release Date: Mar 2003

- 31 - Revision A1

Operating Timing Example, continued

Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

CLK

RAS

CAS

WE

BS0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CS

t

RCD

W982516CH

BS1

A10

A0-A9, A11,12

DQM

CKE

DQ

Bank #0 Bank #1 Bank #2 Bank #3

RBa

Idle

CBv CBw CBx CBy

t

AC

av0 av1

Q Q Q Q D DD Q Q Q Q

Read

av3 aw0 ax0 ay0 az0 az1 az2 az3

av2

Single WriteActive

CBz

Read

t

AC

- 32 -

Operating Timing Example, continued

PowerDown Mode

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CS

RAS

CAS

WE

BS

W982516CH

(CLK = 100 MHz)

A10

A0-A9

A11,12

DQM

CKE

DQ

RAa RAa

RAa CAa RAa CAx

t

CKS

Active

SB

t

CKS

Active Standby

Power Down mode

ax0

ax1 ax2 ax3

NOP Precharge NOP Active

Read

t

SB

t

CKS

t

CKS

Precharge Standby

Power Down mode

Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode. When CKE goes high, command input must be No operation at next CLK rising edge.

Publication Release Date: Mar 2003

- 33 - Revision A1

Operating Timing Example, continued

Autoprecharge Timing (Read Cycle)

W982516CH

(1) CAS

Latency=2

( a ) burst length = 1

Command

( b ) burst length = 2

( d ) burst length = 8

( a ) burst length = 1

( b ) burst length = 2

( c ) burst length = 4

( d ) burst length = 8

DQ

Command

DQ

( c ) burst length = 4

Command

DQ

Command

DQ

(2) CAS

Latency=3

Command

DQ

Command

DQ

Command

DQ

Command

DQ

0 1110987654321

Read AP

Act

t

RP

Q0

Read AP Act

Q0

t

RP

Q1

Q1 Q2

t

Q3

RP

AP ActRead

t

RP

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Read AP Act

t

RP

Q0

Read AP Act

t

RP

Q0

Q1

Q0

Q1 Q2 Q3

t

RP

t

RP

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Note )

Read

AP

Act

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least t

RAS

(min).

- 34 -

Operating Timing Example, continued

Autoprecharge Timing (Write Cycle)

W982516CH

(1) CAS Latency = 2

(a) burst length = 1

Command

DQ

(b) burst length = 2

Command

DQ

(c) burst length = 4

Command

DQ

(d) burst length = 8

Command

DQ

(2) CAS Latency = 3

(a) burst length = 1

Command

DQ

(b) burst length = 2

Command

DQ

(c) burst length = 4

Command

(d) burst length = 8

Command

DQ

0 1 32

Write

D0

Write

D0

Write

D0

Write

D0

Write

D0

Write

D0

Write

D0

tWR

D1

tWR

D1

4 5 76 8 9 1110

ActAP

tRP

ActAP

tWR

D2 D3

D2 D3 D4 D5 D6 D7

tWR

D2 D3

D2 D3 D4 D5 D6 D7

tRP

ActAP

tWR

tRP

tWR

tRP

ActAP

tRP

12

ActAP

AP

tRP

Act

tRP

Act

tWR

ActAP

tWR

Publication Release Date: Mar 2003

- 35 - Revision A1

Operating Timing Example, continued

Timing Chart of Read to Write Cycle

In the case of Burst Length = 4

W982516CH

DQM

0

Read Write

DQ

D0 D1 D2 D3

Read Write

DQ

Read

Write

DQ

D0 D1 D2 D3

Read

Note: The Output data must be masked by DQM to avoid I/O conflict

Write

(1) CAS Latency=2

( a ) Command

( b ) Command

(2) CAS Latency=3

( a ) Command

( b ) Command

Timing Chart of Write to Read Cycle

In the case of Burst Length=4

DQM

0

ReadWrite

DQ

D0

ReadWrite

DQ

D0 D1

Write

D0 D1

Read

(1) CAS Latency=2

( a ) Command

( b ) Command

(2) CAS Latency=3

( a ) Command

( b ) Command

D0 D1 D2 D3

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3D0

Q0

Q1

1110987654321

Q2 Q3

- 36 -

Timing Chart of Burst Stop Cycle (Burst Stop Command)

W982516CH

(1) Read cycle

( a ) CAS latency =2

( b )CAS latency = 3

(2) Write cycle

0 1110987654321

Read BST

Command

DQ

Read

Command

DQ

Command

Write

DQ

Q0 Q1 Q2 Q3 Q4

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3 Q4

Note: represents the Burst stop commandBST

Q4

BST

Timing Chart of Burst Stop Cycle (Precharge Command)

Publication Release Date: Mar 2003

- 37 - Revision A1

(1) Read cycle

W982516CH

0 1 111098765432

(a) CAS latency =2

Command

(b) CAS latency =3

Command

(2) Write cycle

(a) CAS latency =2

Command

(b) CAS latency =3

Command

DQ

DQM

DQ

DQM DQ

Q0 Q1 Q2 Q3 Q4

Write

Q0 Q1 Q2 Q3 Q4

Write

Q0 Q1 Q2 Q3 Q4

PRCGRead

PRCG

tWR

PRCG

tWR

- 38 -

Operating Timing Example, continued

CKE/DQM Input Timing (Write Cycle)

W982516CH

CLK cycle No.

CLK

CLK cycle No.

CLK

CLK cycle No.

CLK

External

Internal

CKE

DQM

External

Internal

CKE

External

Internal

DQ

DQM

DQ

DQM

1

765432

D1 D6D5D3D2

DQM MASK

( 1 )

CKE MASK

7654321

D1 D6D5D3D2

DQM MASK CKE MASK

( 2 )

1

CKE

DQ

D1

CKE MASK

( 3 )

5432

D5D4D3D2

76

D6

Publication Release Date: Mar 2003

- 39 - Revision A1

Operating Timing Example, continued

CKE/DQM Input Timing (Read Cycle)

W982516CH

CLK cycle No.

External

CLK

CLK cycle No.

External

CLK

CLK cycle No.

Internal

CKE DQM

DQ

Internal

CKE

DQM DQ

1

Q

1

Q

2

Q

3

1

Q

1

Q

2

Q

3

( 1 )

Q

4

( 2 )

Open Open

5432

Q

4

6

Open

1

765432

Q

6

7

Q

6

765432

External

CLK

Internal

CKE

DQM

DQ

Q

1

Q

2

Q

3

( 3 )

Q

4

Q

5

Q

6

- 40 -

Operating Timing Example, continued

Self Refresh/Power Down Mode Exit Timing

Asynchronous Control Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min)

A ) tCK < tCKS(min)+tCK(min)

t

CK

CLK

W982516CH

CKE

Command

B) tCK >= tCKS(min) + tCK (min)

CLK

CKE

Command

Note )

All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode

NOP

Command

t

CKS

(min)+tCK(min)

CK

t

CKS

(min)+tCK(min)

Command

Input Buffer Enable

Command

Input Buffer Enable

NOP

t

Represents the No-Operation command Represents one command

Publication Release Date: Mar 2003

- 41 - Revision A1

PACKAGE DIMENSION

54L TSOP (II)-400 mil

54 28

1 27

W982516CH

HE

E

e

D

b

C

L

L1

ZD

A2A1A

Y

SEATING PLANE

Controlling Dimension: Millimeters

DIMENSION

SYM.

A

A1 A2

b c

H

E

e 0.80 0.0315

L

L1 0.80 0.032

Y

ZD

(MM)

MAX.MIN. NOM.

1.20

0.05

0.24

0.40 0.50 0.60 0.020 0.024

0.15

0.10 0.004

1.00

0.40

0.32

0.15

0.10 0.004

0.71 0.028

DIMENSION

(INCH)

MAX.MIN. NOM.

0.047

0.039

0.012

0.006

0.016

0.002

0.009

0.871D 22.2222.12 22.62 0.875 0.905

0.396E 10.06 10.16 10.26 0.400 0.404

0.45511.7611.56 11.96 0.463 0.471

0.016

- 42 -

11. REVERSION HISTORY

No. 4, Creation Rd. III,

FAX: 886

-3-

5796096

11F, No. 115, Sec. 3, Min

-

Sheng East Rd.,

Taipei, Taiwan

Kowloon, Hong Kong

CA 95134, U.S.A.

FAX: 408

-

5441798

No. 4, Creation Rd. III,

FAX: 886

-3-

5796096

11F, No. 115, Sec. 3, Min

-

Sheng East Rd.,

Taipei, Taiwan

Kowloon, Hong Kong

CA 95134, U.S.A.

FAX: 408

-

5441798

W982516CH

REVERSION

A1

DATE PAGE DESCRIPTION

March, 2003

- Preliminary datasheet

Oct, 2003 Add –6 speed grade

Headquarters

Science-Based Industrial Park,

Science-Based Industrial Park, Hsinchu, Taiwan

Hsinchu, Taiwan TEL: 886-3-5770066

TEL: 886-3-5770066

http://www.winbond.com.tw/

http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

TEL: 886-2-27190505

TEL: 886-2-27190505 FAX: 886-2-27197502

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd;

No. 378 Kwun Tong Rd;

TEL: 852-27513100

TEL: 852-27513100 FAX: 852-27552064

FAX: 852-27552064

Winbond Electronics North America Corp.

Winbond Electronics North America Corp. Winbond Memory Lab.

Winbond Memory Lab. Winbond Microelectronics Corp.

Winbond Microelectronics Corp. Winbond Systems Lab.

Winbond Systems Lab.

2727 N. First Street, San Jose,

TEL: 408-9436666

Publication Release Date: Mar 2003

- 43 - Revision A1

Rainbow Electronics W982516CH User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual