Rainbow Electronics W90N745CDG User Manual
W90N745CD/W90N745CDG
32-BIT ARM7TDMI-BASED MCU
W90N745
16/32-bit ARM microcontroller
Product Data Sheet
W90N745CD/W90N745CDG
Revision History
REVISION DATE COMMENTS
A 2006/06/23 Draft
A1 2006/08/30 Add Electrical specification
A2 2006/09/22 Delete Chapter 6: BLOCK DIAGRAM
Publication Release Date: September 22, 2006
- I - Revision A2
W90N745CD/W90N745CDG
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 1
2. FEATURES ................................................................................................................................. 2
3. PIN DIAGRAM ............................................................................................................................ 7
4. PIN ASSIGNMENT ..................................................................................................................... 8
5. PIN DESCRIPTION................................................................................................................... 13
6. FUNCTIONAL DESCRIPTION ................................................................................................. 24
6.1 ARM7TDMI CPU CORE ............................................................................................... 24
6.2 System Manager........................................................................................................... 25
6.2.1 Overview ........................................................................................................................25
6.2.2 System Memory Map......................................................................................................25
6.2.3 Address Bus Generation ................................................................................................28
6.2.4 Data Bus Connection with External Memory ..................................................................28
6.2.5 Bus Arbitration................................................................................................................37
6.2.6 Power Management .......................................................................................................38
6.2.7 Power-On Setting ........................................................................................................... 41
6.2.8 System Manager Control Registers Map........................................................................41
6.3 External Bus Interface .................................................................................................. 56
6.3.1 EBI Overview..................................................................................................................56
6.3.2 SDRAM Controller ..........................................................................................................56
6.3.3 EBI Control Registers Map .............................................................................................60
6.4 Cache Controller........................................................................................................... 79
6.4.1 On-Chip RAM ................................................................................................................. 79
6.4.2 Non-Cacheable Area ......................................................................................................79
6.4.3 Instruction Cache............................................................................................................80
6.4.4 Data Cache ....................................................................................................................82
6.4.5 Write Buffer ....................................................................................................................84
6.4.6 Cache Control Registers Map.........................................................................................84
6.5 Ethernet MAC Controller............................................................................................... 92
6.5.1 EMC Functional Description ........................................................................................... 93
6.5.2 EMC Register Mapping ................................................................................................103
6.6 GDMA Controller ........................................................................................................ 158
6.6.1 GDMA Functional Description ......................................................................................158
6.6.2 GDMA Register Map ....................................................................................................159
6.7 USB Host Controller ................................................................................................... 168
6.7.1 USB Host Functional Description .................................................................................168
6.7.2 USB Host Controller Registers Map .............................................................................169
6.8 USB Device Controller................................................................................................ 192
6.8.1 USB Endpoints ............................................................................................................. 192
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W90N745CD/W90N745CDG
6.8.2 Standard Device Request.............................................................................................192
6.8.3 USB Device Register Description .................................................................................192
6.9 Audio Controller .......................................................................................................... 231
6.9.1 I²S Interface.................................................................................................................. 231
6.9.2 AC97 Interface .............................................................................................................232
6.9.3 Audio Controller Register Map......................................................................................235
6.10 Universal Asynchronous Receiver/Transmitter Controller ......................................... 254
6.10.1 UART0........................................................................................................................256
6.10.2 UART1........................................................................................................................256
6.10.3 UART2........................................................................................................................258
6.10.4 UART3........................................................................................................................260
6.10.5 General UART Controller ...........................................................................................261
6.10.6 High speed UART Controller ......................................................................................274
6.11 Timer/Watchdog Controller......................................................................................... 288
6.11.1 General Timer Controller ............................................................................................ 288
6.11.2 Watchdog Timer .........................................................................................................288
6.11.3 Timer Control Registers Map...................................................................................... 288
6.12 Advanced Interrupt Controller..................................................................................... 297
6.12.1 Interrupt Sources........................................................................................................298
6.12.2 AIC Registers Map .....................................................................................................301
6.13 General-Purpose Input/Output ................................................................................... 314
6.13.1 GPIO Register Description .........................................................................................316
6.13.2 GPIO Register Description .........................................................................................317
6.14 I2C Interface ................................................................................................................ 338
6.14.1 I2C Protocol ................................................................................................................339
6.14.2 I2C Serial Interface Control Registers Map .................................................................342
6.15 Universal Serial Interface............................................................................................ 349
6.15.1 USI Timing Diagram ...................................................................................................350
6.15.2 USI Registers Map .....................................................................................................351
6.16 PWM ........................................................................................................................... 358
6.16.1 PWM Double Buffering and Reload Automatically......................................................359
6.16.2 Modulate Duty Ratio ...................................................................................................359
6.16.3 Dead Zone Generator.................................................................................................360
6.16.4 PWM Timer Start Procedure ......................................................................................360
6.16.5 PWM Timer Stop Procedure.......................................................................................360
6.16.6 PWM Register Map ....................................................................................................361
6.17 Keypad Interface......................................................................................................... 371
6.17.1 Keypad Interface Register Map ..................................................................................372
6.17.2 Register Description ...................................................................................................373
Publication Release Date: September 22, 2006
- III - Revision A2
W90N745CD/W90N745CDG
PS2 Host Interface Controller..................................................................................... 380
6.18
6.18.1 PS2 Host Controller Interface Register Map...............................................................381
6.18.2 Register Description ...................................................................................................382
7. ELECTRICAL SPECIFICATIONS........................................................................................... 386
7.1 Absolute Maximum Ratings ........................................................................................ 386
7.2 DC Specifications ....................................................................................................... 386
7.2.1 Digital DC Characteristics.............................................................................................386
7.2.2 USB Transceiver DC Characteristics............................................................................388
7.3 AC Specifications........................................................................................................ 389
7.3.1 EBI/SDRAM Interface AC Characteristics ....................................................................389
7.3.2 EBI/(ROM/SRAM/External I/O) AC Characteristics ...................................................... 390
7.3.3 USB Transceiver AC Characteristics............................................................................ 391
7.3.4 EMC RMII AC Characteristics ......................................................................................391
7.3.5 AC97/I2S Interface AC Characteristics.........................................................................393
7.3.6 I2C Interface AC Characteristics ...................................................................................395
7.3.7 USI Interface AC Characteristics..................................................................................396
7.3.8 PS2 Interface AC Characteristics ................................................................................. 397
8. ORDERING INFORMATION .................................................................................................. 399
9. PACKAGE SPECIFICATIONS................................................................................................ 400
10. APPENDIX A: W90N745 REGISTERS MAPPING TABLE .................................................... 401
- IV -
W90N745CD/W90N745CDG
1. GENERAL DESCRIPTION
The W90N745 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which
designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static
design is particularly suitable for cost sensitive and power sensitive applications.
One 100/10 Mbit MAC of Ethernet controller is built-in to reduce total system cost.
The W90N745 also provides one USB 1.1 host controller, one USB 1.1 device controller, one
AC97/I²S controller, one 2-channel GDMA, four independent UARTs, one watchdog timer, two 24-bit
timers with 8-bit pre-scale, up to 31 programmable I/O ports, PS2 keyboard controller and an
advanced interrupt controller. The external bus interface (EBI) controller provides for SDRAM,
ROM/SRAM, flash memory and I/O devices. The system manager includes an internal 32-bit system
bus arbiter and a PLL clock controller.
With a wide range of serial communication and Ethernet interfaces, the W90N745 is suitable for
communication gateways as well as many other general purpose applications.
Publication Release Date: September 22, 2006
- 1 - Revision A2
W90N745CD/W90N745CDG
2. FEATURES
Architecture
• Fully 16/32-bit RISC architecture
• Little/Big-Endian mode supported
• Efficient and powerful ARM7TDMI core
• Cost-effective JTAG-based debug solution
External Bus Interface
• 8/16-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os
• Support for SDRAM
• Programmable access cycle (0-7 wait cycle)
• Four-word depth write buffer for SDRAM write data
• Cost-effective memory-to-peripheral DMA interface
Instruction and Data Cache
• Two-way, set-associative, 4K-byte I-cache and 4K-byte D-cache
• Support for LRU (Least Recently Used) protocol
• Cache can be configured as internal SRAM
• Support cache lock function
Ethernet MAC Controller
• DMA engine with burst mode
• MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)
• Data alignment logic
• Endian translation
• 100/10 Mbit per second operation
• Full compliance with IEEE standard 802.3
• RMII interface only
• Station Management Signaling
• On-chip CAM (up to 16 destination addresses)
• Full-duplex mode with PAUSE feature
• Long/short packet modes
• PAD generation
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W90N745CD/W90N745CDG
DMA Controller
• 2-channel general DMA for memory-to-memory data transfers without CPU intervention
• Initialed by a software or external DMA request
• Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers
• 4-data burst mode
UART
• Four UART (serial I/O) blocks with interrupt-based operation
• Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive
• Programmable baud rates
• 1, ½ or 2 stop bits
• Odd or even parity
• Break generation and detection
• Parity, overrun and framing error detection
• X16 clock mode
• UART1 supports Bluetooth, and UART2 supports IrDA1.0 SIR
Timers
• Two programmable 24-bit timers with 8-bit pre-scaler
• One programmable 20 bit with selectable additional 8-bit prescaler watchdog timer
• One-shot mode, periodical mode or toggle mode operation
Programmable I/Os
• 31 programmable I/O ports
• Pins individually configurable to input, output or I/O mode for dedicated signals
• I/O ports are configurable for multiple functions
Advanced Interrupt Controller
• 24 interrupt sources, including 4 external interrupt sources
• Programmable normal or fast interrupt mode (IRQ, FIQ)
• Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources
• Programmable as either low-active or high-active for 4 external interrupt sources
• Priority methodology is encoded to allow for interrupt daisy-chaining
• Automatically mask out the lower priority interrupt during interrupt nesting
Publication Release Date: September 22, 2006
- 3 - Revision A2
W90N745CD/W90N745CDG
USB Host Controller
• USB 1.1 compliant
• Compatible with Open HCI 1.0 specification
• Supports low-speed and full speed devices
• Build-in DMA for real time data transfer
• Two on-chip USB transceivers with one optionally shared with USB device controller
USB Device Controller
• USB 1.1 compliant
• Support four USB endpoints including one control endpoint and 3 configurable endpoints for rich
USB functions
Two PLLs
• The external clock can be multiplied by on-chip PLL to provide high frequency system clock
• The input frequency range is 3-30MHz; 15MHz is preferred.
• One PLL for both CPU and USB host/device controller
• One PLL for audio I²S 12.288/16.934MHz clock source
• Programmable clock frequency
4-Channel PWM
• Four 16-bit timers with PWM
• Two 8-bit pre-scalers & Two 4-bit dividers
• Programmable duty control of output waveform (PWM)
• Auto reload mode or one-shot pulse mode
• Dead-zone generator
2
C Master
I
2
• 2-channel I
• Compatible with Philips I
• Support multi master operation
• Clock stretching and wait state generation
• Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer
• Software programmable acknowledge bit
• Arbitration lost interrupt, with automatic transfer cancellation
C
2
C standard, support master mode only
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus busy detection
- 4 -
W90N745CD/W90N745CDG
• Supports 7 bit addressing mode
2
• Software mode I
Universal Serial Interface (USI)
• 1-channel USI
• Support USI (Microwire/SPI) master mode
• Full duplex synchronous serial data transfer
• Variable length of transfer word up to 32 bits
• Provide burst mode operation, transmit/receive can be executed up to four times in one transfer
• MSB or LSB first data transfer
• Rx and Tx on both rising or falling edge of serial clock independently
• Two slave/device select lines
• Fully static synchronous design with one clock domain
2-Channel AC97/I²S Audio Codec Host Interface
C
• AHB master port and an AHB slave port are offered in audio controller.
• Always 8-beat incrementing burst
• Always bus lock when 8-beat incrementing burst
• When reach middle and end address of destination address, a DMA_IRQ is requested to CPU
automatically
KeyPad Scan Interface
• Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4x8 array without auxiliary
component
• Programmable debounce time
• One or two keys scan with interrupt and three keys reset function.
• Wakeup CPU from IDEL/Power Down mode
PS2 Host Interface
• APB slave consisted of PS2 protocol.
• Connect IBM keyboard or bar-code reader through PS2 interface.
• Provide hardware scan code to ASCII translation
Publication Release Date: September 22, 2006
- 5 - Revision A2
W90N745CD/W90N745CDG
Power management
• Programmable clock enables for individual peripheral
• IDLE mode to halt ARM core and keep peripheral working
• Power-Down mode to stop all clocks included external crystal oscillator.
• Exit IDLE by all interrupts
y Exit Power-Down by keypad,USB device and external interrupts
Operation Voltage Range
• 3.0 ~ 3.6 V for IO buffer
• 1.62 ~ 1.98 V for core logic
Operation Temperature Range
• TBD
Operating Frequency
• Up to 80 MHz
Package Type
• 128-pin LQFP
- 6 -
3. PIN DIAGRAM
W90N745CD/W90N745CDG
Figure 3.1 Pin Diagram
Publication Release Date: September 22, 2006
- 7 - Revision A2
W90N745CD/W90N745CDG
4. PIN ASSIGNMENT
Table 4.1 W90N745 Pins Assignment
PIN NAME 128-PIN LQFP
Clock & Reset ( 3 pins )
EXTAL (15M) 40
XTAL (15M) 41
nRESET 25
JTAG Interface ( 5 pins )
TMS 33
TDI 34
TDO 35
TCK 36
nTRST 37
External Bus Interface ( 53 pins )
A [20:0] 89-86,84-82,80-77,75-71,69-65
D [15:0] 110-111,113-116,118-122,124-128
nWBE [1;0] /
SDQM [1:0]
nSCS [1:0] 100,99
nSRAS 101
nSCAS 102
MCKE 98
nSWE 106
MCLK 104
nWAIT /
GPIO [30] /
nIRQ [3]
nBTCS 97
nECS [3:0] 90,92-94
nOE 95
108,107
96
- 8 -
W90N745CD/W90N745CDG
Table 4.1 W90N745 Pins Assignment, continued
PIN NAME 128-PIN LQFP
Ethernet Interface ( 10 pins )
PHY_MDC /
GPIO [29] /
KPROW [1]
PHY_MDIO /
GPIO [28] /
KPROW [0]
PHY_TXD [1:0] /
GPIO [27:26] /
KPCOL [7:6]
PHY_TXEN /
GPIO [25] /
KPCOL [5]
PHY_REFCLK /
GPIO [24] /
KPCOL [4]
PHY_RXD [1:0] /
GPIO [23:22] /
KPCOL [3:2]
PHY_CRSDV /
GPIO [21] /
KPCOL [1]
PHY_RXERR /
GPIO [20] /
KPCOL [0]
AC97/I²S/PWM/UART3
AC97_nRESET /
I²S_MCLK /
GPIO [0] /
nIRQ [2] /
USB_PWREN
64
63
62,60
59
58
57,55
54
53
( 5 pins )
44
Publication Release Date: September 22, 2006
- 9 - Revision A2
W90N745CD/W90N745CDG
Table 4.1 W90N745 Pins Assignment, continued
PIN NAME 128-PIN LQFP
AC97/I²S/PWM/UART3
AC97_DATAI /
I²S_DATAI /
PWM [0] /
DTR3 /
GPIO [1]
AC97_DATAO /
I²S_DATAO /
PWM [1] /
DSR3 /
GPIO [2]
AC97_SYNC /
I²S_LRCLK /
PWM [2] /
TXD3 /
GPIO [3]
AC97_BITCLK /
I²S_BITCLK /
PWM [3] /
RXD3
GPIO [4]
USB Interface ( 4 pins )
DP0 7
DN 0 6
DP1 2
DN1 3
Miscellaneous ( 7 pins )
nIRQ [1] /
GPIO [17] /
USB_OVRCUR
nIRQ [0] /
GPIO [16]
nWDOG /
GPIO [15] /
USB_PWREN
TEST 26
( 5 pins )
45
46
47
48
32
31
38
- 10 -
W90N745CD/W90N745CDG
Table 4.1 W90N745 Pins Assignment, continued
PIN NAME 128-PIN LQFP
I2C/USI(SPI/MW)
SCL0 /
SFRM /
TIMER0 /
GPIO [11]
SDA0 /
SSPTXD /
TIMER1 /
GPIO [12]
SCL1 /
SCLK /
GPIO [13] /
KPROW [3]
SDA1 /
SSPRXD /
GPIO [14] /
KPROW [2]
UART0/UART1/UART2/PS2 ( 6 pins )
TXD0 /
GPIO [5]
RXD0 /
GPIO [6]
TXD1 /
GPIO [7]
RXD1 /
GPIO [8]
CTS1 /
TXD2(IrDA) /
PS2_CLK /
GPIO [9]
RTS1 /
RXD2(IrDA) /
PS2_DATA /
GPIO [10]
( 4 pins )
17
18
19
20
10
11
12
13
14
15
Publication Release Date: September 22, 2006
- 11 - Revision A2
W90N745CD/W90N745CDG
Table 4.1 W90N745 Pins Assignment, continued
PIN NAME 128-PIN LQFP
XDMA ( 2 pins )
nXDREQ /
GPIO [19] /
nXDACK /
GPIO [18] /
Power/Ground ( 36 pins )
VDD18 21,43,49,85,112
VSS18 22,50,81,109
VDD33 9,23,42,61,76,103,117
VSS33 16,24,39,56,70,91,105,123
USBVDD 1,8
USBVSS 4,5
PLLVDD18 27,30
PLLVSS18 28,29
51
52
- 12 -
W90N745CD/W90N745CDG
5. PIN DESCRIPTION
Table 5.1 W90N745 Pins Description
PIN NAME IO TYPE DESCRIPTION
Clock & Reset
EXTAL (15M) I 15MHz External Clock / Crystal Input
XTAL (15M) O 15MHz Crystal Output
nRESET IS System Reset, active-low
JTAG Interface
TMS IUS JTAG Test Mode Select, internal pull-up with 70K ohm
TDI IUS JTAG Test Data in, internal pull-up with 70K ohm
TDO O JTAG Test Data out
TCK IDS JTAG Test Clock, internal pull-down with 58K ohm
nTRST IUS JTAG Reset, active-low, internal pull-up with 70K ohm
External Bus Interface
A [20:18] O Address Bus (MSB) of external memory and IO devices.
A [17:0] IOS Address Bus of external memory and IO devices.
D [15:0] IOS Data Bus (LSB) of external memory and IO device.
nWBE [1:0] /
SDQM [1:0]
nSCS [1:0] O SDRAM chip select for two external banks, active-low.
nSRAS O Row Address Strobe for SDRAM, active-low.
nSCAS O Column Address Strobe for SDRAM, active-low.
MCKE O SDRAM Clock Enable, active-high
nSWE O SDRAM Write Enable, active-low
MCLK O System Master Clock Out, SDRAM clock, output with slew-rate control
nWAIT /
GPIO[30] /
nIRQ3
nBTCS O ROM/Flash Chip Select, active-low.
nECS [3:0] IO External I/O Chip Select, active-low.
nOE O ROM/Flash, External Memory Output Enable, active-low.
IOS
IUS
Write Byte Enable for specific device (nECS [1:0]).
Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low.
External Wait, active-low. This pin indicates that the external devices need
more active cycle during access operation.
General Programmable In/Out Port GPIO[30]. If memory and IO devices in EBI
do not need wait request, it can be configured as GPIO[30] or nIRQ3.
Publication Release Date: September 22, 2006
- 13 - Revision A2
W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, continued
PIN NAME IO TYPE DESCRIPTION
Ethernet Interface
PHY_MDC /
GPIO [29] /
KPROW [1]
PHY_MDIO /
GPIO [28] /
KPROW [0]
PHY_TXD [1:0] /
GPIO [27:26] /
KPCOL [7:6]
PHY_TXEN /
GPIO [25] /
KPCOL [5]
PHY_REFCLK /
GPIO [24] /
KPCOL [4]
PHY_RXD [1:0] /
GPIO [23:22] /
KPCOL [3:2]
PHY_CRSDV /
GPIO [21] /
KPCOL [1]
PHY_RXERR /
GPIO [20] /
KPCOL [0]
IOU
IO
IOU
IOU
IOS
IOS
IOS
IOS
RMII Management Data Clock for Ethernet. It is the reference clock of MDIO.
Each MDIO data will be latched at the rising edge of MDC clock.
General Programmable In/Out Port [29]
Keypad ROW[1] scan output.
RMII Management Data I/O for Ethernet. It is used to transfer RMII control and
status information between PHY and MAC.
General Programmable In/Out Port [28]
Keypad ROW[0] scan output.
2-bit Transmit Data bus for Ethernet.
General programmable In/Out Port [27:26]
Keypad column input [7:6], active low
PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble
and shall remain asserted while all di-bits to be transmitted are presented. Of
course, it is synchronized with PHY_REFCLK.
General Programmable In/Out Port [25]
Keypad column input [5], active low
Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35%
duty cycle at high or low state.
General Programmable In/Out port [24]
Keypad column input [4], active low
2-bit Receive Data bus for Ethernet.
General Programmable In/Out Port [23:22]
Keypad column input [3:2], active low
Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be
asserted by PHY when the receive medium is non-idle. Loss of carrier shall
result in the de-assertion of PHY_CRSDV synchronous to the cycle of
PHY_REFCLK, and only on 2-bit receive data boundaries.
General Programmable In/Out port [21]
Keypad column input [1], active low
Receive Data Error for Ethernet. It indicates a data error detected by PHY.The
assertion should be lasted for longer than a period of PHY_REFCLK. When
PHY_RXERR is asserted, the MAC will report a CRC error.
General programmable In/Out port [20]
Keypad column input [0], active low
- 14 -
W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, continued
PIN NAME IO TYPE DESCRIPTION
AC97/I²S/PWM/UART3
AC97_nRESET /
I²S_MCLK /
GPIO [0] /
nIRQ [2] /
USB_PWREN
AC97_DATAI /
I²S_DATAI /
PWM [0] /
DTR3 /
GPIO [1]
AC97_DATAO /
I
²S_DATAO /
PWM [1] /
DSR3 /
GPIO [2]
AC97_SYNC /
I²S_LRCLK /
PWM [2] /
TXD3 /
GPIO [3]
AC97_BITCLK /
I
²S_BITCLK /
PWM [3] /
RXD3 /
GPIO [4]
USB Interface
DP0 IO Differential Positive USB IO signal
DN0 IO Differential Negative USB IO signal
DP1 IO Differential Positive USB IO signal
DN1 IO Differential Negative USB IO signal
Miscellaneous
nIRQ [1:0] /
GPIO [17:16] /
USB_OVRCUR
nWDOG /
GPIO [15] /
USB_PWREN
TEST IDS This test pin must be short to ground or left unconnected
IOU
IOU
IOU
IOU
IOS
IOU
IOU
AC97 CODEC Host Interface RESET Output.
I²S CODEC Host Interface System Clock Output.
General Purpose In/Out port [0]
External interrupt request.
USB host power enable output
AC97 CODEC Host Interface Data Input.
I²S CODEC Host Interface Data Input.
PWM Channel 0 output.
Data Terminal Ready for UART3.
General Purpose In /Out port [1]
AC97 CODEC Host Interface Data Output.
²S CODEC Host Interface Data Output.
I
PWM Channel 1 output.
Data Set Ready for UART3.
General Purpose In/Out port [2]
AC97 CODEC Host Interface Synchronous Pulse Output.
I²S CODEC Host Interface Left/Right Channel Select Clock.
PWM Channel 2 output.
Transmit Data for UART3.
General Purpose In/Out port [3]
AC97 CODEC Host Interface Bit Clock Input.
I²S CODEC Host Interface Bit Clock.
PWM Channel 3 output.
Receive Data for UART3.
General Purpose In/Out port [4].
External Interrupt Request
General Purpose I/O
nIRQ1 is used as USB host over-current detection input
Watchdog Timer Timeout Flag and Keypad 3-keys reset output, active low
General Purpose In/output
USB host power switch enable output
Publication Release Date: September 22, 2006
- 15 - Revision A2
W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, continued
PIN NAME IO TYPE DESCRIPTION
I2C/USI
SCL0 /
SFRM /
TIMER0 /
GPIO [11]
SDA0 /
SSPTXD /
TIMER1 /
GPIO [12]
SCL1 /
SCLK /
GPIO [13] /
KPROW [3]
SDA1 /
SSPRXD /
GPIO [14] /
KPROW [2]
UART0/UART1/UART2
TXD0 /
GPIO [5]
RXD0 /
GPIO [6]
TXD1 /
GPIO [7]
RXD1 /
GPIO [8]
CTS1/
TXD2(IrDA) /
PS2_CLK /
GPIO [9]
RTS1/
RXD2(IrDA) /
PS2_DATA /
GPIO [10]
XDMA
nXDREQ /
GPIO [19] /
nXDACK /
GPIO [18] /
IOU
IOU
IOU
IDU
IOU
IOU
IOU
IOU
IOU
IOU
IO
IO
I2C Serial Clock Line 0.
USI Serial Frame.
Timer0 time out output.
General Purpose In/Out port [11].
I2C Serial Data Line 0
USI Serial Transmit Data
Timer1 time out output
General Purpose In/Out port [12]
I2C Serial Clock Line 1
USI Serial Clock
General Purpose In/Out port [13]
Keypad row scan output [3]
I2C Serial Data Line 1
USI Serial Receive Data
General Purpose In/Out port [14]
Keypad scan output [2]
UART0 Transmit Data.
General Purpose In/Out [5]
UART0 Receive Data.
General Purpose In/Out [6]
UART1 Transmit Data.
General Purpose In/Out [7]
UART1 Receive Data.
General Purpose In/Out [8]
UART1 Clear To Send for Bluetooth application
UART2 Transmit Data supporting SIR IrDA.
PS2 Interface Clock Input/Output
General Purpose In/Out [9]
UART1 Request To Send for Bluetooth application
UART2 Receive Data supporting SIR IrDA.
PS2 Interface Bi-Directional Data Line.
General Purpose In/Out [10]
External DMA Request.
General Purpose In/Out [19]
External DMA Acknowledgement.
General Purpose In/Out [18]
- 16 -
W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, continued
PIN NAME IO TYPE DESCRIPTION
Power/Ground
VDD18 P Core Logic power (1.8V)
VSS18 G Core Logic ground (0V)
VDD33 P IO Buffer power (3.3V)
VSS33 G IO Buffer ground (0V)
USBVDD P USB power (3.3V)
USBVSS G USB ground (0V)
DVDD18 P PLL Digital power (1.8V)
DVSS18 G PLL Digital ground (0V)
AVDD18 P PLL Analog power (1.8V)
AVSS18 G PLL Analog ground (0V)
Publication Release Date: September 22, 2006
- 17 - Revision A2
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List
PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3
USB1.1 Host/Device Interface
1 USBVDD
2 DP1
3 DN1
4 USBVSS
5 USBVSS
6 DN0
7 DP0
8 USBVDD
9 VDD33
10 GPIO[5]
11 GPIO[6]
12 GPIO[7]
13 GPIO[8]
14 GPIO[9]
15 GPIO[10]
16 VSS33
USBVDD - - -
DP1 - - -
DN1 - - -
USBVSS - - -
USBVSS - - -
DN0 - - -
DP0 - - -
USBVDD - - -
VDD33 - - -
UART[2:0]/PS2 Interface
GPIO[5] UART_TXD0 - -
GPIO[6] UART_RXD0 - -
GPIO[7] UART_TXD1 - -
GPIO[8] UART_RXD1 - -
GPIO[9] UART_TXD2 UART_CTS1 PS2_CLK
GPIO[10] UART_RXD2 UART_RTS1 PS2_DATA
VSS33 - - -
I2C/USI Interface
17 GPIO[11]
18 GPIO[12]
19 GPIO[13]
20 GPIO[14]
21 VDD18
22 VSS18
23 VDD33
24 VSS33
25 nRESET
26 TEST
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
VDD18 - - -
VSS18 - - -
VDD33 - - -
VSS33 - - -
System Reset & TEST
nRESET - - -
TEST - - -
I2C_SCL0
2
C_SDA0
I
I2C_SCL1
I2C_SDA1
SSP_FRAM TIMER0
SSP_TXD TIMER1
SSP_SCLK KPI_ROW[3]
SSP_RXD KPI_ROW[2]
- 18 -
Table 5.2 W90N745 128-pin LQFP Multi-function List, continued
PLL Power/Ground
W90N745CD/W90N745CDG
27 PLL_VDD18
28 PLL_VSS18
29 PLL_VSS18
30 PLL_VDD18
31 GPIO[16]
32 GPIO[17]
33 TMS
34 TDI
35 TDO
36 TCK
37 nTRST
38 GPIO[15]
39 VSS33
PLL_VDD18 - - -
PLL_VSS18 - - PLL_VSS18 - - PLL_VDD18 - - -
External IRQ[1:0]/USB Over Current
GPIO[16] nIRQ [0] - -
GPIO[17] nIRQ [1] USB_OVRCUR -
JTAG Interface
TMS - - -
TDI - - -
TDO - - -
TCK - - -
nTRST - - -
WatchDog/USB Power Enable
GPIO[15] nWDOG USB_PWREN -
VSS33 - - -
System Clock
40 EXTAL(15M)
41 XTAL(15M)
42 VDD33
43 VDD18
EXTAL(15M) - - -
XTAL(15M) - - -
VDD33 - - -
VDD18 - - -
Publication Release Date: September 22, 2006
- 19 - Revision A2
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List, continued
PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3
AC97/I²S/PWM/UART3 Interface
AC97_nRESET
44 GPIO[0]
45 GPIO[1]
46 GPIO[2]
47 GPIO[3]
48 GPIO[4]
49 VDD18
50 VSS18
51 GPIO[19]
52 GPIO[18]
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
VDD18
VSS18 - - -
XDMAREQ
GPIO[19] nXDREQ - -
GPIO[18] nXDACK - -
Ethernet RMII/KeyPad Interface
or
²SMCLK
I
AC97_DATAI
or
²SDATAI
I
AC97_DATAO
or
²SDATAO
I
AC97_SYNC
or
²SLRCLK
I
AC97_BITCLK
or
²SBITCLK
I
-
nIRQ [2] USB_PWREN
PWM0 UART_DTR3
PWM1 UART_DSR3
PWM2 UART_TXD3
PWM3 UART_RXD3
- -
53 GPIO[20]
54 GPIO[21]
55 GPIO[22]
56 VSS33
57 GPIO[23]
58 GPIO[24]
59 GPIO[25]
60 GPIO[26]
61 VDD33
62 GPIO[27]
63 GPIO[28]
64 GPIO[29]
GPIO[20] PHY_RXERR KPI_COL[0] -
GPIO[21] PHY_CRSDV KPI_COL[1] -
GPIO[22] PHY_RXD[0] KPI_COL[2] -
VSS33 - - -
GPIO[23] PHY_RXD[1] KPI_COL[3] -
GPIO[24] PHY_REFCLK KPI_COL[4] -
GPIO[25] PHY_TXEN KPI_COL[5] -
GPIO[26] PHY_TXD[0] KPI_COL[6] -
VDD33 - - -
GPIO[27] PHY_TXD[1] KPI_COL[7] -
GPIO[28] PHY_MDIO KPI_ROW[0]
GPIO[29] PHY_MDC KPI_ROW[1]
- 20 -
Table 5.2 W90N745 128-pin LQFP Multi-function List, continued
W90N745CD/W90N745CDG
PIN
NO.
65 A[0]
66 A[1]
67 A[2]
68 A[3]
69 A[4]
70 VSS33
71 A[5]
72 A[6]
73 A[7]
74 A[8]
75 A[9]
76 VDD33
77 A[10]
78 A[11]
DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3
Memory Address/Data/Control
A[0] - - -
A[1] - - -
A[2] - - -
A[3] - - -
A[4] - - -
VSS33 - - -
A[5] - - -
A[6] - - -
A[7] - - -
A[8] - - -
A[9] - - -
VDD33 - - -
A[10] - - -
A[11] - - -
79 A[12]
80 A[13]
81 VSS18
82 A[14]
83 A[15]
84 A[16]
85 VDD18
86 A[17]
87 A[18]
88 A[19]
89 A[20]
90 nECS[3]
91 VSS33
A[12] - - -
A[13] - - -
VSS18 - - -
A[14] - - -
A[15] - - -
A[16] - - -
VDD18 - - -
A[17] - - -
A[18] - - -
A[19] - - -
A[20] - - -
nECS[3] - - -
VSS33 - - -
Publication Release Date: September 22, 2006
- 21 - Revision A2
Table 5.2 W90N745 128-pin LQFP Multi-function List, continued
W90N745CD/W90N745CDG
PIN
NO.
92 nECS[2]
93 nECS[1]
94 nECS[0]
95 nOE
96 nWAIT
97 nBTCS
98 MCKE
99 nSCS[0]
100 nSCS[1]
101 nSRAS
102 nSCAS
103 VDD33
104 MCLK
105 VSS33
106 nSWE
DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3
Memory Address/Data/Control
nECS[2] - - -
nECS[1] - - -
nECS[0] - - -
nOE - - -
GPIO[30] nWAIT nIRQ [3] -
nBTCS - - -
MCKE - - -
nSCS[0] - - -
nSCS[1] - - -
nSRAS - - -
nSCAS - - -
VDD33 - - -
MCLK - - -
VSS33 - - -
nSWE - - -
107 nWBE/SDQM[0]
108 nWBE/SDQM[1]
109 VSS18
110 D[15]
111 D[14]
112 VDD18
113 D[13]
114 D[12]
115 D[11]
116 D[10]
117 VDD33
118 D[9]
119 D[8]
120 D[7]
nWBE or SDQM[0]
nWBE or SDQM[1]
VSS18 - - -
D[15] - - -
D[14] - - -
VDD18 - - -
D[13] - - -
D[12] - - -
D[11] - - -
D[10] - - -
VDD33 - - -
D[9] - - -
D[8] - - -
D[7] - - -
- 22 -
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List, continued
PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3
Memory Address/Data/Control
121 D[6]
122 D[5]
123 VSS33
124 D[4]
125 D[3]
126 D[2]
127 D[1]
128 D[0]
D[6] - - -
D[5] - - -
VSS33 - - -
D[4] - - -
D[3] - - -
D[2] - - -
D[1] - - -
D[0] - - -
Publication Release Date: September 22, 2006
- 23 - Revision A2
W90N745CD/W90N745CDG
6. FUNCTIONAL DESCRIPTION
6.1 ARM7TDMI CPU CORE
The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of generalpurpose 32-bit microprocessors, which offer high performance for very low power consumption. The
architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set
Computers. Pipelining is employed so that all parts of the processing and memory systems can operate
continuously. The high instruction throughput and impressive real-time interrupt response are the major
benefits.
The ARM7TDMI CPU core has two instruction sets:
(1) The standard 32-bit ARM set
(2) A 16-bit THUMB set
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core
while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit
registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent
interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding
32-bit ARM instruction with the same effect on the processor model.
ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 sets are visible; the other registers
are used to speed up exception processing. All the register specified in ARM instructions can address
any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt,
memory aborts, attempted execution of an undefined instruction and software interrupts.
A[31:0]
Address Register
PC Bus
Register Bank
(31 x 32-bit registers)
(6 status registers)
ALU Bus
A Bus
Address
Incrementer
32 x8 Multiplier
Barrel Shifter
32-bit ALU
Incrementer Bus
B Bus
Thumb Instruction Decoder
Scan Control
Instruction Decoder
Control Logic
Instruction Pipeline
Read Data Register
Writer Data
Register
D[31:0]
Figure 6.1.1 ARM7TDMI CPU Core Block Diagram
- 24 -
W90N745CD/W90N745CDG
6.2 System Manager
6.2.1 Overview
The W90N745 system manager has the following functions.
y System memory map
y Data bus connection with external memory
y Product identifier register
y Bus arbitration
y PLL module
y Clock select and power saving control register
y Power-On setting
6.2.2 System Memory Map
W90N745 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The
On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 – 0xFFFF_FFFF) and the OnChip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable
space:0x0000_0000~0x7FDF_FFFF if Cache ON; non-cacheable space:
0x8000_0000~0xFFDF_FFFF).
The size and location of each bank is determined by the register settings for “current bank base address
pointer” and “current bank size”. Please note that when setting the bank control registers, the address
boundaries of consecutive banks must not overlap.
Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You
can use bank control registers to assign a specific bank start address by setting the bank’s base pointer
(13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer <<
18” and the bank’s size is “current bank size”.
In the event of an access requested to an address outside any programmed bank size, an abort signal is
generated. The maximum accessible memory size of each external IO bank is 4M bytes (by word
format), and 64M bytes on each SDRAM bank.
Publication Release Date: September 22, 2006
- 25 - Revision A2
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