The W90N745 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which
designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static
design is particularly suitable for cost sensitive and power sensitive applications.
One 100/10 Mbit MAC of Ethernet controller is built-in to reduce total system cost.
The W90N745 also provides one USB 1.1 host controller, one USB 1.1 device controller, one
AC97/I²S controller, one 2-channel GDMA, four independent UARTs, one watchdog timer, two 24-bit
timers with 8-bit pre-scale, up to 31 programmable I/O ports, PS2 keyboard controller and an
advanced interrupt controller. The external bus interface (EBI) controller provides for SDRAM,
ROM/SRAM, flash memory and I/O devices. The system manager includes an internal 32-bit system
bus arbiter and a PLL clock controller.
With a wide range of serial communication and Ethernet interfaces, the W90N745 is suitable for
communication gateways as well as many other general purpose applications.
Publication Release Date: September 22, 2006
- 1 - Revision A2
W90N745CD/W90N745CDG
2. FEATURES
Architecture
• Fully 16/32-bit RISC architecture
• Little/Big-Endian mode supported
• Efficient and powerful ARM7TDMI core
• Cost-effective JTAG-based debug solution
External Bus Interface
• 8/16-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os
• Support for SDRAM
• Programmable access cycle (0-7 wait cycle)
• Four-word depth write buffer for SDRAM write data
RMII Management Data Clock for Ethernet. It is the reference clock of MDIO.
Each MDIO data will be latched at the rising edge of MDC clock.
General Programmable In/Out Port [29]
Keypad ROW[1] scan output.
RMII Management Data I/O for Ethernet. It is used to transfer RMII control and
status information between PHY and MAC.
General Programmable In/Out Port [28]
Keypad ROW[0] scan output.
2-bit Transmit Data bus for Ethernet.
General programmable In/Out Port [27:26]
Keypad column input [7:6], active low
PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble
and shall remain asserted while all di-bits to be transmitted are presented. Of
course, it is synchronized with PHY_REFCLK.
General Programmable In/Out Port [25]
Keypad column input [5], active low
Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35%
duty cycle at high or low state.
General Programmable In/Out port [24]
Keypad column input [4], active low
2-bit Receive Data bus for Ethernet.
General Programmable In/Out Port [23:22]
Keypad column input [3:2], active low
Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be
asserted by PHY when the receive medium is non-idle. Loss of carrier shall
result in the de-assertion of PHY_CRSDV synchronous to the cycle of
PHY_REFCLK, and only on 2-bit receive data boundaries.
General Programmable In/Out port [21]
Keypad column input [1], active low
Receive Data Error for Ethernet. It indicates a data error detected by PHY.The
assertion should be lasted for longer than a period of PHY_REFCLK. When
PHY_RXERR is asserted, the MAC will report a CRC error.
General programmable In/Out port [20]
Keypad column input [0], active low
DP0 IO Differential Positive USB IO signal
DN0 IO Differential Negative USB IO signal
DP1 IO Differential Positive USB IO signal
DN1 IO Differential Negative USB IO signal
Miscellaneous
nIRQ [1:0] /
GPIO [17:16] /
USB_OVRCUR
nWDOG /
GPIO [15] /
USB_PWREN
TEST IDS This test pin must be short to ground or left unconnected
IOU
IOU
IOU
IOU
IOS
IOU
IOU
AC97 CODEC Host Interface RESET Output.
I²S CODEC Host Interface System Clock Output.
General Purpose In/Out port [0]
External interrupt request.
USB host power enable output
AC97 CODEC Host Interface Data Input.
I²S CODEC Host Interface Data Input.
PWM Channel 0 output.
Data Terminal Ready for UART3.
General Purpose In /Out port [1]
AC97 CODEC Host Interface Data Output.
²S CODEC Host Interface Data Output.
I
PWM Channel 1 output.
Data Set Ready for UART3.
General Purpose In/Out port [2]
AC97 CODEC Host Interface Synchronous Pulse Output.
I²S CODEC Host Interface Left/Right Channel Select Clock.
PWM Channel 2 output.
Transmit Data for UART3.
General Purpose In/Out port [3]
AC97 CODEC Host Interface Bit Clock Input.
I²S CODEC Host Interface Bit Clock.
PWM Channel 3 output.
Receive Data for UART3.
General Purpose In/Out port [4].
External Interrupt Request
General Purpose I/O
nIRQ1 is used as USB host over-current detection input
Watchdog Timer Timeout Flag and Keypad 3-keys reset output, active low
General Purpose In/output
USB host power switch enable output
I2C Serial Clock Line 0.
USI Serial Frame.
Timer0 time out output.
General Purpose In/Out port [11].
I2C Serial Data Line 0
USI Serial Transmit Data
Timer1 time out output
General Purpose In/Out port [12]
I2C Serial Clock Line 1
USI Serial Clock
General Purpose In/Out port [13]
Keypad row scan output [3]
I2C Serial Data Line 1
USI Serial Receive Data
General Purpose In/Out port [14]
Keypad scan output [2]
UART0 Transmit Data.
General Purpose In/Out [5]
UART0 Receive Data.
General Purpose In/Out [6]
UART1 Transmit Data.
General Purpose In/Out [7]
UART1 Receive Data.
General Purpose In/Out [8]
UART1 Clear To Send for Bluetooth application
UART2 Transmit Data supporting SIR IrDA.
PS2 Interface Clock Input/Output
General Purpose In/Out [9]
UART1 Request To Send for Bluetooth application
UART2 Receive Data supporting SIR IrDA.
PS2 Interface Bi-Directional Data Line.
General Purpose In/Out [10]
External DMA Request.
General Purpose In/Out [19]
External DMA Acknowledgement.
General Purpose In/Out [18]
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W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, continued
PIN NAME IO TYPE DESCRIPTION
Power/Ground
VDD18 P Core Logic power (1.8V)
VSS18 G Core Logic ground (0V)
VDD33 P IO Buffer power (3.3V)
VSS33 G IO Buffer ground (0V)
USBVDD P USB power (3.3V)
USBVSS G USB ground (0V)
DVDD18 P PLL Digital power (1.8V)
DVSS18 G PLL Digital ground (0V)
AVDD18 P PLL Analog power (1.8V)
AVSS18 G PLL Analog ground (0V)
Publication Release Date: September 22, 2006
- 17 - Revision A2
W90N745CD/W90N745CDG
Table 5.2 W90N745 128-pin LQFP Multi-function List
The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of generalpurpose 32-bit microprocessors, which offer high performance for very low power consumption. The
architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set
Computers. Pipelining is employed so that all parts of the processing and memory systems can operate
continuously. The high instruction throughput and impressive real-time interrupt response are the major
benefits.
The ARM7TDMI CPU core has two instruction sets:
(1) The standard 32-bit ARM set
(2) A 16-bit THUMB set
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core
while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit
registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent
interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding
32-bit ARM instruction with the same effect on the processor model.
ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 sets are visible; the other registers
are used to speed up exception processing. All the register specified in ARM instructions can address
any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt,
memory aborts, attempted execution of an undefined instruction and software interrupts.
A[31:0]
Address Register
PC Bus
Register Bank
(31 x 32-bit registers)
(6 status registers)
ALU Bus
A Bus
Address
Incrementer
32 x8 Multiplier
Barrel Shifter
32-bit ALU
Incrementer Bus
B Bus
Thumb Instruction Decoder
Scan Control
Instruction Decoder
Control Logic
Instruction Pipeline
Read Data Register
Writer Data
Register
D[31:0]
Figure 6.1.1 ARM7TDMI CPU Core Block Diagram
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W90N745CD/W90N745CDG
6.2 System Manager
6.2.1 Overview
The W90N745 system manager has the following functions.
y System memory map
y Data bus connection with external memory
y Product identifier register
y Bus arbitration
y PLL module
y Clock select and power saving control register
y Power-On setting
6.2.2 System Memory Map
W90N745 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The
On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 – 0xFFFF_FFFF) and the OnChip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable
space:0x0000_0000~0x7FDF_FFFF if Cache ON; non-cacheable space:
0x8000_0000~0xFFDF_FFFF).
The size and location of each bank is determined by the register settings for “current bank base address
pointer” and “current bank size”. Please note that when setting the bank control registers, the address
boundaries of consecutive banks must not overlap.
Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You
can use bank control registers to assign a specific bank start address by setting the bank’s base pointer
(13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer <<
18” and the bank’s size is “current bank size”.
In the event of an access requested to an address outside any programmed bank size, an abort signal is
generated. The maximum accessible memory size of each external IO bank is 4M bytes (by word
format), and 64M bytes on each SDRAM bank.
Publication Release Date: September 22, 2006
- 25 - Revision A2
W90N745CD/W90N745CDG
0x7FFF_FFFF
512KB
(Fixed)
0x7F F8.0000
512KB
(Fixed)
0x7FF0 _0000
8KB
0x7 FE0_0000
EBI Space
RESERVED
RESERVED
RESERVED
RESERVED
External I/O Bank 3
256 KB - 4M B
External I/O Bank 2
256 KB - 4M B
External I/O Bank 1
256 KB - 4M B
External I/O Bank 0
256 KB - 4M B
0xFFFF_FFFF
512KB
(Fixed)
0xFFF8_0000
512KB
(Fixed)
0xFFF0_0000
8KB
0xFFE0_0000
EBI Space
On-Chip APB
Peripherals
On-Chip AHB
Peripherals
RESERVED
On-Chip RAM
4KB,4KB
External I/O Bank 3
256 KB - 4MB
External I/O Bank 2
256 KB - 4MB
External I/O Bank 1
256 KB - 4MB
External I/O Bank 0
256 KB - 4MB
0x0000 _0000
SDRAM Bank 1
2MB - 64MB
SDRAM Bank 0
2MB - 64MB
ROM/FLASH
256 KB - 4M B
Figure 6.2.1 System Memory Map
SDRAM Bank 1
2MB - 64M B
SDRAM Bank 0
2MB - 64M B
ROM/FLASH
256 KB - 4MB
0x8000_0000
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W90N745CD/W90N745CDG
Table 6.2.1 On-Chip Peripherals Memory Map
BASE ADDRESS DESCRIPTION
AHB Peripherals
0xFFF0_0000 Product Identifier Register (PDID)
0xFFF0_0004 Arbitration Control Register (ARBCON)
0xFFF0_0008 PLL Control Register 0(PLLCON0)
0xFFF0_000C Clock Select Register (CLKSEL)
0xFFF0_0010 PLL Control Register 1 (PLLCON1)
0xFFF0_0014
0xFFF0_0020 IRQ Wakeup Control Register (IRQWAKEUPCON)
0xFFF0_0024 IRQ Wakeup Flag Register (IRQWAKEFLAG)
0xFFF0_0028 Power Manager Control Register (PMCON)
0xFFF0_0030 USB Transceiver Control Register (USBTXRCON)
0xFFF0_1000 EBI Control Register (EBICON) Control Registers
0xFFF0_1004 ROM/FLASH (ROMCON) Control Registers
0xFFF0_1008 SDRAM bank 0 – 1 Control Registers
0xFFF0_1018 External I/O 0 – 3 Control Registers
0xFFF0_2000 Cache Controller Control Registers
0xFFF0_3000 Ethernet MAC Controller Control Registers
0xFFF0_4000 GDMA 0 – 1 Control Registers
0xFFF0_5000 USB Host Controller Control Registers
0xFFF0_6000 USB Device Controller Control Registers
0xFFF8_7000 Pulse Width Modulation (PWM) Control Registers
0xFFF8_8000 KeyPad Interface Control Register (KPI)
0xFFF8_9000 PS2 Control Registers
2
I
C-0 Control Registers
2
I
C-1 Control Registers
Publication Release Date: September 22, 2006
- 27 - Revision A2
W90N745CD/W90N745CDG
6.2.3 Address Bus Generation
The W90N745 address bus generation is depended on the required data bus width of each memory
bank. The data bus width is determined by DBWD bits in each bank’s control register.
The maximum accessible memory size of each external IO bank is 4M bytes.
Table 6.2.2 Address Bus Generation Guidelines
DATA BUS EXTERNAL ADDRESS PINS
WIDTH A [20:0]
8-bit
16-bit
A20 – A0
(Internal)
A21 – A1
(Internal)
MAXIMUM ACCESSIBLE MEMORY SIZE
2M bytes
2M half-words
6.2.4 Data Bus Connection with External Memory
6.2.4.1. Memory formats
The W90N745 can be configured as big endian or little endian mode by pull up or down the external data
bus D14 pin. If D14 is pull up, then it is a little endian mode, otherwise, it is a big endian mode.
Little endian
In little endian format, the lowest addressed byte in a word is considered the least significant byte of the
word and the highest addressed byte is the most significant. So the byte at address 0 of the memory
system connects to data lines 7 through 0.
For a word aligned address A, Figure 6.2.2 shows how the half-word at addresses A and A+2, and the
bytes at addresses A, A+1, A+2, and A+3 map on to each other when D14 pin is High.
15 14 13 12 11 10 9 87 65 43 21 0
Half-word at address A
Half-word at address A+2
Byte at address A+1Byte at address A
Byte at address A+3Byte at address A+2
Figure 6.2.2 Little endian addresses of bytes and half-words within half words
- 28 -
W90N745CD/W90N745CDG
Big endian
In Big endian format, the W90N745 stores the most significant byte of a word at the lowest numbered
byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory
system connects to data lines 31 through 24.
For a word aligned address A, Figure 6.2.3 shows how the half-word at addresses A and A+2, and the
bytes at addresses A, A+1, A+2, and A+3 map on to each other when the D14 pin is Low.
15 14 13 12 1110987654321 0
Half-word at address A
Half-word at address A+2
Byte at address A Byte at address A+1
Byte at address A+2Byte at address A+3
Figure 6.2.3 Big endian addresses of bytes and half-words within half words
6.2.4.2. Connection of External Memory with Various Data Width
The system diagram for W90N745 connecting with the external memory is shown in Figure 6.2.4. Below
tables (Table 6.2.3 through Table 6.2.14) show the program/data path between CPU register and the
external memory using little / big endian and word/half-word/byte access.
Figure 6.2.4 Address/Data bus connection with external memory
Publication Release Date: September 22, 2006
- 29 - Revision A2
W90N745CD/W90N745CDG
Figure 6.2.5 CPU registers Read/Write with external memory
Table 6.2.3 and Table 6.2.4
Using big-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0,4,8,C X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table 6.2.3 Word access write operation with Big Endian
ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
Table 6.2.8 Byte access read operation with Big Endian
ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
XD WIDTH HALF WORD BYTE
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
7 0
C
BAL BAU BA
7 0
C
7 0
C
7 0
D
7 0
D
15 8
D
7 0
D
7 0
D
7 0
D
XA
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
BAL BAL BA
AU UA XA
15 0
CD
15 0
CD
15 0
CD
7 0
D
7 0
D
Publication Release Date: September 22, 2006
- 33 - Revision A2
W90N745CD/W90N745CDG
Table 6.2.9 and Table 6.2.10
Using little-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0,4,8,C X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table 6.2.9 Word access write operation with little Endian
ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
Using little-endian and half-word access, Program/Data path between register and external memory.
HA = Address whose LSB is 0,2,4,6,8,A,C,E X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table 6.2.11 Half-word access write operation with little Endian
ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
XD Width Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
nWBE [1-0] /
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence 1st write 2nd write
31 0
ABCD
HA HA
31 0
CD CD
31 0
CD CD
HA HA HA+1
AA XA XA
15 0
CD
15 0
CD
31 0
CD CD
7 0
7 0
7 0
31 0
ABCD
31 0
CD CD
7 0
D
7 0
D
7 0
D
Table 6.2.12 Half-word access read operation with Little Endian
ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
XD Width Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
15 0
CD
HA HA
15 0
CD
15 0
CD
HA HA HA+1
15 0
XD
15 0
CD
15 0
CD
15 0
CD
C
C
C
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence 1st read 2nd read
AA XA XA
15 0
CD
15 0
CD
7 0
D
7 0
D
7 0
C
7 0
C
Publication Release Date: September 22, 2006
- 35 - Revision A2
W90N745CD/W90N745CDG
Table 6.2.13 and Table 6.2.14
Using little-endian and byte access, Program/Data path between register and external memory.
BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F
Table 6.2.13 Byte access write operation with little Endian
ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
XD Width Half Word Byte
Bit Number
CPU Reg Data
31 0
ABCD
31 0
ABCD
SA
Bit Number
SD
Bit Number
ED
XA
nWBE [1-0] /
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
BAL BAU BA
31 0
D D D D
7 0
D
BAL BAL BA
UA AU XA
15 0
X D
7 0
D
31 0
D D D D
15 8
D
15 0
D X
15 8
D
31 0
D D D D
7 0
D
7 0
D
7 0
D
Table 6.2.14 Byte access read operation with Little Endian
ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
XD Width Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
7 0
D
BAL BAU BA
7 0
D
7 0
D
7 0
C
7 0
C
7 0
C
7 0
D
7 0
D
7 0
D
XA
SDQM [1-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
BAL BAL BA
UA AU XA
15 0
CD
15 0
CD
15 0
CD
7 0
D
7 0
D
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W90N745CD/W90N745CDG
6.2.5 Bus Arbitration
The W90N745’s internal function blocks or external devices can request mastership of the system bus
and then hold the system bus in order to perform data transfers. Because the design of W90N745 bus
allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal
units or external devices simultaneously request bus mastership. When bus mastership is granted to an
internal function block or an external device, other pending requests are not acknowledged until the
previous bus master has released the bus.
W90N745 supports two priority modes, the Fixed Priority Mode and the Rotate Priority Mode,
depends on the ARBCON register PRTMOD bit setting.
6.2.5.1. Fixed Priority Mode
In Fixed Priority Mode (PRTMOD=0, default value), to facilitate bus arbitration, priorities are assigned to
each internal W90N745 function block. The bus controller arbitration requests for the bus mastership
according to these fixed priorities. In the event of contention, mastership is granted to the function block
with the highest assigned priority. These priorities are listed in Table 6.2.15.
W90N745 allows raising ARM Core priority to second if an unmasked interrupt occurred. If IPEN bit, Bit 1
of the Arbitration Control Register (ARBCON), is set to “0”, the priority of ARM Core is fixed to lowest.
If IPEN bit is set to “1” and if no unmasked interrupt request, then the ARM Core’s priority is still lowest
and the IPACT=0, Bit 2 of the Arbitration Control Register (ARBCON) ; If there is an unmasked
interrupt request, then the ARM Core’s priority is raised to first and IPACT=1.
If IPEN is set, an interrupt handler will normally clear IPACT at the end of the interrupt routine to allow an
alternate bus master to regain the bus; however, if IPEN is cleared, no additional action need be taken in
the interrupt handler. The IPACT bit can be read and written. Writing with “0”, the IPACT bit is cleared,
but it will be no effect as writing with “1”.
Table 6.2.15 Bus Priorities for Arbitration in Fixed Priority Mode
BUS FUNCTION BLOCK
PRIORITY IPACT = 0 IPEN = 1 AND IPACT = 1
1 (Highest) Audio Controller (AC97 & I²S) ARM Core
2 General DMA0 Audio Controller (AC97 & I²S)
3 General DMA1 General DMA0
4 EMC DMA General DMA1
5 USB Host EMC DMA
6 USB Device USB Host
7(Lowest) ARM Core USB Device
Publication Release Date: September 22, 2006
- 37 - Revision A2
W90N745CD/W90N745CDG
6.2.5.2. Rotate Priority Mode
In Rotate Priority Mode (PRTMOD=1), the IPEN and IPACT bits have no function (i.e. can be ignored).
W90N745 uses a round robin arbitration scheme ensures that all bus masters have equal chance to gain
the bus and that a retracted master does not lock up the bus.
6.2.6 Power Management
W90N745 provide three power management scenarios to reduce power consumption. The
peripherals’ clocks can be enabled / disabled individually by controlling the co-responding bit in
CLKSEL control register. Software can turn-off the unused modules’ clocks to saving the unnecessary
power consumption. It also provides idle and power-down modes to reduce power consumption.
Figure 6.2.6 W90N745 system clock generation diagram
- 38 -
W90N745CD/W90N745CDG
IDLE MODE
If the IDLE bit in Power Management Control Register (PMCON) is set, the ARM CORE clock source
will be halted, the ARM CORE will not go forward. The AHB or APB clocks still active except the clock
to cache controller and ARM are stopped. W90N745 will exit idle state when nIRQ or nFIQ from any
peripheral is revived; like keypad, timer overflow interrupts and so on. The memory controller can also
be forced to enter idle state if both MIDLE and IDLE bits are set. Software must switch SDRAM into
self-refresh mode before forcing memory to enter idle mode.
IDLE Period
FOUT
(PLL)
HCLK
idle_state
MCLK
(ARM)
HCLK
(cache)
HCLK
(memc)
Case1. IDLE=1, PD=0, MIDLE=0
Figure 6.2.7 Clock management for system idle mode
IDLE Period
FOUT
(PLL)
HCLK
idle_state
MCLK
(ARM)
HCLK
(cache)
HCLK
(memc)
Case2. IDLE=1, PD=0, MIDLE=1
Figure 6.2.8 Clock management for system and memory idle mode
Publication Release Date: September 22, 2006
- 39 - Revision A2
W90N745CD/W90N745CDG
Power Down Mode
This mode provides the minimum power consumption. When the W90N745 system is not working or
waiting an external event, software can write PD bit “1” to turn off all the clocks includes system crystal
oscillator to let ARM CORE enter sleep mode. In this state, all peripherals are also in sleep mode
since the clock source is stopped. W90N745 will exit power down state when nIRQ/nFIQ is detected.
W90N745 provides external interrupt nIRQ[1:0], keypad, and USB device interfaces to wakeup the
system clock.
65536 clocks
EXTAL
HCLK
idle _state
pd_state
HCLK
(cache)
Case3. IDLE=0, PD=1, MIDLE=0
wake up by pheripheral's
interrupts
Figure 6.2.9 Clock management for system power down mode and wake up
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W90N745CD/W90N745CDG
6.2.7 Power-On Setting
After power on reset, there are eight Power-On setting pins to configure W90N745 system configuration.
POWER-ON SETTING PIN
Internal System Clock Select D15
Little/Big Endian Mode Select D14
Boot ROM/FLASH Data Bus Width
Default: Pull-Down in Normal Operation D9
Default: Pull-Up in Normal Operation D8
D15 pin:Internal System Clock Select
If pin D15 is pull-down, the external clock from EXTAL pin is served as internal system clock.
If pin D15 is pull-up, the PLL output clock is used as internal system clock.
D14 pin:Little/Big Endian Mode Select
If pin D14 is pull-down, the external memory format is Big Endian mode.
If pin D14 is pull-up, the external memory format is Little Endian mode.
D [13:12] : Boot ROM/FLASH Data Bus Width
D [13:12]
D [13:12] BUS WIDTH
Pull-down Pull-down 8-bit
Pull-down Pull-up 16-bit
Pull-up Pull-down RESERVED
Pull-up Pull-up RESERVED
6.2.8 System Manager Control Registers Map
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
PDID 0xFFF0_0000 R Product Identifier Register 0xX090_0745
ARBCON 0xFFF0_0004 R/WArbitration Control Register 0x0000_0000
PLLCON0 0xFFF0_0008 R/WPLL Control Register 0 0x0000_2F01
W90N745 provides two clock generation options – crystal and oscillator. The external clock via
EXTAL(15M) Minput pin as the reference clock input of PLL module. The external clock can bypass the
PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’s output clock
for the internal system clock, D15 pin must be pull-up.
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
PLLCON
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
0xFFF0_0008 R/W
RESERVED
RESERVED PWDEN
PLL Control Register
0x0000_2F01
FBDV
7 6 5 4 3 2 1 0
FBDV OTDV INDV
BITS DESCRIPTION
[31:17] RESERVED -
Power down mode enable
[16] PWDEN
[15:7] FBDV
[6:5] OTDV
[4:0] INDV
0 = PLL is in normal mode (default)
1 = PLL is in power down mode
PLL VCO output clock feedback divider
Feedback Divider divides the output clock from VCO of PLL.
PLL output clock divider
OTDV [6:5] DIVIDED BY
0 0 1
0 1 2
1 0 2
PLL input clock divider
Input divider divides the input reference clock into the PLL.
1 1 4
- 44 -
W90N745CD/W90N745CDG
O
EXTAL
FIN
INDV[4:0]
FBDV[8:0]
Input Divider
(NR)
PFD
Feedback
Divider
(NF)
Charge
Pump
Figure 6.2.10 System PLL block diagram
The formula of output clock of PLL is:
NF1
FOUT = FIN
NR
∗∗
N
FOUT:Output clock of Output Divider
FIN:External clock into the Input Divider
NR:Input divider value (NR = INDV + 2)
NF:Feedback divider value (NF = FBDV + 2)
NO:Output divider value (NO = OTDV)
PLL
VCO
Output
Divider
(NO)
OTDV[1:0]
480MHz
FOUT
GP0
48MHz
Gen
Clock
Divider
&
Selector
CLKS[2:0]
USBCKS
1
0
0
1
ECLKS
USB
Module
Internal
System
Clock
Publication Release Date: September 22, 2006
- 45 - Revision A2
W90N745CD/W90N745CDG
Clock Select Register (CLKSEL)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
CLKSEL
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
UART3 UART2 UART1
15 14 13 12 11 10 9 8
USBCKS USBD GDMA RESERVED EMC RESERVED WDT
7 6 5 4 3 2 1 0
USBH TIMER UART ECLKS CLKS RESET
BITS DESCRIPTION
[31:29] RESERVED -
[28] PS2
[27] KPI
[26] RESERVED
[25] RESERVED
[24] USI
[23] UART3
[22] UART2
[21] UART1
0xFFF0_000C R/W
RESERVED PS2 KPI RESERVED SSP
PS2 controller clock enable bit
0 = Disable PS2 controller clock
1 = Enable PS2 controller clock
Keypad controller clock enable bit
0 = Disable keypad controller clock
1 = Enable keypad controller clock
-
-
USI controller clock enable bit
0 = Disable USI controller clock
1 = Enable USI controller clock
UART3 controller clock enable bit
0 = Disable UART3 controller clock
1 = Enable UART3 controller clock
UART2 controller clock enable bit
0 = Disable UART2 controller clock
1 = Enable UART2 controller clock
UART1 controller clock enable bit
0 = Disable UART1 controller clock
1 = Enable UART1 controller clock
Clock Select Register
2
I
C1 I2C0
0x1FFF_7FX8
RESERVEDPWM AC97
- 46 -
W90N745CD/W90N745CDG
Continued.
BITS DESCRIPTION
2
I
C1 controller clock enable bit
[20]
I
2
C1
0 = Disable I
1 = Enable I
2
I
C0 controller clock enable bit
[19]
I
2
C0
0 = Disable I
1 = Enable I
[18] RESERVED
-
PWM controller clock enable bit
[17] PWM
0 = Disable PWM controller clock
1 = Enable PWM controller clock
Audio Controller clock enable bit
[16] AC97
0 = Disable AC97 controller clock
1 = Enable AC97 controller clock
USB host/device 48MHz clock source Select bit
[15] USBCKS
0 = USB clock 48MHz input from internal PLL (480MHz/10)
1 = USB clock 48MHz input from external GPIO0 pin, this pin
direction must set to input.
USB device clock enable bit
[14] USBD
0 = Disable USB device controller clock
1 = Enable USB device controller clock
GDMA controller clock enable bit
[13] GDMA
0 = Disable GDMA clock
1 = Enable GDMA clock
[12] RESERVED
[11] RESERVED
-
-
EMC controller clock enable bit
[10] EMC
0 = Disable EMC controller clock
1 = Enable EMC controller clock
[9] RESERVED
-
WDT clock enable bit
[8] WDT
0 = Disable WDT counting clock
1 = Enable WDT counting clock
2
C1 controller clock
2
C1 controller clock
2
C0 controller clock
2
C0 controller clock
Publication Release Date: September 22, 2006
- 47 - Revision A2
W90N745CD/W90N745CDG
Continued.
BITS DESCRIPTION
USB host clock enable bit
[7] USBH
[6] TIMER
[5] UART0
[4] ECLKS
[3:1] CLKS
0 = Disable USB host controller clock
1 = Enable USB host controller clock
Timer clock enable bit
0 = Disable timer clock
1 = Enable timer clock
UART0 controller clock enable bit
0 = Disable UART0 controller clock
1 = Enable UART0 controller clock
External clock select
0 = External clock from EXTAL pin is used as system clock
1 = PLL output clock is used as system clock
After power on reset, the content of ECLKS is the Power-On
Setting value. You can program this bit to change the system clock
source.
PLL output clock select
CLKS [3:1] System clock
0 0 0 58.594 KHz*
0 0 1 24 MHz
0 1 0 48 MHz
0 1 1 60 MHz
1 0 0 80 MHz
1 0 1 RESERVED
1 1 0 RESERVED
1 1 1 RESERVED
[0] RESET
Note:
1. This values are based on PLL output(FOUT) is 480MHz.
2. When 24Mhz ~ 80MHz is selected, the ECLKS bit must be set to
1.
3. About 58.594KHz setting, two steps are needed. First, clear
ECLKS bit, and then clear CLKS.
Software Reset bit
This is a software reset control bit. Set logic 1 to generate an
internal reset pulse. This bit is auto-clear to logic 0 at the end of
the reset pulse.
- 48 -
W90N745CD/W90N745CDG
PLL Control Register 1(PLLCON1)
W90N745 provides extra PLL to provide 12.288/16.934 MHz clock source to Audio Controller. It uses the
same 15MHz crystal clock input source with system PLL mentioned above.
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
PLLCON1
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
0xFFF0_0010 R/W
RESERVED PWDEN1
PLL Control Register 1
RESERVED
FBDV1
0x0001_0000
7 6 5 4 3 2 1 0
FBDV1 OTDV1 INDV1
BITS DESCRIPTION
[31:17] RESERVED -
PLL1 power down enable
[16] PWDEN1
[15:7] FBDV1
[6:5] OTDV1
[4:0] INDV1
0 = PLL1 is in normal mode
1 = PLL1 is in power down mode (default)
PLL1 VCO output clock feedback divider
Feedback Divider divides the output clock from VCO of PLL1.
PLL1 output clock divider
OTDV1 [6:5] Divided by
0 0 1
0 1 2
1 0 2
1 1 4
PLL1 input clock divider
Input divider divides the input reference clock into the PLL1.
Publication Release Date: September 22, 2006
- 49 - Revision A2
INDV1[4:0]
EXTAL
FIN
Input Divider
(NR)
W90N745CD/W90N745CDG
PLL1
Charge
Pump
FBDV1[8:0]
PFD
Feedback
Divider
(NF)
Figure 6.2.11 Audio PLL block diagram
The formula of output clock of PLL is:
FOUT = FIN
NF1
∗∗
NONR
FOUT:Output clock of Output Divider
FIN:External clock into the Input Divider
NR:Input divider value (NR = INDV1 + 2)
NF:Feedback divider value (NF = FBDV1 + 2)
NO:Output divider value (NO = OTDV1)
VCO
Output
Divider
OTDV1[1:0]
480MHz
(NO)
FOUT
to Audio Controller
- 50 -
W90N745CD/W90N745CDG
I²S Clock Control Register (I²SCKCON)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
I²SCKCON
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
BITS DESCRIPTION
[31:9] RESERVED -
0xFFF0_0014 R/W
RESERVED
I²S PLL clock Control Register
RESERVED
RESERVED
PRESCALE
0x0000_0000
I
²SPLLEN
[8] I²SPLLEN
[7:0] PRESCALE
I²S PLL clock source enable
Set this bit will enable PLL1 clock output to audio I²S clock input.
1 = Enable PLL1 clock source for audio I²S
0 = Disable PLL1 clock source for audio I²S
The PLL1 is used by I²S, if in use, software can using this
prescaler to generate an appropriate clock nearly 12.288M or
16.934M. The clock is generated as below, and if PRESCALE =0,
the PLL_AUDIO is the same frequency as FOUT “PLL_AUDIO = PLL_FOUT/(PRESCALE +1)”
Publication Release Date: September 22, 2006
- 51 - Revision A2
W90N745CD/W90N745CDG
IRQ Wakeup Control Register (IRQWAKECON)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
IRQWAKECON
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
RESERVED
BITS DESCRIPTION
[31:6] RESERVED
0xFFF0_0020 R/W
RESERVED
IRQWAKEUPPOL
IRQ Wakeup Control Register
RESERVED
RESERVED
RESERVED
0x0000_0000
IRQWAKEUPEN
[5] IRQWAKEUPPOL[1]
[4] IRQWAKEUPPOL[0]
[3:2] RESERVED
[1] IRQWAKEUPEN[1]
[0] IRQWAKEUPEN[0]
nIRQ1 wake up polarity
1 = nIRQ1 is high level wake up
0 = nIRQ1 is low level wake up
nIRQ0 wake up polarity
1 = nIRQ0 is high level wake up
0 = nIRQ0 is low level wake up
nIRQ1 wake up enable bit
1 = nIRQ1 wake up enable
0 = nIRQ1 wake up disable
nIRQ0 wake up enable bit
1 = nIRQ0 wake up enable
0 = nIRQ0 wake up disable
- 52 -
W90N745CD/W90N745CDG
IRQ Wakeup Flag Register (IRQWAKEFLAG)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
IRQWAKEFLAG
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
This register is used to record the wakeup event, after clock recovery, software should check these flags
to identify which nIRQ is used to wakeup the system. And clear the flags in IRQ interrupt sevice routine.
0xFFF0_0024 R/W
RESERVED
RESERVED
RESERVED
RESERVED IRQWAKEFLAG
IRQ Wakeup Flag Register
0x0000_0000
BITS DESCRIPTION
[31:2] RESERVED -
nIRQ1 wake up flag
[1] IRQWAKEFLAG[1]
[0] IRQWAKEFLAG[0]
1 = chip is waked up by nIRQ1
0 = no active
nIRQ0 wake up flag
1 = chip is waked up by nIRQ0
0 = no active
Publication Release Date: September 22, 2006
- 53 - Revision A2
W90N745CD/W90N745CDG
e
e
p
e
s
E
Power Management Control Register (PMCON)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
PMCON
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
BITS DESCRIPTION
[31:3] RESERVED
[2] MIDLE
0xFFF0_0028 R/W
RESERVED MIDLE PD IDLE
Memory controller IDLE enable
Setting both MIDLE and IDLE bits HIGH will let memory controller
enter IDLE mode, the clock source of memory controller will be halted
while ARM CORE enter IDLE mode.
1=memory controller will be forced into IDLE mode, (clock of memory
controller will be halted), when IDLE bit is set.
0 = memory controller still active when IDLE bit is set.
NOTE: Software must let SDRAM enter self-refresh mode before
enable this function because SDRAM MCLK will be stopped.
Power Management Control Register
RESERVED
RESERVED
RESERVED
0x0000_0000
[1] PD
[0] IDLE
Power down enable
Setting this bit HIGH will let W90N745 enter power saving mode. Th
clock source 15M crystal oscillator and PLLs are stopped to generat
clock. User can use nIRQ[3:0], keypad and external RESET to wakeu
W90N745.
1 = Enable power down
0 = Disable
IDLE mode enable
Setting this bit HIGH will let ARM Core enter power saving mode. Th
peripherals can still keep working if the clock enable bit in CLKSEL i
set. Any nIRQ or nFIQ to ARM Core will let ARM CORE to exit IDL
state.
1 = IDLE mode
0 = Disable
- 54 -
W90N745CD/W90N745CDG
USB Transceiver Control Register (USBTXRCON)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
USBTXRCON
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
BITS DESCRIPTION
[31:1] RESERVED -
[0]
0xFFF0_0030 R/W
RESERVED USBHnD
USBHnD[0]: USB transceiver control
There are two USB1.1 built-in transceivers for data transmission. One
USBHnD
is dedicated for USB host and the other is shared with USB device.
Software can program this bit to switch the transceiver path.
1 = HOST
0 = Device
USB Transceiver Control Register
RESERVED
RESERVED
RESERVED
0x0000_0000
Publication Release Date: September 22, 2006
- 55 - Revision A2
W90N745CD/W90N745CDG
6.3 External Bus Interface
6.3.1 EBI Overview
W90N745 supports External Bus Interface (EBI), which controls the access to the external memory
(ROM/FLASH, SDRAM) and External I/O devices. The EBI has seven chip selects to select one
ROM/FLASH bank, two SDRAM banks, and four External I/O banks.The address bus is 21 bits. It
supports 8-bit, 16-bit external data bus width for each bank.
The EBI has the following functions:
y SDRAM controller
y EBI control register
y ROM/FLASH interface
y External I/O interface
y External bus mastership
6.3.2 SDRAM Controller
The SDRAM controller module within W90N745 contains configuration registers 、 timing control
registers、common control register and other logic to provide 8、16 bits SDRAM interface with a single
8、16 bits SDRAM device or two 8-bit devices wired to give a 16-bit data path. The maximum size of
each bank is 64M bytes, and maximum memory size can span up to 128MB.
The SDRAM controller has the following features:
y Supports up to 2 external SDRAM banks
y Maximum size of each bank is 64M bytes
y 8、16-bit data interface
y Programmable CAS Latency: 1、2 and 3
y Fixed Burst Length: 1
y Sequential burst type
y Auto Refresh Mode and Self Refresh Mode
y Adjustable Refresh Rate
y Power up sequence
- 56 -
W90N745CD/W90N745CDG
6.3.2.1. SDRAM Components Supported
Table 6.3.1 SDRAM supported by W90N745
SIZE TYPE BANKS ROW ADDRESSING COLUMN ADDRESSING
16M bits
64M bits
128M bits
256M bits
AHB Bus Address Mapping to SDRAM Bus
Note: * indicates the signal is not used; ** indicates the signal is fixed at logic 0 and is not used;
The HADDR prefixes have been omitted on the following tables.
A14 ~ A0 are the Address pins of the W90N745 EBI interface;
256M 32Mx8 13x10 R 9 10 222120191817161514 13 12 11
C 9 10
(BS1)
A13
(BS0)
**
** 9 ** 9*
A12A11A10A9 A8 A7 A6A5 A4 A3 A2 A1 A0
9
** 9*
2120191817161514 13 12 11
9*
9* 21*
2120191817161514 13 12 11
9*
9* 21*
22*21*
20191817161514 13 12 1110
AP
23*87654 3
AP
23*87654 3
AP
2387654 3
AP24
87654 3
2 1 0
2 1 1
2 1 0
2 1 0
22
22
23
- 58 -
W90N745CD/W90N745CDG
6.3.2.2. SDRAM Power Up Sequence
The SDRAM must be initialized predefined manner after power on.W90N745 SDRAM Controller
automatically executes the commands needed for initialion and set the mode register of each bank to
default value. The default value is:
— Burst Length = 1
— Burst Type = Sequential (fixed)
— CAS Latency = 2
— Write Burst Length = Burst (fixed)
The value of mode register can be changed after power up sequence by setting the value of
corresponding bank’s configuration register “LENGTH” and “LATENCY” bits and set the MRSET bit
enable to execute the Mode Register Set command.
6.3.2.3. SDRAM Interface
A[20:0]
D[15:0]
MCLK
MCKE
nSCS[1:0]
nSRAS
nSCAS
nSWE
nSDQM[1:0]
W90N745
A[10:0]
A13
A14
nSCS0
nSDQM[1:0]
Figure 6.3.1 SDRAM Interface
A[10:0]
BS0
BS1
DQ[[15:0]
CLK
CKE
nCS
nRAS
nCAS
nWE
DQM[1:0]
SDRAM
32Mb 512Kx4x16
Publication Release Date: September 22, 2006
- 59 - Revision A2
W90N745CD/W90N745CDG
6.3.3 EBI Control Registers Map
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
EBICON
ROMCON
SDCONF0 0xFFF0_1008 R/W SDRAM bank 0 configuration register
SDCONF1 0xFFF0_100C R/W SDRAM bank 1 configuration register
SDTIME0 0xFFF0_1010 R/W SDRAM bank 0 timing control register
SDTIME1
EXT0CON
EXT1CON
EXT2CON
EXT3CON
CKSKEW
0xFFF0_1000
0xFFF0_1004
0xFFF0_1014
0xFFF0_1018
0xFFF0_101C
0xFFF0_1020
0xFFF0_1024
0xFFF0_1F00
R/W EBI control register
R/W ROM/FLASH control register
R/W SDRAM bank 1 timing control register
R/W External I/O 0 control register
R/W External I/O 1 control register
R/W External I/O 2 control register
R/W External I/O 3 control register
R/W Clock skew control register (for testing)
0x0001_0000
0x0000_0XFC
0x0000_0800
0x0000_0800
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0xXXXX_0038
- 60 -
W90N745CD/W90N745CDG
EBI Control Register (EBICON)
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
EBICON
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
0xFFF0_1000
RESERVED EXBE3 EXBE2 EXBE1 EXBE0
RESERVED REFEN REFMOD CLKEN
REFRAT WAITVT LITTLE
R/W EBI control register
REFRAT
0x0001_0000
BITS DESCRIPTION
[31:27] RESERVED
External IO bank 3 byte enable
This function is used for some devices that with high and low bytes
enable signals to control which byte will be write or mask data output
when read. For this kind device, software can set this bit HIGH to
[27] EXBE3
[26] EXBE2
[25] EXBE1
implement this function. Detail pin interconnection is showed as Figure
6.3.8.
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM.
0 = nWBE[1:0] pin is byte write strobe signal.
External IO bank 2 byte enable
The bit function description is the same as EXBE3 above.
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM.
0 = nWBE[1:0] pin is byte write strobe signal.
External IO bank 1 byte enable
The bit function description is the same as EXBE3 above.
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM
0 = nWBE[1:0] pin is byte write strobe signal
Publication Release Date: September 22, 2006
- 61 - Revision A2
W90N745CD/W90N745CDG
Continued.
BITS DESCRIPTION
External IO bank 0 byte enable
This bit function description is the same as EXBE3 above.
[24] EXBE0
[23:19] RESERVED
[18] REFEN
[17] REFMOD
[16] CLKEN
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM
0 = nWBE[1:0] pin is byte write strobe signal
-
Enable SDRAM refresh cycle for SDRAM bank0 & bank1
This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is
according to REFRAT bits.
1 = enable refresh function
0 = disable refresh function
Refresh mode of SDRAM for SDRAM bank
Defines the refresh mode type of external SDRAM bank
Software can write this bit “1” to force SDRAM enter self-refresh mode.
0 = Auto refresh mode
1 = Self refresh mode
NOTE: If any read/write to SDRAM occurs then this bit will be cleared to
“0” by hardware automatically and SDRAM will enters auto-refresh
mode.
Clock enable for SDRAM
Enables the SDRAM clock enable (CKE) control signal
0 = Disable (power down mode)
1 = Enable (Default)
[15:3] REFRAT
Refresh count value for SDRAM
The SDRAM Controller automatically provides an auto refresh cycle for
every refresh period programmed into the REFRAT bits when the
REFEN bit of each bank is set
The refresh period is calculated as
period =
value
fMCLK
- 62 -
W90N745CD/W90N745CDG
Continued.
BITS DESCRIPTION
Valid time of nWAIT signal
W90N745 recognizes the nWAIT signal at the next “nth” MCLK
rising edge after the nOE or nWBE active cycle. WAITVT bits
determine the n.
[2:1] WAITVT
Little Endian mode
After power on reset, the content of LITTLE is the Power-On Setting
value from D14 pin. If pin D14 is pull-down, the external memory format
[0] LITTLE
is Big Endian mode. If pin D14 is pull-up, the external memory format is
Little Endian mode. For more detail, refer to Power-On Setting of System
Manager.
NOTE: This bit is read only.
WAITVT [2:1] nth MCLK
0 0 1
0 1 2
1 0 3
1 1 4
Publication Release Date: September 22, 2006
- 63 - Revision A2
W90N745CD/W90N745CDG
ROM/Flash Control Register (ROMCON)
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
ROMCON
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
BITS DESCRIPTION
[31:19] BASADDR
[18:16] SIZE
[15:12] RESERVED
0xFFF0_1004
BASADDR SIZE
RESERVED tPA
tACC BTSIZE PGMODE
R/W ROM/FLASH control register
BASADDR
Base address pointer of ROM/Flash bank
The start address is calculated as ROM/Flash bank base pointer << 18.
The base address pointer together with the “SIZE” bits constitutes the
whole address range of each bank.
This ROM/Flash bank is designed for a boot ROM. BASADDR bits
determine its start address. The external data bus width is determined by
the data bus signals D [13:12] power-on setting.
0 0 Normal ROM
0 1 4 word page
1 0 8 word page
1 1 16 word page
Publication Release Date: September 22, 2006
- 65 - Revision A2
W90N745CD/W90N745CDG
Figure 6.3.2 ROM/FLASH Read Operation Timing
Figure 6.3.3 ROM/FLASH Page Read Operation Timing
- 66 -
W90N745CD/W90N745CDG
Configuration Registers(SDCONF0/1)
The configuration registers enable software to set a number of operating parameters for the SDRAM
controller. There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1
respectively. Each bank can have a different configuration.
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
SDCONF0 0xFFF0_1008 R/W SDRAM bank 0 configuration register 0x0000_0800
SDCONF1 0xFFF0_100C R/W SDRAM bank 1 configuration register 0x0000_0800
31 30 29 28 27 26 25 24
BASADDR
23 22 21 20 19 18 17 16
BASADDR RESERVED
15 14 13 12 11 10 9 8
MRSET RESERVED AUTOPR LATENCY RESERVED
7 6 5 4 3 2 1 0
COMPBK DBWD COLUMN SIZE
BITS DESCRIPTION
Base address pointer of SDRAM bank 0/1
[31:19] BASADDR
[18:16] RESERVED
[15] MRSET
[14] RESERVED
[13] AUTOPR
[12:11] LATENCY
The start address is calculated as SDRAM bank 0/1 base pointer
<< 18. The SDRAM base address pointer together with the “SIZE”
bits constitutes the whole address range of each SDRAM bank.
SDRAM Mode register set command for SDRAM bank 0/1
This bit set will issue a mode register set command to SDRAM.
Auto pre-charge mode of SDRAM for SDRAM bank 0/1
Enable the auto pre-charge function of external SDRAM bank 0/1
0 = Auto pre-charge
1 = No auto pre-charge
The CAS Latency of SDRAM bank 0/1
Defines the CAS latency of external SDRAM bank 0/1
LATENCY [12:11] MCLK
0 0 1
0 1 2
1 0 3
1 1 REVERSED
Publication Release Date: September 22, 2006
- 67 - Revision A2
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Continued.
BITS DESCRIPTION
[10:8] RESERVED
[7] COMPBK
[6:5] DBWD
Number of component bank in SDRAM bank 0/1
Indicates the number of component bank (2 or 4 banks) in external
SDRAM bank 0/1.
0 = 2 banks
1 = 4 banks
Data bus width for SDRAM bank 0/1
Indicates the external data bus width connect with SDRAM bank 0/1
If DBWD = 00, the assigned SDRAM access signal is not generated
Indicates the number of column address bits in external SDRAM
bank 0/1.
[4:3] COLUMN
Size of SDRAM bank 0/1
Indicates the memory size of external SDRAM bank 0/1
[2:0] SIZE
COLUMN [4:3] Bits
0 0 8
0 1 9
1 0 10
1 1 REVERSED
SIZE [2:0] Size of SDRAM (Byte)
0 0 0 Bank disable
0 0 1 2M
0 1 0 4M
0 1 1 8M
1 0 0 16M
1 0 1 32M
1 1 0 64M
1 1 1 REVERSED
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W90N745CD/W90N745CDG
Timing Control Registers (SDTIME0/1)
W90N745 offers the flexible timing control registers to control the generation and processing of the
control signals and can achieve you use different speed of SDRAM
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
SDTIME0 0xFFF0_1010 R/W SDRAM bank 0 timing control register
SDTIME1
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
0xFFF0_1014
RESERVED tRCD
R/W SDRAM bank 1 timing control register
RESERVED
RESERVED
0x0000_0000
0x0000_0000
tRDL tRP tRAS
BITS DESCRIPTION
[31:11] RESERVED -
SDRAM bank 0/1, /RAS to /CAS delay
tRCD [10:8] MCLK
0 0 0 1
0 0 1 2
[10:8] tRCD
SDRAM bank 0/1, Last data in to pre-charge command
The W90N745 supports an external device control without glue logic. It is very cost effective because
address decoding and control signals timing logic are not needed. Using these control registers you can
configure special external I/O devices for providing the low cost external devices control solution.
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
EXT0CON
EXT1CON
EXT2CON
EXT3CON
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
0xFFF0_1018
0xFFF0_101C
0xFFF0_1020
0xFFF0_1024
R/W External I/O 0 control register
R/W External I/O 1 control register
R/W External I/O 2 control register
R/W External I/O 3 control register
BASADDR
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
BASADDR SIZE
15 14 13 12 11 10 9 8
ADRS tACC tCOH
7 6 5 4 3 2 1 0
tACS tCOS DBWD
BITS DESCRIPTION
Base address pointer of external I/O bank 0~3
The start address of each external I/O bank is calculated as “BASADDR”
[31:11] BASADDR
[18:16] SIZE
base pointer << 18.
Each external I/O bank base address pointer together with the “SIZE” bits
constitutes the whole address range of each external I/O bank.
When ADRS is set, external address (A20~A0) bus is alignment to byte
address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is
AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting.
Access cycles of external I/O bank 0~3
This parameter means nWE, nWBE and nOE active time clock. Detail timing
diagram please refer to Figure 6.3.6 and 6.3.7
tACC[14:11] MCLK tACC[14:11] MCLK
0 0 0 0 Reversed 1 0 0 0 9
0 0 0 1 1 1 0 0 1 11
0 0 1 0 2 1 0 1 0 13
0 0 1 1 3 1 0 1 1 15
0 1 0 0 4 1 1 0 0 17
0 1 0 1 5 1 1 0 1 19
0 1 1 0 6 1 1 1 0 21
0 1 1 1 7 1 1 1 1 23
[10:8] tCOH
Chip selection hold time of external I/O bank 0~3
This parameters control nWBE and nOE hold time. Detail timing diagram
please refer to Figure 6.3.6 and 6.3.7
Programmable data bus width for external I/O bank 0~3
DBWD [1:0] Width of Data Bus
0 0 Disable bus
0 1 8-bit
1 0 16-bit
1 1 RESERVED
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Figure 6.3.6 External I/O write operation timing
Figure 6.3.7 External I/O read operation timing
Publication Release Date: September 22, 2006
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W90N745CD/W90N745CDG
Figure 6.3.8 External IO bank with 16-bit SRAM
Clock Skew Control Register (CKSKEW)
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
CKSKEW
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
0xFFF0_1F00
DLH_CLK_SKEW MCLK_O_D
R/WClock skew control register 0xXXXX_0018
DLH_CLK_REF
DLH_CLK_REF
RESVERED SWPON
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W90N745CD/W90N745CDG
BITS DESCRIPTION
Latch DLH_CLK clock tree by HCLK positive edge
[31:16] DLH_CLK_REF
[15:9] RESERVED -
[8] SWPON
The SDRAM MCLK is generated by inserting a delay (XOR2) chain in
HCLK positive or negedge edge to adjust the MCLK skew. So software
can read these bits to expore MCLK and HCLK relationship. [31:24] is
used for positive edge and [23:16] is for negedge edge.
SDRAM Initialization by Software
Set this bit “1” will issue a SDRAM power on default setting command
sequence like system power on, this bit will be auto-clear by hardware
while SDRAM initialization finish.
Data latch Clock Skew Adjustment
Due to PC board loading or too many devices connect to external
address and data bus, it may causes SDRAM can not work correctly at
high frequency (usually, > 80MHz) software can control
MCLK_O_D[3:0] to adjust address and data bus to adjust setup/hold
time.
DLH_CLK_SKEW[7:4]Gate
Delay
DLH_CLK_SKEW[7:4] Gate
Delay
[7:4] DLH_CLK_SKEW
0 0 0 0 P-0 1 0 0 0 N-0
0 0 0 1 P-1 1 0 0 1 N-1
0 0 1 0 P-2 1 0 1 0 N-2
0 0 1 1 P-3 1 0 1 1 N-3
0 1 0 0 P-4 1 1 0 0 N-4
0 1 0 1 P-5 1 1 0 1 N-5
0 1 1 0 P-6 1 1 1 0 N-6
0 1 1 1 P-7 1 1 1 1 N-7
NOTE: P-x means Data latched Clock shift “X” gates delays by refer
MCLKO positive edge, N-x means Data latched Clock shift “X” gates
delays by refer MCLKO negative edge.
Publication Release Date: September 22, 2006
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Continued.
BITS DESCRIPTION
MCLK output delay adjustment
MCLK_O_D [3:0] Gate
0 0 0 0P-01 0 0 0 N-0
0 0 0 1P-11 0 0 1 N-1
0 0 1 0P-21 0 1 0 N-2
[3:0] MCLK_O_D
0 0 1 1P-31 0 1 1 N-3
0 1 0 0P-41 1 0 0 N-4
0 1 0 1P-51 1 0 1 N-5
0 1 1 0P-61 1 1 0 N-6
0 1 1 1P-71 1 1 1 N-7
Dela
y
MCLK_O_D [3:0] Gate
Dela
y
NOTE: “P-x” means MCLKO shift “X” gates delay by refer HCLK
positive edge, “N-x” means MCLKO shift “X” gates delay by refer HCLK
negative edge. MCLK is the output pin of MCLKO, which is an internal
signal on chip.
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W90N745CD/W90N745CDG
6.4 Cache Controller
The W90N745 incorporates a 4KB Instruction cache, 4KB Data cache and 8 words write buffer. The ICache and D-Cache have similar organization except the cache size. To raise the cache-hit ratio, these
two caches are configured two-way set associative addressing. Each cache has four words cache line
size. When a miss occurs, four words must be fetched consecutively from external memory. The
replacement algorithm is a LRU (Least Recently Used).
If disabling the I-Cache / D-Cache, these cache memories can be treated as On-Chip RAM. The
W90N745 also provides a write buffer to improve system performance. The write buffer can buffer up to
eight words of data.
6.4.1 On-Chip RAM
If I-Cache or D-Cache is disabled, it can be served as On-Chip RAM. If D-Cache is disabled, there has
4KB On-Chip RAM, its start address is 0xFFE01000. If I-Cache is disabled, there has 4KB On-Chip RAM
and the start address of this RAM is 0xFFE00000. If both the I-Cache and D-Cache are disabled, it has
8KB On-Chip RAM starting from 0xFFE00000.
The size of On-Chip RAM is depended on the I-Cache and D-Cache enable bits ICAEN, DCAEN in
Cache Control Register (CAHCON).
Table 6.4.1 The size and start address of On-Chip RAM
ICAEN DCAEN
SIZE START ADDRESS
0 0 8KB 0xFFE0_0000
0 1 4KB 0xFFE0_0000
1 0 4KB 0xFFE0.1000
1 1 Unavailable
ON-CHIP RAM
6.4.2 Non-Cacheable Area
Although the cache affects the entire 2GB system memory, it is sometimes necessary to define noncacheable areas when the consistency of data stored in memory and the cache must be ensured. To
support this, the W90N745 provides a non-cacheable area control bit in the address field, A[31].
If A[31] in the ROM/FLASH, SDRAM, or external I/O bank’s access address is “0”, then the accessed
data is cacheable. If the A [31] value is “1”, the accessed data is non-cacheable.
Publication Release Date: September 22, 2006
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6.4.3 Instruction Cache
The Instruction cache (I-cache) is a 4K bytes two-way set associative cache. The cache organization is
128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in
memory. The cache access cycle begins with an instruction request from the instruction unit in the core.
In the case of a cache hit, the instruction is delivered to the instruction unit. In case of a cache miss, the
cache initiates a burst read cycle on the internal bus with the address of the requested instruction. The
first word received from the bus is the requested instruction. The cache forwards this instruction to the
instruction unit of the core as soon as it is received from the internal bus. A cache line is then selected to
receive the data that will be coming from the bus. A least recently used (LRU) replacement algorithm is
used to select a line when no empty lines are available. When I-Cache is disabled, the cache memory is
served as 4KB On-chip RAM. The I-Cache is always disabled on reset.
The following is a list of the instruction cache features:
y 4K bytes instruction cache
y Two-way set associative
y Four words in a cache line
y LRU replacement policy
y Lockable on a per-line basis
y Critical word first, burst access
Instruction Cache Operation
On an instruction fetch, bits 10-4 of the instruction’s address point into the cache to retrieve the tags and
data of one set. The tags from both ways are then compared against bits 30-11 of the instruction’s
address. If a match is found and the matched entry is valid, then it is a cache hit. If neither tags match nor
the matched tag is not valid, it is a cache miss.
Instruction Cache Hit
In case of a cache hit, bits 3-2 of the instruction address is used to select one word from the cache line
whose tag matches. The instruction is immediately transferred to the instruction unit of the core.
Instruction Cache Miss
On an instruction cache miss, the address of the missed instruction is driven on the internal bus with a 4word burst transfer read request. A cache line is then selected to receive the data that will be coming
from the bus. The selection algorithm gives first priority to invalid lines. If neither of the two lines in the
selected set is invalid, then the least recently used line is selected for replacement. Locked lines are
never replaced. The transfer begins with the word requested by the instruction unit (critical word first),
followed by the remaining words of the line, then by the word at the beginning of the lines (wraparound).
Instruction Cache Flushing
The W90N745 does not support external memory snooping. Therefore, if self-modifying code is written,
the instructions in the I-Cache may become invalid. The entire I-Cache can be flushed by software in one
operation, or can be flushed one line at a time by setting the CAHCON register bit FLHS or FLHA with
the ICAH bit is set. As flushing the cache line, the “V” bit of the line is cleared to “0”. The I-Cache is
automatically flushed during reset.
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Instruction Cache Load and Lock
The W90N745 supports a cache-locking feature that can be used to lock critical sections of code into ICache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The
smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular
instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line
command.
To load and lock instruction, the following sequence should be followed:
1. Write the start address of the instructions to be locked into CAHADR register.
2. Set LDLK and ICAH bits in the CAHCON register.
3. Increased the address by 16 and written into CAHADR register.
4. Set LDLK and ICAH bits in the CAHCON register.
5. Repeat the steps 3 and 4, until the desired instructions are all locked.
When using I-Cache load and lock command, there are some notes should be cared.
y The programs executing load and lock operation should be held in a non-
cacheable area of memory.
y The cache should be enabled and interrupts should be disabled.
y Software must flush the cache before execute load and lock to ensure that the
code to be locked down is not already in the cache.
Instruction Cache Unlock
The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line
is cleared to “0”. W90N745 has two unlock command, unlock line and unlock all.
The unlock line operation is performed on a cache line granularity. In case the line is found in the cache,
it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the
cache, no operation is done and the command terminates with no exception. To unlock one line the
following unlock line sequence should be followed:
1. Write the address of the line to be unlocked into the CAHADR Register.
2. Set the ULKS and ICAH bits in the CAHCON register.
The unlock all operation is used to unlock the whole I-Cache. This operation is performed on all cache
lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a
line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA
and ICAH bits.
Publication Release Date: September 22, 2006
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W90N745CD/W90N745CDG
6.4.4 Data Cache
The W90N745 data cache (D-Cache) is a 4KB two-way set associative cache. The cache organization is
128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in
memory. The cache is designed for buffer write-through mode of operation and a least recently used
(LRU) replacement algorithm is used to select a line when no empty lines are available.
When D-Cache is disabled, the cache memory is served as 4KB On-chip RAM.
The D-Cache is always disabled on reset.
The following is a list of the data cache features:
y 4K bytes data cache
y Two-way set associative
y Four words in a cache line
y LRU replacement policy
y Lockable on a per-line basis
y Critical word first, burst access
y Buffer Write-through mode
y 8 words write buffer
y Drain write buffer
Data Cache Operation
On a data fetch, bits 10-4 of the data’s address point into the cache to retrieve the tags and data of one
set. The tags from both ways are then compared against bits 30-11 of the data’s address. If a match is
found and the matched entry is valid, then it is a cache hit. If neither tags match nor the matched tag is
not valid, it is a cache miss.
Data Cache Read
Read Hit:On a cache hit, the requested word is immediately transferred to the core.
Read Miss:A line in the cache is selected to hold the data, which will be fetched from memory. The
selection algorithm gives first priority to invalid lines and if both lines are invalid the line in way zero is
selected first. If neither of the two candidate lines in the selected set is invalid, then one of the lines is
selected by the LRU algorithm to replace. The transfer begins with the aligned word containing the
missed data (critical word first), followed by the remaining word in the line, then by the word at the
beginning of the line (wraparound). As the missed word is received from the bus, it is delivered directly to
the core.
Data Cache Write
As buffer write-through mode, store operations always update memory. The buffer write-through mode is
used when external memory and internal cache images must always agree.
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Write Hit:Data is written into both the cache and write buffer. The processor then continues to access
the cache, while the cache controller simultaneously downloads the contents of the write buffer to main
memory. This reduces the effective write memory cycle time from the time required for a main memory
cycle to the cycle time of the high-speed cache.
Write Miss:Data is only written into write buffer, not to the cache (write no allocate).
Data Cache Flushing
The W90N745 allows flushing of the data cache under software control. The data cache may be
invalidated through writing flush line (FLHS) or flush all (FLHA) commands to the CAHCON register.
Flushing the entire D-Cache also flushed any locked down code. As flushing the data cache, the “V” bit
of the line is cleared to “0”. The D-cache is automatically flushed during reset.
Data Cache Load and Lock
The W90N745 supports a cache-locking feature that can be used to lock critical sections of data into DCache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The
smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular
instruction SRAM. The locked lines are not replaced during misses and it is not affected by flush per line
command.
To load and lock data, the following sequence should be followed:
1. Write the start address of the data to be locked into CAHADR register.
2. Set LDLK and DCAH bits in the CAHCON register.
3. Increased the address by 16 and written into CAHADR register.
4. Set LDLK and DCAH bits in the CAHCON register.
5. Repeat the steps 3 and 4, until the desired data are all locked.
When using D-Cache load and lock command, there are some notes should be cared.
y The programs executing load and lock operation should be held in a non-
cacheable area of memory.
y The cache should be enabled and interrupts should be disabled.
y Software must flush the cache before execute load and lock to ensure that the
data to be locked down is not already in the cache.
Data Cache Unlock
The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line
is cleared to “0”. W90N745 has two unlock command, unlock line and unlock all.
The unlock line operation is performed on a cache line granularity. In case the line is found in the cache,
it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the
cache, no operation is done and the command terminates with no exception. To unlock one line the
following unlock line sequence should be followed:
1. Write the address of the line to be unlocked into the CAHADR Register.
2. Set the ULKS and DCAH bits in the CAHCON register.
Publication Release Date: September 22, 2006
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W90N745CD/W90N745CDG
The unlock all operation is used to unlock the whole D-Cache. This operation is performed on all cache
lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a
line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA
and DCAH bits.
6.4.5 Write Buffer
The W90N745 provides a write buffer to improve system performance. The write buffer can buffer up to
eight words of data. The write buffer may be enabled or be disabled via the WRBEN bit in the CAHCNF
register, and the buffer is disabled and flushed on reset.
Drain write buffer
To force data, this is in write buffer, to be written to external main memory. This operation is useful in real
time applications where the processor needs to be sure that a write to a peripheral has completed before
program execution continues.
To perform this command, you can set the DRWB and DCAH bits in CAHCON register.
Cache controller has a configuration register to enable or disable the I-Cache, D-Cache, and Write
buffer.
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
CAHCNF
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
0xFFF0_2000
R/W Cache configuration register 0x0000_0000
RESERVED
RESERVED
RESERVED
RESERVED WRBENDCAEN ICAEN
BITS DESCRIPTION
[31:3] RESERVED
[2] WRBEN
[1] DCAEN
[0] ICAEN
-
Write buffer enable
Write buffer is disabled after reset.
1 = enable write buffer
0 = disable write buffer
D-Cache enable
D-Cache is disabled after reset.
1 = enable D-cache
0 = disable D-cache
I-Cache enable
I-Cache is disabled after reset.
1 = enable I-cache
0 = disable I-cache
Publication Release Date: September 22, 2006
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Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
y Flush I-Cache and D-Cache
y Load and lock I-Cache and D-Cache
y Unlock I-Cache and D-Cache
y Drain write buffer
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
CAHCON
31 30 29 28 27 26 25 24
0xFFF0_2004
R/W Cache control register
RESERVED
0x0000_0000
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
DRWB ULKS ULKA LDLK FLHS FLHA DCAH ICAH
BITS DESCRIPTION
[31:8] RESERVED
[7] DRWB
[6] ULKS
[5] ULKA
[4] LDLK
-
Drain write buffer
Forces write buffer data to be written to main memory.
Unlock I-Cache/D-Cache single line
Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in
CAHADR register must be specified.
Unlock I-Cache/D-Cache entirely
Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared
to 0.
Load and Lock I-Cache/D-Cache
Loads the instruction or data from external memory and locks into
cache. Both WAY and ADDR bits in CAHADR register must be
specified.
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Continued.
BITS DESCRIPTION
Flush I-Cache/D-Cache single line
[3] FLHS
[2] FLHA
[1] DCAH
[0] ICAH
NOTE:When using the FLHA or ULKA command, you can set bothICAH and DCAH bits to execute
entire I-Cache and D-Cache flushing or unlocking. But, FLHS and ULKS commands can only be
executed with a cache line specified by CAHADR register in I-Cache or D-Cache at a time. If you set bothICAH and DCAH bits, and set FLHS or ULKS command bit, it will be treated as an invalid
command and no operation is done and the command terminates with no exception.
The Drain Write Buffer operation is only for D-Cache. To perform this operation, you must set DRWB
and DCAH bits. If the ICAH bit is set when using DRWB command, it will be an invalid command and no
operation is done and the command terminates with no exception.
Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR
bits in CAHADR register must be specified.
Flush I-Cache/D-Cache entirely
To flush the entire I-Cache/D-Cache, also flushes any locked-down
code. If the I-Cache/D-Cache contains locked down code, the
programmer must flush lines individually
D-Cache selected
When set to “1”, the command set is executed with D-Cache.
I-Cache selected
When set to “1”, the command set is executed with I-Cache.
Publication Release Date: September 22, 2006
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W90N745CD/W90N745CDG
Address Register (CAHADR)
W90N745 Cache Controller supports one address register. This address register is used with the
command set in the control register (CAHCON) by specifying instruction/data address.
[30:0] ADDR The absolute address of instruction or data
0 = Way0 is selected
1 = Way1 is selected
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W90N745CD/W90N745CDG
Cache Test Register 0 (CTEST0)
Cache test control register that configures the cache and tag ram testing enable or disable. In addition,
this register controls the built-in-self-test (BIST) function of SRAM.
REGISTER ADDRESS R/WDESCRIPTION RESET VALUE
CTEST0
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
BISTEN RESERVED BST_GP3BST_GP2 BST_GP1 BST_GP0
7 6 5 4 3 2 1 0
0xFFF6_0000
R/W Cache test register 0 0x0000_0000
RESERVED
RESERVED
RESERVED CATEST
BITS DESCRIPTION
[31:16] RESERVED
[15] BISTEN
[14:12] RESERVED
[11] BIST_GP3
[10] BIST_GP2
[9] BIST_GP1
[8] BIST_GP0
[7:0] RESERVED
-
BIST mode enable
When set to “1”, BIST mode will be enabled, the selected memory
groups begins to be tested by BIST.
-
Memory group 3 is selected to test by BIST
When set to “1”, memory group 3, including data cache tag ram
way 0 and way 1, are selected to be tested by BIST.
Memory group 2 is selected to test by BIST
When set to “1”, memory group 2, including program cache tag
ram way 0 and way 1, are selected to be tested by BIST.
Memory group 1 is selected to test by BIST
When set to “1”, memory group 1, including data cache ram way 0
and way 1, are selected to be tested by BIST.
Memory group 0 is selected to test by BIST
When set to “1”, memory group 0, including program cache ram
way 0 and way 1, are selected to be tested by BIST.
-
** Note: The 4 memory groups can be selected and tested simultaneously by BIST.
Publication Release Date: September 22, 2006
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W90N745CD/W90N745CDG
Cache Test Register 1 (CTEST1)
Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST
is finish and all of bank of SRAM are tested successfully will be presented in this register.
This bit is “0” initially. When BIST mode enabled, this bit will be “1”
after BIST test completed. The values of BFAIL0-7 are valid only
after FINISH = 1.
-
BIST test fail for data cache tag ram way 1
If this bit equals to “1”, it indicates the data cache tag ram for way
1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for data cache tag ram way 0
If this bit equals to “1”, it indicates the data cache tag ram for way
0 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache tag ram way 1
If this bit equals to “1”, it indicates the instruction cache tag ram for
way 1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache tag ram way 0
If this bit equals to “1”, it indicates the instruction cache tag ram for
way 0 is tested fail by BIST. “0” means the test is passed.
BIST test fail for data cache ram way 1
If this bit equals to “1”, it indicates the data cache ram for way 1 is
tested fail by BIST. “0” means the test is passed.
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Continued.
BITS DESCRIPTION
BIST test fail for data cache ram way 0
[2] BFAIL2
[1] BFAIL1
[0] BFAIL0
If this bit equals to “1”, it indicates the data cache ram for way 0 is
tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache ram way 1
If this bit equals to “1”, it indicates the instruction cache ram for
way 1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache ram way 0
If this bit equals to “1”, it indicates the instruction cache ram for
way 0 is tested fail by BIST. “0” means the test is passed.
Publication Release Date: September 22, 2006
- 91 - Revision A2
W90N745CD/W90N745CDG
6.5 Ethernet MAC Controller
Overview
The W90N745 provides an Ethernet MAC Controller (EMC) for LAN application. This EMC has its
DMA controller, transmit FIFO, and receive FIFO.
The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM
function for Ethernet MAC address recognition, Transmit-FIFO, Receive-FIFO, TX/RX state machine
controller and status controller. The EMC only supports RMII (Reduced MII) interface to connect with
PHY operating on 50MHz REF_CLK.
Features
y Supports IEEE Std. 802.3 CSMA/CD protocol.
y Supports both half and full duplex for 10M/100M bps operation.
y Supports RMII interface.
y Supports MII Management function.
y Supports pause and remote pause function for flow control.
y Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes)
reception.
y Supports 16 entries CAM function for Ethernet MAC address recognition.
y Supports internal loop back mode for diagnostic.
y Supports 256 bytes embedded transmit and receive FIFO.
y Supports DMA function.
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W90N745CD/W90N745CDG
6.5.1 EMC Functional Description
MII Management State Machine
The MII management function of EMC is compliant to IEEE 802.3 Std. Through the MII management
interface, software can access the control and status registers of the external PHY chip. Tow
programmable register MIID (MAC MII Management Data Register) and MIIDA (MAC MII
Management Data Control and Address Register) are for MII management function. Set the bit BUSY
of MIIDA register will trigger the MII management state machine. After the MII management cycle is
finished, the BUSY bit will be cleared automatically.
Media Access Control (MAC)
The function of W90N745 MAC fully meets the requirements defined by the IEEE802.3u specification.
The following paragraphs will describe the frame structure and the operation of the transmission and
receive.
The transmission data frame sent from the transmit DMA will be encapsulated by the MAC before
transmitting onto the MII bus. The sent data will be assembled with the preamble, the start frame
delimiter (SFD), the frame check sequence and the padding for enforcing those less than 64 bytes to
meet the minimum size frame and CRC sequence. The out going frame format will be as following
10101010 --- 10101010 10101011 d0 d1 d2
As mentioned by the above format, the preamble is a consecutive 7-byte long with the pattern
“10101010” and the SFD is a one byte 10101011 data. The padding data will be all 0 value if the sent
data frame is less than 64 bytes. The padding disable function specified in the bit P of the transmit
descriptor is used to control if the MAC needs to pad data at the end of frame data or not when the
transmitted data frame is less than 64 bytes. The padding data will not be appended if the padding
disable bit is set to be high. The bits CRC0 ... CRC31 are the 32 bits cyclic redundancy check (CRC)
sequence. The CRC encoding is defined by the following polynomial specified by the IEEE802.3. This
32 bits CRC appending function will be disabled if the Inhibit CRC of the transmission descriptor is set
to high.
The MAC also performs many other transmission functions specified by the IEEE802.3, including the
inter-frame spacing function, collision detection, collision enforcement, collision back off and
retransmission. The collision back-off timer is a function of the integer slot time, 512 bit times. The
number of slot times to delay between the current transmissions attempts to the next attempt is
determined by a uniformly distributed random integer algorithm specified by the IEEE802.3. The MAC
performs the receive functions specified by the IEEE 802.3 including the address recognition function,
the frame check sequence validation, the frame disassembly, framing and collision filtering.
dn Padding CRC31 CRC30 --- CRC0
Publication Release Date: September 22, 2006
- 93 - Revision A2
W90N745CD/W90N745CDG
EMC Descriptors
A link-list data structure named as descriptor is used to keep the control, status and data
information of each frame. Through the descriptor, CPU and EMC exchange the information for frame
reception and transmission.
Two different descriptors are defined in W90N745. One named as Rx descriptor for frame
reception and the other names as Tx descriptor for frame transmission. Each Rx descriptor consists of
four words. There is much information kept in the descriptors and details are described as below.
6.5.1.1. Rx Buffer Descriptor
31 30 2
9
O Rx Status Receive Byte Count
Receive Buffer Starting Address BO
Next Rx Descriptor Starting Address
161
5
Reserved
0
Rx Descriptor Word 0
31 30 29 28 27 26 25 24
Owner Reserved
23 22 21 20 19 18 17 16
Reserved RP ALIE RXGD PTLE ReservedCRCE RXINTR
15 14 13 12 11 10 9 8
RBC
7 6 5 4 3 2 1 0
RBC
Owner [31:30]: Ownership
The ownership field defines which one, the CPU or EMC, is the owner of each Rx descriptor. Only the
owner has right to modify the Rx descriptor and the others can read the Rx descriptor only.
00: The owner is CPU
01: Undefined
10: The owner is EMC
11: Undefined
If the O=2’b10 indicates the EMC RxDMA is the owner of Rx descriptor and the Rx descriptor is
available for frame reception. After the frame reception completed, if the frame needed NAT
translation, EMC RxDMA modify ownership field to 2’b11. Otherwise, the ownership field will be
modified to 2’b00.
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W90N745CD/W90N745CDG
If the O=2’b00 indicates the CPU is the owner of Rx descriptor. After the CPU completes processing
the frame, it modifies the ownership field to 2’b10 and releases the Rx descriptor to EMC RxDMA.
Rx Status [29:16]: Receive Status
This field keeps the status for frame reception. All status bits are updated by EMC. In the receive
status, bits 29 to 23 are undefined and reserved for the future.
RP [22]: Runt Packet
The RP indicates the frame stored in the data buffer pointed by Rx descriptor is a short frame (frame
length is less than 64 bytes).
1’b0: The frame is not a short frame.
1’b1: The frame is a short frame.
ALIE [21]: Alignment Error
The ALIE indicates the frame stored in the data buffer pointed by Rx descriptor is not a multiple of
byte.
1’b0: The frame is a multiple of byte.
1’b1: The frame is not a multiple of byte.
RXGD [20]: Frame Reception Complete
The RXGD indicates the frame reception has completed and stored in the data buffer pointed by Rx
descriptor.
1’b0: The frame reception not complete yet.
1’b1: The frame reception completed.
PTLE [19]: Packet Too Long
The PTLE indicates the frame stored in the data buffer pointed by Rx descriptor is a long frame (frame
length is greater than 1518 bytes).
1’b0: The frame is not a long frame.
1’b1: The frame is a long frame.
CRCE [17]: CRC Error
The CRCE indicates the frame stored in the data buffer pointed by Rx descriptor incurred CRC error.
1’b0: The frame doesn’t incur CRC error.
1’b1: The frame incurred CRC error.
Publication Release Date: September 22, 2006
- 95 - Revision A2
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