Rainbow Electronics W90N740 User Manual
W90N740
Data Sheet
WINBOND
32-BIT ARM7TDMI-BASED
MICRO-CONTROLLER
Publication Release Date: November 26, 2004
- I - Revision A4
W90N740
The information described in this document is the exclusive intellectual property of
Winbond Electronics Corporation and shall not be reproduced without permission from Winbond.
Winbond is providing this document only for reference purposes of W90N740-based system design. Winbond
assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Winbond Electronics Corp.
- II -
W90N740
Table of Contents-
1. GENERAL DESCRIPTION .......................................................................................................... 1
2. FEATURES .................................................................................................................................. 1
3. BLOCK DIAGRAM ....................................................................................................................... 5
4. PIN CONFIGURATION................................................................................................................ 6
5. PIN ASSIGNMENT ...................................................................................................................... 7
6. PIN DESCRIPTION.................................................................................................................... 10
7. FUNCTIONAL DESCRIPTION .................................................................................................. 14
7.1 ARM7TDMI CPU Core................................................................................................. 14
7.2 System Manager.......................................................................................................... 15
7.2.1 Overview .......................................................................................................................15
7.2.2 System Memory Map.....................................................................................................15
7.2.3 Address Bus Generation ...............................................................................................17
7.2.4 Data Bus Connection with External Memory .................................................................18
7.2.5 Bus Arbitration............................................................................................................... 27
7.2.6 Power-On Setting ..........................................................................................................28
7.2.7 System Manager Control Registers Map....................................................................... 29
7.3 External Bus Interface (EBI) ........................................................................................ 35
7.3.1 EBI Overview.................................................................................................................35
7.3.2 SDRAM Controller.........................................................................................................35
7.3.3 External Bus Mastership................................................................................................41
7.3.4 EBI Control Registers Map ............................................................................................41
7.4 Cache Controller.......................................................................................................... 59
7.4.1 On-Chip RAM ................................................................................................................ 59
7.4.2 Non-Cacheable Area .....................................................................................................59
7.4.3 Instruction Cache ..........................................................................................................59
7.4.4 Data Cache ...................................................................................................................62
7.4.5 Write Buffer ...................................................................................................................64
7.5 Ethernet MAC Controller (EMC) .................................................................................. 68
7.5.1 EMC Descriptors ...........................................................................................................68
7.5.2 7.5.2 EMC Register Mapping ........................................................................................73
7.6 Network Address Translation Accelerator (NATA) .................................................... 114
7.6.1 NAT Process Flow.......................................................................................................115
7.6.2 NATA Registers Map...................................................................................................116
7.7 GDMA Controller ....................................................................................................... 127
7.7.1 GDMA Function Description ........................................................................................127
7.7.2 GDMA Registers Map .................................................................................................128
Publication Release Date: November 26, 2004
- III - Revision A4
W90N740
7.8
USB Host Controller .................................................................................................. 136
7.8.1 USB Host Controller Registers Map ............................................................................137
7.9 UART Controller ........................................................................................................ 154
7.9.1 UART Control Registers Map ...................................................................................... 155
7.10 TIMER Controller ....................................................................................................... 165
7.10.1 General Timer Controller ........................................................................................... 165
7.10.2 Watch Dog Timer ......................................................................................................165
7.10.3 Timer Control Registers Map.....................................................................................166
7.11 Advanced Interrupt Controller (AIC) .......................................................................... 172
7.11.1 Interrupt Sources.......................................................................................................173
7.11.2 AIC Registers Map ....................................................................................................174
7.12 General-Purpose Input/Output Controller (GPIO) ..................................................... 188
7.12.1 GPIO Controller Registers Map.................................................................................189
8. ELECTRICAL CHARACTERISTICS........................................................................................ 195
8.1 Absolute Maximum Ratings ....................................................................................... 195
8.2 DC Characteristics..................................................................................................... 196
8.2.1 USB Transceiver DC Characteristics ..........................................................................196
8.3 AC Characteristics ..................................................................................................... 197
8.3.1 EBI/SDRAM Interface AC Characteristics ...................................................................197
8.3.2 EBI/External Master Interface AC Characteristics ....................................................... 197
8.3.3 EBI/(ROM/SRAM/External I/O) AC Characteristics ..................................................... 198
8.3.4 USB Transceiver AC Characteristics........................................................................... 199
8.3.5 EMC MII AC Characteristics........................................................................................ 200
9. PACKAGE DIMENSIONS........................................................................................................ 202
10. W90N740 REGISTERS MAPPING TABLE ............................................................................. 203
11. ORDERING INFORMATION ................................................................................................... 215
12. REVISION HISTORY ............................................................................................................... 215
- IV -
W90N740
1. GENERAL DESCRIPTION
The W90N740 micro-controller is 16/32 bit, ARM7TDMI based RISC micro-controller for network as
well as embedded applications. An integrated dual Ethernet MAC, the W90N740, is designed for use in
broadband routers, wireless access points, residential gateways and LAN camera.
The W90N740N is built around The ARM7TDMI CPU core designed by Advanced RISC Machines, Ltd.
And achieves 80MHz under worse conditions. Its small size, fully static design is particularly suitable
for cost-sensitive and power-sensitive applications. It designs as Harvard architecture by offering an 8K-
byte I-cache/SRAM and an 2K-byte D-cache/SRAM with flexible configuration and two way set
associative structure to balance data movement between CPU and external memory. Four stages write
buffer also improves latency for write operations.
The external bus interface (EBI) controller provides single bus architecture, 8/16/32 bit data width to
access external SDRAM, ROM/SRAM, flash memory and I/O devices. It achieves same frequency as
CPU core to minimize latency if internal cache misses. Memory controller supports different kinds of
SDRAM types and configurations to ease system design. The System Manager includes an internal 32bit system bus arbiter and a PLL clock controller. Generic I/O bus is easily served as PCMCIA-like
interface for 802.11b wireless LAN connection.
Two 10/100Mb MACs of Ethernet controller is built in to reduce total system cost and increase
performance between WAN and LAN port. Either MII or RMII of MAC is selected for external 10/100
PHY chip to design for varieties of applications. A powerful NAT accelerator (Patent Pending) between
LAN and WAN reduces the software loading of CPU and speeds up performance between LAN and
WAN.
W90N740 integrates root hub of USB 1.1 host controller with one port transceiver and uses
additional port with external transceiver if necessary, which can add valuable functions like flash disk,
printer server, Bluetooth device via USB port. The important peripheral functions include one full wired
high speed UART channel, 2-Channel GDMA, one watch-dog timer, two 24-bit timers with 8-bit prescale, 20 programmable I/O ports, and an advanced interrupt controller.
2. FEATURES
Architecture
• Highly-integrated system for embedded Ethernet applications
• Powerful ARM7TDMI core and fully 16/32-bit RISC architecture
• Big /Little-Endian mode supported
• Cost-effective JTAG-based debug solution
System Manager
• System memory map & on-chip peripherals memory map
• The data bus width of external memory address & data bus connection with external memory
• Bus arbitration supports the Fixed Priority Mode & Rotate Priority Mode
• Power-On setting
• On-Chip PLL module control & Clock select control
Publication Release Date: November 26, 2004
- 1 - Revision A4
W90N740
External Bus Interface (EBI)
• External I/O Control with 8/16/32 bit external data bus
• Cost-effective memory-to-peripheral DMA interface
• SDRAM Controller supports up to 2 external SDRAM & the maximum size of each device is 32MB
• ROM/FLASH & External I/O interface
• Support for PCMCIA 16-bit PC Card devices
On-Chip Instruction and Data Cache
• Two-way, Set-associative, 8K-byte I-cache and 2K-byte D-cache
• Support for LRU (Least Recently Used) Protocol
• Cache can be configured as an internal SRAM
• Support Cache Lock function
Ethernet MAC Controller (EMC)
• IEEE 802.3 protocol engine with programmable MII or RMII interface for 10/100 Mbits/s
• DMA engine with burst mode
• 256 bytes transmit & 256 bytes receive FIFO for MAC protocol engine and DMA access
• Built-in 16 entry CAM Address Register
• Support long frame (more than 1518 bytes) and short frame (less than 64 bytes)
• Re-transmit (during collision) the frame without DMA access
• Half or full duplex function option
• Support Station Management for external PHY
• On-Chip Pad generation
NAT Accelerator (Patent Pending)
• Hardware acceleration on IP address / port number look up and replacement for network address
translation, including MAC address translation
• Provide 64 entries of translation table
• Support TCP / UDP packets
GDMA Controller
• 2 Channel GDMA for memory-to-memory data transfers without CPU intervention
• Increase or decrease source / destination address in 8-bit, 16-bit, or 32-bit data transfers
• Supports 4-data burst mode to boost performance
• Support external GDMA request
- 2 -
USB Host Controller
• USB 1.1 compatible
• Open Host Controller Interface (OHCI) 1.0 compatible.
• Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices.
• Built-in DMA for real-time data transfer
UART
• One UART (serial I/O) blocks with interrupt-based operation
• Full set of MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
• Fully programmable serial-interface characteristics:
• Break generation and detection
• False start bit detection
• Parity, overrun, and framing error detection
• Full prioritized interrupt system controls
W90N740
Timers
• Two programmable 24-bit timers with 8-bit pre-scalar
• One programmable 24-bit Watch-Dog timer
• One-short mode, period mode or toggle mode operation
Programmable I/Os
• 21 programmable I/O ports
I• /O ports Configurable for Multiple functions
Advanced Interrupt Controller (AIC)
• 18 interrupt sources, including 4 external interrupt sources
• Programmable normal or fast interrupt mode (IRQ, FIQ)
• Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources
• Programmable as either low-active or high-active for 4 external interrupt sources
• Priority methodology is encoded to allow for interrupt daisy-chaining
• Automatically mask out the lower priority interrupt during interrupt nesting
GPIO Controller
• Programmable as an input or output pin
Publication Release Date: November 26, 2004
- 3 - Revision A4
W90N740
On-Chip PLL
• One PLL for both CPU and USB host controller
• The external clock can be multiplied by on-chip PLL to provide high frequency system clock
• Programmable clock frequency, and the input frequency range is 3-30MHz; 15MHz is preferred.
Operation Voltage Range
• 2.7 – 3.6 V for IO Buffer
• 1.62 – 1.98 V for Core Logic
Operation Temperature Range
• 0 – 70 Degree C
Operating Frequency
• 80 MHz (default)
Package Type
• 176-pin LQFP
- 4 -
3. BLOCK DIAGRAM
W90N740
W90N740
JTAG
ICE
SDRAM
ROM
Flash
RAM
PCMCIA
IO Dev
ARM7TDMI
PLL
EBI Bus
TDMI Bus
Clock
Controller
AHB
Decoder
External Bus
Controller
GDMA
Controller
Wrapper
AHB Bus
8K-Byte
AHB
Arbiter
APB
Bridge
Cache
Controller
I Cache
APB Bus
2K-Byte
D Cache
UART
Interrupt
Controller
TIMER x2
WDT
COM Port
External
Interrupts
USB
Device
USB Host
Controller
Ethenet
MAC
Controller 0
PHY PHY
Fig 3.1 W90N740 Functional Block Diagram
NAT
Accelerator
- 5 - Revision A4
GPIO
Ethenet
MAC
Controller 1
Publication Release Date: November 26, 2004
4. PIN CONFIGURATION
RX1_CLK
DVDD18
DVSS18
AVSS18
AVDD18
RX1_DV
RX1D0
RX1D3
RX1D2
RX1D1
RX1_ERR
EXTAL
VSS33
W90N740
GP18/nIRQ1
GP17/nIRQ0
GP20/nIRQ3
GP19/nIRQ2
GP5/nRTS
GP6/nCTS
GP11/RxD
RX0_ERR
RX0_DV
VDD33
XTAL
VDD18
RX0D3
RX0D2
RX0D1
VSS18
TX0_CLK
RX0_CLK
RX0D0
TX0D3
CRS0
COL0
TX0_EN
VSS33
TX0D0
TX0D2
TX0D1
GP10/TxD
VDD33
MDIO0
MDC0
TX1D0
TX1D1
TX1D2
TX1D3
TX1EN
COL1
CRS1
MDIO1
VSS33
MDC1
TX1CLK
VDD33
GP0
GP1
GP2
GP3
GP12/nWDOG
GP13/TIMER0
GP14/TIMER1
TMS
TDI
VDD18
VSS18
TDO
TCK
nTRST
nRESET
P15/nXDACK
P16/nXDREQ
EMACK
EMREQ
nWAIT
VDD33
nOE
VSS33
nECS0
nECS1
nECS2
nECS3
nBTCS
nSCS0
nSCS1
SDQM0
SDQM1
A17
A18
A19
140
A21
A20
135
85
VDD33
A24
A23
A22
D0
USBVDD
DP
DN
130
USBVSS
GP9/nDSR
GP8/nDTR
GP7/nCD
125
GP4/nRI
D31
D30
D29
D28
120
D27
D26
VSS33
D25
VDD33
D24
115
D23
VDD18
VSS18
D22
110
D21
D20
D19
D18
D17
105
D16
D15
D14
VSS33
D13
100
VDD33
D12
D11
D10
D9
95
D8
D7
D6
D5
D4
90
D3
D2
VSS33
D1
165 160 155 150 145175 170
5
10
15
W90N740
20
25
176-Pin LQFP
30
35
40
50 55 60 80757065
SDQM3
SDQM2
NC
NC
MCKE
nSWE
nSCAS
nSRAS
VDD33
VSS33
MCLK
A0A2A1
A3
A8
A7
A6
A5
A4
VDD18
VDD33
A12
A13
VSS33
A16
A15
A14
VSS18
A11
A10
A9
Fig 4.1 176-Pin LQFP Pin Diagram
- 6 -
5. PIN ASSIGNMENT
Table 4 W90N740 Pins Assignment
PIN NAME 176-PIN LQFP
Clock & Reset ( 4 pins )
W90N740
EXTAL
XTAL
MCLK
nRESET
TAP Interface ( 5 pins )
TCK
TMS
TDI
TDO
nTRST
External Bus Interface ( 78 pins )
A [24:22]
A [21:0]
D [31:16]
D [15:0]
nWBE [3:0]/ SDQM [3:0]
nSCS[1:0]
NSRAS
NSCAS
NSWE
MCKE
NC
NC
EMREQ
EMACK
nWAIT
NBTCS
nECS[3:0]
NOE
z
164
z
163
z
54
z
27
z
25
z
20
z
21
z
24
z
26
z
84-82
81-74, 72, 70,
z
67-56
124-119, 117,
z
115-114, 111-105
104-103, 101,
z
99-88, 86
z
46-43
z
42, 41
z
51
z
52
z
50
z
49
z
48
z
47
z
31
z
30
z
32
z
40
z
39-36
z
34
Publication Release Date: November 26, 2004
- 7 - Revision A4
Table 4 W90N740 Pins Assignment (Continued)
PIN NAME 176-PIN LQFP
Ethernet Interface (0) ( 17 pins )
W90N740
MDC0
MDIO0
COL0 /
CRS0 /
R1B_CRSDV
TX0_CLK
TX0D [3:0] / R1B_TXD [1:0],
R0_TXD [1:0]
TX0_EN / R0_TXEN
RX0_CLK / R0_REFCLK
RX0D [3:0] / R1B_RXD [1:0],
R0_RXD [1:0]
RX0_DV / R0_CRSDV
RX0_ERR
Ethernet Interface (1) ( 17 pins )
MDC1
MDIO1
COL1
CRS1
TX1_CLK
TX1D [3:0] / R1A_TX [1:0]
TX1_EN /R1A_TXEN
RX1_CLK / R1A_REFCLK
RX1D [3:0] / R1A_RXD [1:0]
RX1_DV / R1A_CRSDV
RX1_ERR / R1A_RXERR
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
142
143
151
152
150
149-146
144
153
159-157, 154
160
161
10
8
6
7
11
4-1
5
167
172-169
168
166
- 8 -
Table 4 W90N740 Pins Assignment (Continued)
NAME 176-PIN LQFP
USB Interface ( 2 pins )
DP
DN
Miscellaneous ( 21 pins )
GP [20:17] / nIRQ [3:0]
GP16 / nXDREQ
GP15 /nXDACK
GP14 /
TIMER1/ SPEED
GP13 /
TIMER0/ STDBY
GP12 /nWDOG
GP11 /RxD
GP10 /TxD
GP9/nDSR/nTOE
GP8 /nDTR/FSE0
GP7 /nCD / VO
GP6 /nCTS/ VM
GP5 /nRTS/ VP
GP4 /nRI / RCV
GP [3:0]
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
W90N740
131
130
136-133
29
28
19
18
17
140
139
128
127
126
138
137
125
16-13
Name 176-Pin LQFP
Power/Ground (32 pins)
VDD18
VSS18
VDD33
VSS33
USBVDD
USBVSS
DVDD18
DVSS18
AVDD18
AVSS18
z
22, 69, 113, 155
z
23, 68, 112, 156
12, 33, 53, 71, 85,
z
100, 116, 141, 162
9, 35, 55, 73, 87, 102, 118, 145,
z
165
z
132
z
129
z
175
z
176
z
173
z
174
Publication Release Date: November 26, 2004
- 9 - Revision A4
6. PIN DESCRIPTION
Table 6.1 W90N740 Pins Description
W90N740
PIN NAME
System Clock & Reset
EXTAL I - External Clock / Crystal Input
XTAL O - Crystal Output
MCLK O - System Master Clock Out, SDRAM clock
nRESET I - System Reset, active-low
TAP Interface
TCK ID
TMS IU
TDI IU
TDO O - JTAG Test Data out
nTRST IU
External Bus Interface
A [24:22] O - Address Bus (MSB) of external memory and IO devices
A [21:0] IO - Address Bus of external memory and IO devices
D [31:16] IO - Data Bus (MSB) of external memory and IO device,
D [15:0] IO - Data Bus (LSB) of external memory and IO device
nWBE [3:0]/
SDQM [3:0]
nSCS [1:0] O - SDRAM chip select for two external banks, active-low.
nSRAS O - Row Address Strobe for SDRAM, active-low
nSCAS O - Column Address Strobe for SDRAM, active-low
nSWE O - SDRAM Write Enable, active-low
MCKE O - SDRAM Clock Enable, active-high
EMREQ ID
EMACK O - External Bus Acknowledge
nWAIT IU
nBTCS O - ROM/Flash Chip Select, active-low
nECS [3:0] IO - External I/O Chip Select, active-low.
nOE O - ROM/Flash, External Memory Output Enable, active-low
IO
TYPE
IO -
PAD
TYPE
internal
pulldown
internal
pull-up
internal
pull-up
internal
pull-up
internal
pulldown
internal
pull-up
DESCRIPTION
JTAG Test Clock,
JTAG Test Mode Select,
JTAG Test Data in,
JTAG Reset, active-low,
Write Byte Enable for specific device(nECS[3:0]),
Data input/output Mask signal for SDRAM (nSCS[1:0]), active-low These pins
are always Output in normal mode, and Input type in internal SRAM test mode.
External Master Bus Request
This is used to request external bus. When EMACK active, indicates the bus
grants the bus, chip drives all the output pins of the external bus to high
impedance.
External Wait, active-low
- 10 -
Pins Description, continued
W90N740
PIN NAME
Ethernet Interface (0)
MDC0 O
MDIO0 IO
COL0 I
CRS0 I
TX0_CLK I
TX0D [3:0]/
--, R0_TXD
[1:0]
TX0_EN /
R0_TXEN
RX0_CLK /
R0_REFCLK
RX0D [3:0] /
--, R0_RXD
[1:0]
RX0_DV /
R0_CRSDV
RX0_ERR I
IO
TYPE
O
O
I
I
I
PAD
TYPE
-
-
-
-
-
-
-
-
-
-
-
DESCRIPTION
MII Management Data Clock for Ethernet 0. It is the reference clock of MDIO0.
Each MDIO0 data will be latched at the rising edge of MDC0 clock.
MII Management Data I/O for Ethernet 0. It is used to transfer MII control and
status information between PHY and MAC.
Collision Detect for Ethernet 0 in MII mode. This shall be asserted by PHY upon
detecting a collision happened over the medium. It will be asserted and lasted until
collision condition vanishes.
Carrier Sense for Ethernet 0 in MII mode. In RMII mode, external pull-up is
necessary.
Transmit Data Clock for Ethernet 0 in MII mode.
provides the timing reference for TX0_EN and TX0D. The clock will be 25MHz or
2.5 MHz.
Transmit Data bus (4-bit) for Ethernet 0 in MII mode. The nibble transmit data bus
is synchronized with TX0_CLK. It should be latched by PHY at the rising edge of
TX0_CLK.
In RMII mode, TX0D [1:0] are used as R0_TXD [1:0], 2-bit Transmit Data bus for
Ethernet 0;
Transmit Enable for Ethernet 0 in MII. It indicates the transmit activity to external
PHY. It will be synchronized with TX0_CLK.
In RMII mode, R0_TXEN shall be asserted synchronously with the first nibble of
the preamble and shall remain asserted while all di-bits to be transmitted are
presented. Of course, it is synchronized with R0_REFCLK.
Receive Data Clock for Ethernet 0 in MII mode When it is used as a received clock
pin, it is from PHY. The clock will be either 25 MHz or 2.5 MHz. The minimum duty
cycle at its high or low state should be 35% of the nominal period for all conditions.
In RMII mode, this pin is used as R0_REFCLK, Reference Clock;
be 50MHz +/- 50 ppm with minimum 35% duty cycle at high or low state.
Receive Data bus (4-bit) for Ethernet 0 in MII mode. They are driven by external
PHY, and should be synchronized with RX0_CLK and valid only when RX0_DV is
valid.
In RMII mode, RX0D [1:0] are used as R0_RXD [1:0], 2-bit Receive Data bus for
Ethernet 0;
Receive Data Valid for Ethernet 0 in MII mode. It will be asserted when received data
is coming and present, and de-asserted at the end of the frame.
In RMII mode, this pin is used as the R0_CRSDV, Carrier Sense / Receive Data
Valid for Ethernet 0. The R0_CRSDV shall be asserted by PHY when the receive
medium is non-idle. Loss of carrier shall result in the de-assertion of R0_CRSDV
synchronous to the cycle of R0_REFCLK, and only on nibble boundaries.
Receive Data Error for Ethernet 0 in MII mode. It indicates a data error detected by
PHY. The assertion should be lasted for longer than a period of RX0_CLK. When
RX0_ERR is asserted, the MAC will report a CRC error.
TX0_CLK is driven by PHY and
The clock shall
Publication Release Date: November 26, 2004
- 11 - Revision A4
Pins Description, continued
W90N740
PIN NAME
Ethernet Interface (1)
MDC1 O -
MDIO1 IO -
COL1 I -
CRS1 I -
TX1_CLK I -
TX1D [3:0] /
--,R1A_TXD [1:0]
TX1_EN/
R1A_TXEN/R1B_TXEN
RX1_CLK /
R1A_REFCLK
RX1D [3:0] /
--, R1A_RXD[1:0]
RX1_DV/
R1A_CRSDV
RX1_ERR /
R1A_RXERR
IO
TYPE
PAD
TYPE
MII Management Data Clock for Ethernet 1. It is the reference clock of MDIO1.
Each MDIO1 data will be latched at the rising edge of MDC1 clock.
MII Management Data I/O for Ethernet 1. It is used to transfer MII control and
status information between PHY and MAC.
Collision Detect for Ethernet 1 in MII mode. This shall be asserted by PHY upon
detecting a collision happened over the medium. It will be asserted and lasted
until collision condition vanishes. External pull-up is necessary in RMII mode.
Carrier Sense for Ethernet 1 in MII mode. External pull-up is necessary in RMII
mode.
Transmit Data Clock for Ethernet 1 in MII mode, TX1_CLK is driven by PHY and
provides the timing reference for TX1_EN and TX1D. The clock will be 25MHz or
2.5 MHz. External pull-up will be necessary in RMII mode.
Transmit Data bus (4-bit) for Ethernet 1 in MII mode. The nibble transmit data
bus is synchronized with TX1_CLK. It should be latched by PHY at the rising
O -
O -
I -
I -
I -
I -
edge of TX1_CLK.
In RMII mode, TX1D [1:0] are used as R1A_TXD [1:0], 2-bit Transmit Data bus
for Ethernet 1
Transmit Enable for Ethernet 1 in MII and RMII mode. It indicates the transmit
activity to external PHY. It will be synchronized with TX1_CLK in MII mode.
Receive Data Clock for Ethernet 1 in MII mode. When it is used as a received
clock pin, it is from PHY. The clock will be either 25 MHz or 2.5 MHz. The
minimum duty cycle at its high or low state should be 35% of the nominal period
for all conditions.
In RMII mode, this pin is used as R1A_REFCLK, Reference Clock and only
available for 176-pin package. The clock shall be 50MHz +/-50 ppm with
minimum 35% duty cycle at high or low state.
Receive Data bus (4-bit) for Ethernet 1 in MII mode. They are driven by external
PHY, and should be synchronized with RX1_CLK and valid only when RX1_DV
is valid.
In RMII mode, RX1D [1:0] are used as R1A_RXD [1:0], 2-bit Receive Data bus
for Ethernet 1.
Receive Data Valid for Ethernet 1 in MII mode. It will be asserted when received
data is coming and present, and de-asserted at the end of the frame.
In RMII mode, this pin is used as the R1A_CRSDV, Carrier Sense / Receive
Data Valid for Ethernet 1 and only available for 176-pin package. The
R1A_CRSDV shall be asserted by PHY when the receive medium is non-idle.
Loss of carrier shall result in the de-assertion of R1A_CRSDV synchronous to
the cycle of R1A_REFCLK, and only on nibble boundaries.
Receive Data Error for Ethernet 1 in MII and RMII mode. It indicates a data error
detected by PHY. The assertion should be lasted for longer than a period of
RX0_CLK. When RX0_ERR is asserted, the MAC will report a CRC error.
DESCRIPTION
- 12 -
Pins Description, continued
W90N740
NAME
USB Interface
DP IO - Differential Positive USB IO signal
DN IO - Differential Negative (Minus) USB IO signal
Miscellaneous
GP[20:17] /
nIRQ[3:0]
GP16 / nXDREQ IO
GP15 /nXDACK IO
GP14 /
TIMER1/SPEED
GP13 /
TIMER0/STDBY
GP12 /nWDOG IO
GP11 /RxD IO
GP10 /TxD IO
GP9/nDSR/nTOE IO
GP8 /nDTR/FSE0 IO
GP7 /nCD /VO IO
GP6 /nCTS/ VM IO
GP5 /nRTS/ VP IO
GP4 /nRI /RCV IO
GP[3:0] IO - General Purpose I/O.
IO
TYPE
IO
IO
IO
PAD
TYPE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DESCRIPTION
External Interrupt Request or General Purpose I/O
External DMA Request or General Purpose I/O
External DMA Acknowledge or General Purpose I/O
Timer 1 or General Purpose I/O. This pin is also used as SPEED,
Speed mode control for external USB transceiver
Timer 0 or General Purpose I/O. This pin is also used as STDBY, StandBy control
for external USB transceiver
Watchdog Timer Timeout Flag (active-low) or General Purpose I/O
UART Receive Data or General Purpose I/O
UART Transmit Data or General Purpose I/O
UART Receive Clock or General Purpose I/O. This pin is also used as nTOE,
Output Enable control (active-low) for external USB transceiver.
UART Transmit Clock or General Purpose I/O. This pin is also used as SE0,
Differential Data Transceiver Output for external USB transceiver. T
UART Carrier Detector or General Purpose I/O. This pin is also used as VO, Data
Output for external USB transceiver.
UART Clear to Send or General Purpose I/O. This pin is also used as VM, Data
Negative (Minus) Input for external USB receiver.
UART Ready to Send or General Purpose I/O. This pin is also used as VP, Data
Positive Input for external USB receiver.
UART Ring Indicator or General Purpose I/O. This pin is also used as RCV,
Difference Receiver Input.
Power/Ground
VDD18 P Core Logic power (1.8V)
VSS18 G Core Logic ground (0V)
VDD33 P IO Buffer power (3.3V)
VSS33 G IO Buffer ground (0V)
USBVDD P USB power (3.3V)
USBVSS G USB ground (0V)
DVDD18 P PLL Digital power (1.8V)
DVSS18 G PLL Digital ground (0V)
AVDD18 P PLL Analog power (1.8V)
AVSS18 G PLL Analog ground (0V)
Publication Release Date: November 26, 2004
- 13 - Revision A4
W90N740
7. FUNCTIONAL DESCRIPTION
7.1 ARM7TDMI CPU Core
The ARM7TDMI CPU core is a member of the ARM family of general-purpose 32-bit microprocessors,
which offer high performance for very low power consumption. The architecture is based on Reduced
Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are
much simpler than those of micro-programmed Complex Instruction Set Computer (CISC) systems.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously.
The high instruction throughput and impressive real-time interrupt response are the major benefits.
The ARM7TDMI core can execute two instruction sets:
(1) The standard 32-bit ARM instruction set
(2) The 16-bit THUMB instruction set
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core
while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit
registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent
interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding
32-bit ARM instruction with the same effect on the processor model. In the other words, the THUMB
architecture give 16-bit systems a way to access the 32-bit performance of the ARM Core without
requiring the full overhead of 32-bit processing.
ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 set are visible; the other registers
are used to speed up exception processing. All the register specifies in ARM instructions can address
any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt,
memory aborts, attempted execution of an undefined instruction and software interrupts.
A[31:0]
ALU Bus
Address Register
PC Bus
(31 x 32-bit registers)
(6 status registers)
A Bus
Address
Incrementer
Register Bank
32 x8 Multiplier
Barrel Shifter
32-bit ALU
Incrementer Bus
B Bus
Scan Control
Instruction Decoder
Control Logic
Instruction Pipeline
Read Data Register
Thumb Instruction Decoder
Writer Data
Register
D[31:0]
Fig 7.1 ARM7TDMI CPU Core Block Diagram
- 14 -
W90N740
7.2 System Manager
7.2.1 Overview
The functions of the System Manager:
• System memory map & on-chip peripherals memory map
• The data bus width of external memory address & data bus connection with external memory
• Bus arbitration supports the Fixed Priority Mode & Rotate Priority Mode
• Power-On setting
• On-Chip PLL module control & Clock select control
7.2.2 System Memory Map
W90N740 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The
On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0.0000 – 0xFFFF.FFFF) and the OnChip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable
space: 0x0~0x7FDF.FFFF if Cache ON; non-cacheable space: 0x8000.0000 ~ 0xFFDF.FFFF).
The size and location of each bank is determined by the register settings for “current bank base address
pointer” and “current bank size”. (*Note: The address boundaries of consecutive banks must not overlap,
when setting the bank control registers.)
The start address of each memory bank is not fixed, except On-Chip Peripherals and On-Chip RAM. You
can use bank control registers to assign a specific bank start address by setting the bank’s base pointer
(13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer <<
18” and the bank’s size is “current bank size”.
In the event of an access request to an address outside any programmed bank size, an abort signal is
generated. The maximum accessible memory size of each external IO bank is 32M bytes, and 64M
bytes on SDRAM banks.
Publication Release Date: November 26, 2004
- 15 - Revision A4
0x7FFF.FFFF
512KB
(Fixed)
0x7FF8.0000
512KB
(Fixed)
0x7FF0.0000
W90N740
Cacheable space Non-Cacheable space
RESERVED
RESERVED
RESERVED
0xFFFF.FFFF
512KB
(Fixed)
0xFFF8.0000
512KB
(Fixed)
0xFFF0.0000
On-Chip APB
Peripherals
On-Chip AHB
Peripherals
RESERVED
10KB
0x7FE0.0000
EBI Space
RESERVED
External I/O Bank 3
256KB - 32MB
External I/O Bank 2
256KB - 32MB
External I/O Bank 1
256KB - 32MB
External I/O Bank 0
256KB - 32MB
SDRAM Bank 1
2MB - 64MB
SDRAM Bank 0
2MB - 64MB
10KB
0xFFE0.0000
EBI Space
On-Chip RAM
2KB,8KB
External I/O Bank 3
256KB - 32MB
External I/O Bank 2
256KB - 32MB
External I/O Bank 1
256KB - 32MB
External I/O Bank 0
256KB - 32MB
SDRAM Bank 1
2MB - 64MB
SDRAM Bank 0
2MB - 64MB
0x0000.0000
ROM/FLASH
256KB - 32MB
Fig7.2.1 System Memory Map
ROM/FLASH
256KB - 32MB
0x8000.0000
- 16 -
Table 7.2.1 On-Chip Peripherals Memory Map
BASE ADDRESS DESCRIPTION
AHB Peripherals
0xFFF0.0000 Product Identifier Register (PDID)
0xFFF0.0004
0xFFF0.0008
0xFFF0.000C
0xFFF0.1000
0xFFF0.1004
0xFFF0.1008
0xFFF0.1018
0xFFF0.2000
0xFFF0.3000
0xFFF0.4000
0xFFF0.5000
0xFFF0.6000
0xFFF6.0000
0xFFF7.0000
Arbitration Control Register (ARBCON)
PLL Control Register (PLLCON)
Clock Select Register (CLKSEL)
EBI Control Register (EBICON)
ROM/FLASH (ROMCON)
SDRAM bank 0 - 1
External I/O 0 - 3
Cache Controller
Ethernet MAC Controller 0 - 1
GDMA 0 - 1
USB (Host)
NAT Accelerator
Reserved
Reserved
APB Peripherals
W90N740
0xFFF8.0000
0xFFF8.1000
0xFFF8.2000
0xFFF8.3000
UART
Timer 0 - 1, WDOG Timer
Interrupt Controller
GPIO
7.2.3 Address Bus Generation
The W90N740 address bus generation is depended on the required data bus width of each memory
bank. The data bus width is determined by DBWD bits in each bank’s control register.
The maximum accessible memory size of each external IO bank is 32M bytes .
Table 7.2.2 Address Bus Generation Guidelines
DATA BUS EXTERNAL ADDRESS PINS MAXIMUM ACCESSIBLE
Width A [22:0] A23 A24 Memory Size
8-bit A22 – A0 (Internal) A23 (Internal) A24 (Internal) 32M bytes
16-bit A23 – A1 (Internal) A24 (Internal) NA 16M half-words
32-bit A24 – A2 (Internal) NA NA 8M words
Publication Release Date: November 26, 2004
- 17 - Revision A4
W90N740
7.2.4 Data Bus Connection with External Memory
7.2.4.1 Memory formats
The internal architecture is big endian. The little endian mode only support for external memory.
The W90N740 can be configured as big endian or little endian mode by pull up or down the data D14
pin. If D14 is pull-up then it is a little endian mode, otherwise, it is a big endian mode.
Big Endian
In Big endian format, the W90N740 stores the most significant byte of a word at the lowest numbered
byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory
system connects to data lines 31 through 24.
For a word aligned address A, Fig7.2.2 shows how the word at address A, the half-word at addresses A
and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when the LITTLE pin
is Low.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word at address A
Half-word at address A Half-word at address A+2
Byte at address A Byte at address A+1 Byte at address A+2 Byte at address A+3
Fig. 7.2.2 Big endian addresses of bytes and half-words within words
Little Endian
In Little endian format, the lowest addressed byte in a word is considered the least significant byte of the
word and the highest addressed bye is the most significant. So the byte at address 0 of the memory
system connects to data lines 7 through 0.
For a word aligned address A, Fig7.2.3 shows how the word at address A, the half-word at addresses A
and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when LITTLE pin is
High.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word at address A
Half-word at address A+2 Half-word at address A
Byte at address A+3 Byte at address A+2 Byte at address A+1 Byte at address A
Fig. 7.2.3 Little endian addresses of bytes and half-words within words
- 18 -
W90N740
7.2.4.2 Connection of External Memory with Various Data Width
The system diagram for W90N740 connecting with the external memory is shown in Fig. 7.2.4. Below
tables (Table7.2.3 − Table7.2.14) show the program/data path between CPU register and the external
memory using little / big endian and word/half-word/byte access.
Fig. 7.2.4 Address/Data bus connection with external memory
Fig. 7.2.5 CPU register Read/Write with external memory
Publication Release Date: November 26, 2004
- 19 - Revision A4
W90N740
Table 7.2.3 and Table 7.2.4
Using big-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0, 4, 8, C X = Don’t care
nWBE [3-0] / SDQM [3-0] = A means active and U means inactive
Table7.2.3 Word access write operation with Big Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
nWBE [3-0] /
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
31 0
ABCD
WA WA WA
31 0
ABCD
31 0
ABCD
WA WA WA+2 WA WA+1 WA+2 WA+3
AAAA XXAA XXAA XXXA XXXA XXXA XXXA
31 0
ABCD
31 0
ABCD
1st write 2nd write 1st write 2nd write 3rd write 4th write
15 0
AB
15 0
AB
15 0
AB
31 0
ABCD
31 0
AB CD
15 0
CD
15 0
CD
15 0
CD
7 0
A
7 0
A
7 0
A
7 0
B
7 0
B
7 0
B
31 0
ABCD
31 0
A B C D
7 0
C
7 0
C
7 0
C
7 0
D
7 0
D
7 0
D
Table7.2.4 Word access read operation with Big Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
31 0
ABCD
WA WA WA
31 0
ABCD
31 0
ABCD
WA WA WA+2 WA WA+1 WA+2 WA+3
AAAA XXAA XXAA XXXA XXXA XXXA XXXA
31 0
ABCD
31 0
ABCD
1st read 2nd read 1st read 2nd read 3rd read 4th read
31 0
CD XX
15 0
CD
15 0
CD
31 0
CDAB
31 0
CD AB
31 0
CD AB
15 0
AB
15 0
AB
31 0
D X X X
7 0
D
7 0
D
31 0
DCBA
31 0
D C B A
31 0
D C X X
7 0
C
7 0
C
- 20 -
31 0
D C B X
7 0
B
7 0
B
31 0
D C B A
7 0
A
7 0
A
W90N740
Table 7.2.5 and Table 7.2.6
Using big-endian and half-word access, Program/Data path between register and external memory.
HA = Address whose LSB is 0, 2, 4, 6, 8, A, C, E HAL = Address whose LSB is 0, 4, 8, C
HAU = Address whose LSB is 2, 6, A, E X = Don’t care
nWBE [3-0] / SDQM [3-0] = A means active and U means inactive
Table7.2.5 Half-word access write operation with Big Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
nWBE [3-0] /
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence 1st write 2nd write
31 0
ABCD
HAL HAU HA HA
31 0
CD CD
31 0
CD CD
HAL HAL HA HA HA+1
AAUU UUAA XXAA XXXA XXXA
31 0
CD CD
31 16
CD
31 0
CD CD
31 0
CD CD
31 0
CD CD
15 0
CD
31 0
ABCD
31 0
CD CD
31 0
CD CD
15 0
CD
15 0
CD
31 0
CD CD
7 0
C
7 0
C
7 0
C
31 0
ABCD
31 0
CD CD
7 0
D
7 0
D
7 0
D
Table7.2.6 Half-word access read operation with Big Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence 1st read 2nd read
15 0
AB
HAL HAU HA HA
15 0
AB
15 0
AB
HAL HAL HA HA HA+1
AAUU UUAA XXAA XXXA XXXA
31 0
AB CD
31 0
ABCD
15 0
CD
15 0
CD
15 0
CD
31 0
AB CD
15 0
CD
15 0
CD
15 0
CD
15 0
CD
15 0
CD
15 0
DX
7 0
D
7 0
D
15 0
DC
15 0
DC
15 0
DC
7 0
C
7 0
C
Publication Release Date: November 26, 2004
- 21 - Revision A4
W90N740
Table 7.2.7 and Table 7.2.8
Using big-endian and byte access, Program/Data path between register and external memory.
BA = Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
BAL = Address whose LSB is 0, 2, 4, 6, 8, A, C, E BAU = Address whose LSB is 1, 3, 5, 7, 9, B, D,
F
BA0 = Address whose LSB is 0, 4, 8, C BA1 = Address whose LSB is 1, 5, 9, D
BA2 = Address whose LSB is 2, 6, A, E BA3 = Address whose LSB is 3, 7, B, F
Table7.2.7 Byte access write operation with Big Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
nWBE [3-0] /
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
31 0
ABCD
BA0 BA1 BA2 BA3 BAL BAU BA
31 0
D D D D
31 24
D
BA0 BA0 BA0 BA0 BAL BAL BA
AUUU UAUU UUAU UUUA XXAU XXUA XXXA
31 0
D X X X
31 24
D
31 0
D D D D
23 16
D
31 0
X D X X
23 16
D
31 0
D D D D
15 8
31 0
X X D X
15 8
31 0
D D D D
7 0
D
D
D
31 0
X X X D
7 0
D
31 0
D D D D
15 8
D
15 0
D X
15 8
D
31 0
ABCD
31 0
D D D D
7 0
D
15 0
X D
7 0
D
31 0
ABCD
31 0
D D D D
7 0
D
7 0
D
7 0
D
- 22 -
W90N740
Table7.2.8 Byte access read operation with Big Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
7 0
A
BA0 BA1 BA2 BA3 BAL BAU BA
7 0
A
7 0
A
BA0 BA0 BA0 BA0 BAL BAL BA
AUUU UAUU UUAU UUUA XXAU XXUA XXXA
31 0
ABCD
7 0
B
7 0
B
15 8
B
31 0
ABCD
31 0
ABCD
7 0
C
7 0
C
23 16
C
31 0
ABCD
7 0
D
7 0
D
31 24
D
31 0
ABCD
7 0
C
7 0
C
7 0
C
15 0
CD
7 0
D
7 0
D
15 8
D
15 0
CD
15 0
CD
7 0
D
7 0
D
7 0
D
7 0
D
7 0
D
Publication Release Date: November 26, 2004
- 23 - Revision A4
W90N740
Table 7.2.9 and Table 7.2.10
Using little-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0, 4, 8, C X = Don’t care
nWBE [3-0] / SDQM [3-0] = A means active and U means inactive
Table7.2.9 Word access write operation with Little Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
nWBE [3-0] /
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
31 0
ABCD
WA WA WA
31 0
ABCD
31 0
ABCD
WA WA WA+2 WA WA+1 WA+2 WA+3
AAAA XXAA XXAA XXXA XXXA XXXA XXXA
31 0
ABCD
31 0
ABCD
1st write 2nd write 1st write 2nd write 3rd write 4th write
15 0
CD
15 0
CD
15 0
CD
31 0
ABCD
31 0
AB CD
15 0
AB
15 0
AB
15 0
AB
7 0
D
7 0
D
7 0
D
7 0
C
7 0
C
7 0
C
31 0
ABCD
31 0
A B C D
7 0
B
7 0
B
7 0
B
7 0
A
7 0
A
7 0
A
Table7.2.10 Word access read operation with Little Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
31 0
ABCD
WA WA WA
31 0
ABCD
31 0
ABCD
WA WA WA+2 WA WA+1 WA+2 WA+3
AAAA XXAA XXAA XXXA XXXA XXXA XXXA
31 0
ABCD
31 0
ABCD
1st read 2nd read 1st read 2nd read 3rd read 4th read
31 0
XX CD
15 0
CD
15 0
CD
31 0
ABCD
31 0
AB CD
31 0
AB CD
15 0
AB
15 0
AB
31 0
X X X D
7 0
D
7 0
D
A B C D
31 0
X X C D
7 0
C
7 0
C
31 0
ABCD
31 0
31 0
X B C D
- 24 -
7 0
B
7 0
B
31 0
A B C D
7 0
A
7 0
A
W90N740
Table 7.2.11 and Table 7.2.12
Using little-endian and half-word access, Program/Data path between register and external memory.
HA = Address whose LSB is 0, 2, 4, 6, 8, A, C, E HAL = Address whose LSB is 0,4,8,C
HAU = Address whose LSB is 2, 6, A, E X = Don’t care
nWBE [3-0] / SDQM [3-0] = A means active and U means inactive
Table7.2.11 Half-word access write operation with Little Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
nWBE [3-0] /
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
31 0
ABCD
HAL HAU HA HA
31 0
CD CD
31 0
CD CD
HAL HAL HA HA HA+1
UUAA AAUU XXAA XXXA XXXA
31 0
CD CD
15 0
CD
31 0
CD CD
31 0
CD CD
31 0
CD CD
31 16
CD
31 0
ABCD
31 0
CD CD
31 0
CD CD
15 0
CD
15 0
CD
31 0
CD CD
7 0
D
7 0
D
7 0
D
31 0
ABCD
31 0
CD CD
7 0
C
7 0
C
7 0
C
1st write 2nd write
Table7.2.12 Half-word access read operation with Little Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
15 0
CD
HAL HAU HA HA
15 0
CD
15 0
CD
HAL HAL HA HA HA+1
UUAA AAUU XXAA XXXA XXXA
31 0
AB CD
31 0
ABCD
15 0
AB
15 0
AB
15 0
AB
31 0
AB CD
15 0
CD
15 0
CD
15 0
CD
15 0
CD
15 0
CD
15 0
XD
7 0
D
7 0
D
15 0
CD
15 0
CD
15 0
CD
7 0
C
7 0
C
1st read 2nd read
Publication Release Date: November 26, 2004
- 25 - Revision A4
W90N740
Table 7.2.13 and Table 7.2.14
Using little-endian and byte access, Program/Data path between register and external memory.
BA = Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
BAL = Address whose LSB is 0, 2, 4, 6, 8, A, C, E BAU = Address whose LSB is 1, 3, 5, 7, 9, B, D, F
BA0 = Address whose LSB is 0, 4, 8, C BA1 = Address whose LSB is 1, 5, 9, D
BA2 = Address whose LSB is 2, 6, A, E BA3 = Address whose LSB is 3, 7, B, F
Table7.2.13 Byte access write operation with Little Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
nWBE [3-0] /
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
BA0 BA1 BA2 BA3 BAL BAU BA
31 0
D D D D
7 0
D
BA0 BA0 BA0 BA0 BAL BAL BA
UUUA UUAU UAUU AUUU XXUA XXAU XXXA
31 0
X X X D
7 0
D
31 0
D D D D
31 0
X X D X
15 8
D
15 8
D
31 0
ABCD
31 0
D D D D
23 16
D
31 0
X D X X
23 16
D
31 0
D D D D
31 24
D
31 0
D X X X
31 24
D
31 0
D D D D
7 0
D
15 0
X D
7 0
D
31 0
ABCD
31 0
D D D D
15 8
D
15 0
D X
15 8
D
31 0
ABCD
31 0
D D D D
7 0
D
7 0
D
7 0
D
Table7.2.14 Byte access read operation with Little Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
7 0
D
BA0 BA1 BA2 BA3 BAL BAU BA
7 0
D
7 0
D
BA0 BA0 BA0 BA0 BAL BAL BA
UUUA UUAU UAUU AUUU XXUA XXAU XXXA
31 0
ABCD
7 0
C
7 0
C
7 0
C
31 0
ABCD
31 0
ABCD
7 0
B
7 0
B
7 0
B
31 0
ABCD
7 0
A
7 0
A
7 0
A
31 0
ABCD
7 0
D
7 0
D
7 0
D
15 0
CD
7 0
C
7 0
C
7 0
C
15 0
CD
15 0
CD
- 26 -
7 0
D
7 0
D
7 0
D
7 0
D
7 0
D
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