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W79E8213R
User Manual
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Rainbow Electronics W79E8213R User Manual

Preliminary W79E8213/W79E8213R Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 4
2. FEATURES.................................................................................................................................5
3. PARTS INFORMATION LIST ..................................................................................................... 6
3.1 Lead Free (RoHS) Parts information list......................................................................... 6
4. PIN CONFIGURATION...............................................................................................................6
5. PIN DESCRIPTIONS.................................................................................................................. 7
6. FUNCTIONAL DESCRIPTION.................................................................................................... 8
6.1 On-Chip Flash EPROM .................................................................................................. 8
6.2 I/O Ports.......................................................................................................................... 8
6.3 Timers.............................................................................................................................8
6.4 Interrupts......................................................................................................................... 8
6.5 Data Pointer....................................................................................................................8
6.6 Architecture..................................................................................................................... 8
6.7 Power Management........................................................................................................ 9
7. MEMORY ORGANIZATION......................................................................................................10
7.1 Program Memory (on-chip Flash).................................................................................10
7.2 Data Flash Memory ...................................................................................................... 10
7.3 Data Memory (accessed by MOVX)............................................................................. 11
7.4 Scratch-pad RAM and Register Map............................................................................ 11
8. SPECIAL FUNCTION REGISTERS ......................................................................................... 14
9. INSTRUCTION SET.................................................................................................................. 41
9.1 Instruction Timing.......................................................................................................... 49
10. POWER MANAGEMENT.......................................................................................................... 52
10.1 Idle Mode...................................................................................................................... 52
10.2 Power-down Mode........................................................................................................ 52
11. RESET CONDITIONS............................................................................................................... 53
11.1 Sources of reset............................................................................................................ 53
Publication Release Date: July 11, 2008
- 1 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
11.2 Reset State................................................................................................................... 55
12. INTERRUPTS........................................................................................................................... 56
12.1 Interrupt Sources .......................................................................................................... 56
12.2 Priority Level Structure ................................................................................................. 58
12.3 Response Time............................................................................................................. 59
12.4 Interrupt Inputs.............................................................................................................. 60
13. PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 61
13.1 Timer/Counters 0 & 1.................................................................................................... 61
14. NVM MEMORY.........................................................................................................................65
15. WATCHDOG TIMER................................................................................................................. 66
15.1 WATCHDOG CONTROL.............................................................................................. 67
15.2 CLOCK CONTROL of Watchdog.................................................................................. 67
16. TIME ACCESS PROCTECTION .............................................................................................. 68
17. EDGE DETECT INTERRUPT................................................................................................... 70
18. I/O PORT CONFIGURATION................................................................................................... 72
18.1 Quasi-Bidirectional Output Configuration..................................................................... 72
18.2 Open Drain Output Configuration................................................................................. 73
18.3 Push-Pull Output Configuration.................................................................................... 73
18.4 Input Only Configuration...............................................................................................74
19. OSCILLATOR ........................................................................................................................... 75
19.1 Internal RC Oscillator Option........................................................................................75
19.2 External Clock Input Option..........................................................................................75
20. BUZZER OUTPUT.................................................................................................................... 76
21. POWER MONITORING FUNCTION ........................................................................................ 79
21.1 Power On Detect........................................................................................................... 79
21.2 Brownout Detect ........................................................................................................... 79
22. PULSE-WIDTH-MODULATED (PWM) OUTPUTS................................................................... 80
23. ANALOG-TO-DIGITAL CONVERTER...................................................................................... 83
23.1 ADC Resolution and Analog Supply:............................................................................ 84
24. ICP (IN-CIRCUIT PROGRAM) FLASH PROGRAM ................................................................. 86
25. CONFIG BITS........................................................................................................................... 87
25.1 CONFIG0...................................................................................................................... 87
25.2 CONFIG1...................................................................................................................... 89
26. ELECTRICAL CHARACTERISTICS......................................................................................... 90
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
26.1
Absolute Maximum Ratings..........................................................................................90
26.2 DC ELECTRICAL CHARACTERISTICS...................................................................... 90
26.3 The ADC Converter DC ELECTRICAL CHARACTERISTICS ..................................... 92
26.4 Internal RC Oscillator Accuracy DC ELECTRICAL CHARACTERISTICS................... 92
26.5 AC ELECTRICAL CHARACTERISTICS ...................................................................... 93
26.6 EXTERNAL CLOCK CHARACTERISTICS.................................................................. 93
26.7 AC SPECIFICATION .................................................................................................... 93
26.8 TYPICAL APPLICATION CIRCUITS............................................................................ 93
27. PACKAGE DIMENSIONS......................................................................................................... 94
27.1 20-pin SOP-300mil ....................................................................................................... 94
27.2 20-pin PDIP-300mil....................................................................................................... 95
28. REVISION HISTORY................................................................................................................96
Publication Release Date: July 11, 2008
- 3 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
1. GENERAL DESCRIPTION
The W79E8213 series are an 8-bit 4T-8051 microcontroller which has Flash EPROM which is programmable by ICP (In Circuit Program) or by hardware writer. The instruction set of the W79E8213 series are fully compatible with the standard 8052. The W79E8213 series contain a 4K bytes of main Flash EPROM; a 128 bytes of RAM; two 16-bit timer/counters; 4-channel 10-bit PWM; 3 edge detector inputs; 8-channel multiplexed 10-bit A/D convert. The W79E8213 series supports 128 bytes NVM Data Flash EPROM. These peripherals are supported by 10 sources four-level interrupt capability. To facilitate programming and verification, the Flash EPROM inside the W79E8213 series allow the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security.
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
2. FEATURES
z Fully static design 8-bit 4T-8051 CMOS microcontroller:
VDD = 4.5V to 5.5V @20MHz  VDD = 2.7V to 5.5V @12MHz
VDD = 2.4V to 5.5V @4MHz z Instruction-set compatible with MSC-51. z Flexible CPU clock source configurable by config bit and software:
High speed external oscillator: upto 20MHz Crystal and resonator (enabled by config bit).
Internal RC oscillator: 20/10MHz selectable by config bit, only W79E8213R supports ±2%
accuracy internal RC oscillator at fixed voltage and temperature condition.
z 4K bytes of AP Flash EPROM, with ICP and external writer programmable mode. z 128 bytes of on-chip RAM. z W79E8213 series supports 128 bytes NVM Data Flash EPROM for customer data storage used
and 10K writer cycles.
8 pages. Page size is 16 bytes. z Two 16-bit timer/counters. z Ten interrupts source with four levels of priority. z Three-edge detect interrupt inputs. z Programmable Watchdog Timer. z Four-channel 10-bit PWM (Pulse Width Modulator). z Internal square wave generator for buzzer. z Up to 18 I/O pins. z The 4 outputs mode and TTL/Schmitt trigger selectable Port. z LED drive capability (20mA) on all port pins. Sink 20mA; Drive: -15~-20mA @push-pull mode. z Eight high sink capability (40mA) port pins. z Eight-channel multiplexed with 10-bits A/D convert. z Low Voltage Detect interrupt and reset. z Development Tools:
ICP(In Circuit Programming) writer z Packages:
- Lead Free (RoHS) DIP 20: W79E8213AKG
- Lead Free (RoHS) SOP 20: W79E8213ASG
- Lead Free (RoHS) DIP 20: W79E8213RAKG
- Lead Free (RoHS) SOP 20: W79E8213RASG
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
3. PARTS INFORMATION LIST
3.1 Lead Free (RoHS) Parts information list
PART NO.
W79E8213AKG 4KB W79E8213ASG 4KB W79E8213RAKG 4KB W79E8213RASG 4KB
EPROM
FLASH SIZE
Table 3-1: Lead Free (RoHS) Parts information list
4. PIN CONFIGURATION
RAM
128B 128B 128B 128B
NVM FLASH
EPROM
128B 128B 128B 128B
INTERNAL RC
OSCILLATOR
ACCURACY
±25% ±25%
±2% ±2%
PACKAGE
DIP-20 Pin
SOP-20 Pin
DIP-20 Pin
SOP-20 Pin
Figure 4-1: Pin Configuration
- 6 - Revision A2
Publication Release Date: July 11, 2008
Preliminary W79E8213/W79E8213R Data Sheet
5. PIN DESCRIPTIONS
SYMBOL
VDD P VSS P GROUND: Ground potential.
P0.0 AD6 PWM3 I/O P0.1 AD5 PWM0 I/O P0.2 AD4 BRAKE I/O P0.3 AD0 I/O P0.4 AD1 Data I/O P0.5 AD2 Clock I/O P0.6 AD3 I/O P0.7 AD7 T1 I/O P1.0 BUZ ED0 I/O P1.1 ED1 I/O P1.2 ED2 T0 I/O P1.3 /INT0 I/O P1.4 STADC /INT1 I/O
P1.5 P1.6 PWM1 I/O P1.7 PWM2 I/O
P2.0 XTAL2/CLKOUT I/O
P2.1 XTAL1 I/O
* TYPE: P: power, I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open-drain.
ALTERNATE FUNCTION 1
STR
ALTERNATE FUNCTION 2
ALTERNATE FUNCTION 3
HV I
ALTERNATE FUNCTION 4
(ICP MODE)
TYPE DESCRIPTIONS
POWER SUPPLY: Supply voltage for operation.
Port0: Support 4 output modes and
TTL/Schmitt trigger.
Multifunction pins for T1, PWM0, PWM3, BRAKE, AD0-7, Data and Clock (for ICP).
Port1: Support 4 output modes and
TTL/Schmitt trigger (except for P1.5 input only).
Multifunction pins for /RST, T0, /INT0-1, BUZ, PWM1-2, ED0-2, STADC, and HV (for ICP).
P1.0-P1.7 have 40mA high sink capability.
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. Also a configurable i/o pin.
When operating as I/O, it supports 4 output modes and TTL/Schmitt trigger.
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock or configurable I/O pin.
When operating as I/O, it supports 4 output modes and TTL/Schmitt trigger.
Table 5-1: Pin Descriptions Note: On power-on-reset, all port pins will be tri-stated. After power-on-reset, all port pins state will follow CONFIG0.PRHI bit definition.
Publication Release Date: July 11, 2008
- 7 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
6. FUNCTIONAL DESCRIPTION
The W79E8213 series architecture consist of a 4T 8051 core controller surrounded by various registers, 4K bytes Flash EPROM, 128 bytes of RAM, up to 18 general purpose I/O ports, two timer/counters, 3 edge detector inputs, 4-channel PWM with 10-bits counter, 8-channel multiplexed with 10-bit ADC analog input, Flash EPROM program by Writer and ICP. W79E8213 series supported 128 bytes NVM Data Flash EPROM.
6.1 On-Chip Flash EPROM
The W79E8213 series include one 4K bytes of main Flash EPROM for application program. A Writer or ICP programming board is required to program the Flash EPROM or NVM Data Flash EPROM.
This ICP (In-Circuit Programming) feature makes the job easy and efficient when the application’s firmware needs to be updated frequently. In some applications, the in-circuit programming feature makes it possible for the end-user to easily update the system firmware without opening the chassis.
6.2 I/O Ports
The W79E8213 series have up to 18 I/O pins using internal RC oscillator & /RST is input only by reset options. All ports can be used as four outputs mode when it may set by PxM1.y and PxM2.y SFR’s registers, it has strong pull-ups and pull-downs, and does not need any external pull-ups. Otherwise it can be used as general I/O port as open drain circuit. All ports can be used bi-directional and these are as I/O ports. These ports are not true I/O, but rather are pseudo-I/O ports. This is because these ports have strong pull-downs and weak pull-ups.
6.3 Timers
The W79E8213 series have two 16-bit timers that are functionally and similar to the timers of the 8052 family. When used as timers, the user has a choice of 12 or 4 clocks per count that emulates the timing of the original 8052.
6.4 Interrupts
The Interrupt structure in the W79E8213 series is slightly different from that of the standard 8052. Due to the presence of additional features and peripherals, the number of interrupt sources and vectors has been increased.
6.5 Data Pointer
The data pointer of W79E8213 series is same as standard 8052 which have 16-bit Data Pointer (DPTR).
6.6 Architecture
The W79E8213 series are based on the standard 8052 device. It is built around an 8-bit ALU that uses internal registers for temporary storage and control of the peripheral devices. It can execute the standard 8052 instruction set.
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
6.6.1 ALU
The ALU is the heart of the W79E8213 series. It is responsible for the arithmetic and logical functions. It is also used in decision making, in case of jump instructions, and is also used in calculating jump addresses. The user cannot directly use the ALU, but the Instruction Decoder reads the op-code, decodes it, and sequences the data through the ALU and its associated registers to generate the required result. The ALU mainly uses the ACC which is a special function register (SFR) on the chip. Another SFR, namely B register is also used in Multiply and Divide instructions. The ALU generates several status signals which are stored in the Program Status Word register (PSW).
6.6.2 Accumulator
The Accumulator (ACC) is the primary register used in arithmetic, logical and data transfer operations in the W79E8213 series. Since the Accumulator is directly accessible by the CPU, most of the high speed instructions make use of the ACC as one argument.
6.6.3 B Register
This is an 8-bit register that is used as the second argument in the MUL and DIV instructions. For all other instructions it can be used simply as a general purpose register.
6.6.4 Program Status Word
This is an 8-bit SFR that is used to store the status bits of the ALU. It holds the Carry flag, the Auxiliary Carry flag, General purpose flags, the Register Bank Select, the Overflow flag, and the Parity flag.
6.6.5 Scratch-pad RAM
The W79E8213 series have a 128 bytes on-chip scratch-pad RAM. These can be used by the user for temporary storage during program execution. A certain section of this RAM is bit addressable, and can be directly addressed for this purpose.
6.6.6 Stack Pointer
The W79E8213 series have an 8-bit Stack Pointer which points to the top of the Stack. This stack resides in the Scratch Pad RAM in the W79E8213 series. Hence the size of the stack is limited by the size of this RAM.
6.7 Power Management
Power Management like the standard 8052, the W79E8213 series also have the IDLE and POWER DOWN modes of operation. In the IDLE mode, the clock to the CPU is stopped while the timers, serial ports and interrupt block continue to operate. In the POWER DOWN mode, all clocks are stopped and the chip operation is completely stopped. This is the lowest power consumption state.
Publication Release Date: July 11, 2008
- 9 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
7. MEMORY ORGANIZATION
The W79E8213 series separate the memory into two separate sections, the Program Memory and the Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is used to store data or for memory mapped devices.
FFFFH FFFFH
FC7FH
(16 bytes/page)
FC00H
1000H
0FFFH
0000H
Unused
Code Memory
128B NVM
Data Memory
Unused
Code Memory
4K Bytes
On-Chip
Code Memory
Figure 7-1: W79E8213 series memory map
(128B NVM, 16bytes/page)
Page 7
Page 6
Page 5
Page 4
Page 3
Page 2
Page 1
Page 0
FC7Fh
FC70h FC6Fh
FC60h FC5Fh
FC50h FC4Fh
FC40h FC3Fh
FC30h FC2Fh
FC20h FC1Fh
FC10h FC0Fh
FC00h
NVM Data Memory Area
CONFIG 1
CONFIG 0
Unused
Data Memory
0000H
External Data Memory SpaceOn-Chip Code Memory Space
7.1 Program Memory (on-chip Flash)
The Program Memory on the W79E8213 series can be up to 4K bytes long. All instructions are fetched for execution from this memory area. The MOVC instruction can also access this memory region.
7.2 Data Flash Memory
The NVM Data Memory of Flash EPROM on the W79E8213 series is 128 bytes long, with page size of 16 bytes, respectively. The W79E8213 series’ NVM size is controllable through CONFIG1 register. The W79E8213 series read the content of data memory by using “MOVC A, @A+DPTR”. To write data is by NVMADDRL, NVMDATA and NVMCON SFR’s registers.
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
7.3 Data Memory (accessed by MOVX)
Not available in this product series.
7.4 Scratch-pad RAM and Register Map
As mentioned before the W79E8213 series have separate Program and Data Memory areas. The on­chip 128 bytes scratch pad RAM is in addition to the external memory. There are also several Special Function Registers (SFRs) which can be accessed by software. The SFRs can be accessed only by direct addressing, while the on-chip RAM can be accessed by either direct or indirect addressing.
Figure 7-2: W79E8213 RAM and SFR memory map
Since the scratch-pad RAM is only 128 bytes it can be used only when data contents are small. There are several other special purpose areas within the scratch-pad RAM. These are described as follows.
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
FFH
Indirect RAM
80H 7FH
Direct RAM
30H 2FH
2EH
2DH
2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H
1FH
18H 17H
10H 0FH
08H 07H
00H
454647
353637
Figure 7-3: Scratch pad RAM
34
Bank 3
Bank 2
Bank 1
Bank 0
7B 7A 79 787C7D7E7F 73 72 71 7074757677 6B 6A 69 686C6D6E6F 63 62 61 6064656667 5B 5A 59 585C5D5E5F 53 52 51 5054555657 4B 4A 49 484C4D4E4F 43 42 3B 3A 39 383C3D3E3F 33
32 2B 2A 29 282C2D2E2F 23 22 21 2024252627 1B 1A 19 181C1D1E1F 13 12 11 1014151617 0B 0A 09 080C0D0E0F 03 02 01 0004050607
41
31
4044
30
7.4.1 Working Registers
There are four sets of working registers, each consisting of eight 8-bit registers. These are termed as Banks 0, 1, 2, and 3. Individual registers within these banks can be directly accessed by separate instructions. These individual registers are named as R0, R1, R2, R3, R4, R5, R6 and R7. However, at one time the W79E8213 series can work with only one particular bank. The bank selection is done by setting RS1-RS0 bits in the PSW. The R0 and R1 registers are used to store the address for indirect accessing.
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
7.4.2 Bit addressable Locations
The Scratch-pad RAM area from location 20h to 2Fh is byte as well as bit addressable. This means that a bit in this area can be individually addressed. In addition some of the SFRs are also bit addressable. The instruction decoder is able to distinguish a bit access from a byte access by the type of the instruction itself. In the SFR area, any existing SFR whose address ends in a 0 or 8 is bit addressable.
7.4.3 Stack
The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP), which stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the return address is placed on the stack. There is no restriction as to where the stack can begin in the RAM. By default however, the Stack Pointer contains 07h at reset. The user can then change this to any value desired. The SP will point to the last used value. Therefore, the SP will be incremented and then address saved onto the stack. Conversely, while popping from the stack the contents will be read first, and then the SP is decreased.
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
8. SPECIAL FUNCTION REGISTERS
The W79E8213 series uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of the SFRs are bit addressable. This is very useful in cases where users wish to modify a particular bit without changing the others. The SFRs that are bit addressable are those whose addresses end in 0 or 8. The W79E8213 series contain all the SFRs present in the standard 8052. However some additional SFRs are added. In some cases the unused bits in the original 8052, have been given new functions. The list of the SFRs is as follows.
F8 F0
E8 E0 D8 D0 C8 C0 B8 B0 A8
A0 98
90 88
IP1 BUZCON
B PADIDS IP1H
EIE
ACC ADCCON ADCH ADCCON1
WDCON PWMPL PWM0L PWM1L PWMCON1 PWM2L PWM3L PWMCON2
PSW PWMPH PWM0H PWM1H
NVMCON NVMDATA NVMADDRL TA
IP0
P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 IP0H
IE
P2 AUXR1 EDIC
P1
TCON TMOD TL0 TL1 TH0 TH1 CKCON
PWM2H PWM3H PWMCON3
80
Note: 1. The SFRs in the column with dark borders are bit-addressable
2. The table is condensed with eight locations per row. Empty locations indicate that these are no registers at these
P0 SP DPL DPH PCON
Table 8-1: Special Function Register Location Table
addresses. When a bit or register is not implemented, it will read high.
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
A
ADD
SYMBOL DEFINITION
BUZCON Square wave control register F9H - -
IP1 Interrupt priority 1 F8H IP1H Interrupt high priority 1 F7H PEDH PPWMH PBKH PWDIH - - - - 0000xxxxB PADIDS B B register F0H (F7) (F6) (F5) (F4) (F3) (F2) (F1) (F0) 00000000B
EIE Interrupt enable 1 E8H
ADCCON1 ADC control register 1 E3H
ADCH ADCCON ADC control register E1H ADC.1 ADC.0 ADCEX ADCI ADCS RCCLK AADR1 AADR0 00000000B
ACC Accumulator E0H (E7) (E6) (E5) (E4) (E3) (E2) (E1) (E0) 00000000B PWMCON2 PWM control register 2 DFH BKCH BKPS BPEN BKEN PWM3B PWM2B PWM1B PWM0B 00000000B
PWM3L PWM 3 low bits register DEH PWM3.7 PWM3.6 PWM3.5 PWM3.4 PWM3.3 PWM3.2 PW M3.1 PWM3.0 00000000B PWM2L PWM 2 low bits register DDH PWM2.7 PWM2.6 PWM2.5 PWM2.4 PW M2.3 PWM2.2 PWM2.1 PWM2.0 00000000B
PWMCON1 PWM control register 1 DCH
PWM1L PWM 1 low bits register DBH PWM1.7 PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 PWM1.0 00000000B PWM0L PWM 0 low bits register DAH PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0 00000000B
PWMPL PWM counter low register D9H
WDCON Watch-Dog control D8H
PWMCON3 PWM control register 3 D7H - - - - FP1 FP0 - BKF xxxx00x0B PWM3H PWM 3 high bits register D6H - - - - - - PWM3.9 PWM3.8 xxxxxx00B PWM2H PWM 2 high bits register D5H - - - - - - PWM2.9 PWM2.8 xxxxxx00B PWM1H PWM 1 high bits register D3H - - - - - - PWM1.9 PWM1.8 xxxxxx00B PWM0H PWM 0 high bits register D2H - - - - - - PWM0.9 PWM0.8 xxxxxx00B
PWMPH PWM counter high register D1H - - - - - -
PSW Program status word D0H NVMDATA NVM Data CFH 00000000B
NVMCON NVM Control CEH EER EWR - - - - - - 00xxxxxxB TA Timed Access Protection C7H TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TA.0 11111111B
NVMADDRL NVM low byte address C6H -
IP0 Interrupt priority B8H
Port ADC digital input disable
ADC converter result high register
MSB BIT_ LSB
RESS
BUZDIV.5 BUZDIV.4 BUZDIV.3 BUZDIV.2 BUZDIV.1 BUZDIV.
(FF) PED
F6H 00000000B
(EF) EED
ADCLK.1 ADCLK.
E2H ADC.9 ADC.8 ADC.7 ADC.6 ADC.5 ADC.4 ADC.3 ADC.2 00000000B
PWMRU N
PWMP0.7 PWMP0.6 PWMP0.5 PWMP0.4 PWMP0.3 PWMP0.2 PWMP0.1 PWMP0.
(DF) WDRUN
(D7) CY
(BF) - (BE)
(FE) PPWM
(EE) EPWMU
F
0
load PWMF
(DE) - (DD)
(D6) AC
NVMAD DR.6
PADC
(FD) PBK
(ED) EPWM
- - - AADR2 - - 10xxx0xxB
WD1
(D5) F0
NVMAD DR.5
(BD) PBO
DDRESS, SYMBOL
(FC) PWDI
(EC) EWDI
CLRPW M
(DC) WD0
(D4) RS1
NVMAD DR.4
(BC) - (BB)
(FB) - (FA) - (F9) - (F8)
(EB) - (EA) - (E9) - (E8)
PWM3I PWM2I PWM1I PWM0I 00000000B
(DB) WDIF
(D3) RS0
NVMAD DR.3
PT1
(DA) WTRF
(D2) OV
NVMAD DR.2
(BA) PX1
(D9) EWRST
PWMP0.9 PWMP0.
(D1) F1
NVMAD DR.1
(B9) PT0
0
-
-
0
(D8) WDCLR
8 (D0)
P
NVMAD DR.0
(B8) PX0
RESET
xx00 0000B
0000xxxxB
0000xxxxB
00000000B External
reset: 0x00 0000B Watchdog
reset: 0x00 0100B
Power on reset 0x000000B
00000000B
00000000B
00000000B
x00x0000B
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Preliminary W79E8213/W79E8213R Data Sheet
A
Continued
ADD
SYMBOL DEFINITION
IP0H Interrupt high priority B7H - PADCH PBOH - PT1H PX1H PT0H PX0H x00x0000B P2M2 Port 2 output mode 2 B6H - - - - - - P2M2.1 P2M2.0 xxxxxx 00B P2M1 Port 2 output mode 1 B5H P2S P1S P0S ENCLK T1OE T0OE P2M2.1 P2M2.0 00000000B P1M2 Port 1 output mode 2 B4H P1M2.7 P1M2.6 - P1M2.4 P1M2.3 P1M2.2 P1M2.1 P1M2.0 00x00000B P1M1 Port 1 output mode 1 B3H P1M1.7 P1M1.6 - P1M1.4 P1M1.3 P1M1.2 P1M1.1 P1M1.0 00x00000B P0M2 Port 0 output mode 2 B2H P0M2.7 P0M2.6 P0M2.5 P0M2.4 P0M2.3 P0M2.2 P0M2.1 P0M2.0 00000000B P0M1 Port 0 output mode 1 B1H P0M1.7 P0M1.6 P0M1.5 P0M1.4 P0M1.3 P0M1.2 P0M1.1 P0M1.0 00000000B
IE Interrupt enable A8H EDIC Edge detect control register A3H EDFLT.1 EDFLT.0 ED2TRG ED2EN ED1TRG ED1EN ED0TRG ED0EN 00000000B
AUXR1 AUX function register A2H EDF BOD BOI LPBOV SRST ADCEN BUZE - 000X000xB
P2 Port 2 A0H
P1 Port 1 90H
CKCON Clock control 8EH - - - T1M T0M - - - xxx00xxxB TH1 Timer high 1 8DH 00000000B TH0 Timer high 0 8CH 00000000B TL1 Timer low 1 8BH 00000000B TL0 Timer low 0 8AH 00000000B TMOD Timer mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00000000B
TCON Timer control 88H PCON Power control 87H - - BOF POR GF1 GF0 PD IDL xxxx0000B
DPH Data pointer high 83H 00000000B DPL Data pointer low 82H 00000000B SP Stack pointer 81H 00000111B
P0 Port 0 80H
MSB BIT_ LSB
RESS
(AF) EA
(A7) - (A6) - (A5) - (A4) - (A3) (A2)
(97) P1.7 PWM2
(8F) TF1
(87) P0.7 AD7 T1
(AE) EADC
(96) P1.6 PWM1
(8E) TR1
(86) P0.6 AD3
(AD) EBO
(95) P1.5 /RST
(8D) TF0
(85) P0.5 AD2
DDRESS, SYMBOL
(AC) - (AB)
(94) P1.4 /INT1 STADC
(8C) TR0
(84) P0.4 AD1
ET1
(93) P1.3 /INT0
(8B) IE1
(83) P0.3 AD0
(AA) EX1
(92) P1.2 ED2 T0
(8A) IT1
(82) P0.2 AD4 BRAKE
(A9) ET0
(A1) P2.1 XTAL1
(91) P1.1 ED1
(89) IE0
(81) P0.1 AD5 PWM0
(A8) EX0
(A0) P2.0 XTAL2 CLKOUT
(90) P1.0 ED0 BUZ
(88) IT0
(80) P0.0 AD6 PWM3
RESET
000x0000B
xxxxxxxxB
11111111B
00000000B
11111111B
Table 8-2: Special Function Registers
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
PORT 0
Bit: 7 6 5 4 3 2 1 0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
Mnemonic: P0 Address: 80h P0.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate functions are described below:
BIT NAME FUNCTION
7 P0.7 AD7 pin or Timer 1 pin by alternative. 6 P0.6 AD3 pin by alternative. 5 P0.5 AD2 pin by alternative. 4 P0.4 AD1 pin by alternative. 3 P0.3 AD0 pin by alternative. 2 P0.2 AD4 pin or BRAKE pin by alternative. 1 P0.1 AD5 pin or PWM0 pin by alternative. 0 P0.0 AD6 pin or PWM3 pin by alternative.
Note: During power-on-reset, the port pins are tri-stated. After power-on -reset, the value of the port is set by CONFIG0.PRHI
bit. The default setting for CONFIG0.PRHI =1 which the alternative function output is turned on upon reset. If CONFIG0.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the alternative function output.
STACK POINTER
Bit: 7 6 5 4 3 2 1 0 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
Mnemonic: SP Address: 81h
BIT NAME FUNCTION
7-0 SP.[7:0]
DATA POINTER LOW
Bit: 7 6 5 4 3 2 1 0 DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
Mnemonic: DPL Address: 82h
BIT NAME FUNCTION
7-0 DPL.[7:0] This is the low byte of the standard 8052 16-bit data pointer.
The Stack Pointer stores the Scratch-pad RAM address where the stack begins. In other words it always points to the top of the stack.
Publication Release Date: July 11, 2008
- 17 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
DATA POINTER HIGH
Bit: 7 6 5 4 3 2 1 0 DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
Mnemonic: DPH Address: 83h
BIT NAME FUNCTION
7-0 DPH.[7:0]
POWER CONTROL
Bit: 7 6 5 4 3 2 1 0
- - BOF POR GF1 GF0 PD IDL
Mnemonic: PCON Address: 87h
BIT NAME FUNCTION
7 - Reserved. 6 - Reserved.
This is the high byte of the standard 8052 16-bit data pointer. This is the high byte of the DPTR 16-bit data pointer.
0: Cleared by software.
5 BOF
4 POR
3 GF1 General purpose user flags. 2 GF0 General purpose user flags.
1 PD
0 IDL
TIMER CONTROL
Bit: 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Mnemonic: TCON Address: 88h
1: Set automatically when a brownout reset or interrupt has occurred. Also set at
power on.
0: Cleared by software. 1: Set automatically when a power-on reset has occurred.
1: The CPU goes into the POWER DOWN mode. In this mode, all the clocks are
stopped and program execution is frozen.
1: The CPU goes into the IDLE mode. In this mode, the clocks CPU clock stopped,
so program execution is frozen. But the clock to the serial, timer and interrupt blocks is not stopped, and these blocks continue operating.
Publication Release Date: July 11, 2008
- 18 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
BIT NAME FUNCTION
Timer 1 Overflow Flag. This bit is set when Timer 1 overflows. It is cleared
7 TF1
6 TR1
5 TF0
4 TR0
3 IE1
2 IT1
1 IE0
0 IT0
automatically when the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
Timer 1 Run Control. This bit is set or cleared by software to turn timer/counter on or off.
Timer 0 Overflow Flag. This bit is set when Timer 0 overflows. It is cleared automatically when the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
Timer 0 Run Control. This bit is set or cleared by software to turn timer/counter on or off.
Interrupt 1 Edge Detect Flag: Set by hardware when an edge/level is detected on
INT1
. This bit is cleared by hardware when the service routine is vectored to only if
the interrupt was edge triggered. Otherwise it follows the inverse of the pin. Interrupt 1 Type Control. Set/cleared by software to specify falling edge/ low level
triggered external inputs. Interrupt 0 Edge Detect Flag. Set by hardware when an edge/level is detected on
INT0
. This bit is cleared by hardware when the service routine is vectored to only if
the interrupt was edge triggered. Otherwise it follows the inverse of the pin. Interrupt 0 Type Control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
TIMER MODE CONTROL
Bit: 7 6 5 4 3 2 1 0 GATE
TIMER1 TIMER0
TC/
M1 M0 GATE
TC/
M1 M0
Mnemonic: TMOD Address: 89h
BIT NAME FUNCTION
INT1
7 GATE
Gating control: When this bit is set, Timer/counter 1 is enabled only while the pin is high and the TR1 control bit is set. When cleared, the
INT1 pin has no effect,
and Timer 1 is enabled whenever TR1 control bit is set.
6
Timer or Counter Select: When clear, Timer 1 is incremented by the internal clock.
TC/
When set, the timer counts falling edges on the T1 pin. 5 M1 Timer 1 mode select bit 1. See table below. 4 M0 Timer 1 mode select bit 0. See table below.
3 GATE
Gating control: When this bit is set, Timer/counter 0 is enabled only while the
pin is high and the TR0 control bit is set. When cleared, the
INT0 pin has no effect,
INT0
and Timer 0 is enabled whenever TR0 control bit is set. 2
Timer or Counter Select: When clear, Timer 0 is incremented by the internal clock.
TC/
When set, the timer counts falling edges on the T0 pin. 1 M1 Timer 0 mode select bit 1. See table below. 0 M0 Timer 0 mode select bit 0. See table below.
M1, M0: Mode Select bits:
Publication Release Date: July 11, 2008
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Preliminary W79E8213/W79E8213R Data Sheet
M1 M0 MODE
0 0
Mode 0: 13-bits timer/counter; THx 8 bits and TLx 5 bits which serve as pre-scalar. 0 1 1 0
1 1
TIMER 0 LSB
Bit: 7 6 5 4 3 2 1 0 TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
Mnemonic: TL0 Address: 8Ah
BIT NAME FUNCTION
7-0 TL0.[7:0] Timer 0 LSB.
TIMER 1 LSB
Bit: 7 6 5 4 3 2 1 0 TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
Mnemonic: TL1 Address: 8Bh
BIT NAME FUNCTION
7-0 TL1.[7:0] Timer 1 LSB.
Mode 1: 16-bit timer/counter, no pre-scale.
Mode 2: 8-bit timer/counter with auto-reload from THx.
Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer0
control bits. TH0 is an 8-bit timer only controlled by Timer1 control bits. (Timer 1) Timer/Counter 1 is stopped.
TIMER 0 MSB
Bit: 7 6 5 4 3 2 1 0 TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
Mnemonic: TH0 Address: 8Ch
BIT NAME FUNCTION
7-0 TH0.[7:0] Timer 0 MSB.
TIMER 1 MSB
Bit: 7 6 5 4 3 2 1 0 TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
Mnemonic: TH1 Address: 8Dh
BIT NAME FUNCTION
7-0 TH1.[7:0] Timer 1 MSB.
Publication Release Date: July 11, 2008
- 20 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
CLOCK CONTROL
Bit: 7 6 5 4 3 2 1 0
- - - T1M T0M - - -
Mnemonic: CKCON Address: 8Eh
BIT NAME FUNCTION
7-5
4
3
- Reserved. Timer 1 clock select:
T1M
T0M
0: Timer 1 uses a divide by 12 clocks. 1: Timer 1 uses a divide by 4 clocks.
Timer 0 clock select: 0: Timer 0 uses a divide by 12 clocks. 1: Timer 0 uses a divide by 4 clocks.
2-0
PORT 1
Bit: 7 6 5 4 3 2 1 0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
Mnemonic: P1 Address: 90h P1.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate functions are described below:
BIT NAME FUNCTION
7 6 5 4 3 2 1 0
Note: During power-on-reset, the port pins are tri-stated. After power-on-reset, the value of the port is set by CONFIG0.PRHI
- Reserved.
P1.7 PWM2 pin by alternative. P1.6 PWM1 pin by alternative. P1.5 /RST pin or input pin by alternative. P1.4 STADC pin or /INT1 interrupt pin by alternative. P1.3 /INT0 interrupt pin by alternative. P1.2 Timer 0 pin or ED2 pin by alternative. P1.1 ED1 pin by alternative. P1.0 BUZ pin or ED0 pin by alternative.
bit. The default setting for CONFIG0.PRHI =1 which the alternative function output is turned on upon reset. If CONFIG0.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the alternative function output.
PORT 2
Bit: 7 6 5 4 3 2 1 0
- - - - - - P2.1 P2.0
Mnemonic: P2 Address: A0h
Publication Release Date: July 11, 2008
- 21 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
BIT NAME FUNCTION
7-2 - Reserved.
1 P2.1 XTAL1 clock input pin. 0 P2.0 XTAL2 or CLKOUT pin by alternative.
Note: During power-on-reset, the port pins are tri-stated. After power-on -reset, the value of the port is set by CONFIG0.PRHI
bit. The default setting for CONFIG0.PRHI =1 which the alternative function output is turned on upon reset. If CONFIG0.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the alternative function output.
AUX FUNCTION REGISTER 1
Bit: 7 6 5 4 3 2 1 0 EDF BOD BOI LPBOV SRST ADCEN BUZE -
Mnemonic: AUXR1 Address: A2h
BIT NAME FUNCTION
Edge detect Interrupt Flag:
7 EDF
6 BOD
5 BOI
4 LPBOV
3 SRST
2 ADCEN
1 BUZE
0 - Reserved.
1: When any pin of port 1.0-1.2 that is enabled for the Edge Detect Interrupt
function trigger (falling/rising edge trigger configurable). Must be cleared by software.
Brown Out Disable: 0: Enable Brownout Detect function. 1: Disable Brownout Detect function and save power.
Brown Out Interrupt: 0: Disable Brownout Detect Interrupt function and it will cause chip reset when
BOF is set.
1: This prevents Brownout Detection from causing a chip reset and allows the
Brownout Detect function to be used as an interrupt.
Low Power Brown Out Detect control: 0: When BOD is enable, the Brown Out detect is always turned on by normal run
or Power-down mode.
1: When BOD is enable, the Brown Out detect circuit is turned on by Power-
down mode. This control can help save 15/16 of the Brownout circuit power. When uC is in Power-down mode, the BOD will enable internal RC OSC (600KHz+/- 50%)
Software reset: 1: reset the chip as if a hardware reset occurred.
0: Disable ADC circuit. 1: Enable ADC circuit.
Square-wave enable bit: 0: Disable square wave output. 1: The square wave is output to the BUZ (P1.0) pin.
Publication Release Date: July 11, 2008
- 22 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
EDGE DETECT CONTROL REGISTER
Bit: 7 6 5 4 3 2 1 0 EDFILT.1 EDFILT.0 ED2TRG ED2EN ED1TRG ED1EN ED0TRG ED0EN
Mnemonic: EDIC Address: A3h
BIT NAME FUNCTION
Edge detect filter type bits: 00 – Filter clock = Fosc.
7-6
5 ED2TRG
4 ED2EN
01 – Filter clock = Fosc/2. 10 – Filter clock = Fosc/4. 11 – Filter clock = Fosc/8.
Edge detect 2 (ED2) trigger type bit: 0 – Falling edge on ED2 pin will cause EDF to be set (if ED2EN is enabled). 1 – Either falling or rising edge on ED2 pin will cause EDF to be set (if ED2EN is
enabled).
Edge detect 2 (ED2) enable bit: 0 – Disabled. 1 – Enable ED2 (P1.2 pin) as a cause of an edge detect interrupt.
Edge detect 1 (ED1) trigger type bit:
3 ED1TRG
2 ED1EN
1 ED0TRG
0 ED0EN
INTERRUPT ENABLE
Bit: 7 6 5 4 3 2 1 0 EA EADC EBO - ET1 EX1 ET0 EX0
Mnemonic: IE Address: A8h
0 – Falling edge on ED1 pin will cause EDF to be set (if ED1EN is enabled). 1 – Either falling or rising edge on ED1 pin will cause EDF to be set (if ED1EN is
enabled).
Edge detect 1 (ED1) enable bit: 0 – Disabled. 1 – Enable ED1 (P1.1 pin) as a cause of an edge detect interrupt.
Edge detect 0 (ED0) trigger type bit: 0 – Falling edge on ED0 pin will cause EDF to be set (if ED0EN is enabled). 1 – Either falling or rising edge on ED0 pin will cause EDF to be set (if ED0EN is
enabled).
Edge detect 0 (ED0) enable bit: 0 – Disabled. 1 – Enable ED0 (P1.0 pin) as a cause of an edge detect interrupt.
Publication Release Date: July 11, 2008
- 23 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
BIT NAME FUNCTION
7 EA Global enable. Enable/Disable all interrupts. 6 EADC Enable ADC interrupt. 5 EBO Enable Brown Out interrupt. 4 - Reserved. 3 ET1 Enable Timer 1 interrupt. 2 EX1 Enable external interrupt 1. 1 ET0 Enable Timer 0 interrupt. 0 EX0 Enable external interrupt 0.
PORT 0 OUTPUT MODE 1
Bit: 7 6 5 4 3 2 1 0 P0M1.7 P0M1.6 P0M1.5 P0M1.4 P0M1.3 P0M1.2 P0M1.1 P0M1.0
Mnemonic: P0M1 Address: B1h
BIT NAME FUNCTION
7-0 P0M1.[7:0] To control the output configuration of P0 bits [7:0]
PORT 0 OUTPUT MODE 2
Bit: 7 6 5 4 3 2 1 0 P0M2.7 P0M2.6 P0M2.5 P0M2.4 P0M2.3 P0M2.2 P0M2.1 P0M2.0
Mnemonic: P0M2 Address: B2h
BIT NAME FUNCTION
7-0 P0M2.[7:0] To control the output configuration of P0 bits [7:0]
PORT 1 OUTPUT MODE 1
Bit: 7 6 5 4 3 2 1 0 P1M1.7 P1M1.6 - P1M1.4 P1M1.3 P1M1.2 P1M1.1 P1M1.0
Mnemonic: P1M1 Address: B3h
BIT NAME FUNCTION
7-0 P1M1.[7:0] To control the output configuration of P1 bits [7:0]
PORT 1 OUTPUT MODE 2
Bit: 7 6 5 4 3 2 1 0 P1M2.7 P1M2.6 - P1M2.4 P1M2.3 P1M2.2 P1M2.1 P1M2.0
Mnemonic: P1M2 Address: B4h
BIT NAME FUNCTION
7-0 P1M2.[7:0] To control the output configuration of P1 bits [7:0]
Publication Release Date: July 11, 2008
- 24 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
PORT 2 OUTPUT MODE 1
Bit: 7 6 5 4 3 2 1 0 P2S P1S P0S ENCLK T1OE T0OE P2M1.1 P2M1.0
Mnemonic: P2M1 Address: B5h
BIT NAME FUNCTION
7 P2S
0: Disable Schmitt trigger inputs on port 2 and enable TTL inputs on port 2. 1: Enables Schmitt trigger inputs on Port 2.
6 P1S
5 P0S
4 ENCLK 1: Enabled clock output to XTAL2 pin (P2.0). 3 T1OE
2 T0OE 1 P2M1.1 To control the output configuration of P2.1.
0 P2M1.0 To control the output configuration of P2.0.
PORT 2 OUTPUT MODE 2
Bit: 7 6 5 4 3 2 1 0
- - - - - - P2M2.1 P2M2.0
Mnemonic: P2M2 Address: B6h
BIT NAME FUNCTION
7-2 - Reserved. 1-0 P2M2.[1:0] To control the output configuration of P2 bits [1:0]
0: Disable Schmitt trigger inputs on port 1 and enable TTL inputs on port 1. 1: Enables Schmitt trigger inputs on Port 1.
0: Disable Schmitt trigger inputs on port 0 and enable TTL inputs on port 0 1: Enables Schmitt trigger inputs on Port 0.
1: The P0.7 pin is toggled whenever Timer 1 overflows. The output frequency is
therefore one half of the Timer 1 overflow rate.
1: The P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is
therefore one half of the Timer 0 overflow rate.
PXM1.Y
(SEE NOTE)
0 0 Quasi-bidirectional 0 1 Push-Pull
1 0
1 1 Open Drain
Port Output Configuration Settings:
PXM2.Y PORT INPUT/OUTPUT MODE
Input Only (High Impedance) P2M1.PxS=0, TTL input P2M1.PxS=1, Schmitt input
Publication Release Date: July 11, 2008
- 25 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
INTERRUPT HIGH PRIORITY
Bit: 7 6 5 4 3 2 1 0
- PADCH PBOH - PT1H PX1H PT0H PX0H
Mnemonic: IP0H Address: B7h
BIT NAME FUNCTION
7 - This bit is un-implemented and will read high. 6 PADCH 1: To set interrupt high prio rity of ADC is highest priority level. 5 PBOH 1: To set interrupt high priority of Brown Out Detector is highest priority level. 4 - Reserved. 3 PT1H 1: To set interrupt high priority of Timer 1 is highest priority level. 2 PX1H 1: To set interrupt high priority of External interrupt 1 is highest priority level. 1 PT0H 1: To set interrupt high priority of Timer 0 is highest priority level. 0 PX0H 1: To set interrupt high priority of External interrupt 0 is highest priority level.
INTERRUPT PRIORITY 0
Bit: 7 6 5 4 3 2 1 0
- PADC PBO - PT1 PX1 PT0 PX0
Mnemonic: IP Address: B8h
BIT NAME FUNCTION
7 - This bit is un-implemented and will read high. 6 PADC 1: To set interrupt priority of ADC is higher priority level. 5 PBO 1: To set interrupt priority of Brown Out Detector is higher priority level. 4 - Reserved. 3 PT1 1: To set interrupt priority of Timer 1 is higher priority level. 2 PX1 1: To set interrupt priority of External interrupt 1 is higher priority level. 1 PT0 1: To set interrupt priority of Timer 0 is higher priority level. 0 PX0 1: To set interrupt priority of External interrupt 0 is higher priority level.
NVM LOW BYTE ADDRESS
Bit: 7 6 5 4 3 2 1 0
-
NVMADDR .6
NVMADDR .5
NVMADDR .4
NVMADDR .3
NVMADDR .2
NVMADDR .1
NVMADDR .0
Mnemonic: NVMADDRL Address: C6h
Publication Release Date: July 11, 2008
- 26 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
BIT NAME FUNCTION
7 - Please Keep it at 0.
The NVM address:
6~0 NVMADDR.[7:0]
TIMED ACCESS
Bit: 7 6 5 4 3 2 1 0 TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TA.0
Mnemonic: TA Address: C7h
BIT NAME FUNCTION
7-0 TA.[7:0]
The register indicates NVM data memory address on On-Chip code memory space.
The Timed Access register: The Timed Access register controls the access to protected bits. To access
protected bits, the user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA. Now a window is opened in the protected bits for three machine cycles, during which the user can write to these bits.
NVM CONTROL
Bit: 7 6 5 4 3 2 1 0 EER EWR - - - - - -
Mnemonic: NVMCON Address: CEh
BIT NAME FUNCTION
NVM page(n) erase bit: 0: Without erase NVM page(n). 1: Set this bit to erase page(n) of NVM. The NVM has 8 pages and each page
7 EER
have 16 bytes data memory. Initiate page select by programming NVMADDL register, which will automaticly enable page area. When user set this bit, the page erase process will begin and program counter will halt at this instruction. After the erase process is completed, program counter will continue executing next instruction.
NVM data write bit:
6 EWR
0: Without write NVM data. 1: Set this bit to write NVM bytes and program counter will halt at this instruction.
After write is finished, program counter will kept next instruction then executed.
5-0 - Reserved
NVM DATA
Bit: 7 6 5 4 3 2 1 0 NVMDAT
A.7
NVMDAT A.6
NVMDAT A.5
NVMDAT A.4
NVMDAT A3
NVMDAT A.2
NVMDAT A.1
NVMDAT A.0
Mnemonic: NVMDATA Address: CFh
Publication Release Date: July 11, 2008
- 27 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
BIT NAME FUNCTION
7~0 NVMDATA.[7:0] The NVM data write register. The read NVM data is by MOVC instruction.
PROGRAM STATUS WORD
Bit: 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P
Mnemonic: PSW Address: D0h
BIT NAME FUNCTION
Carry flag:
7 CY
Set for an arithmetic operation which results in a carry being generated from the ALU. It is also used as the accumulator for the bit operations.
6
AC
5 F0
4~3 RS1~RS0 Register bank select bits.
2 OV
1 F1
0 P
RS1 RS0 REGISTER BANK ADDRESS
0 0 0 00-07h 0 1 1 08-0Fh 1 0 2 10-17h 1 1 3 18-1Fh
Auxiliary carry: Set when the previous operation resulted in a carry from the high order nibble.
User flag 0: The General purpose flag that can be set or cleared by the user.
Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as
a result of the previous operation, or vice-versa. User Flag 1:
The General purpose flag that can be set or cleared by the user software. Parity flag:
Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
RS.1-0: Register Bank Selection Bits:
PWMP COUNTER HIGH BITS REGISTER
Bit: 7 6 5 4 3 2 1 0
- - - - - - PWMP.9 PWMP.8
Mnemonic: PWMPH Address: D1h
Publication Release Date: July 11, 2008
- 28 - Revision A2
Preliminary W79E8213/W79E8213R Data Sheet
BIT NAME FUNCTION
7-2 - Reserved. 1-0 PWMP.[9:8] The PWM Counter Register bits 9~8.
PWM 0 HIGH BITS REGISTER
Bit: 7 6 5 4 3 2 1 0
- - - - - - PWM0.9 PWM0.8
Mnemonic: PWM0H Address: D2h
BIT NAME FUNCTION
7~2 - Reserved. 1~0 PWM0.[9:8] The PWM 0 High Bits Register bit 9~8.
PWM 1 HIGH BITS REGISTER
Bit: 7 6 5 4 3 2 1 0
- - - - - - PWM1.9 PWM1.8
Mnemonic: PWM1H Address: D3h
BIT NAME FUNCTION
7~2 - Reserved. 1~0 PWM1.[9:8] The PWM 1 High Bits Register bit 9~8.
PWM 2 HIGH BITS REGISTER
Bit: 7 6 5 4 3 2 1 0
- - - - - - PWM2.9 PWM2.8
Mnemonic: PWM2H Address: D5h
BIT NAME FUNCTION
7~2 - Reserved. 1~0 PWM2.[9:8] The PWM 2 High Bits Register bit 9~8.
PWM 3 HIGH BITS REGISTER
Bit: 7 6 5 4 3 2 1 0
- - - - - - PWM3.9 PWM3.8
Mnemonic: PWM3H Address: D6h
BIT NAME FUNCTION
7~2 - Reserved. 1~0 PWM3.[9:8] The PWM 3 High Bits Register bit 9~8.
Publication Release Date: July 11, 2008
- 29 - Revision A2
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