Rainbow Electronics W78C801 User Manual

W78C801

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78C801 is an 8-bit microcontroller which can accommodate a wide frequency range with low power consumption. The instruction set for the W78C801 is fully compatible with the standard 8051. The W78C801 contains an 4K bytes Mask ROM; a 256 bytes RAM; four 8-bit bi-directional and bitaddressable I/O ports; an additional 6-bit I/O port P4; two 16-bit timer/counters; a hardware watchdog timer. These peripherals are supported by a twelve sources two-level interrupt capability. The W78C801 does not contain serial port.

The W78C801 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.

FEATURES

• Fully static design 8-bit CMOS microcontroller

• DC-40 MHz operation

• 256 bytes of on-chip scratchpad RAM

• 4 KB Mask-ROM

• 64 KB program memory address space

• 64 KB data memory address space

• Four 8-bit bi-directional ports

• Two 16-bit timer/counters

• Watchdog Timer

• Direct LED drive outputs

•

Twelve sources, two-level interrupt capability

• Wake-up via external interrupts at Port 1

• EMI reduction mode

•

Built-in power management

• Code protection mechanism

• Packages:

− DIP 40: W78C801-24/40

− PLCC 44: W78C801P-24/40

− PQFP 44: W78C801F-24/40

Publication Release Date: February 1999

- 1 - Revision A3

PIN CONFIGURATIONS

40-Pin DIP (W78C801)

INT2, P1.0

INT3, P1.1

INT4,P1.2

INT5,P1.3

INT6,P1.4

INT7,P1.5 INT8,P1.6 INT9,P1.7

RST

P3.0

P3.1 INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

WR, P3.6

RD, P3.7

XTAL2 XTAL1

VSS

W78C801

VDD1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

P0.0, AD0

P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA ALE,P4.5

PSEN,P4.6 P2.7, A15

P2.6, A14

P2.5, A13

P2.4, A12

P2.3, A11

P2.2, A10

P2.1, A9

P2.0, A8

44-Pin PLCC (W78C801P)

I

N

T

4

6

5

,

P

1

.

2

3

4

6543

RST

P3.0

P4.3

P3.1

7

8

9

10

11

12

13

14

15

16 17

X

P

T

3

A

.

L

7

6

2

,

/

R

W

D

R

INT7,P1.5 INT8,P1.6

INT9,P1.7

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

I

N

T

3

2

,

, P

P

1

4

.

0

1

2

2 1 44 43 42

X

V

P

S

T

4

A

S

.

L

0

1

44-Pin QFP (W78C801F)

I

N

A

D

3

1

2

0

,

P

P V D D

P 2 . 0 , A 8

0

.

3

2

1

0

40

41

P

2

.

3

2

1

,

A

1

9

1

0

P0.4, AD4

39 38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE,P4.5

32

PSEN,P4.6

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P 2 . 4 , A 1 2

INT7,P1.5 INT8,P1.6

INT9,P1.7

INT0, P3.2

INT1, P3.3

T0, P3.4 T1, P3.5

RST

P3.0

P4.3

P3.1

1 2

3

4 5

6 7 8 9

10

11

T 6

,

P 1 . 4

P 3 . 6 , / W R

T

4

5

,

P

1

.

2

3

43 42 41

X

P

T

3

A

.

L

7

2

, / R D

N

T

2

3

,

P

1

4

.

0

1

2

403938 37 36

X

V

P

S

T

4

A

S

.

L

0

1

V D D

P 2 . 0 , A 8

A

D

3

1

2

0

,

P

0

.

3

1

2

0

34

3544

P

2

.

3

2

1

,

A

1

9

1

0

P0.4, AD4

33 32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE,P4.5

26

PSEN,P4.6

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

2221201918171615141312

P 2 . 4 , A 1 2

- 2 -

PIN DESCRIPTION

SYMBOL DESCRIPTIONS

EA

PSEN PROGRAM STORE ENABLE:

ALE

RST

XTAL1

XTAL2

VSS

VDD

P0.0−P0.7

P1.0−P1.7

P2.0−P2.7

P3.0−P3.7

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of

external ROM. It should be kept high to access internal ROM. The ROM address and data will not be presented on the bus if

within on-chip ROM area. Otherwise they will be presented on the bus.

PSEN

address/ data bus during fetch and MOVC operations. When internal ROM access is

PSEN

performed, no alternative function P4.6.

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates

the address from the data on Port 0. This pin also serves the alternative function P4.5

RESET: A high on this pin for two machine cycles while the oscillator is running resets

the device.

CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external

clock.

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: Ground potential POWER SUPPLY: Supply voltage for operation. PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order

address/data bus during accesses to external memory. The pins of Port 0 can be individually configured to open-drain or standard port with internal pull-ups.

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate

functions which are described below:

INT2−INT9(P1.0−P1.7): External interrupt 2 to 9

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides

the upper address bits for accesses to external memory.

PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. The pins P3.4 to P3.7

can be configured with high sink current which can drive LED displays directly. All bits have alternate functions, which are described below:

INT0 (P3.2) : External Interrupt 0

strobe signal outputs from this pin. This pin also serves the

EA pin is high and the program counter is

enables the external ROM data onto the Port 0

W78C801

P4.0−P4.6

INT1(P3.3) : External Interrupt 1

T0(P3.4) : Timer 0 External Input T1(P3.5) : Timer 1 External Input

WR (P3.6) : External Data Memory Write Strobe

RD (P3.7) : External Data Memory Read Strobe

PORT 4: A 6-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are

available on 44-pin PLCC/QFP package. Pins P4.5 and P4.6 are the alternative

PSEN

function corresponding to ALE and

.

Publication Release Date: February 1999

- 3 - Revision A3

BLOCK DIAGRAM

W78C801

P1.0

P1.7

P3.0

P3.7

P4.0

P4.6

Port

INT2~9

Interrupt

Port 1

Latch

Timer

Port 3

Latch

Port 4

Latch

0

1

XTAL1

Oscillator

ACC

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

ALE

PSEN

ALU

SFR RAM

Address

256 bytes

RAM & SFR

Watchdog

Timer

Reset Block

B

Port 0

T2T1

Stack

Pointer

Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

Port 0

P0.0

P0.7

P2.0

Port 2 Latch

Port 2

P2.7

Power control

VssVCCRSTXTAL2

1

Port

3

Port

4

FUNCTIONAL DESCRIPTION

The W78C801 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, two timer/counters. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space.

Timers 0, 1

Timers 0, 1 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1. The TCON and TMOD registers provide control functions for timers 0 and 1. The operations of Timer 0 and Timer 1 are the same as in the W78C51.

I/O Port Options

The Port 0 and Port 3 of W78C801 may be configured with different types by setting the bits of the Port Options Register POR that is located at 86H. The pins of Port 0 can be configured with either the open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When the PUP bit in the POR register is set, the pins of Port 0 will perform a quasi-bidirectional I/O port with internal pull-up that is structurally the same as Port 2. The high nibble of Port

- 4 -

W78C801

3 (P3.4 to P3.7) can be selected to serve the direct LED displays drive outputs by setting the HDx bit in the PO register. When the HDx bit is set, the corresponding pin P3.x can sink about 20mA current for driving LED display directly. After reset, the POR register is cleared and the pins of Ports 0 and 3 are the same as those of the standard 80C31. The POR register is shown below.

Port Options Register

Bit: 7 6 5 4 3 2 1 0

EP6 EP5 - HD7 HD6 HD5 HD4 PUP

Mnemonic: POR Address: 86H

PUP : Enable Port 0 weak pull-up.

HD4-7: Enable pins P3.4 to P3.7 individually with High Drive outputs.

EP5 : Enable P4.5. To set this bit shifts ALE pin to the alternate function P4.5.

EP6 : Enable P4.6. To set this bit shifts

PSEN pin to the alternate function P4.6

Port 4

The W78C801 has one additional bit-addressable I/O port P4 in which the port address is D8H. The Port 4 contains seven bits; P4.0 to P4.3 are only available on 44-pin PLCC/QFP package; P4.5 and

P4.6 are the alternate function corresponding to pins ALE,

internal memory without any access to external memory, ALE and configured to the alternate functions P4.5 and P4.6 that serve as general purpose I/O pins. To enable I/O port P4.5 and P4.6, the bits EP5 and EP6 in the POR register must be set. During reset, the ALE

PSEN perform as in the standard 80C32. The alternate functions P4.5 and P4.6 must be

and enabled by software. Care must be taken with the ALE pins when configured as the alternate functions. The ALE will emit pulses until either the EP5 bit in POR register or AO bit in AUXR register is set to 1. i.e. User's applications should elude the ALE pulses before software configure it with I/O port P4.5.

Port 4

Bit: 7 6 5 4 3 2 1 0

- P4.6 P4.5 - P4.3 P4.2 P4.1 P4.0

Mnemonic: P4 Address: D8H

PSEN . When program is running in the

PSEN may be individually

Interrupt System

The W78C801 has twelve interrupt sources: INT0 and INT1; Timer 0,1; INT2 to INT9. Each interrupt vectors to a specific location in program memory for its interrupt service routine. Each of these sources can be individually enabled or disabled by setting or clearing the corresponding bit in Special Function Register IE0 and IE1. The individual interrupt priority level depends on the Interrupt Priority Register IP0 and IP1. Additional external interrupts INT2 to INT9 are level sensitive and may be used to awake the device from power down mode. The Port 1 interrupts can be initialized to either active HIGH or LOW via setting the Interrupt Polarity Register IX. The IRQ register contains the flags of Port

1 interrupts. Each flag in IRQ register will be set when an interrupt request is recognized but must be cleared by software. Note that the interrupt flags have to be cleared before the interrupt service

routine is completed, or else another interrupt will be generated.

Publication Release Date: February 1999

- 5 - Revision A3

Interrupt Enable Register 0

Bit: 7 6 5 4 3 2 1 0

EA - - - ET1 EX1 ET0 EX0

Mnemonic: IE Address: A8H

EA : Global enable. Enable/disable all interrupts. ET1: Enable Timer 1 interrupt EX1: Enable external interrupt 1 ET0: Enable Timer 0 interrupt EX0: Enable external interrupt 0

Interrupt Enable Register 1

Bit: 7 6 5 4 3 2 1 0

EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2

Mnemonic: IE1 Address: E8H

EX9: Enable external interrupt 9 EX8: Enable external interrupt 8 EX7: Enable external interrupt 7 EX6: Enable external interrupt 6 EX5: Enable external interrupt 5 EX4: Enable external interrupt 4 EX3: Enable external interrupt 3 EX2: Enable external interrupt 2

W78C801

Note: 0 = interrupt disabled, 1 = interrupt enabled.

Interrupt Priority Register 0

Bit: 7 6 5 4 3 2 1 0

- PS1 PT2 PS PT1 PX1 PT0 PX0

Mnemonic: IP0 Address: B8h

IP.7: Unused. PS1: This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level. PT2: This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level. PS : This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level. PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level. PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level. PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level. PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.

- 6 -