The W78C54 is a derivative of the W78C52 microcontroller family that provides extended internal
ROM. The chip has 16K bytes of mask ROM and 256 bytes of RAM.
This device provides an enhanced architecture that makes it more powerful and suitable for a variety
of applications for general control systems. It provides on-chip 16KB mask ROM to accommodate
large program codes, 256-bytes of non-volatile on-chip RAM, four 8-bit I/O ports, one 4-bit I/O port,
three 16-bit timer/counters, eight sources with two-level interrupt structures, and on-chip oscillator
clock circuits.
FEATURES
• DC to 40 MHz extensive operating frequency
• 256-byte on-chip scratch pad RAM
• 16K-byte on-chip mask ROM
• 64K-byte address space for external Program Memory
• 64K-byte address space for external Data Memory
• Three 16-bit timer/counters
Four 8-bit bit-addressable I/O ports
•
• One extra 4-bit bit-addressable I/O port, additional INT2/ INT3
EAIEXTERNAL ACCESS ENABLE: This pin forces the processor to execute out
of external ROM. The ROM address and data will not be present on the bus if
EA pin is high and the program counter is within the 16 KB area.
the
Otherwise they will be present on the bus.
PSENO H
ALEO HADDRESS LATCH ENABLE: ALE is used to enable the address latch that
RSTI LRESET: A high on this pin for two machine cycles while the oscillator is
XTAL1ICRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
XTAL2OCRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSSIGROUND: ground potential.
VDDIPOWER SUPPLY: Supply voltage for operation.
P0.0−P0.7
P1.0−P1.7
P2.0−P2.7
P3.0−P3.7
P4.0−P4.3
INT2 (P4.3)I HExternal interrupt 2: An extra interrupt input source. It cascades to pin P4.3
INT3 (P4.2)I HExternal interrupt 3: An extra interrupt input source. It cascades to pin P4.2
I/O DPORT 0: Function is the same as that of the standard 8052.
I/O HPORT 1: Function is the same as that of the standard 8052.
I/O HPORT 2: Function is the same as that of the standard 8052.
I/O HPORT 3: Function is the same as that of the standard 8052.
I/O HPORT 4: A 4-bit bi-directional parallel port and bit-addressable with internal
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus.
When internal ROM access is performed, no PSEN strobe signal outputs
originate from this pin.
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency. An ALE pulse is omitted during external data memory
accesses.
running resets the device.
external clock.
pull-ups. Pin P4.3 and P4.2 have alternative function as external interrupt
(INT2/INT3) source input.
internally.
internally.
* Note : TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Publication Release Date: December 1997
- 3 -Revision A2
BLOCK DIAGRAM
W78C54
P1.0
~
P1.7
P3.0
~
P3.7
P4.0
~
P4.3
INT2
INT3
Port
1
Port
Port
Port 1
Latch
ACC
Interrupt
Timer
2
Timer
0
Timer
1
UART
3
4
Port 3
Latch
Port 4
Latch
Oscillator
PSW
Instruction
Decoder
&
Sequencer
Bus & Clock
Controller
ALU
Reset Block
T2T1
SFR RAM
Address
256 bytes
RAM & SFR
B
Stack
Pointer
Power control
Port 0
Latch
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
16KB
ROM
Port 2
Latch
Port
0
Port
2
P0.0
~
P0.7
P2.0
~
P2.7
XTAL1PSENALEGNDVCCRSTXTAL2
Figure 2. Architecture of the W78C54
- 4 -
W78C54
FUNCTIONAL DESCRIPTION
The W78C54 is pin-to-pin compatible with the W78C52, except that the internal 8K mask ROM has
been replaced with 16K of internal mask ROM. The processor supports 111 different opcodes and
references both 64K program address space and 64K data storage space.
Clock
The W78C54 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78C54 relatively insensitive to duty cycle
variations in the clock.
Crystal Oscillator
The W78C54 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal is
connected across pins XTAL1 and XTAL2. In addition, a load capacitance of 30 pf (typically) must be
connected from each pin to ground. Resistor must also be connected from XTAL1 to XTAL2 to
provide a DC bias when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level greater than 3.5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDLE bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
W78C54 is used
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
Publication Release Date: December 1997
- 5 -Revision A2
W78C54
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3, whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
2. PORT4
Another bit-address port P4 is also available except only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1,except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources
(INT2/INT3).
Example:
P4REG0D8H
MOVP4, #0AH ; Output data "A" through P4.0−P4.3.
MOVA, P4; Read P4 status to Accumulator.
SETBP4.0; Set bit P4.0
CLRP4.1; Clear bit P4.1
Reduce EMI Emission
Because of the large on-chip mask-ROM, when a program is running in internal ROM space, the ALE
will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI
emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the
AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program
accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will
turn off again after it has been completely accessed or the program returns to internal ROM code
space..
POF Flag
The Power-Off-Reset flag is set by on-chip circuitry when the VCC level rises from 0 to 5V. The POF
bit can be set/cleared by software allowing a user to determine if the reset is the result of a power-on
or a warm up by external reset. To avoid effect of POF flag, the power voltage must remain above
3V.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature
of the W78C52C: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
- 6 -
W78C54
DESCRIPTIONS OF THE SPECIAL FUNCTION REGISTERS (SFRS)
Note: In column BIT_ADDRESS, SYMBOL, containing ( ) item means the bit address.
* SFRs modified or added to the W78C52. + Reset value depends on reset condition.
W78C54 SFRs address location map:
F8FF
F0+ BF7
E8EF
E0+ ACCE7
D8+P4DF
D0+ PSWD7
C8+T2CONRCAP2LRCAP2HTL2TH2CF
C0+XICONC7
B8+ IPBF
B0+ P3B7
A8+ IEAF
A0+ P2A7
98+ SCONSBUF9F
90+ P197
88+ TCONTMODTL0TL1TH0TH1AUXR8F
80+P0SPDPLDPHPCON87
Notes:
1. + SFR is bit-addressable.
2. is additional defined function.
Power-off Flag
***PCON - Power Control (87H)
SMODSMOD0
-
POF
SMOD: Double baud rate bit. When set to a 1, the baud rate is doubled when the serial port is
being used in either modes 1, 2, 3.
SMOD0: Enable FE bit in SCON. This bit is an alternative switch of SM0 and FE (Frame Error)
bit. When set to a 1, SCON.7 means a FE bit, otherwise a SM0 bit.
POF: Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD: Power down mode bit. Set it to enter power down mode.
IDL: Idle mode bit. Set it to enter idle mode.
The power-off flag is located at PCON.4. This bit is set when V
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
GF1GF0PDIDL
DD has been applied to the part. It can
- 8 -
* Interrupts
***IE - Interrupt Enable (A8H)
EA-ET2ESET1EX1ET0EX0
EA: Lobal interrupt enable flag
ET2: Timer 2 overflow interrupt enable
ES: Serial port interrupt enable
EX1: External interrupt 1 enable
ET1: Timer 1 overflow interrupt enable
EX0: External interrupt 0 enable
***IP - Interrupt Priority (B8H)
--PT2PSPT1PX1PT0PX0
PT2: Timer 2 interrupt priority high if set
PS: Serial port priority high if set
PT1: Timer 1 interrupt priority high if set
PX1: External interrupt 1 priority high if set
PT0: Timer 0 interrupt priority high if set
PX0: External interrupt 0 priority high if set
W78C54
***XICON - External Interrupt Control (C0H)
PX3EX3IE3IT3PX2EX2IE2IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
The W78C54 supports an eight-source and a four-priority-level interrupt architectures. Besides the
SFRs of IP and IE to control the six-source of the standard 8052 interrupt functions. There is an
another SFR (XICON) to control the extra two-source of the external interrrupt (INT2 and INT3). This
priority scheme is formed by combining IPH with IP to determine the priority of each interrupt. Except
the INT2 and INT3, they are not defined in IP
SFR but in XICON.
Publication Release Date: December 1997
- 9 -Revision A2
Following tables show the interrupt informations and priority definitions.
GATE: Gating control. When set, Timer/counter x is enabled only while INTx pin is high and TRx
control pin is set. When cleared, Timer x is enabled whenever the TRx conrol bit is set.
C//T: Timer or Counter Selector. Cleared for timer operation. Set for counter operation.
M1 M0: Operating Mode
0 0: 13-bit Timer/Counter.
0 1: 16-bit Timer/Counter.
1 0: 8-bit auto-reload Timer/Counter. THx holds a value which is to be reloaded into TLx
each time it overflows.
1 1: Timer 0: TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
Timer 1: Timer/counter 1 stopped.
***TCON - Timer 0, 1 Control (88H)
TF1TR1TF0TR0IE1IT1IE0IT0
TF1: Timer 1 overflow flag. Set by hardware on timer/counter overflow. cleared by hardware when
processor vectors to interrupt routine.
- 10 -
W78C54
TR1: Timer 1 run control bit. Set/cleared by software to turn timer/counter on or off.
TF0: Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when
processor vectors to interrupt routine.
TR0: Timer 0 run control bit. Set/cleared by software to turn timer/counter on or off.
IE1: Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when
interrupt processed.
IT1: Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupt.
IE0: Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when
interrupt processed.
IT0: Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupt.
***T2CON - Timer 2 Control (C8H)
TF2EXF2RCLKTCLKEXEN2TR2C//TCP//RL2
TF2:Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2 will
not be set when RCLK = 1 or TCLK = 1.
EXF2: Timer2 external flag. Set when either a capture or reload is caused by a negative transition
on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK: Receive clock flag. RCLK = 1 causes the serial port to use Timer 2 overflow pulses for its
receive clock in mode 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
TCLK: Transmit clock flag. TCLK = 1 causes the serial port to use Timer 2 overflow pulses for its
transmit clock in mode 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for the
transmit clock.
EXEN2: Timer 2 external enable flag. EXEN2 = 1 allows a capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not used to clock the serial port. EXEN2 = 0
causes Timer 2 to ignore events at T2EX.
TR2: TR2 = 1/0: turns on/off Timer 2.
C//T: Timer or Counter select. Set 1/0 for external event counter(falling edge triggered)/inter
timer.
CP//RL2: Capture/reload flag.
*Reduced EMI Mode
The AO bit in the AUXR register, when set, disables the ALE output.
***AUXR - Auxiliary Register (8EH)
-------AO
AO: Turn off ALE output.
Publication Release Date: December 1997
- 11 -Revision A2
W78C54
ABSOLUTE MAXIMUM RATINGS
PARAMETERSYMBOLMIN.MAX.UNIT
DC Power SupplyVCC−VSS-0.3+7.0V
Input VoltageVINVSS -0.3VCC +0.3V
Operating TemperatureTA070
Storage TemperatureTST-55+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
*1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 KΩ.
*3. P0, ALE and /PSEN are tested in the external access mode.
*4. XTAL1 is a CMOS input.
*5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V
VIH12.4VDD +0.2VVDD = 5.5V
VIH23.5VDD +0.2VVDD = 5.5V
VIH33.5VDD +0.2VVDD = 5.5V
VOL1-0.45VVDD = 4.5V
I
OL = +2 mA
VOL2-0.45VVDD = 4.5V
OL = +4 mA
I
ISK148mAVDD = 4.5V
Vs = 0.45V
ISK21014mAVDD = 4.5V
Vs = 0.45V
VOH12.4-VVDD = 4.5V
I
OH = -100 µA
VOH22.4-VVDD = 4.5V
I
OH = -400 µA
ISR1-120-180
µA
VDD = 4.5V
Vs = 2.4V
ISR2-10-14mAVDD = 4.5V
Vs = 2.4V
IN approximates to 2V.
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.8 micron CMOS process when using 2 and 4 mA output buffers.
Publication Release Date: December 1997
- 13 -Revision A2
CP), and actual parts will
Clock Input Waveform
W78C54
XTAL1
T
CH
F
Continued
OP,
T
CL
T
CP
PARAMETERSYMBOLMIN.TYP.MAX.UNITNOTES
Operating SpeedFOP0-40MHz1
Clock PeriodTCP25--nS2
Clock HighTCH10--nS3
Clock LowTCL10--nS3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The T
CP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
External Program Memory Fetch Cycle (see Figure 6)
PARAMETERSYMBOLMIN.TYP.MAX.UINTNOTES
Address Valid to ALE LowTAAS
Address Hold After ALE LowTAAH
T
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold After PSEN High
Data Float After PSEN High
APL
PDA--2TCPnS2
T
PDH0-1TCPnS3
T
PDZ0-1TCPnS
T
ALE Pulse WidthTALW
PSW
PSEN Pulse Width
Notes:
1. P00-P07, P20-P27 remain stable through entire memory cycle.
2. Memory access time is 3 Tcp.
3. Data has been latched internally prior to /PSEN going high.
4. ∆ is 20 ns (due to buffer driving delay and wire loading).
T
1TCP -∆
1TCP -∆
1TCP -∆
2TCP -∆
3TCP -∆
--nS
--nS1
CP
1T
2T
3T
CP
CP
1TCP+∆
2TCP +∆
3TCP +∆
nS
nS4
nS4
- 14 -
Data Read Cycle
External Data Memory Read Cycle (see Figure 7)
PARAMETERSYMBOLMIN.TYP.MAX.UINTNOTES
T
ALE Low to RD Low
RD Low to Data Valid
Data hold After RD High
Data Float After RD High
RD Pulse Width
Notes:
1. Data Memory access time is 5 Tcp.
2. ∆ is 20 ns (due to buffer driving delay and wire loading.
DAR
T
DDA--4 TcpnS1
DDH0-2 TcpnS
T
DDZ0-2 TcpnS
T
DRD
T
3 Tcp-∆
6 Tcp-∆
Data Write Cycle
External Data Memory Write Cycle (see Figure 8)
PARAMETERSYMBOLMIN.TYP.MAX.UINTNOTE
DAW
ALE Low to WR Low
Data Valid to WR Low
Data hold After WR High
WR Pulse Width
T
T
T
T
DAD
DWD
DWR
3 Tcp-∆
1 Tcp-∆
1 Tcp-∆
6 Tcp-∆
W78C54
3 Tcp
6 Tcp
3 Tcp
3 Tcp+∆
6 Tcp+∆
3 Tcp+∆
--nS
--nS
6 Tcp
6 Tcp+∆
nS1, 2
nS2
nS*
nS*
*Note: ∆ is 20 ns (due to buffer driving delay and wire loading)
Port Access Cycle
Port Access Cycle (see Figure 9)
PARAMETERSYMBOLMIN.TYP.MAX.UINT
Port Input Setup to ALE LowTPDS1Tcp--nS
Port Input Hold After ALE LowTPDH0--nS
Port Output to ALE HighTPDA
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
1Tcp-∆
Publication Release Date: December 1997
- 15 -Revision A2
--nS
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