Rainbow Electronics W78C54 User Manual

W78C54

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78C54 is a derivative of the W78C52 microcontroller family that provides extended internal
ROM. The chip has 16K bytes of mask ROM and 256 bytes of RAM.

This device provides an enhanced architecture that makes it more powerful and suitable for a variety
of applications for general control systems. It provides on-chip 16KB mask ROM to accommodate
large program codes, 256-bytes of non-volatile on-chip RAM, four 8-bit I/O ports, one 4-bit I/O port,
three 16-bit timer/counters, eight sources with two-level interrupt structures, and on-chip oscillator
clock circuits.

FEATURES

• DC to 40 MHz extensive operating frequency

• 256-byte on-chip scratch pad RAM

• 16K-byte on-chip mask ROM

• 64K-byte address space for external Program Memory

• 64K-byte address space for external Data Memory

• Three 16-bit timer/counters

Four 8-bit bit-addressable I/O ports

•

• One extra 4-bit bit-addressable I/O port, additional INT2/ INT3

(Available on 44-pin PLCC/QFP package)

• Eight-source, two priority-level interrupts

• Low EMI emission mode

• Built-in programmable power-saving modes - Idle mode & Power-down mode

• Packages:

− DIP 40: W78C54-16/24/40

− PLCC 44: W78C54P-16/24/40

− QFP 44: W78C54F-16/24/40

− TQFP 44: W78C54M-16/24/40

Publication Release Date: December 1997

- 1 - Revision A2

PIN CONFIGURATIONS

40-Pin DIP (W78C54)

T2, P1.0

T2EX, P1.1

P1.2

P1.3
P1.4

P1.5

P1.6

P1.7
RST

RXD, P3.0
TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL2
XTAL1

VSS

W78C54

VCC1

2

3
4

5
6

7

8

9
10

11

12
13

14
15

16

17
18

19

20

40

39

P0.0, AD0

38

P0.1, AD1

37

P0.2, AD2
P0.3, AD3

36
35

P0.4, AD4

34

P0.5, AD5
P0.6, AD6

33

P0.7, AD7

32

31

EA
ALE

30
29

PSEN

28

P2.7, A15
P2.6, A14

27
26

P2.5, A13

25

P2.4, A12

24

P2.3, A11

23

P2.2, A10
P2.1, A9

22
21

P2.0, A8

44-Pin PLCC (W78C54P)

T
2
E
X
,
P

P

P

P

1

1

1

1

.

.

.

.

1

3

4

2

6543

7

P1.5

8

P1.6

9

P1.7

10

RST

RXD, P3.

INT2, P4.3

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

11

12

13
14

15
16
17

P

P

X

X

3

3

T

T

.

.

A

A

6

7

L

L

,

,

2

1

/

/

W

R

R

D

/
I

A

N

T

D

T

2

0

3

,

,

,

P

P

P

1

0

V

4

C

.

.

.

0

0

C

2

2 1 44 43 42

P

P

V

P

S

2

2

4

S

.

.

.

0

1

0

,

,

A

A

8

9

44-Pin QFP/TQFP (W78C54F/W78C54M)

/

T

I

P
1
.
4

P
3
.
6
,
/
W
R

P

P

1

1

.

.

3

2

43 42 41

X

P

T

3

A

.

L

7

2

,
/
R
D

2
E

T

X

2

,

,

P

P

1

1

.

.

1

0

40 39 38 37 36

X

V

T

S
S

A
L
1

A

A

A

D

D

D

3

1

2

,

,

,
P

P

P

0

0

0

.

.

.

3

1

2

40

41

P

P
2

2
.

.
2

3
,

,

A

A
1

1
1

0

P0.4, AD4

39
38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P
2
.
4
,
A
1
2

RXD, P3.0

INT2, P4.3

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

P1.5

P1.6

P1.7

RST

1
2

3

4
5

6
7
8
9
10

11

A

A

A

N
T
3
,
P
4
.
2

P
4
.
0

A

D

D

D

D

1

3

0

2

,

,

,

,

P

P

P

P

0

0

0

0

V
C
C

P
2
.
0
,
A
8

.

.

.

.

1

3

0

2

34

3544

P

P

P

2

2

2

.

.

.

1

3

2

,

,

,
A

A

A

9

1

1
1

0

P0.4, AD4

33
32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

2221201918171615141312

P
2
.
4
,
A
1
2

- 2 -

W78C54

PIN DESCRIPTION

SYMBOL TYPE DESCRIPTIONS

EA I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out

of external ROM. The ROM address and data will not be present on the bus if

EA pin is high and the program counter is within the 16 KB area.

the
Otherwise they will be present on the bus.

PSEN O H

ALE O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that

RST I L RESET: A high on this pin for two machine cycles while the oscillator is

XTAL1 I CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an

XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.

VSS I GROUND: ground potential.

VDD I POWER SUPPLY: Supply voltage for operation.

P0.0−P0.7

P1.0−P1.7

P2.0−P2.7

P3.0−P3.7

P4.0−P4.3

INT2 (P4.3) I H External interrupt 2: An extra interrupt input source. It cascades to pin P4.3

INT3 (P4.2) I H External interrupt 3: An extra interrupt input source. It cascades to pin P4.2

I/O D PORT 0: Function is the same as that of the standard 8052.

I/O H PORT 1: Function is the same as that of the standard 8052.

I/O H PORT 2: Function is the same as that of the standard 8052.

I/O H PORT 3: Function is the same as that of the standard 8052.

I/O H PORT 4: A 4-bit bi-directional parallel port and bit-addressable with internal

PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus.

When internal ROM access is performed, no PSEN strobe signal outputs
originate from this pin.

separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency. An ALE pulse is omitted during external data memory
accesses.

running resets the device.

external clock.

pull-ups. Pin P4.3 and P4.2 have alternative function as external interrupt
(INT2/INT3) source input.

internally.

internally.

* Note : TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

Publication Release Date: December 1997

- 3 - Revision A2

BLOCK DIAGRAM

W78C54

P1.0
~
P1.7

P3.0
~
P3.7

P4.0
~
P4.3

INT2

INT3

Port

1

Port

Port

Port 1

Latch

ACC

Interrupt

Timer

2

Timer

0

Timer

1

UART

3

4

Port 3

Latch

Port 4
Latch

Oscillator

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

ALU

Reset Block

T2T1

SFR RAM

Address

256 bytes

RAM & SFR

B

Stack

Pointer

Power control

Port 0

Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

16KB
ROM

Port 2

Latch

Port
0

Port
2

P0.0
~
P0.7

P2.0
~
P2.7

XTAL1 PSENALE GNDVCCRSTXTAL2

Figure 2. Architecture of the W78C54

- 4 -

W78C54

FUNCTIONAL DESCRIPTION

The W78C54 is pin-to-pin compatible with the W78C52, except that the internal 8K mask ROM has
been replaced with 16K of internal mask ROM. The processor supports 111 different opcodes and
references both 64K program address space and 64K data storage space.

Clock

The W78C54 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78C54 relatively insensitive to duty cycle
variations in the clock.

Crystal Oscillator

The W78C54 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal is
connected across pins XTAL1 and XTAL2. In addition, a load capacitance of 30 pf (typically) must be
connected from each pin to ground. Resistor must also be connected from XTAL1 to XTAL2 to
provide a DC bias when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level greater than 3.5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDLE bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

W78C54 is used

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:

Publication Release Date: December 1997

- 5 - Revision A2