Rainbow Electronics Preliminary User Manual

Features

•

Single Voltage Operation

–5V Read
– 5V Programming

•

Fast Read Access Time - 55 ns

•

Internal Erase/Program Control

•

Sector Architecture

– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 4K Words (8K bytes) Parameter Blocks
– One 240K Words (480K bytes) Main Memory Array Block

•

Fast Sector Erase Time - 10 seconds

•

Byte-by-Byte or Word-By-Word Programming - 10 µs Typical

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Low-Power Dissipation

– 50 mA Active Current
– 300 µA CMOS Standby Current

•

Typical 10,000 Write Cycles

Description

The AT49F004(T) and AT49F 4096A(T) are 5-volt, 4-megabit Flash Memori es orga­nized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured
with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times
to 55 ns with power dissipation of just 275 mW. When deselected, the CMOS standby
current is less than 300 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT4 9F004/40 96A lo cates the boot bloc k at low est order
addresses (“bottom boot”); the AT49F004T/4096AT locates it at highest o rder
addresses (“top boot”).

To allow for simple in-system reprogrammability, the AT49F004(T)/4096A(T) does not
require high input v ol tage s for p rogr amm in g. R ead ing data out of the devic e is s imil ar
to reading from an EPROM; it has standard CE
tention. Reprogramming the AT49F004(T)/4096A(T) is performed by first erasing a

, OE, and WE inputs to avoid bus con-

(continued)

Pin Configurations

4-Megabit
(512K x 8/
256K x 16)
Flash Memory

AT49F004
AT49F004T
AT49F4096A
AT49F4096AT
Preliminary

Pin Name Function

A0 - A18 Addresses
CE
OE
WE Write Enable
RESET
RDY/BUSY
I/O0 - I/O14 Data Inputs/Outputs

I/O15(A-1)

BYTE
NC No Connect

Chip Enable
Output Enable

Reset
Ready/Busy Output

I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

Rev. 1167A–09/98

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A16
A15
A14
A13
A12
A11

A9
A8

WE

RESET

NC

RDY/BUSY

A18

A7
A6
A5
A4
A3
A2
A1

A17
GND
NC
NC
A10
I/O7
I/O6
I/O5
I/O4
VCC
VCC
NC
I/O3
I/O2
I/O1
I/O0
OE
GND
CE
A0

AT49F4096A(T) SOIC (SOP)

AT49F4096A(T) TSOP Top View

Type 1

AT49F004(T) TSOP Top View

Type 1

1

A15
A14
A13
A12
A11
A10

WE

RESET

A17

2
3
4
5
6
7

A9

8

A8

9

NC

10

NC

11
12
13

NC

14

NC

15

NC

16

NC

17
18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

A17

GND

I/O0
I/O8
I/O1
I/O9
I/O2

I/O10

I/O3

I/O11

NC
NC

CE

OE

1
2
3
4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12
13
14
15
16
17
18
19
20
21
22

44

RESET

43

WE

42

A8

41

A9

40

A10

39

A11

38

A12

37

A13

36

A14

35

A15

34

A16

33

BYTE

32

GND

31

I/O15/A-1

30

I/O7

29

I/O14

28

I/O6

27

I/O13

26

I/O5

25

I/O12

24

I/O4

23

VCC

block of data an d then p rogrammi ng on a byte-by -byte or
word-by-word basis.

The device is erased by executing the er ase command
sequence; the device internally controls the erase opera­tion. The memory is divided into four bloc k s for eras e oper ­ations. There are two 4K word parameter block sections,
the boot block, and the main memor y array blo ck. Th e typ i­cal number of program and erase cycles is in excess of
10,000 cycles.

The 8K word boot block section includes a reprogramming
lock out feature to provide data integrity. This feature is
enabled by a command sequence. Once the boot block
programming lockout feature is enabled, the data in the

48

A16

47

BYTE

46

GND

45

I/O15 / A-1

44

I/O7

43

I/O14

42

I/O6

41

I/O13

40

I/O5

39

I/O12

38

I/O4

37

VCC

36

I/O11

35

I/O3

34

I/O10

33

I/O2

32

I/O9

31

I/O1

30

I/O8

29

I/O0

28

OE

27

GND

26

CE

25

A0

boot block cannot be chang ed when input levels of 5 .5
volts or less are used. The boot sector is designed to con­tain user secure code.

For the AT49F4096A(T), the BYTE

pin controls whether
the device data I/O pi ns op er ate in the by te or wo rd c onfig­uration. If the BYTE

pin is set at a logi c “1” o r lef t ope n, the
device is in word co nfigurat ion, I/O0 - I/O15 are activ e and
controlled by CE

If the BYTE

and OE.

pin is set at logic “0”, the devi ce is in byte con­figuration, and only data I/O pins I/O 0 - I/O7 ar e active an d
controlled by CE

and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.

2

AT49F004/4096A(T)

AT49F004(T) Block Diagram

VCC

GND

OE

WE

CE

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

AT49F4096A(T) Block Diagram

VCC

GND

OE

WE

CE

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

AT49F004 AT49F004T

DATA INPUTS/OUTPUTS

I/O0 - I/O7

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES
Y-GATING

MAIN MEMORY

(480K BYTES)
PARAMETER

BLOCK 2

8K BYTES

PARAMETER

BLOCK 1

8K BYTES

BOOT BLOCK

16K BYTES

AT49F4096A AT49F4096AT

DATA INPUTS/OUTPUTS

I/O0 - I/O15

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES
Y-GATING

MAIN MEMORY
(240K WORDS)

PARAMETER

BLOCK 2

4K WORDS

PARAMETER

BLOCK 1

4K WORDS

BOOT BLOCK

8K WORDS

AT49F004/4096A(T)

DATA INPUTS/OUTPUTS

I/O0 - I/O7

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

7FFFF 7FFFF

08000

07FFF

06000

05FFF

04000

03FFF
00000 00000

DATA INPUTS/OUTPUTS

3FFFF 3FFFF

04000

03FFF
03000

02FFF

02000

01FFF
00000 00000

Y-GATING

BOOT BLOCK

16K BYTES

PARAMETER

BLOCK 1

8K BYTES

PARAMETER

BLOCK 2

8K BYTES

MAIN MEMORY

480K BYTES

I/O0 - I/O15

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES
Y-GATING

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK 1

4K WORDS

PARAMETER

BLOCK 2

4K WORDS

MAIN MEMORY
(240K WORDS)

7C000
7BFFF

7A000
79FFF

78000
77FFF

3E000
3DFFF

3D000

3CFFF

3C000

3BFFF

Device Operation

READ:

EPROM. When CE
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE
high. This dual-line con tr ol gi v es d esign er s fl ex ibi lit y in pr e­venting bus contention.

COMMAND SEQUENCES:

ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command

The AT49F004(T)/4096A(T) is accessed like an

and OE are low and WE is high, th e

or OE is

When the device is first pow-

sequences are shown in the Com mand Definition s table
(I/O8 - I/O15 are don’t care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE
tively) and OE
edge of CE
latched by the first rising edge of CE

or CE input with CE or WE low (respec-

high. The address is latched on the falling

or WE, whichever occurs last. The data is

or WE. Standard
microprocessor write timings are used. The address loca­tions used in the command sequences are not affected by
entering the command sequences.

RESET:

A RESET

tem applications. When RESET

input pin is prov ided to eas e so me s ys-

is at a logic high level, the

3

device is in its standa rd oper at ing mod e. A low l ev el on the
RESET
the outputs of the de vice in a hi gh imped ance stat e. When
a high level is reasse rted on the RES ET
returns to the Read or Standby mod e, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RE SE T
grammed even if the boot block program lockout feature
has been enable d (see Boot B lock Pr ogrammi ng Lock out
Override section).

ERASURE:

must be erased. The erased state of memory bits is a logi­cal “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase commands.

CHIP ERASE:

by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is t

If the boot block lockou t has be en enabled, the Ch ip Eras e
will not erase the data in t he boot block; it wil l erase the
main memory block and the parameter blocks only. After
the chip erase, the de vi ce wi ll retu rn to the read or standby
mode.

SECTOR ERASE:

device is organized into four sectors that can be individually
erased. There are two 4K word parameter block sections,
one boot block, and the main memory array block. The
Sector Erase command is a six bus cycle operation. The
sector address is latched on the falling WE
sixth cycle while the 30 H data in put com mand is la tched at
the rising edge of WE
ing edge of WE
internally controlled; it will automatically time to completion.
Whenever the main memory block is erased and repro­grammed, the two parame ter bloc ks should be erased and
reprogrammed before the main memory block is erased
again. Whenever a parameter block is erased and repro­grammed, the other parameter block should be erased and
reprogrammed before the first parameter block is erased
again. Whenever the boot block is erased and repro­grammed, the ma in memory block and th e parameter
blocks should be erased and reprogrammed before the
boot block is erased again.

BYTE/WORD PROGRAMMING:

erased, it is programmed (to a logical “0”) on a byte-by-byte
or word-by-word bas is. Progr amming is accom plished via
the internal device command register and is a 4 bus cycle
operation. The device will automatically generate the
required internal program pulses.

Any commands written to the c hip during the em bedded
programming cycle will be ignored. If a hardware reset hap-

input halts the prese nt device oper ation and puts

pin, the device

pin the boot blo ck ar ray c an b e r epro-

Before a byte or word can be reprogrammed, it

The entire device can be erased at one time

.

EC

As an alternative to a full chip erase, the

edge of the

. The sector erase s tar ts after the ris-

of the sixth cycle. The erase o peration is

Once a memory block is

pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “ 0”s to “ 1”s. Pro grammi ng is co mplete d after
the specified t
also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

has one designated block that has a programming lockout
feature. This feature prevents programming of data in th e
designated block once the feature has been enabled. The
size of the block is 8K words. Thi s blo ck, refe rred to a s the
boot block, can contain secure code that is used to bring up
the system. Enablin g the l ockou t feature w ill al low the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti­vated; the boot block’ s u sag e as a wr i te pro t ected r eg io n is
optional to the user. The address range of the boot block is
00000H to 03FFFH for the AT49F004; 7C000H to 7FFFFH
for the AT49F004T; 00000H to 01FFFH for the
AT49F4096A; and 3E000H to 3FFFFH for the
AT49F4096AT.

Once the feature is enabled, the data in the boot blo ck ca n
no longer be erased or programmed when input levels of

5.5V or less are u sed. Dat a in the ma in memo ry bloc k can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot
block section is locked out. When the device is in the soft­ware product identification mode (see Software Product
Identification Entry and Exit section s) a read from the fol­lowing address location will show if programming the boot
block is locked out—00002H for AT49F004 and
AT49F4096A; 7C002 for the AT49F004T; and 3E002H for
the AT49F4096AT. If the data on I/O0 is low, the boot block
can be programmed; if the data on I/O0 is high, the pro­gram lockout featu re has been en abled an d the block can­not be programmed. The software product identification
exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override th e boot blo ck progr amming lo ckout
by taking the RESET
erase, sector erase or word pro grammin g oper ation. W hen
the RESET
programming lockout feature is again active.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro­grammer to identify the correct programming algorithm for
the Atmel product.

cycle time. The DATA polling feature may

BP

The device

A software

pin to 12 volts during the entire chip

pin is brought back to TTL levels the boot block

The product identification

4

AT49F004/4096A(T)

AT49F004/4096A(T)

For details, see O peratin g Modes (for har dware operatio n)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING:

polling to indic ate the en d o f a program cycle. Dur in g

DATA

The AT49F004(T)/4096A(T) features

a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and th e next cyc le may be gin. Du ring a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.

polling may begi n at any ti me during the program

DATA
cycle.

TOGGLE BIT:

In addition to DATA

polling the
AT49F004(T)/4096A(T) p rovi des another method for deter­mining the end of a program or erase cycle. During a pro­gram or erase o pera tion, succe ssiv e atte mpts to r ead data
from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop

toggling and valid data will be read . Examining the toggle
bit may begin at any time during a program cycle.

READY/BUSY

drain READY/BUSY

:

For the AT49F004 (T), pin 12 is an open

output pin whic h provides anot her
method of detecting the end of a program or erase opera­tion. RDY/BUSY

is actively pulled low during the internal
program and erase cycles and it is rele ased at the co mple­tion of the cycle. The open drain connec tion allow s for OR­tying of several devices to the same RDY/BUSY

HARDWARE DATA PROTECTION:

Hardware features

line.

protect against inadvertent programs to the
AT49F004(T)/4096A(T ) in the following wa ys: (a) V

CC

sense: if VCC is below 3.8V (typical), the program function
is inhibited. (b) V
the V

sense level, the device will automaticall y time out

CC

power on delay: onc e VCC has reached

CC

10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE

low, CE high or WE h igh inhi bits
program cycles. (d) Noise filter: pulses o f less than 15 ns
(typical) on the WE

or CE inputs will not initiate a program

cycle.

5

Command Definition (in Hex)

(1)

1st Bus

Command
Sequence

Read 1 Addr D
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA
Byte/Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D
Boot Block Lockout
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

(3)

(3)

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t Care)

2. The boot sector has the address range 00000H to 03FFFH for the AT49F004; 7C000H to 7FFFFH for the AT49F004T;
00000H to 01FFFH for the AT49F4096A; and 3E000H to 3FFFFH for the AT49F4096AT.

3. Either one of the Product ID Exit commands can be used.

4. SA = sector addresses: (A18 - A0)
For the AT49F004
SA = 03XXX for BOOT BLOCK
SA = 05XXX for PARAMETER BLOCK 1
SA = 07XXX for PARAMETER BLOCK 2
SA = 7FXXX for MAIN MEMORY ARRAY

Bus
Cycles

(2)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0
1xxxxF0

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

IN

SA = sector addresses: (A17 - A0)
For the AT49F4096A
SA = 01XXX for BOOT BLOCK
SA = 02XXX for PARAMETER BLOCK 1
SA = 03XXX for PARAMETER BLOCK 2
SA = 3FXXX for MAIN MEMORY ARRAY

5th Bus

Cycle

6th Bus

Cycle

(4)

30

For the AT49F004(T)
SA = 7FXXX for BOOT BLOCK
SA = 7BXXX for PARAMETER BLOCK 1
SA = 79XXX for PARAMETER BLOCK 2
SA = 77XXX for MAIN MEMORY ARRAY

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on RESET

with Respect to Ground...................................-0.6V to +13.5V

+ 0.6V

CC

For the AT49F4096AT
SA = 3FXXX for BOOT BLOCK
SA = 3DXXX for PARAMETER BLOCK 1
SA = 3CXXX for PARAMETER BLOCK 2
SA = 3BXXX for MAIN MEMORY ARRAY

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a s tress rating only an d
functional oper ation of the device at thes e or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .

6

AT49F004/4096A(T)

AT49F004/4096A(T)

DC and AC Operating Range

AT49F004(T)/4096A(T)-55 AT49F004(T)/4096A(T)-70 AT49F004(T)/4096A(T)-90

Operating
Temperature (Case)

V

Power Supply 5V ± 10% 5V ± 10% 5V ± 10%

CC

Com. 0°C - 70°C0
Ind. N/A -40°C - 85°C-40

Operating Modes

Mode CE OE WE RESET Ai I/O

Read V
Program/Erase

(2)

Standby/Program
Inhibit

IL

V

IL

V

IH

V

IL

V

IH

(1)

X

Program Inhibit X X V
Program Inhibit X V
Output Disable X V

IL

IH

Reset X X X V
Product Identification

Hardware V

Software

(5)

IL

V

IL

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

= 12.0V ± 0.5V.

3. V

H

4. Manufacturer Code: 161FH
Device Code: 11H (AT49F004), 1692H (AT49F4096A), 10H (AT49F004T), 1690H (AT49F4096AT).

5. See details under Software Product Identification Entry/Exit.

V

IH

V

IL

XV

IH

XV
XV

V

IH

V

IH

V

IH

IH

V

IH

IH

IH

IL

V

IH

V

IH

°

C - 70°C0

Ai D
Ai D

OUT

IN

X High Z

High Z

X High Z

A1 - A18 = VIL, A9 = VH,

A0 = V

A1 - A18 = VIL, A9 = VH,

A0 = V
A0 = VIL, A1 - A18 = V
A0 = VIH, A1 - A18 = V

(3)

IL

IH

Manufacturer Code

(3)

Device Code

Manufacturer Code

IL

Device Code

IL

°

C - 70°C

°

C - 85°C

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

(1)

I

CC

V

IL

V

IH

V

OL

V

OH

Input Load Current VIN = 0V to V
Output Leakage Current V
VCC Standby Current CMOS CE = VCC - 0.3V to V
VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -400 µA 2.4 V

Note: 1. In the e rase mode, I

is 90 mA.

CC

= 0V to V

I/O

CC

CC

CC

CC

= 0 mA 50 mA

OUT

10 µA
10 µA

300 µA

3mA

7

AC Read Characteristics

5.0V

5.0V

90 ns55/70 ns

30

Symbol Parameter

t

ACC

(1)

t

CE

(2)

t

OE

(3)(4)

t

DF

t

OH

t

RO

Address to Output Delay 55 70 90 ns
CE to Output Delay 55 70 90 ns
OE to Output Delay 0 30 0 35 0 40 ns
CE or OE to Output Float 0 2 5 0 25 0 25 ns
Output Hold from OE,CE or Address,

whichever occurred first
RESET to Output Delay 800 800 800 ns

AT49F004(T)/4096A(T)-55 AT49F004(T)/4096A(T)-70 AT49F004(T)/4096A(T)-90

UnitsMin Max Min Max Min Max

000ns

AC Read Waveforms

Notes: 1. CE may be delayed up to t

(1)(2)(3)(4)

ADDRESS

CE

OE

RESET

OUTPUT

- tCE after the address transition without impact on t

ACC

ADDRESS VALID

t

ACC

t

RO

HIGH Z

t

CE

t

OE

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impac t on tCE or by t
without impact on t

ACC

.

3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and Measurement Level

OUTPUT

VALID

t

DF

t

OH

.

ACC

- tOE after an address c han ge

ACC

Output Test Load

3.0V

0.0V

tR, tF < 5 ns

Pin Capacitance

f = 1 MHz, T = 25°C

Symbol Typ Max Units Conditions

C

IN

C

OUT

Note: 1. This parameter is characterized and is not 100% tested.

8

(1)

46pFV
812pFV

AT49F004/4096A(T)

IN

OUT

= 0V

= 0V

AT49F004/4096A(T)

AC Word Load Characteristics

Symbol Parameter Min Max Units

tAS, t

OES

t

AH

t

CS

t

CH

t

WP

t

DS

tDH, t

OEH

t

WPH

AC Byte/Word Load Waveforms

WE Controlled

Address, OE Set-up Time 10 ns
Address Hold Time 100 ns
Chip Select Set-up Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE) 100 ns
Data Set-up Time 100 ns
Data, OE Hold Time 10 ns
Write Pulse Width High 50 ns

CE Controlled

9

Program Cyc le Characteristics

Symbol Parameter Min Typ Max Units

t

BP

t

AS

t

AH

t

DS

t

DH

t

WP

t

WPH

t

EC

Byte/Word Programming Time 10 50 µs
Address Set-up Time 0 ns
Address Hold Time 100 ns
Data Set-up Time 100 ns
Data Hold Time 0 ns
Write Pulse Width 100 ns
Write Pulse Width High 50 ns
Erase Cycle Time 10 seconds

Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t

WP

WE

t

DH

2AAA

t

DS

55

A0-A18

DATA

t

AS

t

AH

5555 5555

AA

Sector or Chip Erase Cycle Waveforms

(1)

OE

CE

WE

A0-A18

DATA

t

WP

t

AS

5555

t

AH

AA

BYTE/

WORD 0

t

DH

2AAA 2AAA

t

DS

BYTE/

WORD 1

t

WPH

5555

55 55

WORD 2

80

BYTE/

t

WPH

t

BP

ADDRESS

A0

5555

AA

BYTE/

WORD 3

INPUT DATA

WORD 4

BYTE/

Note 2

Note 3

BYTE/

WORD 5

5555

AA

t

EC

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

10

AT49F004/4096A(T)

AT49F004/4096A(T)

Data Po lling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay

(2)

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in AC Read Characteristics.

Data Polling Waveforms

WE

CE

OE

tDH

I/O7

A0-A18

tOEH

tOE

HIGH Z

An An An

An

tWR

An

ns

Toggle Bit Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay

(2)

OE High Pulse 150 ns
Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in AC Read Characteristics.

Toggle Bit Waveforms

(1)(2)(3)

ns

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

specification must be met by the toggling

OEHP

11

Software Product Identification Entry

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 80

TO

ADDRESS 5555

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 40

TO

ADDRESS 5555

PAUSE 1 second

(2)

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 90

TO

ADDRESS 5555

ENTER PRODUCT

IDENTIFICATION

(2)(3)(5)

MODE

(1)

Boot Block
Lockout Enable Algorithm

(1)

Software Product Identification Exit

LOAD DATA AA

TO

ADDRESS 5555

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA F0

TO

ADDRESS 5555

EXIT PRODUCT

IDENTIFICATION

2.

3. The device does not remain in identification mode if pow-

4. The device returns to standard operation mode.

5. Manufacturer Code: 161FH

6. Either one of the Product ID Exit commands can be used.

(4)

MODE

Address Format: A15 - A0 (Hex), A-1, and A15 - A18
(Don’t Care).

A1 - A18 = VIL.
Manufacture Code is read for A0 = V
Device Code is read for A0 = V

ered down.

Device Code: 11H (AT49F004), 1692H (AT49F4096A),
1692H (AT49F004T), 1690H (AT49F4096AT)

OR

LOAD DATA F0

TO

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

.

IH

MODE

;

IL

(4)

(1)(6)

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A15 - A0 (Hex), A-1, and A15 - A18
(Don’t Care).

2. Boot block lockout feature enabled.

12

AT49F004/4096A(T)

AT49F004/4096A(T)

AT49F0 04(T) Ordering Information

I

(mA)

t

ACC

(ns)

55 50 0.3 AT49F004-55TC 40T Commercial

70 50 0.3 AT49F004-70TC 40T Commercial

90 50 0.3 AT49F004-90TC 40T Commercial

55 50 0.3 AT49F004T-55TC 40T Commercial

70 50 0.3 AT49F004T-70TC 40T Commercial

90 50 0.3 AT49F004T-90TC 40T Commercial

CC

Standby

Ordering Code Package Operation RangeActive

(0° to 70°C)

(0° to 70°C)

AT49F004-70TI 40T Industrial

(-40° to 85°C)

(0° to 70°C)

AT49F004-90TI 40T Industrial

(-40° to 85°C)

(0° to 70°C)

(0° to 70°C)

AT49F004T-70TI 40T Industrial

(-40° to 85°C)

(0° to 70°C)

AT49F004T-90TI 40T Industrial

(-40° to 85°C)

Package Type

40T 40-Lead, Plastic Thin Small Outline Package (TSOP)

13

AT49F4096A(T) Ordering Information

I

(mA)

t

ACC

(ns)

55 50 0.3 AT49F4096A-55RC

70 50 0.3 AT49F4096A-70RC

90 50 0.3 AT49F4096A-90RC

55 50 0.3 AT49F4096AT-55RC

70 50 0.3 AT49F4096AT-70RC

90 50 0.3 AT49F4096AT-90RC

CC

Ordering Code Package Operation RangeActive Standby

AT49F4096A-55TC

AT49F4096A-70TC
AT49F4096A-70RI

AT49F4096A-70TI

AT49F4096A-90TC
AT49F4096A-90RI

AT49F4096A-90TI

AT49F4096AT-55TC

AT49F4096AT-70TC
AT49F4096AT-70RI

AT49F4096AT-70TI

AT49F4096AT-90TC
AT49F4096AT-90RI

AT49F4096AT-90TI

44R
48T

44R
48T

44R
48T

44R
48T

44R
48T

44R
48T

44R
48T

44R
48T

44R
48T

44R
48T

Commercial
(0° to 70°C)

Commercial
(0° to 70°C)

Industrial

(-40° to 85°C)

Commercial
(0° to 70°C)

Industrial

(-40° to 85°C)

Commercial
(0° to 70°C)

Commercial
(0° to 70°C)

Industrial

(-40° to 85°C)

Commercial
(0° to 70°C)

Industrial

(-40° to 85°C)

Package Type

44R 44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline (SOIC)
48T 48-Lead, Plastic Thin Small Outline Package (TSOP)

14

AT49F004/4096A(T)

Packaging Information

AT49F004/4096A(T)

44R

, 44-Lead, 0.525" Wide, Plastic Gull Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)

40T

, 40-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Inches and (Millimeters)

*Controlling dimension: millimeters

48T

, 48-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*

JEDEC OUTLINE MO-142 D

*Controlling dimension: millimeters

15

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e-mail

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BBS

1-[phone]

© Atmel Corporation 1998.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war ­ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop­erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.

®

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