Rainbow Electronics Preliminary User Manual

Features

•

Single Voltage Operation

–5V Read
– 5V Programming

•

Fast Read Access Time - 55 ns

•

Internal Erase/Program Control

•

Sector Architecture

– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 4K Words (8K bytes) Parameter Blocks
– One 240K Words (480K bytes) Main Memory Array Block

•

Fast Sector Erase Time - 10 seconds

•

Byte-by-Byte or Word-By-Word Programming - 10 µs Typical

•

Hardware Data Protection

•

DAT A Polling For End Of Program Detection

•

Low-Power Dissipation

– 50 mA Active Current
– 300 µA CMOS Standby Current

•

Typical 10,000 Write Cycles

Description

The AT49F004(T) and AT49F 4096A(T) are 5-volt, 4-megabit Flash Memori es orga­nized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured
with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times
to 55 ns with power dissipation of just 275 mW. When deselected, the CMOS standby
current is less than 300 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT4 9F004/40 96A lo cates the boot bloc k at low est order
addresses (“bottom boot”); the AT49F004T/4096AT locates it at highest o rder
addresses (“top boot”).

To allow for simple in-system reprogrammability, the AT49F004(T)/4096A(T) does not
require high input v ol tage s for p rogr amm in g. R ead ing data out of the devic e is s imil ar
to reading from an EPROM; it has standard CE
tention. Reprogramming the AT49F004(T)/4096A(T) is performed by first erasing a

, OE, and WE inputs to avoid bus con-

(continued)

Pin Configurations

4-Megabit
(512K x 8/
256K x 16)
Flash Memory

AT49F004
AT49F004T
AT49F4096A
AT49F4096AT
Preliminary

Pin Name Function

A0 - A18 Addresses
CE
OE
WE Write Enable
RESET
RDY/BUSY
I/O0 - I/O14 Data Inputs/Outputs

I/O15(A-1)

BYTE
NC No Connect

Chip Enable
Output Enable

Reset
Ready/Busy Output

I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

Rev. 1167A–09/98

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A16
A15
A14
A13
A12
A11

A9
A8

WE

RESET

NC

RDY/BUSY

A18

A7
A6
A5
A4
A3
A2
A1

A17
GND
NC
NC
A10
I/O7
I/O6
I/O5
I/O4
VCC
VCC
NC
I/O3
I/O2
I/O1
I/O0
OE
GND
CE
A0

AT49F4096A(T) SOIC (SOP)

AT49F4096A(T) TSOP Top View

Type 1

AT49F004(T) TSOP Top View

Type 1

1

A15
A14
A13
A12
A11
A10

WE

RESET

A17

2
3
4
5
6
7

A9

8

A8

9

NC

10

NC

11
12
13

NC

14

NC

15

NC

16

NC

17
18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

A17

GND

I/O0
I/O8
I/O1
I/O9
I/O2

I/O10

I/O3

I/O11

NC
NC

CE

OE

1
2
3
4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12
13
14
15
16
17
18
19
20
21
22

44

RESET

43

WE

42

A8

41

A9

40

A10

39

A11

38

A12

37

A13

36

A14

35

A15

34

A16

33

BYTE

32

GND

31

I/O15/A-1

30

I/O7

29

I/O14

28

I/O6

27

I/O13

26

I/O5

25

I/O12

24

I/O4

23

VCC

block of data an d then p rogrammi ng on a byte-by -byte or
word-by-word basis.

The device is erased by executing the er ase command
sequence; the device internally controls the erase opera­tion. The memory is divided into four bloc k s for eras e oper ­ations. There are two 4K word parameter block sections,
the boot block, and the main memor y array blo ck. Th e typ i­cal number of program and erase cycles is in excess of
10,000 cycles.

The 8K word boot block section includes a reprogramming
lock out feature to provide data integrity. This feature is
enabled by a command sequence. Once the boot block
programming lockout feature is enabled, the data in the

48

A16

47

BYTE

46

GND

45

I/O15 / A-1

44

I/O7

43

I/O14

42

I/O6

41

I/O13

40

I/O5

39

I/O12

38

I/O4

37

VCC

36

I/O11

35

I/O3

34

I/O10

33

I/O2

32

I/O9

31

I/O1

30

I/O8

29

I/O0

28

OE

27

GND

26

CE

25

A0

boot block cannot be chang ed when input levels of 5 .5
volts or less are used. The boot sector is designed to con­tain user secure code.

For the AT49F4096A(T), the BYTE

pin controls whether
the device data I/O pi ns op er ate in the by te or wo rd c onfig­uration. If the BYTE

pin is set at a logi c “1” o r lef t ope n, the
device is in word co nfigurat ion, I/O0 - I/O15 are activ e and
controlled by CE

If the BYTE

and OE.

pin is set at logic “0”, the devi ce is in byte con­figuration, and only data I/O pins I/O 0 - I/O7 ar e active an d
controlled by CE

and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.

2

AT49F004/4096A(T)

AT49F004(T) Block Diagram

VCC

GND

OE

WE

CE

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

AT49F4096A(T) Block Diagram

VCC

GND

OE

WE

CE

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

AT49F004 AT49F004T

DATA INPUTS/OUTPUTS

I/O0 - I/O7

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES
Y-GATING

MAIN MEMORY

(480K BYTES)
PARAMETER

BLOCK 2

8K BYTES

PARAMETER

BLOCK 1

8K BYTES

BOOT BLOCK

16K BYTES

AT49F4096A AT49F4096AT

DATA INPUTS/OUTPUTS

I/O0 - I/O15

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES
Y-GATING

MAIN MEMORY
(240K WORDS)

PARAMETER

BLOCK 2

4K WORDS

PARAMETER

BLOCK 1

4K WORDS

BOOT BLOCK

8K WORDS

AT49F004/4096A(T)

DATA INPUTS/OUTPUTS

I/O0 - I/O7

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

7FFFF 7FFFF

08000

07FFF

06000

05FFF

04000

03FFF
00000 00000

DATA INPUTS/OUTPUTS

3FFFF 3FFFF

04000

03FFF
03000

02FFF

02000

01FFF
00000 00000

Y-GATING

BOOT BLOCK

16K BYTES

PARAMETER

BLOCK 1

8K BYTES

PARAMETER

BLOCK 2

8K BYTES

MAIN MEMORY

480K BYTES

I/O0 - I/O15

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES
Y-GATING

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK 1

4K WORDS

PARAMETER

BLOCK 2

4K WORDS

MAIN MEMORY
(240K WORDS)

7C000
7BFFF

7A000
79FFF

78000
77FFF

3E000
3DFFF

3D000

3CFFF

3C000

3BFFF

Device Operation

READ:

EPROM. When CE
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE
high. This dual-line con tr ol gi v es d esign er s fl ex ibi lit y in pr e­venting bus contention.

COMMAND SEQUENCES:

ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command

The AT49F004(T)/4096A(T) is accessed like an

and OE are low and WE is high, th e

or OE is

When the device is first pow-

sequences are shown in the Com mand Definition s table
(I/O8 - I/O15 are don’t care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE
tively) and OE
edge of CE
latched by the first rising edge of CE

or CE input with CE or WE low (respec-

high. The address is latched on the falling

or WE, whichever occurs last. The data is

or WE. Standard
microprocessor write timings are used. The address loca­tions used in the command sequences are not affected by
entering the command sequences.

RESET:

A RESET

tem applications. When RESET

input pin is prov ided to eas e so me s ys-

is at a logic high level, the

3

device is in its standa rd oper at ing mod e. A low l ev el on the
RESET
the outputs of the de vice in a hi gh imped ance stat e. When
a high level is reasse rted on the RES ET
returns to the Read or Standby mod e, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RE SE T
grammed even if the boot block program lockout feature
has been enable d (see Boot B lock Pr ogrammi ng Lock out
Override section).

ERASURE:

must be erased. The erased state of memory bits is a logi­cal “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase commands.

CHIP ERASE:

by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is t

If the boot block lockou t has be en enabled, the Ch ip Eras e
will not erase the data in t he boot block; it wil l erase the
main memory block and the parameter blocks only. After
the chip erase, the de vi ce wi ll retu rn to the read or standby
mode.

SECTOR ERASE:

device is organized into four sectors that can be individually
erased. There are two 4K word parameter block sections,
one boot block, and the main memory array block. The
Sector Erase command is a six bus cycle operation. The
sector address is latched on the falling WE
sixth cycle while the 30 H data in put com mand is la tched at
the rising edge of WE
ing edge of WE
internally controlled; it will automatically time to completion.
Whenever the main memory block is erased and repro­grammed, the two parame ter bloc ks should be erased and
reprogrammed before the main memory block is erased
again. Whenever a parameter block is erased and repro­grammed, the other parameter block should be erased and
reprogrammed before the first parameter block is erased
again. Whenever the boot block is erased and repro­grammed, the ma in memory block and th e parameter
blocks should be erased and reprogrammed before the
boot block is erased again.

BYTE/WORD PROGRAMMING:

erased, it is programmed (to a logical “0”) on a byte-by-byte
or word-by-word bas is. Progr amming is accom plished via
the internal device command register and is a 4 bus cycle
operation. The device will automatically generate the
required internal program pulses.

Any commands written to the c hip during the em bedded
programming cycle will be ignored. If a hardware reset hap-

input halts the prese nt device oper ation and puts

pin, the device

pin the boot blo ck ar ray c an b e r epro-

Before a byte or word can be reprogrammed, it

The entire device can be erased at one time

.

EC

As an alternative to a full chip erase, the

edge of the

. The sector erase s tar ts after the ris-

of the sixth cycle. The erase o peration is

Once a memory block is

pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “ 0”s to “ 1”s. Pro grammi ng is co mplete d after
the specified t
also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

has one designated block that has a programming lockout
feature. This feature prevents programming of data in th e
designated block once the feature has been enabled. The
size of the block is 8K words. Thi s blo ck, refe rred to a s the
boot block, can contain secure code that is used to bring up
the system. Enablin g the l ockou t feature w ill al low the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti­vated; the boot block’ s u sag e as a wr i te pro t ected r eg io n is
optional to the user. The address range of the boot block is
00000H to 03FFFH for the AT49F004; 7C000H to 7FFFFH
for the AT49F004T; 00000H to 01FFFH for the
AT49F4096A; and 3E000H to 3FFFFH for the
AT49F4096AT.

Once the feature is enabled, the data in the boot blo ck ca n
no longer be erased or programmed when input levels of

5.5V or less are u sed. Dat a in the ma in memo ry bloc k can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine if programming of the boot
block section is locked out. When the device is in the soft­ware product identification mode (see Software Product
Identification Entry and Exit section s) a read from the fol­lowing address location will show if programming the boot
block is locked out—00002H for AT49F004 and
AT49F4096A; 7C002 for the AT49F004T; and 3E002H for
the AT49F4096AT. If the data on I/O0 is low, the boot block
can be programmed; if the data on I/O0 is high, the pro­gram lockout featu re has been en abled an d the block can­not be programmed. The software product identification
exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override th e boot blo ck progr amming lo ckout
by taking the RESET
erase, sector erase or word pro grammin g oper ation. W hen
the RESET
programming lockout feature is again active.

PRODUCT IDENTIFICATION:

mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro­grammer to identify the correct programming algorithm for
the Atmel product.

cycle time. The DATA polling feature may

BP

The device

A software

pin to 12 volts during the entire chip

pin is brought back to TTL levels the boot block

The product identification

4

AT49F004/4096A(T)

AT49F004/4096A(T)

For details, see O peratin g Modes (for har dware operatio n)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING:

polling to indic ate the en d o f a program cycle. Dur in g

DATA

The AT49F004(T)/4096A(T) features

a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and th e next cyc le may be gin. Du ring a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.

polling may begi n at any ti me during the program

DATA
cycle.

TOGGLE BIT:

In addition to DATA

polling the
AT49F004(T)/4096A(T) p rovi des another method for deter­mining the end of a program or erase cycle. During a pro­gram or erase o pera tion, succe ssiv e atte mpts to r ead data
from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop

toggling and valid data will be read . Examining the toggle
bit may begin at any time during a program cycle.

READY/BUSY

drain READY/BUSY

:

For the AT49F004 (T), pin 12 is an open

output pin whic h provides anot her
method of detecting the end of a program or erase opera­tion. RDY/BUSY

is actively pulled low during the internal
program and erase cycles and it is rele ased at the co mple­tion of the cycle. The open drain connec tion allow s for OR­tying of several devices to the same RDY/BUSY

HARDWARE DATA PROTECTION:

Hardware features

line.

protect against inadvertent programs to the
AT49F004(T)/4096A(T ) in the following wa ys: (a) V

CC

sense: if VCC is below 3.8V (typical), the program function
is inhibited. (b) V
the V

sense level, the device will automaticall y time out

CC

power on delay: onc e VCC has reached

CC

10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE

low, CE high or WE h igh inhi bits
program cycles. (d) Noise filter: pulses o f less than 15 ns
(typical) on the WE

or CE inputs will not initiate a program

cycle.

5