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NUC130
User Manual
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Rainbow Electronics NUC130 User Manual

NUC130 Series DATA SHEET
Cortex™-M0
32-BIT MICROCONTROLLER
NUC130 Product Data Sheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
Publication Release Date: May 31, 2010
- 1 - Revision V1.02
NUC130 Series DATA SHEET
Table of Contents-
1 GENERAL DESCRIPTION ......................................................................................................... 5
2 FEATURES ................................................................................................................................. 6
3 PARTS INFORMATION LIST AND PIN CONFIGURATION .................................................... 10
3.1 NUC130 Products Selection Guide .............................................................................. 10
3.2 Pin Configuration .......................................................................................................... 11
3.2.1 NUC130 LQFP 100 pin...................................................................................................11
3.2.2 NUC130 LQFP 64 pin.....................................................................................................12
3.2.3 NUC130 LQFP 48 pin.....................................................................................................13
3.3 Pin Description.............................................................................................................. 14
3.3.1 NUC130 Pin Description.................................................................................................14
4 BLOCK DIAGRAM .................................................................................................................... 21
4.1 NUC130 Block Diagram................................................................................................ 21
5 FUNCTIONAL DESCRIPTION.................................................................................................. 22
5.1 ARM® Cortex™-M0 core............................................................................................... 22
5.2 System Manager........................................................................................................... 24
5.2.1 Overview ........................................................................................................................24
5.2.2 System Reset ................................................................................................................. 24
5.2.3 System Timer (SysTick) .................................................................................................25
5.2.4 Nested Vectored Interrupt Controller (NVIC) .................................................................. 26
5.3 Clock Controller ............................................................................................................ 30
5.3.1 Clock Generator .............................................................................................................30
5.3.2 System Clock & SysTick Clock.......................................................................................31
5.3.3 Peripherals Clock ...........................................................................................................32
5.3.4 Power down mode (Deep Sleep Mode) Clock ................................................................32
5.3.5 Frequency Divider Output...............................................................................................33
5.4 General Purpose I/O..................................................................................................... 34
5.4.1 Overview and Features ..................................................................................................34
5.5 I2C Serial Interface Controller (Master/Slave).............................................................. 36
5.5.1 Introduction.....................................................................................................................36
5.5.2 Features .........................................................................................................................37
5.6 PWM Generator and Capture Timer............................................................................. 38
5.6.1 Introduction.....................................................................................................................38
5.6.2 Features .........................................................................................................................39
5.7 Real Time Clock (RTC)................................................................................................. 40
5.7.1 Overview ........................................................................................................................40
5.7.2 RTC Features .................................................................................................................40
5.8 Serial Peripheral Interface (SPI) Controller .................................................................. 41
5.8.1 Overview ........................................................................................................................41
5.8.2 Features .........................................................................................................................41
Publication Release Date: May 31, 2010
- 2 - Revision V1.02
NUC130 Series DATA SHEET
5.9
Timer Controller ............................................................................................................ 42
5.9.1 General Timer Controller ................................................................................................ 42
5.9.2 Features .........................................................................................................................42
5.10 Watchdog Timer............................................................................................................ 43
5.11 UART Interface Controller ............................................................................................ 44
5.11.1 Overview ......................................................................................................................44
5.11.2 Features of UART controller.........................................................................................46
5.12 Controller Area Network (CAN Bus) ............................................................................. 47
5.12.1 Introduction................................................................................................................... 47
5.12.2 Features .......................................................................................................................47
5.13 PS2 Device Controller (PS2D)...................................................................................... 48
5.13.1 Overview ......................................................................................................................48
5.13.2 Features .......................................................................................................................48
5.14 I2S Controller................................................................................................................ 49
5.14.1 Overview ......................................................................................................................49
5.14.2 Features .......................................................................................................................49
5.15 Analog-to-Digital Converter (ADC) ............................................................................... 50
5.15.1 Functional Description .................................................................................................. 50
5.15.2 Features .......................................................................................................................50
5.16 Analog Comparator....................................................................................................... 51
5.16.1 Functional Description .................................................................................................. 51
5.16.2 Features .......................................................................................................................51
5.17 PDMA Controller........................................................................................................... 52
5.17.1 Overview ......................................................................................................................52
5.17.2 Features .......................................................................................................................52
6 FLASH MEMORY CONTROLLER (FMC) ................................................................................ 53
6.1 Overview ....................................................................................................................... 53
6.2 Features........................................................................................................................ 53
7 ELECTRICAL CHARACTERISTICS......................................................................................... 54
7.1 Absolute Maximum Ratings .......................................................................................... 54
7.2 DC Electrical Characteristics ........................................................................................ 55
7.3 AC Electrical Characteristics ........................................................................................ 59
7.3.1 External XTAL1 Oscillator ..............................................................................................59
7.3.2 External 32kHz XTAL Oscillator .....................................................................................61
7.3.3 Internal 22.1184MHz Oscillator ......................................................................................61
7.3.4 Internal 10kHz Oscillator ................................................................................................61
7.4 Analog Characteristics.................................................................................................. 62
7.4.1 Specification of 12-bit SARADC .....................................................................................62
7.4.2 Specification of LDO & Power management ..................................................................63
7.4.3 Specification of Low Voltage Reset ................................................................................64
Publication Release Date: May 31, 2010
- 3 - Revision V1.02
NUC130 Series DATA SHEET
7.4.4 Specification of Brownout Detector.................................................................................64
7.4.5 Specification of Power-On Reset (5V) ............................................................................64
7.4.6 Specification of Temperature Sensor .............................................................................65
7.4.7 Specification of Comparator ...........................................................................................65
8 PACKAGE DIMENSIONS......................................................................................................... 67
8.1.1 100L LQFP (14x14x1.4 mm footprint 2.0mm) ................................................................67
8.1.2 64L LQFP (10x10x1.4mm footprint 2.0 mm ) .................................................................68
8.1.3 48L LQFP (7x7x1.4mm footprint 2.0mm) .......................................................................69
9 REVISION HISTORY ................................................................................................................ 70
Publication Release Date: May 31, 2010
- 4 - Revision V1.02
NUC130 Series DATA SHEET

1 GENERAL DESCRIPTION

The NUC130 series are 32-bit microcontrollers with embedded ARM® Cortex™-M0 core for industrial control and applications support CAN bus network. The Cortex™-M0 is the newest ARM embedded processor with 32-bit performance and at a cost equivalent traditional 8-bit microcontroller.
The NUC130 series embeds Cortex™-M0 core running up to 50 MHz with 64K/128K-byte embedded flash and 8K/16K-byte embedded SRAM. It also equips with plenty of peripheral devices, such as Timers, Watchdog Timer, RTC, PDMA, UART, SPI/SSP, I ADC, Analog Comparator, Low Voltage Detector and Brown-out detector.
2
C, I2S, PWM Timer, GPIO, LIN, CAN, 12-bit
Publication Release Date: May 31, 2010
- 5 - Revision V1.02
NUC130 Series DATA SHEET

2 FEATURES

• Core
– ARM® Cortex™-M0 core runs up to 50 MHz. – One 24-bit system timer. – Supports low power sleep-mode. – Single-cycle 32-bit hardware multiplier. – NVIC for the 32 interrupt inputs, each with 4-levels of priority. – Serial Wire Debug supports with 2 watchpoints/4 breakpoints.
• Wide operating voltage ranges from 2.5V to 5.5V
• Flash EPROM Memory
– 64K/128K bytes Flash EPROM for program code. – 4KB flash for ISP loader – Support In-system program(ISP) and In-application program(IAP) application code update – 512 byte page erase for flash – Configurable data flash address and size for 128KB system, fixed 4KB data flash for 64KB
system.
– Support 2 wire ICP update from ICE interface – Support fast parallel programming mode by external programmer.
• SRAM Memory
– 8K/16k bytes embedded SRAM. – Support PDMA mode
• PDMA (Peripheral DMA)
– Support 9 channels PDMA for automatic data transfer between SRAM and peripherals.
• Clock Control
– Flexible selection for different applications. – Build-in 22 MHz OSC (Trimmed to 1%) for system operation, and low power 10 kHz OSC for
watchdog and wakeup sleep operation.
– Support one PLL, up to 50 MHz, for high performance system operation. – External 4~24MHz crystal input for precise timing operation. – External 32 kHz crystal input for RTC function and low power system operation.
• GPIO
– Four I/O modes:
Quasi bi-direction Push-Pull output Open-Drain output Input only with high impendence
– TTL/Schmitt trigger input selectable. – I/O pin can be configured as interrupt source with edge/level setting. – High driver and high sink IO mode support.
Publication Release Date: May 31, 2010
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NUC130 Series DATA SHEET
• Timers
– 4 sets of 24-bit timer with 8-bit prescaler. – Counter auto reload.
• Watch Dog Timer
– Default ON/OFF by configuration setting – Multiple clock sources – 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source) – WDT can wake up power down/sleep. – Interrupt or reset selectable on watchdog time-out.
• RTC
– Support software compensation by setting frequency compensate register (FCR) – Support RTC counter (second, minute, hour) and calendar counter (day, month, year) – Support Alarm registers (second, minute, hour, day, month, year) – Selectable 12-hour or 24-hour mode – Automatic leap year recognition – Support time tick interrupt – Support wake up function.
• PWM/Capture
– Built-in up to four 16-bit PWM generators provide eight PWM outputs or four complementary
paired PWM outputs.
– Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit
prescaler and one Dead-Zone generator for complementary paired PWM.
– PWM interrupt synchronous to PWM period. – Up to eight 16-bit digital Capture timers (shared with PWM timers) provide eight rising/falling
capture inputs.
– Support Capture interrupt
• UART
– Three compatible 16550 UART devices. – UART ports with flow control (TX, RX, CTS and RTS) – UART0 with 64-byte FIFO is for high speed – UART1/2 with 16-byte FIFO for standard device – Support IrDA (SIR) and LIN function – Programmable baud-rate generator up to 1/16 system clock
Support PDMA mode
–
• SPI
– Up to four sets of SPI device. – Master up to 16 Mbps / Slave up to 10 Mbps. – Support MICROWIRE/SPI master/slave mode (SSP) – Full duplex synchronous serial data transfer – Variable length of transfer data from 1 to 32 bits – MSB or LSB first data transfer – Rx and Tx on both rising or falling edge of serial clock independently – 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as
the slave
– Byte Sleeping mode in 32-bit transmission – Support PDMA mode
Publication Release Date: May 31, 2010
- 7 - Revision V1.02
NUC130 Series DATA SHEET
2
• I
C
– Two sets of I – Master/Slave up to 1Mbit/s – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master). – Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
– Serial clock synchronization allows devices with different bit rates to communicate vian one
serial bus.
– Serial clock synchronization can be used as a handshake mechanism to suspend and resume
serial transfer.
– Programmable clocks allow versatile rate control. – I2C-bus controllers support multiple address recognition ( two slave address with mask option)
2
S
• I
– Interface with external audio CODEC – Operate as either master or slave mode – Capable of handling 8, 16, 24, and 32 bit word sizes – Mono and stereo audio data supported
2
S and MSB justified data format supported
– I – Two 8 word FIFO data buffers are provided, one for transmit and one for receive – Generates interrupt requests when buffer levels cross a programmable boundary – Support two DMA requests, one for transmit and one for receive
2
C device.
• CAN 2.0
– CAN 2.0B protocol compatible device – Support 11-bit identifier as well as 29-bit identifier – Bit rates up to 1Mbits/s – NRZ bit Coding/ Encoding – Error Detection & Status Report
Bit error, Form error, Stuffing error, 15-bit CRC detection, and Acknowledge error
Interrupt
Each CAN-bus error and Transmission/Receive Done.
– Bit Timing Synchronization – Acceptance filter extension – Sleep mode wake up
• ADC
– 12-bit SAR ADC with 800ksps – Up to 8-ch single-end mode or 4-ch differential mode – Single scan/single cycle scan/continuous scan – Each channel with individual result register – Scan on enabled channels – Threshold voltage detection – Conversion start by S/W, external pins – Support PDMA Mode
• Analog Comparator
– Two analog comparator modules – External input or internal bandgap voltage selectable at negative node – Interrupt when compare result change – Power down wake up
Publication Release Date: May 31, 2010
- 8 - Revision V1.02
NUC130 Series DATA SHEET
• One built-in temperature sensor with 1℃ resolution.
• Brown-out detector
– With 4 levels: 4.5V/3.8V/2.7V/2.2V – Support Brownout Interrupt and Reset option
• One built-in LDO
• Low Voltage Reset
• Operating Temperature: -40℃~85℃
• Packages:
– All Green package (RoHS)
LQFP 100-pin / 64-pin / 48-pin
Publication Release Date: May 31, 2010
- 9 - Revision V1.02
NUC130 Series DATA SHEET

3 PARTS INFORMATION LIST AND PIN CONFIGURATION

3.1 NUC130 Products Selection Guide

Part number Flash SRAM
UART
NUC130LE3AN 128 KB 16 KB 3 1 2 2 1 1 4 1 8x12-bit 4x24-bit v v up to 35 LQFP48
NUC130LD3AN 64 KB 16 KB 3 1 2 2 1 1 4 1 8x12-bit 4x24-bit v v up to 35 LQFP48
NUC130LD2AN 64 KB 8 KB 3 1 2 2 1 1 4 1 8x12-bit 4x24-bit v v up to 35 LQFP48
NUC130RE3AN 128 KB 16 KB 3 2 2 2 1 1 6 2 8x12-bit 4x24-bit v v up to 49 LQFP64
NUC130RD3AN 64 KB 16 KB 3 2 2 2 1 1 6 2 8x12-bit 4x24-bit v v up to 49 LQFP64
NUC130RD2AN 64 KB 8 KB 3 2 2 2 1 1 6 2 8x12-bit 4x24-bit v v up to 49 LQFP64
NUC130VE3AN 128 KB 16 KB 3 4 2 2 1 1 8 2 8x12-bit 4x24-bit v v up to 80 LQFP100
NUC130VD3AN 64 KB 16 KB 3 4 2 2 1 1 8 2 8x12-bit 4x24-bit v v up to 80 LQFP100
NUC130VD2AN 64 KB 8 KB 3 4 2 2 1 1 8 2 8x12-bit 4x24-bit v v up to 80 LQFP100
Connectivity
SPI/SSI
I2C LIN CAN
I2S PWM Comp. ADC Timer RTC
ISP ICP
I/O Package
Publication Release Date: May 31, 2010
- 10 - Revision V1.02

3.2 Pin Configuration

3.2.1 NUC130 LQFP 100 pin

PA.1/ADC1
PA.2/ADC2
PA.0/ADC0
5
AVSS
70
6
ADC5/PA.5
ADC6/PA.6
ADC7/SS21/PA.7
Vref
AVDD
SS20/PD.0
SPICLK2/PD.1
MISO20/PD.2
MOSI20/PD.3
MISO21/PD.4
MOSI21/PD.5
CPN0/PC.7
CPP0/PC.6
CPN1/PC.15
CPP1/PC.14
INT1/PB.15
XT1_Out
XT1_In
/RESET
VSS1
VDD1
PS2DAT
PS2CLK
PVSS
STADC/TM0/PB.8
PA.4/ADC4
7574737271
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
PA.3/ADC3
234
NUC130 Series DATA SHEET
VSS2
VDD2
ICE_DAT
ICE_CK
686766656469636261
7
8
9
PA.13/PWM1
PA.12/PWM0
LQFP 100-pin
101112131415161718192021222324
PC.9/SPICLK1
PC.10/MISO10
60
59
PC.11/MOSI10
PC.13/MOSI11
PC.12/MISO11
PE.0/PWM6
5857565554
PE.1/PWM7
PE.3
PE.2
535251
PE.4
PB.9/SS11/TM1
50
PB.10/SS01/TM2
49
PB.11/TM3/PWM4
48
PE.5/PWM5
47
PE.6
46
PC.0/SS00/I2SLRCLK
45
PC.1/SPICLK0/I2SBCLK
44
PC.2/MISO00/I2SDI
43
PC.3/MOSI00/I2SDO
42
PC.4/MISO01
41
PC.5/MOSI01
40
PD.15/TX2
39
PD.14/RX2
38
PD.7/CANTX0
37
PD.6/CANRX0
36
PB.3/CTS0
35
PB.2/RTS0
34
PB.1/TX0
33
PB.0/RX0
32
PE.7
31
PE.8
30
PE.9
29
28
PE.10
27
PE.11
26
25
PE.12
PC.8/SS10
PA.15/PWM3/I2SMCLK
PA.14/PWM2
VSS
X32I
PE.15
PE.14
PE.13
SS31/INT0/PB.14
X32O
CPO1/PB.13
CLKO/CPO0/PB.12
I2C1SCL/PA.11
I2C1SDA/PA.10
SS30/PD.8
I2C0SCL/PA.9
SPICLK3/PD.9
I2C0SDA/PA. 8
MISO31/PD.12
MISO30/PD.10
MOSI30/PD.11
TX1/PB.5
RX1/PB.4
MOSI31/PD.13
LDO
VDD
CTS1/PB.7
RTS1/PB.6
Publication Release Date: May 31, 2010
- 11 - Revision V1.02

3.2.2 NUC130 LQFP 64 pin

PA.4/ADC4
PA.3/ADC3
PA.2/ADC2
PA.1/ADC1
PA.0/ADC0
NUC130 Series DATA SHEET
ICE_DAT
ICE_CK
AVSS
PA.13/PWM1
PA.12/PWM0
PA.14/PWM2
PC.9/SPICLK1
PC.8/SS10
PA.15/PWM3/I2SMCLK
PC.11/MOSI10
PC.10/MISO10
ADC5/PA.5
ADC6/PA.6
ADC7//PA.7
AVDD
CPN0/PC.7
CPP0/PC.6
CPN1/PC.15
CPP1/PC.14
INT1/PB.15
XT1_Out
XT1_In
/RESET
VSS1
VDD1
PVSS
STADC/TM0/PB.8
46
48
47
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
INT0/PB.14
CPO1/PB.13
45
3
4
X32O
CLKO/CPO0/PB.12
4443424140
LQFP 64-pin
5
6
7
8
9
X32I
I2C0SCL/PA.9
I2C1SCL/PA.11
I2C0SDA/PA.8
I2C1SDA/PA.10
39
38
10
11
TX1/PB.5
RX1/PB.4
3736353433
1213141516
LDO
VDD
CTS1/PB.7
RTS1/PB.6
32
PB.9/TM1
31
PB.10/TM2
30
PB.11/TM3/PWM4
29
PE.5/PWM5
28
PC.0/SS00/I2SLRCLK
27
PC.1/SPICLK0/I2SBCLK
26
PC.2/MISO00/I2SDI
25
PC.3/MOSI00/I2SDO
24
PD.15/TX2
23
PD.14/RX2
22
PD.7/CANTX0
21
PD.6/CANRX0
20
PB.3/CTS0
19
PB.2/RTS0
18
PB.1/TX0
17
PB.0/RX0
VSS
Publication Release Date: May 31, 2010
- 12 - Revision V1.02

3.2.3 NUC130 LQFP 48 pin

NUC130 Series DATA SHEET
PA.1/ADC1
PA.4/ADC4
PA.3/ADC3
PA.0/ADC0
PA.2/ADC2
ICE_DAT
ICE_CK
AVSS
PA.13/PWM1
PA.12/PWM0
PA.15/PWM3/I2SMCLK
PA.14/PWM2
ADC5/PA.5
ADC6/PA.6
ADC7/PA.7
AVDD
CPN0/PC.7
CPP0/PC.6
INT1/PB.15
XT1_Out
XT1_In
/RESET
PVSS
STADC/TM0/PB.8
32363029282726
34
353133
37
38
39
40
41
42
43
44
45
46
47
48
1
CLKO/CPO0/PB.12
LQFP 48-pin
2
3
4
X32I
X32O
I2C1SCL/PA.11
I2C1SDA/PA.10
6
I2C0SCL/PA.9
7
I2C0SDA/PA.8
8
RX1/PB.4
9
TX1/PB.5
10511
LDO
VDD
25
PC.0/SS00/I2SLRCLK
24
PC.1/SPICLK0/I2SBCLK
23
PC.2/MISO00/I2SDI
22
PC.3/MOSI00/I2SDO
21
PD.15/TX2
20
PD.14/RX2
19
PD.7/CANTX0
18
PD.6/CANRX0
17
PB.3/CTS0
16
PB.2/RTS0
15
PB.1/TX0
14
PB.0/RX0
13
12
VSS
Publication Release Date: May 31, 2010
- 13 - Revision V1.02

3.3 Pin Description

3.3.1 NUC130 Pin Description

Pin No.
LQFP
100
LQFP
64
LQFP
Pin Name Pin Type Description
48
NUC130 Series DATA SHEET
1 PE.15
2 PE.14
3 PE.13
PB.14
4 1
5 2
6 3 1
7 4 2 X32O
8 5 3 X32I
9 6 4
/INT0
/SPISS31
PB.13
CPO1
PB.12
CPO0
CLKO
PA.11
I2C1SCL
I/O I/O I/O I/O
I I/O I/O
O
I/O
O O O
I I/O I/O
General purpose input/output digital pin
General purpose input/output digital pin
General purpose input/output digital pin
General purpose input/output digital pin
/INT0: External interrupt1 input pin
/SPISS31: SPI3 2
General purpose input/output digital pin
Comparator1 output pin
General purpose input/output digital pin
Comparator0 output pin
Frequency Divider output pin
32.768 kHz crystal output pin
32.768 kHz crystal input pin
General purpose input/output digital pin
I2C1SCL: I2C1 clock pin
nd
slave select pin
10 7 5
11 8 6
12 9 7
13
14
PA.10
I2C1SDA
PA.9
I2C0SCL
PA.8
I2C0SDA
PD.8
/SPISS30
PD.9
SPICLK3
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
General purpose input/output digital pin
I2C1SDA: I2C1 data input/output pin
General purpose input/output digital pin
I2C0SCL: I2C0 clock pin
General purpose input/output digital pin
I2C0SDA: I2C0 data input/output pin
General purpose input/output digital pin
/SPISS30: SPI3 slave select pin
General purpose input/output digital pin
SPICLK3: SPI3 serial clock pin
Publication Release Date: May 31, 2010
- 14 - Revision V1.02
LQFP
100
Pin No.
LQFP
64
LQFP
48
NUC130 Series DATA SHEET
Pin Name Pin Type Description
15
PD.10
MISO30
PD.11
16
MOSI30
PD.12
17
MISO31
PD.13
18
MOSI31
PB.4
19 10 8
RX1
PB.5
20 11 9
TX1
PB.6
21 12
RTS1
PB.7
22 13
CTS1
I/O
I I/O
O
I/O
I I/O
O
I/O
I I/O
O
I/O
I/O
General purpose input/output digital pin
MISO30: SPI3 MISO (Master In, Slave Out) pin
General purpose input/output digital pin
MOSI30: SPI3 MOSI (Master Out, Slave In) pin
General purpose input/output digital pin
nd
MISO31: SPI3 2
General purpose input/output digital pin
MOSI31: SPI3 2
General purpose input/output digital pin
RX1: Data Receiver input pin for UART1
General purpose input/output digital pin
TX1: Data transmitter output pin for UART1
General purpose input/output digital pin
RTS1: Request to Send output pin for UART1
General purpose input/output digital pin
CTS1: Clear to Send input pin for UART1
MISO (Master In, Slave Out) pin
nd
MOSI (Master Out, Slave In) pin
23 14 10 LDO
24 15 11 VDD
25 16 12 VSS
26 PE.12
27 PE.11
28 PE.10
29 PE.9
30 PE.8
31 PE.7
PB.0
32 17 13
RX0
P
P
P I/O I/O I/O I/O I/O I/O I/O
I
LDO output pin
Power supply for I/O ports and LDO source for internal PLL and digital function
Ground
General purpose input/output digital pin
General purpose input/output digital pin
General purpose input/output digital pin
General purpose input/output digital pin
General purpose input/output digital pin
General purpose input/output digital pin
General purpose input/output digital pin
RX0: Data Receiver input pin for UART0
Publication Release Date: May 31, 2010
- 15 - Revision V1.02
LQFP
100
Pin No.
LQFP
64
LQFP
48
NUC130 Series DATA SHEET
Pin Name Pin Type Description
33 18 14
PB.1
TX0
PB.2
34 19 15
RTS0
PB.3
35 20 16
CTS0
PD.6
36 21 17
CANRX0
PD.7
37 22 18
CANTX0
PD.14
38 23 19
CANRX1
PD.15
39 24 20
CANTX1
PC.5
40
MOSI01
I/O
O I/O
I/O
I/O
I
I/O
O I/O
I
I/O
O I/O
O
General purpose input/output digital pin
TX0: Data transmitter output pin for UART0
General purpose input/output digital pin
RTS0: Request to Send output pin for UART0
General purpose input/output digital pin
CTS0: Clear to Send input pin for UART0
General purpose input/output digital pin
CAN Bus0 RX Input
General purpose input/output digital pin
CAN Bus0 TX Output
General purpose input/output digital pin
CAN Bus1 RX Input
General purpose input/output digital pin
CAN Bus1 TX Output
General purpose input/output digital pin
nd
MOSI01: SPI0 2
MOSI (Master Out, Slave In) pin
41
42 25 21
43 26 22
44 27 23
45 28 24 PC.0
PC.4
MISO01
PC.3
MOSI00
I2SDO
PC.2
MISO00
I2SDI
PC.1
SPICLK0
I2SBCLK
I/O
I
I/O
O
O I/O
I
I I/O I/O I/O I/O
General purpose input/output digital pin
nd
MISO01: SPI0 2
General purpose input/output digital pin
MOSI00: SPI0 MOSI (Master Out, Slave In) pin
I2SDO: I2S data output
General purpose input/output digital pin
MISO00: SPI0 MISO (Master In, Slave Out) pin
I2SDI: I2S data input
General purpose input/output digital pin
SPICLK0: SPI0 serial clock pin
I2SBCLK: I2S bit clock pin
General purpose input/output digital pin
MISO (Master In, Slave Out) pin
Publication Release Date: May 31, 2010
- 16 - Revision V1.02
LQFP
100
Pin No.
LQFP
64
LQFP
48
NUC130 Series DATA SHEET
Pin Name Pin Type Description
/SPISS00
I2SLRCLK
46 PE.6
47 29
48 30
31
49
/SPISS01
32
50
/SPISS11
51 PE.4
PE.5
PWM5
PB.11
TM3
PWM4
PB.10
TM2
PB.9
TM1
I/O I/O
I/O I/O
O
I/O
O O
I/O
O I/O I/O
O I/O I/O
/SPISS00: SPI0 slave select pin
I2SLRCLK: I2S left right channel clock
General purpose input/output digital pin
General purpose input/output digital pin
PWM5: PWM output
General purpose input/output digital pin
TM3: Timer3 external counter input
PWM4: PWM output
General purpose input/output digital pin
TM2: Timer2 external counter input
/SPISS01: SPI0 2
General purpose input/output digital pin
TM1: Timer1 external counter input
/SPISS11: SPI1 2
General purpose input/output digital pin
nd
slave select pin
nd
slave select pin
52 PE.3
53 PE.2
PE.1
54
PWM7
PE.0
55
PWM6
PC.13
56
MOSI11
PC.12
57
MISO11
PC.11
58 33
MOSI10
59 34 PC.10
I/O I/O I/O
O I/O
O I/O
O I/O
I
I/O
O I/O
General purpose input/output digital pin
General purpose input/output digital pin
General purpose input/output digital pin
PWM7: PWM output
General purpose input/output digital pin
PWM6: PWM output
General purpose input/output digital pin
nd
MOSI11: SPI1 2
General purpose input/output digital pin
MISO11: SPI1 2
General purpose input/output digital pin
MOSI10: SPI1 MOSI (Master Out, Slave In) pin
General purpose input/output digital pin
MOSI (Master Out, Slave In) pin
nd
MISO (Master In, Slave Out) pin
Publication Release Date: May 31, 2010
- 17 - Revision V1.02
LQFP
100
Pin No.
LQFP
64
LQFP
48
NUC130 Series DATA SHEET
Pin Name Pin Type Description
MISO10
PC.9
60 35
SPICLK1
61 36
62 37 25
63 38 26
64 39 27
65 40 28
66 41 29 ICE_DAT
PC.8
/SPISS10
PA.15
PWM3
I2SMCLK
PA.14
PWM2
PA.13
PWM1
PA.12
PWM0
I
I/O
I/O
I/O I/O I/O
O
O I/O
O I/O
O I/O
O I/O
MISO10: SPI1 MISO (Master In, Slave Out) pin
General purpose input/output digital pin
SPICLK1: SPI1 serial clock pin
General purpose input/output digital pin
/SPISS10: SPI1 slave select pin
General purpose input/output digital pin
PWM3: PWM output pin
I2SMCLK: I2S master clock output pin
General purpose input/output digital pin
PWM2: PWM output
General purpose input/output digital pin
PWM1: PWM output
General purpose input/output digital pin
PWM0: PWM output
Serial Wired Debugger Data pin
67 42 30 ICE_CLK
68 VDD2
69 31 VSS2
70 43 AVSS
PA.0
71 44 32
ADC0
PA.1
72 45 33
ADC1
PA.2
73 46 34
ADC2
74 47 35 PA.3
I
P
P AP I/O
AI
I/O
AI
I/O
AI
I/O
Serial Wired Debugger Clock pin
Power supply for I/O ports and LDO source for internal PLL and digital circuit
Ground
Ground Pin for analog circuit
General purpose input/output digital pin
ADC0: ADC analog input
General purpose input/output digital pin
ADC1: ADC analog input
General purpose input/output digital pin
ADC2: ADC analog input
General purpose input/output digital pin
Publication Release Date: May 31, 2010
- 18 - Revision V1.02
LQFP
100
Pin No.
LQFP
64
LQFP
48
NUC130 Series DATA SHEET
Pin Name Pin Type Description
ADC3
75 48 36
76 49 37
77 50 38
78 51 39
79 Vref
80 52 40 AVDD
81
82
PA.4
ADC4
PA.5
ADC5
PA.6
ADC6
PA.7
ADC7
/SPISS21
PD.0
/SPISS20
PD.1
SPICLK2
AI
I/O
AI
I/O
AI
I/O
AI
I/O
AI I/O AP AP I/O I/O I/O I/O
ADC3: ADC analog input
General purpose input/output digital pin
ADC4: ADC analog input
General purpose input/output digital pin
ADC5: ADC analog input
General purpose input/output digital pin
ADC6: ADC analog input
General purpose input/output digital pin
ADC7: ADC analog input
/SPISS21: SPI2 2
Voltage reference input for ADC
Power supply for internal analog circuit
General purpose input/output digital pin
/SPISS20: SPI2 slave select pin
General purpose input/output digital pin
SPICLK2: SPI2 serial clock pin
nd
slave select pin
83
84
85
86
87 53 41
88 54 42
PD.2
MISO20
PD.3
MOSI20
PD.4
MISO21
PD.5
MOSI21
PC.7
CPN0
PC.6
CPP0
I/O
I
I/O
O
I/O
I
I/O
O
I/O
I
I/O
I
General purpose input/output digital pin
MISO20: SPI2 MISO (Master In, Slave Out) pin
General purpose input/output digital pin
MOSI20: SPI2 MOSI (Master Out, Slave In) pin
General purpose input/output digital pin
nd
MISO21: SPI2 2
General purpose input/output digital pin
MOSI21: SPI2 2
General purpose input/output digital pin
CPN0: Comparator0 Negative input pin
General purpose input/output digital pin
CPP0: Comparator0 Positive input pin
MISO (Master In, Slave Out) pin
nd
MOSI (Master Out, Slave In) pin
Publication Release Date: May 31, 2010
- 19 - Revision V1.02
LQFP
100
Pin No.
LQFP
64
LQFP
48
NUC130 Series DATA SHEET
Pin Name Pin Type Description
89 55
PC.15
CPN1
PC.14
90 56
CPP1
PB.15
91 57 43
/INT1
92 58 44 XT1_OUT
93 59 45 XT1_IN
94 60 46 /RESET
95 61 VSS1
96 62 VDD1
97 PS2DAT
98 PS2CLK
99 63 47 PVSS
I/O
I
I/O
I
I/O
I
O
I
I
P
P
I/O I/O I/O
General purpose input/output digital pin
CPN1: Comparator1 Negative input pin
General purpose input/output digital pin
CPP1: Comparator1 Positive input pin
General purpose input/output digital pin
/INT1: External interrupt0 input pin
Crystal output pin
Crystal input pin
External reset input: Low active, set this pin low reset MCU to initial state. With internal pull-up.
Ground
Power supply for I/O ports and LDO source for internal PLL and digital circuit
PS2 Data pin
PS2 clock pin
PLL Ground
PB.8
100 64 48
Note:
1. Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; P=Power Pin; AP=Analog Power
STADC
TM0
I/O
I
O
General purpose input/output digital pin
STADC: ADC external trigger input.
TM0: Timer0 external counter input
- 20 - Revision V1.02
Publication Release Date: May 31, 2010

4 BLOCK DIAGRAM

4.1 NUC130 Block Diagram

NUC130 Series DATA SHEET
FLASH
128KB
ISP 4KB
PS2
SPI 2/3
I2C 1 -1M
UART 1 -115K CAN 0
UART 2 -115K
I2S
Peripherals with PDMA
Cortex-M0
SRAM
16KB
50MHz
RTC
WDG
Timer 0/1/
Timer 2/3
PWM 4~7
I2C 0 -1M
GPIO
A,B,C,D,E
PDMA
CLK_CTL
SPI 0/1
UART 0 -3M
PWM 0~3
P L L
LDO
12-bit ADC
Analog
Comparator
Brown-out
10 kHz
32 KHz
22 MHz
12 MHz
2.5V~
5.5V
POR
LVR
Figure 4-1 NUC130 Block Diagram
Publication Release Date: May 31, 2010
- 21 - Revision V1.02
NUC130 Series DATA SHEET

5 FUNCTIONAL DESCRIPTION

5.1 ARM® Cortex™-M0 core

The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processor.
Figure 5-1 shows the functional blocks of processor.
Cortex-M0 components
DebugCortex-M0 processor
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Cortex-M0
Processor
core
Breakpoint
and
Watchpoint
unit
Wakeup Interrupt
Controller
(WIC)
Bus matrix
AHB-Lite interface
Debugger
interface
Debug
Access Port
(DAP)
Serial Wire or JTAG debug port
Figure 5-1 Functional Block Diagram
The implemented device provides:
• A low gate count processor that features:
– The ARMv6-M Thumb® instruction set. – Thumb-2 technology. – ARMv6-M compliant 24-bit SysTick timer. – A 32-bit hardware multiplier. – The system interface supports little-endian data accesses. – The ability to have deterministic, fixed-latency, interrupt handling. – Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate
rapid interrupt handling.
– C Application Binary Interface compliant exception model.
This is the ARMv6-M, C Application Binary Interface(C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers.
– Low power sleep-mode entry using Wait For Interrupt(WFI), Wait For Even(WFE) instructions,
or the return from interrupt sleep-on-exit feature.
• NVIC that features:
– 32 external interrupt inputs, each with four levels of priority.
- 22 - Revision V1.02
Publication Release Date: May 31, 2010
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