19-5320; Rev 2; 8/10
16-Bit Microcontroller with Infrared Module
General Description
The MAXQ613 is a low-power, 16-bit MAXQ® microcontroller designed for low-power applications including universal remote controls, consumer electronics, and white
goods. The device combines a powerful 16-bit RISC
microcontroller and integrated peripherals including a
universal synchronous/asynchronous receiver-transmitter (USART) and an SPI™ master/slave communications
port, along with an IR module with carrier frequency
generation and flexible port I/O capable of multiplexed
keypad control.
The device includes 48KB of flash program memory and
1.5KB of data SRAM. Intellectual property (IP) protection is provided by a secure MMU that supports multiple
application privilege levels and protects code against
copying and reverse engineering. Privilege levels enable
vendors to provide libraries and applications to execute
on the device, while limiting access to only data and
code allowed by their privilege level.
For the ultimate in low-power battery-operated performance, the device includes an ultra-low-power stop
mode (0.2µA typ). In this mode, the minimum amount of
circuitry is powered. Wake-up sources include external
interrupts, the power-fail interrupt, and a timer interrupt.
The microcontroller runs from a wide 1.70V to 3.6V operating voltage.
Applications
Remote Controls
Battery-Powered
Portable Equipment
Consumer Electronics
Home Appliances
White Goods
MAXQ613
Features
S High-Performance, Low-Power, 16-Bit RISC Core
S DC to 12MHz Operation Across Entire Operating Range
S 1.70V to 3.6V Operating Voltage
S 33 Total Instructions for Simplified Programming
S Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
S Dedicated Pointer for Direct Read from Code Space
S 16-Bit Instruction Word, 16-Bit Data Bus
S 16 x 16-Bit General-Purpose Working Registers
S Secure MMU for Application Partitioning and IP
Protection
S Memory Features
48KB Program Flash Memory
512-Byte Sectors
20,000 Erase/Write Cycles per Sector
Masked ROM Available
1.5KB Data SRAM
S Additional Peripherals
Power-Fail Warning
Power-On Reset (POR)/Brownout Reset
Automatic IR Carrier Frequency Generation and
Modulation
Two 16-Bit Programmable Timers/Counters with
Prescaler and Capture/Compare
One SPI and One USART Port
Programmable Watchdog Timer
8kHz Nanopower Ring Oscillator Wake-Up Timer
Up to 24 General-Purpose I/Os
S Low Power Consumption
0.2µA (typ), 2.0µA (max) in Stop Mode,
TA = +25NC, Power-Fail Monitor Disabled
3.25mA (typ) at 12MHz in Active Mode
Ordering Information/Selector Guide
PART TEMP RANGE
MAXQ613A-0000+
MAXQ613E-0000+
MAXQ613J-0000+
MAXQ613K-0000+
MAXQ613X-0000+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
0NC to +70NC
0NC to +70NC
0NC to +70NC
0NC to +70NC
0NC to +70NC
_______________________________________________________________ Maxim Integrated Products 1
OPERATING
VOLTAGE (V)
1.7 to 3.6 48 Flash 1.5 20 32 TQFN-EP*
1.7 to 3.6 48 Flash 1.5 20 32 LQFP
1.7 to 3.6 48 Flash 1.5 24 44 TQFN-EP*
1.7 to 3.6 48 Flash 1.5 24 44 TQFP
1.7 to 3.6 48 Flash 1.5 24 Bare die
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PROGRAM
MEMORY (KB)
DATA
MEMORY (KB)
GPIO PIN-PACKAGE
16-Bit Microcontroller with Infrared Module
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended Operating Conditions
SPI Electrical Characteristics
Pin Configurations
Pin Description
MAXQ613
Block Diagram
Detailed Description
Microprocessor
Memory
Watchdog Timer
IR Carrier Generation and Modulation Timer
16-Bit Timers/Counters
USART
Serial Peripheral Interface (SPI)
General-Purpose I/O
On-Chip Oscillator
ROM Loader
Loading Flash Memory
In-Application Flash Programming
In-Circuit Debug and JTAG Interface
Operating Modes
Applications Information
Additional Documentation
Development and Technical Support
Package Information
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Protection
Stack Memory
Utility ROM
Carrier Generation Module
IR Transmission
IR Transmit—Independent External Carrier and Modulator Outputs
IR Receive
Carrier Burst-Count Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-Fail Detection
Grounds and Bypassing
Deviations from the MAXQ610 User’s Guide for the MAXQ613
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2 ______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
LIST OF FIGURES
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control
Figure 3. IR Transmission Waveform (IRCFME = 0)
Figure 4. External IRTXM (Modulator) Output
Figure 5. IR Capture
Figure 6. Receive Burst-Count Example
Figure 7. SPI Master Communication Timing
Figure 8. SPI Slave Communication Timing
Figure 9. On-Chip Oscillator
Figure 10. In-Circuit Debugger
Figure 11. Power-Fail Detection During Normal Operation
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LIST OF TABLES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
. . . . . . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MAXQ613
Table 1. Memory Areas and Associated Maximum Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
Table 3. USART Mode Details
Table 4. Power-Fail Detection States During Normal Operation
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . . . . . . 26
_______________________________________________________________________________________ 3
16-Bit Microcontroller with Infrared Module
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD with Respect to GND .....-0.3V to +3.6V
Voltage Range on Any Lead with
Respect to GND Except V
Continuous Power Dissipation (T
............... -0.3V to (VDD + 0.5V)
DD
= +70NC)
A
32-Pin TQFN (single-layer board)
(derate 21.3mW/NC above +70NC)..........................1702.1mW
32-Pin TQFN (multilayer board)
(derate 34.5mW/NC above +70NC)..........................2758.6mW
MAXQ613
32-Pin LQFP (multilayer board)
(derate 20.7mW/NC above +70NC)..........................1652.9mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(VDD = V
Supply Voltage V
1.8V Internal Regulator V
Power-Fail Warning Voltage for
Supply
Power-Fail Reset Voltage V
POR Voltage V
RAM Data-Retention Voltage V
Active Current I
Stop-Mode Current
Current Consumption During
Power-Fail
Power Consumption During
POR
Stop-Mode Resume Time t
Power-Fail Monitor Startup
Time
Power-Fail Warning Detection
Time
Input Low Voltage for IRTX,
IRRX, RESET, and All Port Pins
Input High Voltage for IRTX,
IRRX, RESET, and All Port Pins
to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1)
RST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DD
REG18
V
PFW
RST
POR
DRV
DD_1
I
S1
I
S2
I
PFR
I
POR
ON
t
PFM_ON
t
PFW
V
V
Monitors V
Monitors V
Monitors V
DD
DD
DD
(Note 4) 1.0 V
Sysclk = 12MHz (Note 5) 3.25 4 mA
Power-Fail Off
Power-Fail On
(Note 6)
(Note 7) 100 nA
(Note 4) 150
(Note 8) 10
IL
IH
44-Pin TQFN (single-layer board)
(derate 27mW/NC above +70NC).............................2162.2mW
44-Pin TQFN (multilayer board)
(derate 37mW/NC above +70NC)................................2963mW
44-Pin TQFP (multilayer board)
(derate 19mW/NC above +70NC)................................1504mW
Operating Temperature Range
Storage Temperature Range
Lead Temperature (excluding dice; soldering, 10s)
Soldering Temperature (reflow)
V
RST
............................. 0NC to +70NC
............................ -65NC to +150NC
......+300NC
......................................+260NC
3.6 V
1.62 1.8 1.98 V
(Note 2) 1.75 1.8 1.85 V
(Note 3) 1.64 1.67 1.70 V
1 1.42 V
= +25NC
T
A
T
= 0°C to +70NC
A
= +25NC
T
A
= 0°C to +70NC
T
A
0.2 2.0
0.2 8
22 29.5
27.6 42
[(3 x I
S2
((PCI - 3) x (I
I
))]/PCI
NANO
) +
S1
+
375 + (8192 x
t
HFXIN)
V
GND
0.7 x V
DD
0.3 x V
V
DD
DD
FA
FA
Fs
Fs
Fs
V
V
4 ______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
RECOMMENDED OPERATING CONDITIONS (continued)
(VDD = V
Input Hysteresis (Schmitt) V
Input Low Voltage for HFXIN V
Input High Voltage for HFXIN V
IRRX Input Filter Pulse-Width
Reject
IRRX Input Filter Pulse-Width
Accept
Output Low Voltage for IRTX V
Output Low Voltage for RESET
and All Port Pins (Note 9)
Output High Voltage for IRTX
and All Port Pins
Input/Output Pin Capacitance
for All Port Pins
Input Leakage Current I
Input Pullup Resistor for
RESET, IRTX, IRRX, P0, P1, P2
EXTERNAL CRYSTAL/RESONATOR
Crystal/Resonator f
Crystal/Resonator Period t
Crystal/Resonator Warmup
Time
Oscillator Feedback Resistor R
EXTERNAL CLOCK INPUT
External Clock Frequency f
External Clock Period t
External Clock Duty Cycle t
System Clock Frequency f
System Clock Period t
NANOPOWER RING
Nanopower Ring Frequency f
Nanopower Ring Duty Cycle t
Nanopower Ring Current I
to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1)
RST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IHYS
IL_HFXIN
IH_HFXIN
t
IRRX_R
t
IRRX_A
VDD = 3.3V, TA = +25NC
VDD = 3.6V, IOL = 25mA (Note 3) 1.0
OL_IRTX
= 2.35V, IOL = 10mA (Note 3) 1.0
DD
= 1.85V, IOL = 4.5mA 1.0
V
DD
VDD = 3.6V, IOL = 11mA (Note 3) 0.4 0.5
V
OL
V
OH
C
IO
L
R
PU
HFXIN
HFXIN
t
XTAL_RDY
OSCF
XCLK
XCLK
XCLK_DUTY
CK
CK
= 2.35V, IOL = 8mA (Note 3) 0.4 0.5
DD
= 1.85V, IOL = 4.5mA 0.4 0.5
V
DD
IOH = -2mA VDD - 0.5 V
(Note 4) 15 pF
Internal pullup disabled -100 +100 nA
VDD = 3.0V, VOL = 0.4V (Note 4) 16 28 39
V
= 2.0V, VOL = 0.4V 17 30 41
DD
From initial oscillation
(Note 4) 0.5 1.0 1.5
(Note 4) 45 55 %
HFXOUT = GND f
TA = +25NC
NANO
T
= +25NC, VDD = POR voltage
A
(Note 4)
NANO
NANO
(Note 4) 40 60 %
Typical at VDD = 1.64V,
T
= +25°C (Note 4)
A
300 mV
V
GND
0.7 x V
DD
0.3 x V
V
DD
DD
50 ns
300 ns
DD
1 12 MHz
1/f
HFXIN
8192 x
t
HFXIN
DC 12 MHz
1/f
XCLK
f
HFXIN
XCLK
1/f
CK
3.0 8.0 20.0
1.7 2.4
40 400 nA
MAXQ613
V
V
VV
VV
V
kW
ns
ms
MW
ns
MHz
ns
kHz
_______________________________________________________________________________________ 5
16-Bit Microcontroller with Infrared Module
RECOMMENDED OPERATING CONDITIONS (continued)
(VDD = V
WAKE-UP TIMER
Wake-Up Timer Interval t
FLASH MEMORY
MAXQ613
System Clock During Flash
Programming/Erase
Flash Erase Time
Flash Programming Time per
Word
Write/Erase Cycles 20,000 Cycles
Data Retention
IR
Carrier Frequency f
SPI ELECTRICAL CHARACTERISTICS
(VDD = V
SPI Master Operating
Frequency
SPI Slave Operating
Frequency
SPI I/O Rise/Fall Time t
SCLK Output Pulse-Width
High/Low
MOSI Output Hold Time After
SCLK Sample Edge
MOSI Output Valid to Sample
Edge
MISO Input Valid to SCLK
Sample Edge Rise/Fall Setup
MISO Input to SCLK Sample
Edge Rise/Fall Hold
SCLK Inactive to MOSI
Inactive
SCLK Input Pulse-Width High/
Low
SSEL Active to First Shift
Edge
MOSI Input to SCLK Sample
Edge Rise/Fall Setup
to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1)
RST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WAKEUP
f
FPSYSCLK
t
ME
t
ERASE
t
PROG
IR
to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 11)
RST
Mass erase 20 40
Page erase 20 40
(Note 10) 20 100
= +25NC
T
A
(Note 4) fCK/2 Hz
1/f
NANO
6 MHz
100 Years
65,535/
f
NANO
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
t
MCH
t
SCH
1/t
MCK
1/t
SCK
SPI_RF
, t
t
MOH
t
MOV
t
MIS
t
MIH
t
MLH
, t
t
SSE
t
SIS
CL = 15pF, pullup = 560W
MCL
SCL
8.3 23.6 ns
t
/2 -
MCK
t
SPI_RF
t
/2 -
MCK
t
SPI_RF
t
/2 -
MCK
t
SPI_RF
25 ns
0 ns
t
/2 -
MCK
t
SPI_RF
t
/2 ns
SCK
t
SPI_RF
t
SPI_RF
fCK/2 MHz
fCK/4 MHz
s
ms
Fs
ns
ns
ns
ns
ns
ns
6 ______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
SPI ELECTRICAL CHARACTERISTICS (continued)
(VDD = V
MOSI Input from SCLK
Sample Edge Transition Hold
MISO Output Valid After SCLK
Shift Edge Transition
SSEL Inactive
SCLK Inactive to SSEL Rising
MISO Output Disabled After
SSEL Edge Rise
Note 1:
Note 2: V
Note 3: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals
Note 4: Guaranteed by design and not production tested.
Note 5: Measured on the VDD pin and the device not in reset. All inputs are connected to GND or VDD. Outputs do not source/
Note 6: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles.
Note 7: Current consumption during POR when powering up while VDD is less than the POR release voltage.
Note 8: The minimum amount of time that VDD must be below V
Note 9: The maximum total current, I
Note 10: Programming time does not include overhead associated with utility ROM interface.
Note 11: AC electrical specifications are guaranteed by design and are not production tested.
to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 11)
RST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
t
SIH
t
SOV
t
SSH
t
SD
t
SLH
Specifications to 0NC are guaranteed by design and are not production tested. Typical = +25NC, VDD = +3.3V, unless
otherwise noted.
can be programmed to the following nominal voltage trip points: 1.8V, 1.9V, 2.55V, and 2.75V ±3%. The values
PFW
listed in the Recommended Operating Conditions table are for the default configuration of 1.8V nominal.
is active at all times when VDD < V
achieved.
sink any current. The device is executing code from flash memory.
User’s Guide for details.
OH(MAX)
maximum specified voltage drop. This does not include the IRTX output.
, ensuring the device maintains the reset state until minimum operating voltage is
RST
before a power-fail event is detected; refer to the MAXQ610
PFW
and I
OL(MAX)
, for all listed outputs combined should not exceed 32mA to satisfy the
t
SPI_RF
tCK +
t
SPI_RF
t
SPI_RF
2t
SPI_RF
2tCK +
2t
SPI_RF
ns
ns
ns
ns
ns
MAXQ613
_______________________________________________________________________________________ 7
16-Bit Microcontroller with Infrared Module
Pin Configurations
TOP VIEW
P2.4/TCK
MAXQ613
P2.5/TDI
P2.6/TMS
P2.7/TDO
RESET
V
GND
IRTX
IRRX
25
26
27
28
29
DD
30
31
+
32
1 2
P0.0/IRTXM/INT8
N.C.
P1.7/INT7
P1.6/INT6
P0.3/INT11
P0.4/INT12
HFXOUT
EP
P0.5/TBA0/TBA1/INT13
GND
21
2324 22 20 19 18
MAXQ613
4 5 6 7
3
P0.1/RX/INT9
P0.2/TX/INT10
TQFN
(5mm × 5mm)
TOP VIEW
P1.5/INT5
HFXIN
17
16
15
14
13
12
11
10
9
8
P0.7/TBB1/INT15
P0.6/TBB0/INT14
TOP VIEW
P2.5/TDI
25 16 P1.4/INT4
P1.4/INT4
V
DD
REGOUT
GND
P1.3/INT3
P1.2/INT2
P1.1/INT1
P1.0/INT0
P2.6/TMS
P2.7/TDO
26 15 V
27
28
RESET
29
V
DD
GND
30
31 10IRTX P1.1/INT1
32 9IRRX P1.0/INT0
+
N.C.
N.C.
P2.1/MISO
GND
P2.0/MOSI
P1.7/INT7
P1.6/INT6
P2.2/SCLK
P2.3/SSEL
3332313029282726252423
HFXOUT
N.C.
P2.4/TCK
2324 22 20 19 18
1 2
P0.1/RX/INT9
P0.0/IRTXM/INT8
P1.7/INT7
GND
21
MAXQ613
4 5 6 7
3
P0.3/INT11
P0.2/TX/INT10
LQFP
(7mm × 7mm)
HFXIN
P1.6/INT6
HFXOUT
P0.4/INT12
P0.5/TBA0/TBA1/INT13
P1.5/INT5
HFXIN
17
8
P0.7/TBB1/INT15
P0.6/TBB0/INT14
14
13
12
11
DD
REGOUT
GND
P1.3/INT3
P1.2/INT2
P2.4/TCK
P2.5/TDI
N.C.
N.C.
P2.6/TMS
P2.7/TDO
RESET
V
GND
IRTX
IRRX
34
35
36
37
38
39
40
41
DD
42
43
+
44
123456789
P0.0/IRTXM/INT8
N.C.
P0.1/RX/INT9
MAXQ613
N.C.
P0.2/TX/INT10
TQFN
P0.3/INT11
P0.4/INT12
P0.5/TBA0/TBA1/INT13
P0.6/TBB0/INT14
EP
10
11
P1.0/INT0
P0.7/TBB1/INT15
22
21
20
19
18
17
16
15
14
13
12
P1.5/INT5
P1.4/INT4
GND
V
DD
REGOUT
GND
N.C.
N.C.
P1.3/INT3
P1.2/INT2
P1.1/INT1
(7mm × 7mm)
8 ______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Pin Configurations (continued)
MAXQ613
TOP VIEW
P2.4/TCK
P2.5/TDI
P2.6/TMS
P2.7/TDO
N.C.
N.C.
RESET
V
GND
IRTX
IRRX
P2.3/SSEL
P2.2/SCLK
33
32
34
35
36
37
38
39
40
41
DD
42
43
44
+
1
2
N.C.
P0.0/IRTXM/INT8
N.C.
30
31
3
4
P0.1/RX/INT9
N.C.
N.C.
GND
P2.1/MISO
28
29
MAXQ613
5
P0.3/INT116P0.4/INT12
P0.2/TX/INT10
TQFP
(10mm × 10mm)
NOTE: CONTACT FACTORY FOR BARE DIE PAD CONFIGURATION.
P1.7/INT7
P2.0/MOSI
26
27
7
8
P0.5/TBA0/TBA1/INT13
HFXOUT24HFXIN
P1.6/INT6
23
25
9
11
10
P0.6/TBB0/INT14
P0.7/TBB1/INT15
P1.0/INT0
22 P1.5/INT5
21 P1.4/INT4
20 GND
19 V
DD
18 REGOUT
17 GND
16 N.C.
15 N.C.
14 P1.3/INT3
13 P1.2/INT2
12 P1.1/INT1
Pin Description
PIN
BARE DIE
32 TQFNEP/LQFP
44 TQFN-
EP/TQFP
15, 36 15, 29 19, 41 V
13, 16, 25,
37
13, 22, 30
17, 20, 28,
42
14 14 18 REGOUT
— — — EP Exposed Pad (TQFN Only). Connect EP directly to the ground plane.
_______________________________________________________________________________________ 9
NAME FUNCTION
POWER PINS
DD
Supply Voltage
GND Ground. Connect directly to the ground plane.
1.8V Regulator Output. This pin must be connected to ground through
a 1.0FF (ESR: 2W–10W) external ceramic-chip capacitor. The capacitor
must be placed as close to this pin as possible. No devices other than
the capacitor should be connected to this pin.
16-Bit Microcontroller with Infrared Module
Pin Description (continued)
PIN
BARE DIE
32 TQFNEP/LQFP
MAXQ613
35 28 40 RESET
20 18 23 HFXIN
21 19 24 HFXOUT
38 31 43 IRTX
44 TQFN-
EP/TQFP
NAME FUNCTION
RESET PIN
Digital, Active-Low, Reset Input/Output. The device remains in reset
as long as this pin is low and begins executing from the utility ROM at
address 8000h when this pin returns to a high state. The pin includes
pullup current source; if this pin is driven by an external device, it should
be driven by an open-drain source capable of sinking in excess of 4mA.
This pin can be left unconnected if there is no need to place the device in
a reset state using an external signal. This pin is driven low as an output
when an internal reset condition occurs.
CLOCK PINS
High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT for use as the high-frequency system
clock. Alternatively, HFXIN is the input for an external, high-frequency
clock source when HFXOUT is unconnected.
IR FUNCTION PINS
IR Transmit Output. IR transmission pin capable of sinking 25mA. This
pin defaults to a high-impedance input with the weak pullup disabled
during all forms of reset. Software must configure this pin after release
from reset to remove the high-impedance input condition.
IR Receive Input. This pin defaults to a high-impedance input with the
39 32 44 IRRX
GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS
1 1 1
2 2 3
3 3 5
4 4 6 P0.3/INT11 P0.3 INT11
5 5 7 P0.4/INT12 P0.4 INT12
6 6 8
P0.0/IRTXM/
INT8
P0.1/RX/
INT9
P0.2/TX/
INT10
P0.5/TBA0/
TBA1/INT13
weak pullup disabled during all forms of reset. Software must configure
this pin after release from reset to remove the high-impedance input
condition.
Port 0 General-Purpose, Digital I/O Pins. These port pins function as
general-purpose I/O pins with their input and output states controlled by
the PD0, PO0, and PI0 registers. All port pins default to high-impedance
mode after a reset. Software must configure these pins after release
from reset to remove the high-impedance condition. All alternate functions must be enabled from software before they can be used.
GPIO PORT PIN SPECIAL FUNCTION
P0.0 IR Modulator Output/INT8
P0.1 USART Receive/INT9
P0.2 USART Transmit/INT10
P0.5
Type B Timer 0 Pin A or Type B
Timer 1 Pin A/INT13
10 _____________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Pin Description (continued)
PIN
BARE DIE
7 7 9
8 8 10
9 9 11 P1.0/INT0 P1.0 INT0
10 10 12 P1.1/INT1 P1.1 INT1
11 11 13 P1.2/INT2 P1.2 INT2
12 12 14 P1.3/INT3 P1.3 INT3
17 16 21 P1.4/INT4 P1.4 INT4
18 17 22 P1.5/INT5 P1.5 INT5
22 20 25 P1.6/INT6 P1.6 INT6
23 21 26 P1.7/INT7
24 — 27 P2.0/MOSI P2.0 SPI: Master Out-Slave In
26 — 29 P2.1/MISO P2.1 SPI: Master In-Slave Out
28 — 32 P2.2/SCLK P2.2 SPI: Slave Clock
30 — 33 P2.3/SSEL P2.3 SPI: Active-Low Slave Select
31 24 34 P2.4/TCK P2.4 JTAG: Test Clock
32 25 35 P2.5/TDI P2.5 JTAG: Test Data In
33 26 38 P2.6/TMS P2.6 JTAG: Test Mode Select
34
— 23
32 TQFN-
EP/LQFP
27 39 P2.7/TDO
44 TQFN-
EP/TQFP
2, 4, 15, 16,
30, 31, 36,
37
NAME FUNCTION
P0.6/TBB0/
INT14
P0.7/TBB1/
INT15
Port 1 General-Purpose, Digital I/O Pins with Interrupt Capability. These
port pins function as general-purpose I/O pins with their input and output states controlled by the PD1, PO1, and PI1 registers. All port pins
default to high-impedance mode after a reset. Software must configure
these pins after release from reset to remove the high-impedance condition. All external interrupts must be enabled from software before they
can be used.
Port 2 General-Purpose, Digital I/O Pins. These port pins function as
general-purpose I/O pins with their input and output states controlled by
the PD2, PO2, and PI2 registers. All port pins default to high-impedance
mode after a reset. Software must configure these pins after release
from reset to remove the high-impedance condition. All special functions must be enabled from software before they can be used.
NO CONNECTION PINS
N.C. No Connection. Not internally connected.
P0.6 Type B Timer 0 Pin B/INT14
P0.7 Type B Timer 1 Pin B/INT15
GPIO PORT PIN EXTERNAL INTERRUPT
P1.7 INT7
GPIO PORT PIN SPECIAL FUNCTION
P2.7 JTAG: Test Data Out
MAXQ613
______________________________________________________________________________________ 11
16-Bit Microcontroller with Infrared Module
Block Diagram
MAXQ613
REGULATOR
MAXQ613
VOLTAGE
MONITOR
GPIO
2x
16-BIT TIMER
16-BIT MAXQ
CLOCK
WATCHDOG
8kHz NANO
RING
RISC CPU
48KB FLASH
MEMORY
1.5KB
UTILITY ROM
5.5KB
DATA SRAM
IR DRIVER
IR TIMER
SPI
USART
Detailed Description
The MAXQ613 provides integrated, low-cost solutions
that simplify the design of IR communications equipment
such as universal remote controls. Standard features
include the highly optimized, single-cycle, MAXQ, 16-bit
RISC core; 48KB of program flash memory; 1.5KB data
RAM; soft stack; 16 general-purpose registers; and
three data pointers. The MAXQ core has the industry’s
best MIPS/mA rating, allowing developers to achieve
the same performance as competing microcontrollers
at substantially lower clock rates. Lower active-mode
current combined with the even lower MAXQ613 stopmode current (0.2FA typ) results in increased battery life.
Application-specific peripherals include flexible timers
for generating IR carrier frequencies and modulation. A
high-current IR drive pin capable of sinking up to 25mA
current and output pins capable of sinking up to 5mA
are ideal for IR applications. It also includes generalpurpose I/O pins ideal for keypad matrix input, and a
power-fail-detection circuit to notify the application when
the supply voltage is nearing the microcontroller’s minimum operating voltage.
At the heart of the device is the MAXQ 16-bit, RISC core.
Operating from DC to 12MHz, almost all instructions execute in a single clock cycle (83.3ns at 12MHz), enabling
nearly 12MIPS true-code operation. When active device
operation is not required, an ultra-low-power stop mode
can be invoked from software, resulting in quiescent
current consumption of less than 0.2FA (typ) and 2.0FA
(max). The combination of high-performance instructions
and ultra-low stop-mode current increases battery life
over competing microcontrollers. An integrated POR circuit with brownout support resets the device to a known
condition following a power-up cycle or brownout condition. Additionally, a power-fail warning flag is set, and a
power-fail interrupt can be generated when the system
voltage falls below the power-fail warning voltage, V
PFW
The power-fail warning feature allows the application to
notify the user that the system supply is low and appropriate action should be taken.
Microprocessor
The device is based on Maxim’s low-power, 16-bit MAXQ
family of RISC cores. The core supports the Harvard
memory architecture with separate 16-bit program and
data address buses. A fixed 16-bit instruction word is
standard, but data can be arranged in 8 or 16 bits. The
MAXQ core in the device is implemented as a pipelined processor with performance approaching 1MIPS
per MHz. The 16-bit data path is implemented around
register modules, and each register module contributes
specific functions to the core. The accumulator module
consists of sixteen 16-bit registers and is tightly coupled
with the arithmetic logic unit (ALU). A configurable soft
stack supports program flow.
Execution of instructions is triggered by data transfer
between functional register modules or between a functional register module and memory. Because data movement involves only source and destination modules,
circuit switching activities are limited to active modules
only. For power-conscious applications, this approach
localizes power dissipation and minimizes switching
noise. The modular architecture also provides a maximum of flexibility and reusability that are important for a
microprocessor used in embedded applications.
The MAXQ instruction set is highly orthogonal. All arithmetical and logical operations can use any register
in conjunction with the accumulator. Data movement
is supported from any register to any other register.
Memory is accessed through specific data-pointer registers with autoincrement/decrement support.
.
12 _____________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Memory
The microcontroller incorporates several memory types:
• 48KB program flash memory
• 1.5KB SRAM data memory
• 5.5KB utility ROM
• Soft stack
Memory Protection
The optional memory-protection feature separates code
memory into three areas: system, user loader, and user
application. Code in the system area can be kept confidential. Code in the user areas can be prevented from
reading and writing system code. The user loader can
also be protected from user application code.
Memory protection is implemented using privilege levels
for code. Each area has an associated privilege level.
RAM/ROM are assigned privilege levels as well. Refer to
the MAXQ610 User’s Guide for a more thorough explanation of the topic. See Table 1.
Stack Memory
The device provides a soft stack that can be used to
store program return addresses (for subroutine calls
and interrupt handling) and other general-purpose data.
This soft stack is located in the 1.5KB SRAM data
memory, which means that the SRAM data memory must
be shared between the soft stack and general-purpose
application data storage. However, the location and
size of the soft stack is determined by the user, providing maximum flexibility when allocating resources for a
particular application. The stack is used automatically
by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced. An
application can also store and retrieve values explicitly
using the stack by means of the PUSH, POP, and POPI
instructions.
The SP pointer indicates the current top of the stack,
MAXQ613
which initializes by default to the top of the SRAM data
memory. As values are pushed onto the stack, the SP
pointer decrements, which means that the stack grows
downward towards the bottom (lowest address) of the
data memory. Popping values off the stack causes the
SP pointer value to increase. Refer to the MAXQ610
User’s Guide for more details.
Utility ROM
The utility ROM is a 5.5KB block of internal ROM memory
located in program space beginning at address 8000h.
This ROM includes the following routines:
• In-system programming (bootstrap loader) using
JTAG interface
• In-circuit debugging routines using JTAG interface
• Production test routines (internal memory tests,
memory loader, etc.), which are used for internal
testing only, and are generally of no use to the endapplication developer
• User-callable routines for in-application flash programming, buffer copying, and fast table lookup (more
information on these routines can be found in the
MAXQ610 User’s Guide)
Following any reset, execution begins in the utility ROM
at address 8000h. At this point, unless loader mode or
test mode has been invoked (which requires special programming through the JTAG interface), the utility ROM in
the device always automatically jumps to location 0000h,
which is the beginning of user application code in program flash memory.
Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, in-application programming, or in-circuit debugging functions is
prohibited until a password has been supplied. Three
Table 1. Memory Areas and Associated Maximum Privilege Levels
AREA PAGE ADDRESS MAXIMUM PRIVILEGE LEVEL
System 0 to ULDR-1 High
User Loader ULDR to UAPP-1 Medium
User Application UAPP to top Low
Utility ROM N/A High
Other (RAM) N/A Low
______________________________________________________________________________________ 13
16-Bit Microcontroller with Infrared Module
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
WD[1:0] WATCHDOG CLOCK WATCHDOG INTERRUPT TIMEOUT
00 Sysclk/2
01 Sysclk/2
10 Sysclk/2
11 Sysclk/2
15
18
21
24
MAXQ613
different password locks are provided, each of which
can be used to protect a different area of memory (system memory, user loader, and user application). Each
password lock is controlled by a 16-word area of flash
memory; if the password is set to all FFFFh values or all
0000h values, the password is disabled. Otherwise, the
password is active and must be matched by the user of
the bootloader or debugger before access is granted to
the corresponding area of flash program memory. Refer
to the MAXQ610 User’s Guide for more details.
Watchdog Timer
The internal watchdog timer greatly increases system
reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the application software. If software is operating correctly, the counter is periodically reset and never reaches its maximum
count. However, if software operation is interrupted,
the timer does not reset, triggering a system reset and
optionally a watchdog timer interrupt. This protects the
system against electrical noise or electrostatic discharge
(ESD) upsets that could cause uncontrolled processor
operation. The internal watchdog timer is an upgrade to
older designs with external watchdog devices, reducing
system cost and simultaneously increasing reliability.
The watchdog timer functions as the source of both the
watchdog timer timeout and the watchdog timer reset.
The timeout period can be programmed in a range of
15
to 224 system clock cycles. An interrupt is gener-
2
ated when the timeout period expires if the interrupt
is enabled. All watchdog timer resets follow the programmed interrupt timeouts by 512 system clock cycles.
If the watchdog timer is not restarted for another full
interval in this time period, a system reset occurs when
the reset timeout expires. See Table 2.
WATCHDOG RESET AFTER
WATCHDOG INTERRUPT (µs)
2.7ms 42.7
21.9ms 42.7
174.7ms 42.7
1.4s 42.7
IR Carrier Generation
and Modulation Timer
The dedicated IR timer/counter module simplifies lowspeed infrared (IR) communication. The IR timer implements two pins (IRTX and IRRX) for supporting IR
transmit and receive, respectively. The IRTX pin has no
corresponding port pin designation, so the standard
PD, PO, and PI port control status bits are not present.
However, the IRTX pin output can be manipulated high
or low using the PWCN.IRTXOUT and PWCN.IRTXOE
bits when the IR timer is not enabled (i.e., IREN = 0).
The IR timer is composed of a carrier generator and a
carrier modulator. The carrier generation module uses
the 16-bit IR carrier register (IRCA) to define the high
and low time of the carrier through the IR carrier high
byte (IRCAH) and IR carrier low byte (IRCAL). The carrier
modulator uses the IR data bit (IRDATA) and IR modulator time register (IRMT) to determine whether the carrier
or the idle condition is present on IRTX.
The IR timer is enabled when the IR enable bit (IREN) is
set to 1. The IR Value register (IRV) defines the beginning value for the carrier modulator. During transmission,
the IRV register is initially loaded with the IRMT value
and begins down counting towards 0000h, whereas
in receive mode it counts upward from the initial IRV
register value. During the receive operation, the IRV
register can be configured to reload with 0000h when
capture occurs on detection of selected edges or can be
allowed to continue free-running throughout the receive
operation. An overflow occurs when the IR timer value
rolls over from 0FFFFh to 0000h. The IR overflow flag
(IROV) is set to 1 and an interrupt is generated if enabled
(IRIE = 1).
14 _____________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Carrier Generation Module
The IRCAH byte defines the carrier high time in terms of
the number of IR input clocks, whereas the IRCAL byte
defines the carrier low time.
• IR Input Clock (f
IRCLK
• Carrier Frequency (f
) = f
CARRIER
SYS
IRDIV[1:0]
/2
) = f
IRCLK
/(IRCAH +
IRCAL + 2)
• Carrier High Time = IRCAH + 1
• Carrier Low Time = IRCAL + 1
• Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2)
During transmission, the IRCA register is latched for
each IRV down-count interval, and is sampled along with
the IRTXPOL and IRDATA bits at the beginning of each
new IRV down-count interval so that duty-cycle variation
and frequency shifting is possible from one interval to the
next, which is illustrated in Figure 1.
IRCA
IRMT IRMT = 5
IRCA = 0202h IRCA = 0002h
IRMT = 3
Figure 2 illustrates the basic carrier generation and its
MAXQ613
path to the IRTX output pin. The IR transmit polarity bit
(IRTXPOL) defines the starting/idle state and the carrier
polarity of the IRTX pin when the IR timer is enabled.
IR Transmission
During IR transmission (IRMODE = 1), the carrier generator creates the appropriate carrier waveform, while
the carrier modulator performs the modulation. The carrier modulation can be performed as a function of carrier
cycles or IRCLK cycles dependent on the setting of the
IRCFME bit. When IRCFME = 0, the IRV down counter is
clocked by the carrier frequency and thus the modulation is a function of carrier cycles. When IRCFME = 1, the
IRV down counter is clocked by IRCLK, allowing carrier
modulation timing with IRCLK resolution.
The IRTXPOL bit defines the starting/idle state as well as
the carrier polarity for the IRTX pin. If IRTXPOL = 1, the
3 12 0 5 4 3 2 1 0
CARRIER OUTPUT
(IRV)
IRDATA
0
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0)
IRCA, IRMT, IRDATA SAMPLED AT END OF IRV
DOWN-COUNT INTERVAL
01
______________________________________________________________________________________ 15
16-Bit Microcontroller with Infrared Module
IRTX pin is set to a logic-high when the IR timer module is
enabled. If IRTXPOL = 0, the IRTX pin is set to a logic-low
when the IR timer is enabled.
A separate register bit, IR data (IRDATA), is used to
determine whether the carrier generator output is output
to the IRTX pin for the next IRMT carrier cycles. When
IRDATA = 1, the carrier waveform (or inversion of this
waveform if IRTXPOL = 1) is output on the IRTX pin dur-
MAXQ613
ing the next IRMT cycles. When IRDATA = 0, the idle
CARRIER GENERATION
IRCAL + 1IRCAH + 1
condition, as defined by IRTXPOL, is output on the IRTX
pin during the next IRMT cycles.
The IR timer acts as a down counter in transmit mode. An
IR transmission starts when the IREN bit is set to 1 when
IRMODE = 1; when the IRMODE bit is set to 1 when IREN
= 1; or when IREN and IRMODE are both set to 1 in the
same instruction. The IRMT and IRCA registers, along
with the IRDATA and IRTXPOL bits, are sampled at the
beginning of the transmit process and every time the IR
IRDATA
IRMT
IRTXPOL
CARRIERIRCLK
IRCFME
0
1
SAMPLE
IRDATA ON
IRV = 0000h
CARRIER MODULATION
0
IRTX PIN
1
IR INTERRUPT
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control
IRMT = 3
CARRIER OUTPUT
(IRV)
IRDATA
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
23 1 0 23 1 0
0
01
Figure 3. IR Transmission Waveform (IRCFME = 0)
16 _____________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
timer value reloads its value. When the IRV reaches 0000h
value, on the next carrier clock, it does the following:
1) Reloads IRV with IRMT.
2) Samples IRCA, IRDATA, and IRTXPOL.
3) Generates IRTX accordingly.
4) Sets IRIF to 1.
5) Generates an interrupt to the CPU if enabled (IRIE = 1).
To terminate the current transmission, the user can
switch to receive mode (IRMODE = 0) or clear IREN to 0.
Carrier Modulation Time = IRMT + 1 carrier cycles
IR Transmit—Independent External Carrier
and Modulator Outputs
The normal transmit mode modulates the carrier based
upon the IRDATA bit. However, the user has the option
to input the modulator (envelope) on an external pin if
desired. If the IRENV[1:0] bits are configured to 01b or
10b, the modulator/envelope is output to the IRTXM pin.
The IRDATA bit is output directly to the IRTXM pin (if
IRTXPOL = 0) on each IRV down-count interval boundary just as if it were being used to internally modulate
the carrier frequency. If IRTXPOL = 1, the inverse of
the IRDATA bit is output to the IRTXM pin on the IRV
interval down-count boundaries. See Figure 4. When
the envelope mode is enabled, it is possible to output
either the modulated (IRENV[1:0] = 01b) or unmodulated
(INENV[1:0] = 10b) carrier to the IRTX pin.
IR Receive
MAXQ613
When configured in receive mode (IRMODE = 0), the
IR hardware supports the IRRX capture function. The
IRRXSEL[1:0] bits define which edge(s) of the IRRX pin
should trigger the IR timer capture function.
The IR module starts operating in the receive mode when
IRMODE = 0 and IREN = 1. Once started, the IR timer
(IRV) starts up counting from 0000h when a qualified
capture event as defined by IRRXSEL happens. The IRV
register is, by default, counting carrier cycles as defined
by the IRCA register. However, the IR carrier frequency
detect (IRCFME) bit can be set to 1 to allow clocking of
the IRV register directly with the IRCLK for finer resolution. When IRCFME = 0, the IRCA defined carrier is
counted by IRV. When IRCFME = 1, the IRCLK clocks
the IRV register.
On the next qualified event, the IR module does the
following:
1) Captures the IRRX pin state and transfers its value
to IRDATA. If a falling edge occurs, IRDATA = 0. If a
rising edge occurs, IRDATA = 1.
2) Transfers its current IRV value to the IRMT.
3) Resets IRV content to 0000h (if IRXRL = 1).
4) Continues counting again until the next qualified event.
If the IR timer value rolls over from 0FFFFh to 0000h
before a qualified event happens, the IR timer overflow
(IROV) flag is set to 1 and an interrupt is generated, if
IRTXM
IRTXPOL = 1
IRTXM
IRTXPOL = 0
IRDATA
0 1 0 1 01 01
IR INTERRUPT
IRV INTERVAL
Figure 4. External IRTXM (Modulator) Output
IRMT IRMT IRMTIRMT
______________________________________________________________________________________ 17
16-Bit Microcontroller with Infrared Module
CARRIER GENERATION
IRCLK
IRCAL + 1IRCAH + 1
MAXQ613
IRRX PIN
Figure 5. IR Capture
enabled. The IR module continues to operate in receive
mode until it is stopped by switching into transmit mode
(IRMODE = 1) or clearing IREN = 0.
Carrier Burst-Count Mode
A special mode reduces the CPU processing burden
when performing IR learning functions. Typically, when
operating in an IR learning capacity, some number of
carrier cycles are examined for frequency determination. Once the frequency has been determined, the IR
receive function can be reduced to counting the number
of carrier pulses in the burst and the duration of the
combined mark-space time within the burst. To simplify
this process, the receive burst-count mode (as enabled
by the RXBCNT bit) can be used. When RXBCNT = 0,
the standard IR receive capture functionality is in place.
When RXBCNT = 1, the IRV capture operation is disabled and the interrupt flag associated with the capture
no longer denotes a capture. In the carrier burst-count
mode, the IRMT register only counts qualified edges.
The IRIF interrupt flag (normally used to signal a capture
when RXBCNT = 0) now becomes set if two IRCA cycles
elapse without getting a qualified edge. The IRIF interrupt flag thus denotes absence of the carrier and the
beginning of a space in the receive signal. When the
RXBCNT bit is changed from 0 to 1, the IRMT register
is set to 0001h. The IRCFME bit is still used to define
whether the IRV register is counting system IRCLK
clocks or IRCA-defined carrier cycles. The IRXRL bit
defines whether the IRV register is reloaded with 0000h
on detection of a qualified edge (per the IRXSEL[1:0]
bits). Figure 6 and the descriptive sequence embedded
EDGE DETECT
0
1
IRCFME
CARRIER MODULATION
IR TIMER OVERFLOW
INTERRUPT TO CPU
0000h IRV
IR INTERRUPT
COPY IRV TO IRMT
ON EDGE DETECT
IRXRL
RESET IRV TO 0000h
IRDATA
in the figure illustrate the expected usage of the receive
burst-count mode.
16-Bit Timers/Counters
The microcontroller provides two timers/counters that
support the following functions:
• 16-bit timer/counter
• 16-bit up/down autoreload
• Counter function of external pulse
• 16-bit timer with capture
• 16-bit timer with compare
• Input/output enhancements for pulse-width modulation
• Set/reset/toggle output state on comparator match
• Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10)
USART
The device provides a USART peripheral with the following features:
• 2-wire interface
• Full-duplex operation for asynchronous data transfers
• Half-duplex operation for synchronous data transfers
• Programmable interrupt when transmit or receive data
operation completes
• Independent programmable baud-rate generator
• Optional 9th bit parity support
• Start/stop bit support
18 _____________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
CARRIER FREQUENCY
IRRX
IRV
IRMT
CALCULATION
1
2 3 4 6 7
IRMT = PULSE COUNTING IRMT = PULSE COUNTING
5
IRV = CARRIER CYCLE COUNTING
8
9
MAXQ613
1 4
CAPTURE INTERRUPT (IRIF = 1).
TO
≥ IRMT.
IRV
IRV = 0 (IF IRXRL = 1).
SOFTWARE SETS IRCA = CARRIER FREQUENCY.
SOFTWARE SETS RXBCNT = 1 (WHICH CLEARS IRMT = 0001 IN HARDWARE).
5
SOFTWARE CLEARS IRCFME = 0 SO THAT IRV COUNTS CARRIER CYCLES. IRV IS RESET TO 0 ON QUALIFIED EDGE DETECTION IF IRXRL = 1.
SOFTWARE ADDS TO IRMT THE NUMBER OF PULSES USED FOR CARRIER MEASUREMENT.
IRCA x 2x COUNTER FOR SPACE CAN BEGIN IMMEDIATELY (QUALIFIED EDGE RESETS).
QUALIFIED EDGE DETECTED: IRMT++
6
IRV RESET TO 0 IF IRXRL = 1.
IRCA x 2 PERIOD ELAPSES: IRIF = 1; CARRIER ABSENCE = SPACE.
7
BURST MARK = IRMT PULSES.
SOFTWARE CLEARS RXBCNT = 0 SO THAT WE CAPTURE ON THE NEXT QUALIFIED EDGE.
8
QUALIFIED EDGE DETECTED: IRIF = 1, CAPTURE IRV IRMT AS THE BURST SPACE (PLUS UP TO ONE CARRIER CYCLE).
9
SOFTWARE SET RXBCNT = 1 AS IN (5).
CONTINUE (5) TO (8) UNTIL LEARNING SPACE EXCEEDS SOME DURATION. IRV ROLLOVERS CAN BE USED.
Figure 6. Receive Burst-Count Example
Table 3. USART Mode Details
MODE TYPE START BITS DATA BITS STOP BITS
Mode 0 Synchronous N/A 8 N/A
Mode 1 Asynchronous 1 8 1
Mode 2 Asynchronous 1 8 + 1 1
Mode 3 Asynchronous 1 8 + 1 1
Serial Peripheral Interface (SPI)
The integrated SPI provides an independent serial
communication channel that communicates synchronously with peripheral devices in a multiple master or
multiple slave system. The interface allows access to
a 4-wire, full-duplex serial bus, and can be operated in
either master mode or slave mode. Collision detection
______________________________________________________________________________________ 19
is provided when two or more masters attempt a data
transfer at the same time.
The maximum SPI master transfer rate is Sysclk/2. When
operating as an SPI slave, the device can support up to
Sysclk/4 SPI transfer rate. Data is transferred as an 8-bit
or 16-bit value, MSB first. In addition, the SPI module
supports configuration of an active SSEL state (active
low or active high) through the slave active select.
16-Bit Microcontroller with Infrared Module
SHIFT SAMPLE SHIFT SAMPLE
SSEL
t
SCLK
CKPOL/CKPHA
0/1 OR 1/0
MAXQ613
SCLK
CKPOL/CKPHA
0/0 OR 1/1
MOSI
MCK
t
MCH
t
MOH
MSB MSB-1
t
MCL
t
MOV
t
RF
LSB
t
MLH
t
MIS
MISO
MSB MSB-1
Figure 7. SPI Master Communication Timing
SHIFT SAMPLE SHIFT SAMPLE
SSEL
SCLK
CKPOL/CKPHA
0/1 OR 1/0
SCLK
CKPOL/CKPHA
0/0 OR 1/1
MOSI
t
SSE
t
SIS
MSB MSB-1
t
SCK
t
SCH
t
MIH
LSB
t
SSH
t
SD
t
SCL
t
SIH
LSB
MISO
t
SOV
MSB MSB-1
t
RF
LSB
t
SLH
Figure 8. SPI Slave Communication Timing
20 _____________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
General-Purpose I/O
The microcontroller provides port pins for general-purpose I/O that have the following features:
• CMOS output drivers
• Schmitt trigger inputs
• Optional weak pullup to VDD when operating in input
mode
While the microcontroller is in a reset state, all port pins
become high impedance with both weak pullups and
input buffers disabled, unless otherwise noted.
From a software perspective, each port appears as a
group of peripheral registers with unique addresses.
Special function pins can also be used as general-purpose I/O pins when the special functions are disabled.
For a detailed description of the special functions available for each pin, refer to the MAXQ610 User’s Guide.
On-Chip Oscillator
An external quartz crystal or a ceramic resonator can be
connected between HFXIN and HFXOUT, as illustrated
in Figure 9.
Noise at HFXIN and HFXOUT can adversely affect onchip clock timing. It is good design practice to place the
crystal and capacitors near the oscillator circuitry and
connect HFXIN and HFXOUT to ground with a direct
short trace. The typical values of external capacitors vary
with the type of crystal to be used and should be initially
selected based on load capacitance as suggested by
the manufacturer.
V
DD
HFXIN
HFXOUT
C1
C2
Figure 9. On-Chip Oscillator
R
F
R
= 1MI Q50%
F
C1 = C2 = 12pF
CLOCK CIRCUIT
STOP
MAXQ613
ROM Loader
The ROM loader denies access to the system, user loader, or user-application memories unless an area-specific
password is provided. The ROM loader is not available
in ROM-only versions.
Loading Flash Memory
An internal bootstrap loader allows reloading over a
simple JTAG interface. As a result, software can be
upgraded in-system, eliminating the need for a costly
hardware retrofit when updates are required. Remote
software uploads are possible that enable physically
inaccessible applications to be frequently updated. The
interface hardware can be a JTAG connection to another
microcontroller, or a connection to a PC serial port using
a serial-to-JTAG converter such as the MAXQJTAG-001,
available from Maxim. If in-system programmability is not
required, a commercial gang programmer can be used
for mass programming. Activating the JTAG interface
and loading the test access port (TAP) with the system
programming instruction invokes the bootstrap loader.
Setting the SPE bit to one during reset through the JTAG
interface executes the bootstrap-loader mode program
that resides in the utility ROM. When programming is
complete, the bootstrap loader can clear the SPE bit and
reset the device, allowing the device to bypass the utility
ROM and begin execution of the application software.
In addition, the ROM loader also enforces the memoryprotection policies. Passwords that are 16 words are
required to access the ROM loader interface.
Loading memory is not possible for ROM-only versions
of the device.
In-Application Flash Programming
From user-application code, flash memory can be programmed using the ROM utility functions from either C
or assembly language. The function declarations below
show examples of some of the ROM utility functions
provided for in-application flash memory programming:
/* Write one 16-bit word to code address ‘dest’.
* Dest must be aligned to 16 bits.
* Returns 0 = failure, 1 = OK.
*/
int flash_write (uint16_t dest, uint16_t
data);
______________________________________________________________________________________ 21
16-Bit Microcontroller with Infrared Module
• Debug mode:
Debugger takes over the control of the CPU
DEBUG
SERVICE
MAXQ613
MAXQ613
TMS
TCK
TDI
TDO
Figure 10. In-Circuit Debugger
TAP
CONTROLLER
ROUTINES
(UTILITY ROM)
CPU
DEBUG
ENGINE
CONTROL
BREAKPOINT
ADDRESS
DATA
To erase, the following function would be used:
/* Erase the given Flash page
* addr: Flash offset (anywhere within page)
*/
int flash_erasepage(uint16_t addr);
The in-application flash memory programming must call
ROM utility functions to erase and program any of the
flash memory. Memory protection is enforced by the
ROM utility functions. In-application is not available in
ROM-only versions of the device.
In-Circuit Debug and JTAG
Interface
Embedded debug hardware and software are developed and integrated to provide full in-circuit debugging
capability in a user-application environment. These hardware and software features include the following:
• Debug engine
• Set of registers providing the ability to set breakpoints
on register, code, or data using debug service routines stored in ROM
Collectively, these hardware and software features support two modes of in-circuit debug functionality:
• Background mode:
CPU is executing the normal user program
Allows the host to configure and set up the in-circuit
debugger
Read/write accesses to internal registers and memory
Single-step of the CPU for trace operation
The interface to the debug engine is the TAP controller. The interface allows for communication with a bus
master that can either be automatic test equipment or a
component that interfaces to a higher level test bus as
part of a complete system. The communication operates
across a 4-wire serial interface from a dedicated TAP
that is compatible with the JTAG IEEE Standard 1149.
The TAP provides an independent serial channel to communicate synchronously with the host system.
To prevent unauthorized access of the protected memory regions through the JTAG interface, the debug engine
prevents modification of the privilege registers and
disallows all access to system memory, unless memory
protection is disabled. In addition, all services (such as
register display or modification) are denied when code
is executing inside the system area. The debugger is not
available for ROM-only versions of the device.
Operating Modes
The lowest power mode of operation is stop mode. In this
mode, CPU state and memories are preserved, but the
CPU is not actively running. Wake-up sources include
external I/O interrupts, the power-fail warning interrupt,
wake-up timer, or a power-fail reset. Any time the microcontroller is in a state where code does not need to be
executed, the user software can put the device into stop
mode. The nanopower ring oscillator is an internal ultralow-power (400nA) 8kHz ring oscillator that can be used
to drive a wake-up timer that exits stop mode. The wakeup timer is programmable by software in steps of 125Fs
up to approximately 8s.
The power-fail monitor is always on during normal operation. However, it can be selectively disabled during stop
mode to minimize power consumption. This feature is
enabled using the power-fail monitor disable (PFD) bit
in the PWCN register. The reset default state for the PFD
bit is 1, which disables the power-fail monitor function
during stop mode. If power-fail monitoring is disabled
(PFD = 1) during stop mode, the circuitry responsible
for generating a power-fail warning or reset is shut down
and neither condition is detected. Thus, the V
condition does not invoke a reset state.
DD
< V
RST
22 _____________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Power-Fail Detection
Figures 11, 12, and 13 show the power-fail detection and
response during normal and stop-mode operation. If a
reset is caused by a power-fail, the power-fail monitor
can be set to one of the following intervals:
• Always on—continuous monitoring
11
nanopower ring oscillator clocks (~256ms)
• 2
12
• 2
nanopower ring oscillator clocks (~512ms)
13
• 2
nanopower ring oscillator clocks (~1.024s)
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
V
DD
V
PFW
V
RST
V
POR
A
C
B
< t
t
PFW
D
t ≥ t
PFW
E
nanopower ring-oscillator cycles. If V
detection, V
ring-oscillator period. If V
is monitored for an additional nanopower
DD
remains above V
DD
DD
> V
RST
during
for
RST
the third nanopower ring period, the CPU exits the reset
state and resumes normal operation from utility ROM at
8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watchdog
timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the CPU
exits the reset state in less than 20 crystal cycles after
the reset source is removed.
t ≥ t
PFW
F
t ≥ t
PFW
G
H
I
MAXQ613
INTERNAL RESET
(ACTIVE HIGH)
Figure 11. Power-Fail Detection During Normal Operation
______________________________________________________________________________________ 23
16-Bit Microcontroller with Infrared Module
Table 4. Power-Fail Detection States During Normal Operation
STATE POWER-FAIL
A On Off Off — V
B On On On —
MAXQ613
C On On On —
D On On On —
E On On On —
F
G On On On —
On
(Periodically)
INTERNAL
REGULATOR
Off Off Yes
CRYSTAL
OSCILLATOR
SRAM
RETENTION
COMMENTS
< V
DD
V
POR
Crystal warmup time, t
CPU held in reset.
> V
V
DD
CPU normal operation.
Power drop too short.
Power-fail not detected.
V
RST
PFI is set when V
maintains this state for at least t
which time a power-fail interrupt is generated (if enabled).
CPU continues normal operation.
V
POR
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
VDD > V
Crystal warmup time, t
CPU resumes normal operation from 8000h.
.
POR
< VDD < V
.
RST
< VDD < V
< VDD < V
.
RST
.
RST
.
PFW
< VDD < V
RST
.
RST
XTAL_RDY
XTAL_RDY
.
PFW
PFW
.
and
, at
< VDD < V
V
POR
H
I Off Off Off —
24 _____________________________________________________________________________________
On
(Periodically)
Off Off Yes
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
V
< V
DD
Device held in reset. No operation allowed.
POR
.
RST
.
16-Bit Microcontroller with Infrared Module
V
DD
A
V
PFW
V
RST
V
POR
STOP
INTERNAL RESET
(ACTIVE HIGH)
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
t < t
PFW
B C
t ≥ t
PFW
MAXQ613
t ≥ t
PFW
D
E
F
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
STATE POWER-FAIL
INTERNAL
REGULATOR
A On Off Off Yes
B On Off Off Yes
C On On On Yes
D On Off Off Yes
E
On
(Periodically)
Off Off Yes
F Off Off Off —
CRYSTAL
OSCILLATOR
SRAM
RETENTION
COMMENTS
Application enters stop mode.
> V
V
DD
RST
.
CPU in stop mode.
Power drop too short.
Power-fail not detected.
V
RST
< VDD < V
PFW
.
Power-fail warning detected.
Turn on regulator and crystal.
Crystal warmup time, t
XTAL_RDY
.
Exit stop mode.
Application enters stop mode.
V
> V
RST
.
DD
CPU in stop mode.
V
POR
< VDD < V
RST
.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
V
DD
< V
POR
.
Device held in reset. No operation allowed.
______________________________________________________________________________________ 25
16-Bit Microcontroller with Infrared Module
V
DD
A
V
PFW
V
RST
B
C
D
MAXQ613
V
POR
STOP
INTERNAL RESET
(ACTIVE HIGH)
E
F
INTERRUPT
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
STATE POWER-FAIL
INTERNAL
REGULATOR
A Off Off Off Yes
B Off Off Off Yes
C On On On Yes
CRYSTAL
OSCILLATOR
SRAM
RETENTION
COMMENTS
Application enters stop mode.
> V
V
DD
RST
.
CPU in stop mode.
V
DD
< V
PFW
.
Power-fail not detected because power-fail
monitor is disabled.
V
RST
< VDD < V
PFW
.
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail warning, and sets the power-fail
interrupt flag.
Turn on regulator and crystal.
Crystal warmup time, t
XTAL_RDY
.
On stop mode exit, CPU vectors to the
higher priority of power-fail and the interrupt that causes stop mode exit.
26 _____________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
(continued)
MAXQ613
STATE POWER-FAIL
D Off Off Off Yes
E
F Off Off Off —
On
(Periodically)
INTERNAL
REGULATOR
Off Off Yes
CRYSTAL
OSCILLATOR
Applications Information
The low-power, high-performance RISC architecture of
this device makes it an excellent fit for many portable
or battery-powered applications. It is ideally suited for
applications such as universal remote controls that
require the cost-effective integration of IR transmit/
receive capability.
Grounds and Bypassing
Careful PCB layout significantly minimizes system-level
digital noise that could interact with the microcontroller
or peripheral components. The use of multilayer boards
is essential to allow the use of dedicated power planes.
The area under any digital components should be a continuous ground plane if possible. Keep bypass capacitor
leads short for best noise rejection and place the capacitors as close to the leads of the devices as possible.
CMOS design guidelines for any semiconductor require
that no pin be taken above V
of this guideline can result in a hard failure (damage to
the silicon inside the device) or a soft failure (unintentional modification of memory contents). Voltage spikes
above or below the device’s absolute maximum ratings
can potentially cause a devastating IC latchup.
Microcontrollers commonly experience negative voltage spikes through either their power pins or general-
or below GND. Violation
DD
SRAM
RETENTION
Application enters stop mode.
> V
V
DD
CPU in stop mode.
V
< VDD < V
POR
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail, and puts CPU in reset.
Power-fail monitor is turned on periodically.
V
< V
DD
Device held in reset. No operation allowed.
RST
POR
.
.
COMMENTS
.
RST
purpose I/O pins. Negative voltage spikes on power pins
are especially problematic as they directly couple to the
internal power buses. Devices such as keypads can
conduct electrostatic discharges directly into the microcontroller and seriously damage the device. System
designers must protect components against these transients that can corrupt system memory.
Additional Documentation
Designers must have the following documents to fully
use all the features of this device. This data sheet
contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations
from published specifications. The user’s guides offer
detailed information about device features and operation. The following documents can be downloaded from
www.maxim-ic.com/microcontrollers.
• This MAXQ613 data sheet, which contains electrical/
timing specifications, pin descriptions, and package
information.
• The MAXQ613 revision-specific errata sheet
(www.maxim-ic.com/errata).
• The MAXQ610 User’s Guide, which contains detailed
information on features and operation, including programming.
______________________________________________________________________________________ 27
16-Bit Microcontroller with Infrared Module
Deviations from the MAXQ610 User’s Guide
for the MAXQ613
The MAXQ610 User’s Guide contains all the information that is needed to develop application code for the
MAXQ613 microcontroller. However, even though the
MAXQ610 and the MAXQ613 are largely code-compatible, there are certain differences between the two
devices that must be kept in mind when referring to the
MAXQ610 User’s Guide.
MAXQ613
The following registers on the MAXQ610 (which are
described in the MAXQ610 User’s Guide) do not exist
on the MAXQ613, and all references to them should be
disregarded:
• Port 3 Output Register (PO3)
• Port 3 Direction Register (PD3)
• Port 3 Input Register (PI3)
• Port 4 Output Register (PO4)
• Port 4 Direction Register (PD4)
• Port 4 Input Register (PI4)
Development and
Technical Support
Maxim and third-party suppliers provide a variety of
highly versatile, affordably priced development tools for
this microcontroller, including the following:
• Compilers
• In-circuit emulators
• Integrated Development Environments (IDEs)
• Serial-to-JTAG and USB-to-JTAG interface boards for
programming and debugging (for microcontrollers
with rewritable memory)
A partial list of development tool vendors can be found
at www.maxim-ic.com/MAXQ_tools.
For technical support, go to https://support.maxim-ic.
com/micro.
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
32 TQFN-EP T3255+3
32 LQFP C32+2
44 TQFN-EP T4477+2
44 TQFP C44+2
PACKAGE
CODE
OUTLINE
NO.
21-0140 90-0001
21-0054 90-0111
21-0144 90-0127
21-0293 90-0316
LAND
PATTERN
NO.
28 _____________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Revision History
MAXQ613
REVISION
NUMBER
0 7/10 Initial release —
1 7/10
2 8/10 Corrected the active mode typ value from 2.0mA to 3.25mA in the Features 1
REVISION
DATE
DESCRIPTION
Corrected bare die numbers in the Pin Description table for V
IRTX, IRRX, P2.5/TDI, P2.6/TMS, and P2.7/TDO
, GND, RESET,
DD
PAGES
CHANGED
9, 10, 11
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