Rainbow Electronics MAXQ3108 User Manual

General Description

The MAXQ3108 is a low-power microcontroller that features two high-performance MAXQ20 cores: a dedicated core (DSPCore) for intensive data processing and a user core (UserCore) for supervisory functions. The two cores can operate at different clock speeds, allowing lower system power consumption for even processing intensive applications. The UserCore can be configured to run at the lowest clock rate possible for monitoring the peripherals for communication activities, while the DSPCore runs at the highest speed. Each core has access to an independent math accelerator (a multiply/accumulate unit). The UserCore supports SPI™, I

C, two UART channels with one channel supporting IR carrier modulation, a trimmable real-time clock (RTC), battery-backed RTC registers, and data memory. The DSPCore is fully user programmable and configurable. With the standard 32,768Hz crystal, the DSPCore operates at 10.027MHz, while the UserCore runs at 5.014MHz.

Applications

Electricity Meters

Industrial Control

Battery-Powered and Portable Devices

Smart Transmitters

Medical Instrumentation

Features

♦ High-Performance, Low-Power, Dual 16-Bit RISC

Cores

♦ Approaches 1MIPS per MHz

♦ System Clock

10.027MHz (DSPCore)

5.014MHz (UserCore)

♦ 33 Instructions

♦ Approximately 100ns Execution Time at 10.027MHz

♦ Three Independent Data Pointers Accelerate Data

Movement with Automatic Increment/Decrement

♦ 16-Bit Instruction Word, 16-Bit Data Bus

♦ 16 x 16-Bit General-Purpose Working Registers

for Each Core

♦ 16-Level Hardware Stack for Each Core

♦ Hardware Support for Software Stack

♦ Memory Features

UserCore

64KB Flash Program Memory 16B Battery-Backed (V

BAT

) Data SRAM 4KB Utility ROM 2KB Data SRAM; 10KB Total Data SRAM (If

DSPCore Inactive)

DSPCore

8KB User-Loadable SRAM Code Memory 1KB Data SRAM

♦ Peripherals

FLL (10MHz Output with 32kHz Input) SPI Master, I

C Master

Two UART Channels (One Supports IR Carrier

Modulation)

Math Accelerator for Each Core Three Manchester Decoder and Cubic Sinc Filter

Channels for Interfacing to DS8102 Delta-Sigma Modulators

Two 16-Bit Programmable Timer/Counters RTC with Alarms and Digital Trim, Dedicated

Battery-Backup Pin (V

BAT

) Two Programmable Pulse Generators Independent Watchdog Timer for Each Core External Interrupts JTAG Interface

♦ Operating Modes

Stop Mode: 0.1µA typ Active Current at 10MHz and V

= 2.0V: 1.0mA typ

MAXQ3108

Low-Power, Dual-Core Microcontroller

________________________________________________________________

Maxim Integrated Products

Ordering Information

Rev 0; 1/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be

simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata

Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE PIN-PACKAGE

MAXQ3108-FFN+ -40°C to +85°C 28 TSSOP

Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc.

MAXQ is a registered trademark of Maxim Integrated Products, Inc.

MAXQ3108

Low-Power, Dual-Core Microcontroller

2 _______________________________________________________________________________________

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

DSP Program RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Peripheral Registers—UserCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Peripheral Registers—DSPCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Special Function Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

32,768Hz Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Frequency-Locked Loop (FLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Power Conservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Power-Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Switchback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Power-On Reset/Brownout Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Reset Input Pin Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

GPIO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Infrared Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

ADC Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

MAXQ3108

Low-Power, Dual-Core Microcontroller

_______________________________________________________________________________________ 3

Figure 1. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 2. IR Option on UART 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 3. ADC Bit Stream Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 4. Connecting the MAXQ3108 to a DS8102 Dual Delta-Sigma Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 1. UserCore Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 2. UserCore Peripheral Register Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 3. DSPCore Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 4. DSPCore Peripheral Register Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 5. Multipurpose Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 6. MAXQ3108 Clock Divisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

LIST OF FIGURES

LIST OF TABLES

Dual-Core Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

DSP Code Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Intercore Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Timer B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Timer B Use-Case Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Multiply-Accumulate Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Programmable Pulse Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

In-Application Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

TABLE OF CONTENTS (continued)

MAXQ3108

Low-Power, Dual-Core Microcontroller

4 _______________________________________________________________________________________

RECOMMENDED DC OPERATING CONDITIONS

(VDD= V

RST

to 3.6V, TA= -40°C to +85°C.) (Notes 1, 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on Any Pin

except V

with Respect to VSS...........................-0.3V to V

Voltage Range on VDDwith Respect to VSS.........-0.3V to +3.6V

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Soldering Temperature...........................Refer to the IPC/JEDEC

J-STD-020 Specification.

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VDD V

Power-Fail Reset Voltage V

1.8V Internal Regulator V

1.8V Power-Fail Reset Voltage V

Battery Supply Voltage V

Battery Current (Note 3) I

Monitors VDD 1.875 1.975 V

RST

1.71 1.8 1.89 V

REG18

Monitors REGOUT 1.62 1.71 V

REGRST

1.8 3.6 V

BAT

VDD = 0, V

BAT

RTC enabled

BAT1

VDD = 0, V

BAT

RTC enabled

Active Currentwith 32.768kHz Crystal Connected to CX1, CX2; FLL Selected (10MHz Output); ENDSP = 0; All Decimators and Sinc F ilters Off (Note 4)

DD_FLL10

/1 mode, VDD = 2.0V 1.3 2.2

DD_FLL1

/1 mode, VDD = 3.6V 1.5 2.5

DD_FLL2

PMM2 (32kHz), VDD = 2.0V 0.5 0.8

DD_FLL9

PMM2 (32kHz), VDD = 3.6V 0.6 1.0

Active Current with 32.768kHz Crystal Connected to CX1, CX2;

DD_FLL14

VDD = 2.0V 1.0 1.7 FLL Selected (10MHz Output); UserCore = /256 PMM; DSPCore

= /1 ; ENDSP = 1; Manchester

DD_FLL15

VDD = 3.6V 1.8 3.0 Decoders On; Decimators On

STOP_1

Stop-Mode Current (Note 5)

STOP_2

Input Low (CX1) V

Input Low (All Other Pins) V

Input High (CX1) V

Input High (All Other Pins) V

Input Hystere si s (Schm itt) V

IL1

IL2

IH1

IH2

IHYS

BOD = 1, REGEN = 0, SVMSTOP = 0, RTC off (lowe st current stop mode)

BOD = 0, REGEN = 0, SVMSTOP = 0, RTC off (adds brownout-reset detection)

VSS 0.20 x VDD V

VSS 0.30 x VDD V

0.75 x VDD VDD V

0.70 x VDD VDD V

0.18 V

Output Low (All Port Pins) VOL IOL = 4mA (Note 6) VSS 0.4 V

Output High (All Port Pins) VOH IOH = -4mA (Note 6) VDD - 0.4 V

3.6 V

RST

= 3.6V, 32kHz oscillator and

= 2V, 32kHz oscillator and

0.8

0.6

0.1 2.4

30 125

μA

MAXQ3108

Low-Power, Dual-Core Microcontroller

_______________________________________________________________________________________ 5

RECOMMENDED DC OPERATING CONDITIONS (continued)

(VDD= V

RST

to 3.6V, TA= -40°C to +85°C.) (Notes 1, 2)

Note 1: Results based on simulation data. Characterization data will be available at a later date. All voltages are referenced to

ground. Specifications to T

= -40°C are guaranteed by design and are not production tested.

Note 2: Typical values are not guaranteed. These values are measured at room temperature, V

= 3.3V.

Note 3: This current is from V

BAT

only if (VDD< V

BAT

and VDD< V

RST

) or (STOP = 1, REGEN = 0, BOD = 1). Otherwise, this current

is from V

Note 4: Measured on the V

pin and the device not in reset. All inputs are connected to VSSor VDD. Outputs do not source/sink

any current. Timer enabled, RTC enabled, part executing JUMP $ from flash.

Note 5: If the RTC is on for parameters ISTOP_2, ISTOP_3, and ISTOP_4, a current equal to I

BAT1

is added to IDD.

Note 6: The maximum total current, I

OH(MAX)

and I

OL(MAX)

, for all outputs combined should not exceed 35mA to satisfy the maxi-

mum specified voltage drop.

Note 7: The timing listed above is clocked by 63 cycles of the internal 1MHz ±5% clock. There will be ROM code overhead, which is

a function of system clock. For data sheet purposes, a better way is to specify the limits that include ROM code execution with specified system clock speed.

Input/Output Pin Capacitance CIO Guaranteed by design 15 pF

Input Low Current Al l Pins IIL VIN = 0.4V -30 μA

Input-Leakage Current IL Internal pullup di sabled -100 +100 nA

Input Pullup Resistor (All Inputs) RPU 60 k

CLOCK SOURCE

FLL Output Frequency f

FLL Output Accuracy f

FLASH M EMORY

System Clock During Flash Programm ing/Era se

Flash Erase Time

Flash Programming Time Per Word

Write/Erase C ycles 1000 Cycles

Data Retention TA = +25°C 100 Years

SUPPLY VOLTAGE MONITOR

Set Point SVTR 2.0 3.5 V

Increment Resolution 0.1 V

Default Set Point 2.7 V

Current Consumption I

Start Time t

Setup Time (Change Set Point) t

Setup Time (Stop Mode Exit) t

REAL-TIME CLOCK

RTC Input Frequency f

RTC Operating Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CX1 = 32.768kHz 9.5 10.0 10.5 MHz

FLL

CX1 = 32.768kHz 1.5 ±5 %

FLL

2 MHz

Mas s erase 22.8 24 25.2

Page erase 22.8 24 25.2

(Note 7) 59.5 66.5 μs

10 μA

SVM

200 μs

SVMST

SVM_SU1

SVM_SU2

32KIN

RTC

Changing from one set point to another set point

Exit from stop mode 8 μs

32kHz watch cr ystal 32,768 Hz

VDD = 2.0V 0.6

VDD = 3.6V 0.8

2 μs

μA

MAXQ3108

Low-Power, Dual-Core Microcontroller

6 _______________________________________________________________________________________

Block Diagram

P2.4/MDIN0P

P2.3/MDIN0N/SSEL

P2.2/SCLK/CLKO P2.1/MDIN2N/MISO P2.0/MDIN2P/MOSI

P1.0/TMS

P1.1/TCK

P1.2/TDI

P1.3/TDO/SQW

P1.5/TBA P1.4/TBB

P0.3/MDIN1P/T2PB

P0.2/MDIN1N/T2P

MANCHESTER

DECODER

MANCHESTER

DECODER

MANCHESTER

DECODER

SPI

JTAG

GPIO

CLK

ADMINISTRATIVE CORE

32kW FLASH (CODE)

SINC3

FILTER

SINC3

FILTER

SINC3

FILTER

SINC3

FILTER

SINC3

FILTER

SINC3

FILTER

MAXQ20

2kW ROM (CODE)

1kW SRAM (DATA)

TIMER B

TIMER 2

24-BIT RESULT PULSE GENERATOR P2.5/CF1

24-BIT RESULT

MAILBOX

COMM

1.8V CORE LDO

SUPPLY MONITOR

PULSE GENERATOR P2.6/CF2

MAXQ20

DSPCORE

4kW SRAM (CODE)

512W SRAM (DATA)

MULTIPLY-

ACCUMULATE

UNIT

GND REGOUT P1.6/RST V

BAT

CX1 CX2

FLL

AND

32kHz

OSC

RTC

P1.5/TBA P1.4/TBB

P0.7/RXD1 P0.6/TXD1

P0.1/RXD0 P0.0/TXD0

I2C MASTER

USART

MULTIPLY-

ACCUMULATE

UNIT

MAXQ3108

Low-Power, Dual-Core Microcontroller

_______________________________________________________________________________________ 7

Pin Description

PIN NAME FUNCTION

POWER PINS

21 V

17 GND Ground

20 REGOUT

19 V

15, 16 CX1, CX2

2–7, 23, 22 P0.0–P0.7

10, 11, 12, 13, 14, 18, 24P1.0–P1.6

BAT

Supply Voltage. Must be bypassed with a 4.7μF capacitor with ESR < 5 and a 0.1μF ceramic capacitor.

Regulator Output. 1.8V output. Must be connected to a 1μF low-ESR (< 1) externa l ceramic chip capacitor.

Battery Input for Backing Up the RTC

CLOCK PINS

RTC Crystal Inputs. The RTC requires a 32.768kHz crystal to be connected in order to supply the

time base for the RTC. The 6pF load capacitors are included in the circuitry.

I/O PINS

Port 0. Port 0 functions a s both an 8-bit I/O port and as a special function interface to the I2C

master and serial UARTs 0 and 1. All pins support external interrupt functionality. The default reset condit ion of the pins is weakl y pulled up (input). To drive output, either the port direction register must be programmed to enable output or the alternate function module must be configured to drive the pins. This port is acce ss ible to the UserCore onl y.

PIN PORT ALTERNATE FUNCTION

2 P0.0 TXD0/INT0

3 P0.1 RXD0/INT1

4 P0.2 MDIN1N/T2P/INT2

5 P0.3 MDIN1P/T2PB/INT3

6 P0.4 SDA/INT4

7 P0.5 SCL/INT5

23 P0.6 TXD1/INT6

22 P0.7 RXD1/INT7

Port 1. Port 1 function s a s both a 6-bit I/O port and as a special function interface to the JTAG compatible test access port (TAP), the RTC square-wave output, and as the input/output to and from timer B. All pins support external interrupt functionality. The default reset condition of pins P1.0–P1.3 is the JTAG functions. To use the 4-bit port as standard GPIO, the TAP must be disabled by user code. This port is accessible to the UserCore only.

Active-Low Reset (RST). The RST pin recognizes external active-low reset inputs and employs an internal pullup resistor to allow for a combination of wired-OR external reset sources. An RC is not required for power-up, as this function is provided internally. The RST pin function is enabled on power-on reset. It i s critical that this pin not be held low externally after a power-on reset or the device cannot exit the reset state.

PIN PORT ALTERNATE FUNCTION

10 P1.0 TMS/INT8

11 P1.1 TCK/INT9

12 P1.2 TDI/INT10

13 P1.3 TDO/SQW/INT11

14 P1.4 TBB

18 P1.5 TBA 24 P1.6 RST

MAXQ3108

Low-Power, Dual-Core Microcontroller

8 _______________________________________________________________________________________

Detailed Description

The MAXQ3108 microcontroller is an integrated, lowcost solution to simplify the design of electricity metering and industrial control products. Standard features include two highly optimized, single-cycle, MAXQ 16-bit RISC microcontroller cores; 64KB of flash memory, 11KB RAM, and independent hardware stacks; general-purpose registers; and data pointers for each core. Application-specific peripherals include hardware SPI and I2C masters, real-time clock, programmable pulse generators, dual UARTs (one of which that supports IR carrier frequency modulation), and math accelerators.

At the heart of the MAXQ3108 are two MAXQ20 16-bit RISC microcontrollers. The dual-core approach allows one core (DSPCore) to be entirely dedicated to collection and processing of AFE samples for the metering function, while the second core handles any communication and user-specific administrative functions. The MAXQ3108 DSPCore operates at 10.027MHz with the default crystal and almost all instructions execute in a single clock cycle (100ns), while the UserCore runs at half that frequency (5.014MHz).

The dual-core strategy promotes flexibility by allowing the update of metering routines and parameters separately in DSPCore code and data memory. Furthermore, an independent DSPCore solely responsible for accurate metering introduces a measure of safety and reliability since all administrative/communication functions and interruptions are handled by the UserCore. Both cores feature standard MAXQ power-saving system

clock-divide modes and independently implement lowpower stop (UserCore) and idle (DSPCore) modes. The DSPCore implements an idle mode that allows CPU execution to be halted while awaiting an ADC sample. The UserCore implements an ultra-low-power stop mode that automatically disables the DSPCore and results in a quiescent current consumption of less than

1.5μA. The combination of high performance and corespecific low-power mode implementation provides increased power efficiency and capability over competitive microcontrollers.

Microprocessor

The MAXQ20 is a low-power implementation of the new 16-bit MAXQ family of RISC cores. The core supports the Harvard memory architecture with separate 16-bit program and data address buses, but also provides pseudo-Von Neumann support through utility ROM functions. A fixed 16-bit instruction is standard, but data can be arranged in 8 or 16 bits. The MAXQ20 core is implemented as a nonpipelined processor with single clock-cycle instruction execution. The data path is implemented around register modules, and each register module contributes specific functions to the core. The accumulator module consists of sixteen 16-bit registers and is tightly coupled to the arithmetic logic unit (ALU). Program flow is supported by a dedicated 16level-deep hardware stack.

Execution of instructions is triggered by data transfer between functional register modules, or between a functional register module and memory. Since data

Pin Description (continued)

PIN NAME FUNCTION

Port 2. Port 2 functions a s both a 7-bit I/O port and as a special function interface to the CF pulse

generator outputs, clock output, and the Manchester ENDEC or SPI. The default reset condition of the pins is weakly pulled up (input), with exception of P2.5 and P2.6, which are always outputs and default to strong high. To drive output, either the port direction register must be programmed to enable output, or the a lternate function module mu st be configured to drive the pins. P2.5 and P2.6 are accessible to the DSPCore only.

1, 28, 27, 26,

25, 8, 9

P2.0–P2.6

PIN PORT ALTERNATE FUNCTION

1 P2.0 MDIN2P/MOSI

28 P2.1 MDIN2N/MISO

27 P2.2 SCLK/CLKO 26 P2.3 MDIN0N/SSEL

25 P2.4 MDIN0P

8 P2.5 CF1

9 P2.6 CF2

MAXQ3108

Low-Power, Dual-Core Microcontroller

_______________________________________________________________________________________ 9

movement involves only source and destination modules, circuit switching activities are limited to active modules only. For power-conscious applications, this approach localizes power dissipation and minimizes switching noise. The modular architecture also provides maximum flexibility and reusability, which are important for a microprocessor used in embedded applications.

The MAXQ instruction set is designed to be highly orthogonal. All arithmetical and logical operations can use any register along with the accumulator. Data movement is supported from any register to any other register. Memory is accessed through specific data pointer registers with auto increment/decrement support.

Memory

The MAXQ3108 supports a pseudo-Von Neumann memory structure that can merge program and data into a linear memory map. This is accomplished by mapping the data memory into the program space or mapping the program memory segment into the data space. Memory access is under the control of the memory management unit (MMU). During flash programming, the MMU maps the flash memory into data space, and the built-in firmware provides necessary controls to the

embedded flash memory for all read/erase/write operations when the ROM loader is invoked. Additionally, when the DSPCore is disabled, all its code SRAM (8KB) is mapped into the data SRAM space of the UserCore. This allows streamlined reconfiguration of the DSP code memory or a larger data SRAM for applications not employing DSPCore operation.

The MAXQ3108 incorporates the following:

• 4KB utility ROM

• 64KB program flash

• 2KB SRAM data memory

• 8KB program SRAM (DSPCore)

• 1KB SRAM data memory (DSPCore) The MMU operates automatically and maps data mem-

ory as a function of the contents of the instruction pointer; that is, the execution location controls the structure of the data memory map. The only constraint is that no memory region is available as data when code is being fetched from that region. For example, when executing from flash, flash cannot be read as data. But changing the execution location to the utility ROM through a subroutine call allows the flash memory to be read as data.

Figure 1. Memory Map

0xA800

0xA000

0x8000

0x0000

UTILITY ROM

CODE

RAM 0.5kW

2kW

FLASH

32kW

WHEN EXECUTING FROM FLASH

0xA000

0x8000

0x0800 0x0000

DATA

UTILITY ROM

2kW

RAM 0.5kW

WHEN EXECUTING FROM UTILITY ROM

0x8000

0x0800 0x0000

DATA

FLASH

32kW

RAM 0.5kW

WHEN EXECUTING FROM RAM

0xA000

0x8000

0x0000

DATA

UTILITY ROM

2kW

FLASH

32kW

MAXQ3108

Low-Power, Dual-Core Microcontroller

10 ______________________________________________________________________________________

DSP Program RAM

A 4K Word (8KB) section of memory is available to the DSPCore as code memory. When the DSPCore is disabled (as it is immediately following a reset event) that block of memory appears in the UserCore data memory map at location 0x1000. Thus, a typical startup sequence to operate both cores might include:

1) Low-level initialization of the UserCore.

2) Copy DSP code from program flash to DSPCore code RAM at 0x1000.

3) Enable DSPCore.

4) Poll mailbox registers to verify that DSPCore is correctly running.

For more information, see the

Dual-Core Interfaces

section.

Registers

The MAXQ family of microcontrollers uses a bank of registers to access memory and peripherals and to perform basic CPU activities. These registers are organized into as many as 16 register modules, each of which can have as many as 32 registers, giving a system maximum of 512 registers. The registers are divided into two sections: system registers (modules 7 to 15) and peripheral registers (modules 0 to 5).

Since the MAXQ3108 contains two MAXQ core processors, each has a set of system registers and a set of peripheral registers.

System Registers

The MAXQ3108 UserCore implements the standard set of system registers as described in the

MAXQ Family

User’s Guide

. The exceptions are listed below:

• In the IMR register, bit IM5 is not implemented since

there is no module 5 implemented in the MAXQ3108.

• In the SC register, bits CDA1 and UPM are not implemented since the size of the memory in the device does not require their implementation.

• In the IIR register, bit II5 is not implemented since there is no module 5 implemented in the MAXQ3108.

• In the CKCN register, bits XT/RC, RGSL, and RGMD are not implemented. Instead, bits 5 and 6 are FLLMD and FLLSL, respectively. These bits support the frequency-locked loop (FLL) that forms a core part of the MAXQ3108 clocking scheme. More information is given in the

Clock

section.

The MAXQ3108 DSPCore system register complement is identical to that found in the UserCore, with these exceptions:

• In the IMR register, only IM0 is implemented.

• The system control (SC) register is not implemented.

• In the IIR register, only the II0 bit is implemented.

• The WDCN register is not implemented because there is no watchdog timer in the DSPCore. Watchdog functionality can be implemented in the UserCore by determining if the DSPCore is responding to messages.

• In the CKCN register, the STOP, RGSL, and SWB bits are not implemented because the corresponding functions do not exist in the DSPCore. The FLLMD and FLLSL bits are not implemented because a common clock block is shared with the UserCore, and the control bits here would be redundant.

Peripheral Registers—UserCore

The MAXQ3108 UserCore exposes its peripheral complement in five modules numbered 0 to 4. Table 1 describes the functions associated with the peripheral registers, and Table 2 shows the default values of these registers.

Table 1. UserCore Peripheral Registers

AD0 0:0 ADC0 Output Register

AD1 0:1 ADC1 Output Register

AD2 0:2 ADC2 Output Register

AD3 0:3 ADC3 Output Register

AD4 0:4 ADC4 Output Register

AD5 0:5 ADC5 Output Register

SRSP0 0:6 RSPSDV REQE RSPST

SRSP1 0:7 Slave Resp onse Register 1

AD0LSB 0:8 ADC0 Output Register LSB

MOD:

REG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT

MAXQ3108

Low-Power, Dual-Core Microcontroller

______________________________________________________________________________________ 11

Table 1. UserCore Peripheral Registers (continued)

AD1LSB 0:9 ADC1 Output Register LSB

AD2LSB 0:10 ADC2 Output Register LSB

AD3LSB 0:11 ADC3 Output Register LSB

AD4LSB 0:12 ADC4 Output Register LSB

AD5LSB 0:13 ADC5 Output Register LSB

MREQ0 0:14 REQCDV RSPIE REQCM

MREQ1 0:15 Mast er Request Regi ster 1

MREQ2 0:16 Mast er Request Regi ster 2

ADCN 0:17 IFCS EL IF54E IF 32E IF10E MDCKS MD2E MD1E MD0E OSR ABF5 ABF4 ABF3 ABF2 ABF1 ABF0

ADCC 0:18 ADC Clock Correction Regi ster

MSTC 0:19 CCSL MD2 SNC MD1SNC MD0SNC

PO0 1:0 Port 0 Output Register

PO1 1:1 Port 1 Output Register

PI0 1:2 Port 0 Input Register

PI1 1:3 Port 1 Input Register

EIF0 1:4 Port 0 Interrupt Flag Register

EIE0 1:5 Port 0 Interrupt Enable Register

EIF1 1:6 Port 1 Interrupt Flag Regi ster

EIE1 1:7 Port 1 Interrupt Enable Regis ter

PD0 1:8 Port 0 Direction Register

PD1 1:9 Port 1 Direction Reg ister

EIES0 1:10 Port 0 External Interrupt Edge Select

EIES1 1:11

SVM 1:12 SVTH SVMSTOP SVMI SVMIE SVMRDY SVMEN

FCNTL 1:13 FBUSY FC

FDATA 1:14 Fla sh Data Register

PWCN 1:15 ENDSP BOD REGEN RSTD ECLKO FLOCK FLLEN

BB0 1:16 Battery-Backed General-Purpose Storage 0

BB1 1:17 Battery-Backed General-Purpose Storage 1

BB2 1:18 Battery-Backed General-Purpose Storage 2

BB3 1:19 Battery-Backed General-Purpose Storage 3

BB4 1:20 Battery-Backed General-Purpose Storage 4

BB5 1:21 Battery-Backed General-Purpose Storage 5

BB6 1:22 Battery-Backed General-Purpose Storage 6

BB7 1:23 Battery-Backed General-Purpose Storage 7

RTRM 1:24 TSGN TRM

RCNT 1:25 WE X32D 32KRD Y 32KBYP 32KMD FT SQE ALSF ALDF RDYE RDY BUSY ASE ADE RTCE

RTSS 1:26 RTC Subsecond Counter

RTSH 1:27 RTC Seconds Register MSW

RTSL 1:28 RTC Seconds Register LSW

RSSA 1:29 RTC Subsecond Alarm

RASH 1:30 RTC Seconds A larm MSW

RASL 1:31 RTS Seconds Alarm LSW

T2CNA 2:0 ET2 T2OE0 T2POL0 TR2L TR2 CPRL2 SS2 G2EN

T2H 2:1 Timer 2 MSB

MOD:

REG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT

Port 1 External Interrupt Edge

Select

MAXQ3108

Low-Power, Dual-Core Microcontroller

12 ______________________________________________________________________________________

Table 1. UserCore Peripheral Registers (continued)

T2RH 2:2 Timer 2 MSB Re load Value

T2CH 2:3 Timer 2 MS B Capture/Compare Value

PO2 2:4 Port 2 Output Register

PI2 2:5 Port 2 Input Register

SCON0 2:6

SBUF0 2:7 Serial D ata Bu ffer 0

SMD0 2:8 EPWM OFS ESI SMOD FEDE

PR0 2:9 Phase Regi ster 0

PD2 2:10 Port 2 Direction Reg ister

T2CNB 2:11 ET2L T2OE1 T2POL1 TF2 TF2 L TCC2 TC2L

T2V 2:12 Timer 2 Value Register

T2R 2:13 Timer 2 Reload Register

T2C 2:14 Timer 2 C apture/Compare Regist er

T2CFG 2:15 T2CI T2DIV T2MD CCF C/T2

MCNT 3:0 OF MCW CLD SQU OPCS MSUB MMAC SUS

MA 3:1 Multiplier Operand “A” Register

MB 3:2 Multiplier Operand “B” Register

MC2 3:3 Multiplier Accumulator Register 2 (MSB, bits 47-32)

MC1 3:4 Multiplier Accumulator Regi ster 1 (bit s 31-16)

MC0 3:5 Mult ipl ier Accumulator Register 0 (LSB, bits 15-0)

SPIB 3:7 SPI Data Buffer

MC1R 3:8 Mult iplier Read Regi ster 1 (MSB, bits 31-16)

MC0R 3:9 Mult ipl ier Read Regi ster 0 (LSB, bits 15-0)

SPICN 3:13 STBY SPIC ROVR WCOL MODF MODFE MSTM SPIEN

SPICF 3:14 ESPII CHR CKPHA CKPOL

SPICK 3:15 SPI Clock Register

I2CBUF 4:0 I

I2CST 4:1 I2CBUS I2CBU SY I2CS PI I2CSCL I2CROI I2CGCI

I2CIE 4:2 I2C SPIE I2CR OIE I2CGCIE I2CNACKIE I2CALIE

TB0R 4:4 Timer B Capture/Reload Value

TB0C 4:5 Timer B C ompare Va lue

SCON1 4:6

SBUF1 4:7 Serial D ata Bu ffer 1

SMD1 4:8 ESI SMOD FEDE

PR1 4:9 Phase Regi ster 1

TB0CN 4:10 C/TB T BC S TBC R TB PS T FB E XFB T BOE DCE N EXENB TR B E TB

TB0V 4: 11 Timer B Value Regi ster

I2CCN 4:12 I2CR ST I2CSTREN I2CGCEN I2CSTO P I2CSTART I2CACK I2CSTRS I2CMODE I2CMST I2CEN

I2CCK 4:13 I2C Clock High Period I2C Clock Low Period

I2CTO 4:14 I

I2CSLA 4:15 I

MOD:

REG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT

SM0/

SM1 SM2 REN TB8 RB8 TI RI

C Data Buff er Register

I2CNACK

I2CALI I2 CAMI I2CTOI I2CSTRI I2CRXI I2CTX I I2CSRI

I2CAMI

I2CTO IE I2CSTRIE I2CR XIE I2 CTXIE I2 CSRIE

SM0/

SM1 SM2 REN TB8 RB8 TI RI

C Timeout Period

C Slave Address

CP/

RLB

MAXQ3108

Low-Power, Dual-Core Microcontroller

______________________________________________________________________________________ 13

Table 2. UserCore Peripheral Register Default Values

AD0 0:0 0xFFFF

AD1 0:1 0xFFFF

AD2 0:2 0xFFFF

AD3 0:3 0xFFFF

AD4 0:4 0xFFFF

AD5 0:5 0xFFFF

SRSP0 0:6 0 0 0x0

SRSP1 0:7 0x0000

AD0LSB 0:8 0xFF

AD1LSB 0:9 0xFF

AD2LSB 0:10 0xFF

AD3LSB 0:11 0xFF

AD4LSB 0:12 0xFF

AD5LSB 0:13 0xFF

MREQ0 0:14 0 0 0x0

MREQ1 0:15 0x0000

MREQ2 0:16 0x0000

ADCN 0:17 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0

ADCC 0:18 0x0000

MSTC 0:19 0x3 0 0 0

PO0 1:0 0xFF

PO1 1:1 0x7F

PI0 1:2 0xXX

PI1 1:3 0xXX

EIF0 1:4 0x00

EIE0 1:5 0x00

EIF1 1:6 0x0

EIE1 1:7 0x0

PD0 1:8 0x00

PD1 1:9 0x00

EIES0 1:10 0x00

EIES1 1:11 0x0

SVM 1:12 0x7 0 0 0 0 0

FCNTL 1:13 1 0x0

FDATA 1:14 0x0000

PWCN 1:15 0 0 0 0 0 0 0

BB0 1: 16 0xXXXX

BB1 1: 17 0xXXXX

BB2 1: 18 0xXXXX

BB3 1: 19 0xXXXX

BB4 1: 20 0xXXXX

BB5 1: 21 0xXXXX

BB6 1: 22 0xXXXX

BB7 1: 23 0xXXXX

RTRM 1:24 X X

MOD:

REG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT

MAXQ3108

Low-Power, Dual-Core Microcontroller

14 ______________________________________________________________________________________

Table 2. UserCore Peripheral Register Default Values (continued)

RCNT 1:25 0 X X X 0xX 0 0 0 0 0 0 1 0 0 X

RTSS 1:26 0xXX

RTSH 1:27 0xXXXX

RTSL 1:28 0xXXXX

RSSA 1:29 0 xXXXX

RASH 1:30 0xX

RASL 1:31 0xXXXX

T2CNA 2:0 0 0 0 0 0 0 0 0

T2H 2:1 0x00

T2RH 2:2 0x00

T2CH 2:3 0x00

PO2 2:4 0x7F

PI2 2:5 0xFF

SCON0 2:6 0 0 0 0 0 0 0 0

SBUF0 2:7 0x00

SMD0 2:8 0 0 0 0 0

PR0 2:9 0x0000

PD2 2:10 0x00

T2CNB 2:11 0 0 0 0 0 0 0

T2V 2:12 0x0000

T2R 2:13 0x0000

T2C 2:14 0x0000

T2CFG 2:15 0 0x0 0 0x0 0

MCNT 3:0 0 0 0 0 0 0 0 0

MA 3:1 0x0000

MB 3:2 0x0000

MC2 3:3 0x0000

MC1 3:4 0x0000

MC0 3:5 0x0000

SPIB 3:7 0x0000

MC1R 3:8 0x0000

MC0R 3:9 0x0000

SPICN 3:13 0 0 0 0 0 0 0 0

SPICF 3:14 0 0 0 0

SPICK 3:15 0x00

I2CBUF 4:0 0x0000

I2CST 4:1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I2CIE 4:2 0 0 0 0 0 0 0 0 0 0 0

TB0R 4:4 0x0000

TB0C 4:5 0x0000

SCON1 4:6 0 0 0 0 0 0 0 0

SBUF1 4:7 0x0000

SMD1 4:8 0 0 0

PR1 4:9 0x0000

TB0CN 4:10 0 0 0 0 x0 0 0 0 0 0 0 0 0

MOD:

REG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT

MAXQ3108

Low-Power, Dual-Core Microcontroller

______________________________________________________________________________________ 15

Peripheral Registers—DSPCore

The MAXQ3108 DSPCore exposes its peripheral complement in modules numbered 0 and 1. Table 3

describes the functions associated with the peripheral registers, and Table 4 shows the default values of these registers.

Table 2. UserCore Peripheral Register Default Values (continued)

Table 3. DSPCore Peripheral Registers

TB0V 4:11 0x0000

I2CCN 4:12 0 0 0 0 0 0 0 0 0 0

I2CCK 4:13 0x02 0x04

I2CTO 4:14 0x00

I2CSLA 4:15 0x000

MOD:

REG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AD0 0:0 ADC0 Output Reg ister

AD1 0:1 ADC1 Output Reg ister

AD2 0:2 ADC2 Output Reg ister

AD3 0:3 ADC3 Output Reg ister

AD4 0:4 ADC4 Output Reg ister

AD5 0:5 ADC5 Output Reg ister

SRSP0 0:6 RSPS DV REQE RSPST

SRSP1 0:7 Slave Response Regi ster 1

AD0LSB 0:8 ADC0 Output Register LSB

AD1LSB 0:9 ADC1 Output Register LSB

AD2LSB 0:10 ADC2 Output Register LSB

AD3LSB 0:11 ADC3 Output Register LSB

AD4LSB 0:12 ADC4 Output Register LSB

AD5LSB 0:13 ADC5 Output Register LSB

MREQ0 0:14 REQCDV RSPIE REQCM

MREQ1 0:15 Master Request Register 1

MREQ2 0:16 Master Request Register 2

ADCN 0:17 IFCSEL IF45E IF23E IF10E MDCKS MD2E MD1E MD0E OSRI ABF5 ABF4 ABF3 ABF2 ABF1 ABF0

ADCC 0:18 ADC C lock Correction Register

MSTC 0:19 CCSL MD2S NC MD1S NC MD0SN C

MCNT 1:0 OF MCW CLD SQU OPCS MSUB MMAC SUS

MA 1:1 Multipl ier Operand “A” Register

MB 1:2 Multipl ier Operand “B” Register

MC2 1:3 Multiplier Accumulator Register 2 (MSB, bits 47-32)

MC1 1:4 Multipl ier Accumulator R egister 1 (bits 31-16)

MC0 1:5 Multiplier Accumulat or Regi ster 0 (LSB, bits 15-0)

MOD:

REG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT

MAXQ3108

Low-Power, Dual-Core Microcontroller

16 ______________________________________________________________________________________

Table 3. DSPCore Peripheral Registers (continued)

Table 4. DSPCore Peripheral Register Default Values

PO2 1:7 Port 2 Output Reg ister

MC1R 1:8 Mult iplier Read Regi ster 1 (MSB, bits 31-16)

MC0R 1:9 Mult iplier Read Register 0 (LSB, bits 15-0)

CF1D 1:12 CF1 Delay Register

CF2D 1:13 CF2 Delay Register

AD0 0:0 0xFFFF

AD1 0:1 0xFFFF

AD2 0:2 0xFFFF

AD3 0:3 0xFFFF

AD4 0:4 0xFFFF

AD5 0:5 0xFFFF

SRSP0 0:6 0 0 0x0

SRSP1 0:7 0x0000

AD0LSB 0:8 0xFF

AD1LSB 0:9 0xFF

AD2LSB 0:10 0xFF

AD3LSB 0:11 0xFF

AD4LSB 0:12 0xFF

AD5LSB 0:13 0xFF

MREQ0 0:14 0 0 0x0

MREQ1 0:15 0x0000

MREQ2 0:16 0x0000

ADCN 0:17 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0

ADCC 0:18 0x0000

MSTC 0:19 0x3 0 0 0

MCNT 1:0 0 0 0 0 0 0 0 0

MA 1:1 0x0000

MB 1:2 0x0000

MC2 1:3 0x0000

MC1 1:4 0x0000

MC0 1:5 0x0000

PO2 1:7 0x0000

MC1R 1:8 0x0000

MC0R 1:9 0x0000

CF1D 1:12 0x0000

CF2D 1:13 0x0000

MOD:

REG

MOD:

REG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT

MAXQ3108

Low-Power, Dual-Core Microcontroller

______________________________________________________________________________________ 17

Special Function Register Bit Descriptions

AD0 (00h, 00h) Analog-to-Digital Converter 0 Output Register

Initialization: This register is reset to 0xFFFF on all forms of reset.

Read/Write Access: Unrestricted read access.

Analog-to-Digital Converter 0 Output Register. This register contains the most significant 16 bits of the current ADC0 data sample that was acquired from the respect ive sinc3 f ilter. Reading from

AD0.[15:0]:

AD1 (01h, 00h) Analog-to-Digital Converter 1 Output Register

AD2 (02h, 00h) Analog-to-Digital Converter 2 Output Register

AD3 (03h, 00h) Analog-to-Digital Converter 3 Output Register

AD4 (04h, 00h) Analog-to-Digital Converter 4 Output Register

AD5 (05h, 00h) Analog-to-Digital Converter 5 Output Register

SRSP0 (06h, 00h) Slave Response Register 0

Initialization: Th is register is reset to 00h on all forms of reset.

Read/Write Access:

SRSP0.[3:0]: RSPST[3:0]

SRSP0.4: REQE

SRSP0.5: RSPSDV

SRSP0.[7:6]: Reserved Reserved. Reads return 0.

the ADC0 register(s) results in the ABF0 flag being cleared by hardware (when set), unless the read operation is performed simu ltaneou sly with a write. Reading a di sabled ADC returns the data last acquired if the associated buffer full flag is set and returns FFFFh if the flag is clear.

Unrestricted read acce ss only to the UserCore (except RSPSDV; see the bit description). Unrestricted read/write access to the DSPCore (except RSPSDV and 3:0; see the bit descriptions).

Response Status Bits 3:0. These bits can be u sed to report acknow ledgement and status of the current command being processed by the slave and to report slave system conditions (e.g., watchdog timeout) that are not related to a ma ster command. To notify the master that status is ready to be read, the RSP0DV bit shou ld be set to 1 either by software (in the case of command status) or, in some cases, by hardware (as for the watchdog). In cases where slave hardware sets the status bits, these bits are not writable by slave software until the status condition has been cleared.

When the DSPCore watchdog timer reaches FFFFh, a system interrupt from the DSPCore is signaled by the setting of the SRSP0.5 status flag along with the SRSP0.[3:0] status code of 0000b. This hardware condit ion for the SRSP0 register persists (prevent ing software writes of these bits by the DSPCore) until a reset of the DSPCore is executed (UserCore may disable the DSPCore through ENDSP = 0 to force the reset). Request Registers Interrupt Enable. Setting this bit to 1 enables an interrupt for the master request-command data valid (interrupt) flag (REQCDV). The master request-command data valid flag is reported in MREQ0.5 (and the associated command code is contained in MREQ0.[3:0]). Clearing thi s bit to 0 disable s the interrupt associated with the master request-command data va lid flag.

Response Status Data Valid Flag. This f lag can only be set by the slave (DSPCore) or slave hardware once a va lid status or system interrupt condition is supplied in the RSPST[3:0] field of the SRSP0 register to notif y the master that valid status is read y for reading. Status information or data could also be contained in SRSP1, so the slave should only set this flag when all data has been loaded (included any that is loaded to SRSP1). This flag can onl y be cleared by the master (UserCore) software unle ss the status condition that caused hardware to set the flag persists (e.g., slave watchdog counter timeout). If made ava ilable by the slaveCPU, more information can be ascertained about the status by additional master request read commands.

MAXQ3108

Low-Power, Dual-Core Microcontroller

18 ______________________________________________________________________________________

Special Function Register Bit Descriptions (continued)

SRSP1 (07h, 00h) Slave Response Register 1

Initialization: Th is register is reset to 0000h on all forms of reset. Read/Write Access:

SRSP1.[15:0]:

Unrestricted read acce ss only to the UserCore. Unrestricted read/write access to the DSPCore.

Response Register 1 Bits 15:0. The se bits are used to supply output data to the master. To notif y the master that data is ready to be read, the RSPCDV bit should be set to 1 by software. The slave should not write further data to SRSP1 until the va lid condition (RSPSDV = 1) is cleared by the master software.

AD0LSB (08h, 00h) Analog-to-Digital Converter 0 Least Significant Byte Output Register

Initialization: This register i s reset to FFh on all forms of reset.

Read/Write Access: Unrestricted read access.

Analog-to-Digital Converter 0 Least Significant Byte Output Register. This register always provides read access to the least significant byte of the most current ADC0 data sample acquired from the respective sinc3 filter. See the below table for the least significant byte available OSR options.

Reading from the AD0 register results in the ABF0 f lag being cleared by hardware (when set) unless the read operation is performed simultaneously with a write. What this means is that when OSR > 32, AD0LSB should be read first if the clearing of ABF0 is intended to indicate that the full

AD0LSB.[7:0]:

AD1LSB (09h, 00h) Analog-to-Digital Converter 1 Least Significant Byte Output Register

AD2LSB (0Ah, 00h) Analog-to-Digital Converter 2 Least Significant Byte Output Register

AD3LSB (0Bh, 00h) Analog-to-Digital Converter 3 Least Significant Byte Output Register

AD4LSB (0Ch, 00h) Analog-to-Digital Converter 4 Least Significant Byte Output Register

AD5LSB (0Dh, 00h) Analog-to-Digital Converter 5 Least Significant Byte Output Register

result (AD0LSB and AD0) was read. Reading a disabled ADC returns the data la st acquired if the assoc iated buffer full flag is set and returns FFFFh if the flag is clear.

OSR ADC DATA OUTPUT WIDTH AD0LSB FORMAT

32 16 00000000b 64 19 d2–d0, 00000b

128 22 d5–d0, 00b 256 24 d7–d0

MREQ0 (0Eh, 00h) Master Request Register 0

Initialization: Th is register is reset to 00h on all forms of reset.

Read/Write Access:

MREQ0.[3:0]: REQCM[3:0]

MREQ0.4: RSP1E

MREQ0.5: REQCDV

MREQ0.[7:6]: Reserved Reserved. Reads return 0.

Unrestricted read/write access to the UserCore (except REQCDV; see the bit description). Unrestricted read acce ss only to the DSPCore (except REQCDV; see the bit description).

Request Command Bits 3:0. These bits are written by the master to supply a command request to the sla ve. To notify the slave that a command is ready to be read, the REQ0DV bit should be set to 1.

Response Registers Interrupt Enable. Setting this bit to 1 enables an interrupt for the slave response status data valid flag (which is a ss ociated with Response Registers 0 and 1). The status data va lid (interrupt) flag is reported in SRSP0.5. Clearing this bit to 0 disables the interrupt assoc iated with the respon se status data valid flag.

Request Command Data Valid Flag. This f lag can only be set by the master (UserCore). This flag should be set once a valid command is supplied in the REQCM[3:0] field of the MREQ0 and/or data supplied in the MREQ1, MREQ2 registers to notif y the s lave that the se registers are ready for reading. This flag can only be cleared by slave (DSPCore) software.

MAXQ3108

Low-Power, Dual-Core Microcontroller

______________________________________________________________________________________ 19

Special Function Register Bit Descriptions (continued)

MREQ1 (0Fh, 00h) Master Request Register 1

Initialization: This register is reset to 0000h on all forms of reset. Read/Write Access:

MREQ1.[15:0]:

MREQ2 (10h, 00h) Master Request Register 2

Initialization: This register is reset to 0000h on all forms of reset. Read/Write Access:

MREQ2.[15:0]:

ADCN (11h, 00h) Analog-to-Digital Converter Control Register

Initialization: This register is cleared to 0000h on all forms of reset.

Read/Write Access:

ADCN.0: ABF0

ADCN.1: ABF1

ADCN:2: ABF2

ADCN.3: ABF3

ADCN.4: ABF4

Unrestricted read/write access only to the UserCore. Unrestricted read acce ss only to the DSPCore.

Master Request Register 1 Bits 15:0. These bit s are used to supply follow-on address and data information for commands issued by the master. To notify the slave that data i s read y to be read, the REQCDV bit should be set to 1. The master should poll the REQCDV bit to know when the slave has read MREQ1 and when it is safe to write further data to MREQ1.

Unrestricted read/write access only to the UserCore. Unrestricted read acce ss only to the DSPCore.

Master Request Register 2 Bits 15:0. These bit s are used to supply follow-on address and data information for commands issued by the master. To notify the slave that data i s read y to be read, the REQCDV bit should be set to 1. The master should poll the REQCDV bit to know when the slave has read MREQ2 and when it is safe to write further data to MREQ2.

UserCore: Unrestricted read/write access except bits 0:5 are read only and 6:7 have hardware restricted write access. DSPCore: Read-only.

ADC0 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from ADC0. An interrupt request i s generated to a CPU if IF01E = 1 and interrupts are not otherwise masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore or the DSPCore) of the AD0 output register. The A BF0 and ABF1 flags are set in the same clock cycle. ADC1 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from ADC1. An interrupt request i s generated to a CPU if IF01E = 1 and interrupts are not otherwise masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore or the DSPCore) of the AD1 output register. The A BF0 and ABF1 flags are set in the same clock cycle. ADC2 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from ADC2. An interrupt request i s generated to a CPU if IF23E = 1 and interrupts are not otherwise masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore or the DSPCore) of the AD2 output register. The A BF2 and ABF3 flags are set in the same clock cycle. ADC3 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from ADC3. An interrupt request i s generated to a CPU if IF23E = 1 and interrupts are not otherwise masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore or the DSPCore) of the AD3 output register. The A BF2 and ABF3 flags are set in the same clock cycle. ADC4 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from ADC4. An interrupt request i s generated to a CPU if IF45E = 1 and interrupts are not otherwise masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore or the DSPCore) of the AD4 output register. The A BF4 and ABF5 flags are set in the same clock cycle.

MAXQ3108

Low-Power, Dual-Core Microcontroller

20 ______________________________________________________________________________________

Special Function Register Bit Descriptions (continued)

ADC5 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from ADC5. An interrupt request i s generated to a CPU if IF45E = 1 and interrupts are not otherwise

ADCN:5: ABF5

ADCN.[7:6]: OSR[1:0]

ADCN.8: MD0E

ADCN.9: MD1E

ADCN.10: MD2E

ADCN.11: MDCKS

ADCN.12: IF10E

masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore or the DSPCore) of the AD5 output register. The A BF4 and ABF5 flags are set in the same clock cycle.

Oversampling Rate Bits 1:0. These register bits control the oversampling rate applied by all of the cubic sinc digital fi lter s (as given in the table below). These bits are writable on ly when all Manchester decoders are disabled.

OSR[1:0] OVERSAMPLING RATE

00b 32

01b 64

10b 128

11b 256

Manchester Decoder 0 Enable. Thi s bit controls whether Manchester decoder 0 and the two assoc iated cubic sinc filters are enabled or disabled. When MD0E i s conf igured to logic 1, Manchester decoder 0 and the assoc iated cubic sinc f ilters are enabled. Thi s is a special case where enabling the special function input (Manchester decoder input) forces a specific input mode (single-ended or differentia l) based upon the PO bit for the port pin corresponding to the Manchester decoder positive input (e.g., PO2.4 controls the single-ended or differential configuration for Manchester decoder 0 when MD0E = 1). When the PO bit = 0, single-ended mode is in effect. When PO bit = 1, differential mode is in effect. When MD0E is configured to logic 0, these hardware blocks are disabled. This bit is write acce ssible on ly to the UserCore.

Manchester Decoder 1 Enable. Thi s bit controls whether Manchester decoder 1 and the two assoc iated cubic sinc filters are enabled or disabled. When MD1E i s conf igured to logic 1, Manchester decoder 1 and the assoc iated cubic sinc f ilters are enabled. Thi s is a special case where enabling the special function input (Manchester decoder input) forces a specific input mode (single-ended or differentia l) based upon the PO bit for the port pin corresponding to the Manchester decoder positive input (e.g., PO0.3 controls the single-ended or differential configuration for Manchester decoder 1 when MD1E = 1). When the PO bit = 0, single-ended mode is in effect. When PO bit = 1, differential mode is in effect. When MD1E is configured to logic 0, these hardware blocks are disabled. This bit is write acce ssible on ly to the UserCore.

Manchester Decoder 2 Enable. Thi s bit controls whether Manchester decoder 2 and the two assoc iated cubic sinc filters are enabled or disabled. When MD2E i s conf igured to logic 1, Manchester decoder 2 and the assoc iated cubic sinc f ilters are enabled. Thi s is a special case where enabling the special function input (Manchester decoder input) forces a specific input mode (single-ended or differentia l) based upon the PO bit for the port pin corresponding to the Manchester decoder positive input (e.g., PO2.0 controls the single-ended or differential configuration for Manchester decoder 2 when MD2E = 1). When the PO bit = 0, single-ended mode is in effect. When PO bit = 1, differential mode is in effect. When MD2E is configured to logic 0, these hardware blocks are disabled. This bit is write acce ssible on ly to the UserCore.

Manchester Decoders Clock Speed Select. This bit must be configured to tell the Manchester decoders whether a fast or slow bit-stream sampling clock is used. When configured to 0, the decoders e xpect that the sampling clock is faster than the clock source being used b y the AD02 modulator(s). When configured to 1, the decoders expect that the sampling clock is s lower that than being used by the AD02.

ADC Interrupt Flags 1 and 0 Enable. This bit serves a s the loca l interrupt enable for the ADC cubic sinc filter output buffers 1 and 0.

+ 44 hidden pages