General Description
The MAX9691/MAX9692/MAX9693 are ultra-fast ECL
comparators capable of very short propagation delays.
Their design maintains the excellent DC matching characteristics normally found only in slower comparators.
The MAX9691/MAX9692/MAX9693 have differential
inputs and complementary outputs that are fully compatible with ECL-logic levels. Output current levels are
capable of driving 50Ω terminated transmission lines.
The ultra-fast operation makes signal processing possible at frequencies in excess of 600MHz.
The MAX9692/MAX9693 feature a latch-enable (LE)
function that allows the comparator to be used in a
sample-hold mode. When LE is ECL high, the comparator functions normally. When LE is driven ECL low, the
outputs are forced to an unambiguous ECL-logic state,
dependent on the input conditions at the time of the
latch input transition. If the latch-enable function is not
used on either of the two comparators, the appropriate
LE input must be connected to ground; the companion
LE input must be connected to a high ECL logic level.
These devices are available in SO, QSOP, and tiny
µMAX packages for added space savings.
________________________Applications
High-Speed Line Receivers
Peak Detectors
Threshold Detectors
High-Speed Triggers
Features
♦ 1.2ns Propagation Delay
♦ 100ps Propagation Delay Skew
♦ 150ps Dispersion
♦ 0.5ns Latch Setup Time
♦ 0.5ns Latch-Enable Pulse Width
♦ Available in µMAX and QSOP Packages
♦ +5V, -5.2V Power Supplies
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
________________________________________________________________ Maxim Integrated Products 1
_________________________________________________________Functional Diagrams
19-1789; Rev 0; 8/00
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Ordering Information
Ordering Information continued at the end of data sheet.
Pin Configurations appear at end of data sheet.
Selector Guide
PART
MAX9691EUA -40°C to +85°C8 µMAX
MAX9691ESA -40°C to +85°C 8 SO
MAX9691EPA -40°C to +85°C 8 PDIP
PART
MAX9691 1 No
MAX9692 1 Yes
MAX9693 2 Yes
COMPARATORS
PER PACKAGE
TEMP.
RANGE
ENABLE
PIN-PACKAGE
LATCH
PINPACKAGE
8 µMAX,
8 SO, 8 PDIP
10 µMAX,
16 SO, 16 PDIP
16 QSOP,
16 SO, 16 PDIP
NONINVERTING
IN+
IN-
R
R
L
MAX9691
L
V
Q OUT
Q OUT
T
THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL PULLDOWN
RESISTORS. THESE RESISTORS MAY BE IN THE RANGE OF 50Ω TO 200Ω
CONNECTED TO -2.0V, OR 240Ω TO 2000Ω CONNECTED TO -5.2V.
INPUT
INVERTING
INPUT
R
MAX9693 MAX9693
LATCH ENABLE
L
LE LE
R
Q OUT
L
Q OUT
V
R
L
T
R
NONINVERTING
L
LE LE
LATCH ENABLE
INPUT
INVERTING
INPUT
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +5V, VEE= -5.2V, RL= 50Ω to VT, VT= -2V, LE = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage (VCC) ...............................................-0.3V to +6V
Supply Voltage (VEE)................................................-6V to +0.3V
Input Voltage....................................(VCC+ 0.3V) to (VEE- 0.3V)
Output Short-Circuit Duration ....................................Continuous
Differential Input Voltage ......................................................±5V
Latch Enable ...............................................(V
EE
- 0.3V) to +0.3V
Output Current ....................................................................50mA
Input Current ....................................................................±25mA
Continuous Power Dissipation (T
A
= +70°C)
8-Pin µMAX (derate 4.1mW/°C above 70°C)...............330mW
8-Pin SO (derate 5.88mW/°C above +70°C) ...............471mW
8-Pin PDIP (derate 10.53mW/°C above +70°C)...........842mW
10-Pin µMAX (derate 5.6mW/°C above +70°C)...........444mW
16-Pin QSOP (derate 8.3mW/°C above +70°C) ..........667mW
16-Pin SO (derate 8.7mW/°C above +70°C) ...............696mW
16-Pin PDIP (derate 9.09mW/°C above +70°C) ..........727mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
)
)
Input Offset Voltage V
Temperature Coefficient ∆VOS/∆T10µV/°C
Input Offset Current I
Input Bias Current I
Input Voltage Range V
Common-Mode Rejection Ratio CMRR -2.5V ≤ VCM ≤ +3.0V (Note 1) 60 80 dB
Positive Power-Supply Rejection
Ratio
Negative Power-Supply
Rejection Ratio
Open-Loop Gain AOL VCM = 0 70 dB
Differential Input Resistance R
Differential Input Clamp Voltage 1.7 V
Input Capacitance C
Latch Enable Input Current High I
Latch Enable Input Current Low I
Latch E nab l e Log i c H i g h V ol tag eV
Latch Enable Logic Low Voltage V
Logic Output Low Voltage V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OS
OS
B
CM
+PSRR 4.5V ≤ V
-PSRR -5.7V ≤ V
IH(LE)
IL(LE)
IH(LE
IL(LE
OH
TA = +25°C -6.5 6.5
T
= T
to T
MIN
A
MAX
TA = +25°C 0.2 5
T
= T
A
to T
MIN
MAX
TA = +25°C620
T
= T
A
to T
MIN
MAX
Note 1 -2.5 +3.0 V
≤ 5.5V 60 dB
CC
≤ -4.7V 60 dB
EE
IN
IN
-10mV < V
V
IH(LE)
V
IL(LE)
TA = T
TA = T
< 10mV 60 kΩ
IN
= 1.1V 60 120 µA
= 1.5V 0.2 10 µA
MIN
MAX
TA = +25°C -1.06 -0.76
TA = T
MIN
TA = T
OL
MAX
TA = +25°C -1.89 -1.55
-11.5 11.5
8
30
3pF
-1.1 V
-1.5 V
-1.2 -0.87
-0.99 -0.70 Logic Output High Voltage V
-1.93 -1.57
-1.89 -1.51
mV
µA
µA
V
V
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +5V, VEE= -5.2V, RL= 50Ω to VT, VT= -2V, LE = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1: Guaranteed by design.
Note 2: V
IN
= 100mV, VOD= 10mV.
AC ELECTRICAL CHARACTERISTICS
(VCC= 5V, VEE= -5.2V, RL= 50Ω to VT, VT= -2V, LE = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
p
p
pw(LE)
pag
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9693
Supply Current I
CC
MAX9691/
MAX9692
TA = +25°C3446
= T
MIN
to T
MAX
T
A
TA = +25°C1826
T
= T
MIN
to T
MAX
A
50
36
mA
PARAMETER
SYMBOL CONDITIONS MIN TYP MAX
MAX9691/MAX9692/MAX9693
Propagation Delay (Notes 1, 2) t
d+
Rise/Fall Time tr, t
Propagation Delay Skew ∆
Dispersion P
DSP
, t
PD
TA = +25°C 1.2 1.8
d-
TA = T
10% to 90% 500 ps
f
MIN
to T
VOD from 10mV to 100mV 150 ps
MAX9692/MAX9693
Latch-Enable Time (Note 1) TLE(±)
TA = +25°C 1.0 1.8
= T
MIN
to T
T
A
Latch- Enab le P ul se Wi d th (N ote 1) t
Setup Time (Note 1) t
Hold Time (Note 1) t
Channel-to-Channel
ation Match
Pro
t
PDM
s
h
Note 2 (MAX9693 only) 100 ps
MAX
MAX
UNITS
2.0
ns
100 ps
2.0
ns
0.5 1.0 ns
0.5 1.0 ns
0.5 1.0 ns
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
4 _______________________________________________________________________________________
/3
)
V
(V)
Typical Operating Characteristics
(VCC= +5V, VEE= -5.2V, RL= 50Ω to VT, VT= -2V, V
OD
= 10mV, TA= +25°C, unless otherwise noted.)
WORST-CASE PROPAGATION DELAY
vs. INPUT OVERDRIVE
1400
6000
WORST-CASE PROPAGATION DELAY
vs. SOURCE IMPEDANCE
1800
WORST-CASE PROPAGATION DELAY
vs. C
LOAD
MAX9691/3-01
1200
1000
800
PROPAGATION DELAY (ps)
600
400
0405020 3010 60 70 80 90 100
INPUT OVERDRIVE (mV)
WORST-CASE PROPAGATION DELAY
vs. TEMPERATURE
1400
1300
1200
1100
1000
900
PROPAGATION DELAY (ps)
800
700
600
-40 -15 10 35 60 85
TEMPERATURE (°C)
VOD = 100mV
INPUT OFFSET VOLTAGE
vs. TEMPERATURE
2000
1500
1000
500
0
-500
-1000
INPUT OFFSET VOLTAGE (µV)
-1500
-2000
-40 -15 10 35 60 85
TEMPERATURE (°C)
5000
4000
3000
2000
PROPAGATION DELAY (ps)
1000
0
0 20015050 100 250 300 350 400 450 500
-0.6
MAX9691/3-04
-0.7
-0.8
(V)
OH
V
-0.9
-1.0
-1.1
-40 10-15 35 60 85
8.0
7.5
MAX9691/3-08
7.0
6.5
6.0
5.5
INPUT BIAS CURRENT (µA)
5.0
4.5
4.0
-40 -15 10 35 60 85
SOURCE IMPEDANCE (Ω)
OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
R
= 200Ω
PULLDOWN
TEMPERATURE (°C
INPUT BIAS CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
R
PULLDOWN
R
PULLDOWN
= 100Ω
= 50Ω
MAX9691/3-02
1600
1400
1200
1000
PROPAGATION DELAY (ps)
800
600
0105 152025
-1.60
-05
-1.62
MAX9691
-1.64
-1.66
R
PULLDOWN
OL
-1.68
-1.70
-1.72
-1.74
-1.76
-1.78
-1.80
-40 10-15 35 60 85
vs. DIFFERENTIAL INPUT VOLTAGE
5000
4000
MAX9691/3-09
3000
2000
1000
0
-1000
-2000
INPUT BIAS CURRENT (µA)
-3000
-4000
-5000
-5 -3 -2 -1-4 012 435
C
(pF)
LOAD
OUTPUT LOW VOLTAGE
vs. TEMPERATURE
R
= 100Ω
PULLDOWN
= 200Ω
R
= 50Ω
PULLDOWN
TEMPERATURE (°C)
INPUT BIAS CURRENT
DIFFERENTIAL INPUT VOLTAGE (V)
MAX9691/3-03
MAX9691/3-06
MAX9691/3-10
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(VCC= +5V, VEE= -5.2V, RL= 50Ω to VT, VT= -2V, V
OD
= 10mV, TA= +25°C, unless otherwise noted).
__________ Applications Information
Layout
Because of the MAX9691/MAX9692/MAX9693s’ large
gain-bandwidth characteristic, special precautions
must be taken to use them. A PC board with a ground
plane is mandatory. Mount 0.01µF ceramic decoupling
capacitors as close to the power-supply pins as possible, and process the ECL outputs in microstrip fashion,
consistent with the load termination of 50Ω to 200Ω (for
VT = -2V). For low-impedance applications, microstrip
layout and terminations at the input may also be helpful. Pay close attention to the bandwidth of the decoupling and terminating components. Chip components
can be used to minimize lead inductance. Connect
GND1 and GND2 together to a solid copper ground
plane for the MAX9691/MAX9692. GND1 biases the
input gain stages, while GND2 biases the ECL output
stage. If the LE function is not used, connect the LE pin
to GND (MAX9692/MAX9693) and the complementary
LE to ECL logic high level (MAX9693 only). Do not
leave the inputs of an unused comparator floating for
the MAX9693.
Input Slew-Rate Requirements
As with all high-speed comparators, the high gainbandwidth product of these devices creates oscillation
problems when the input goes through the linear
region. For clean switching without oscillation or steps
in the output waveform, the input must meet certain
minimum slew-rate requirements. The tendency of the
part to oscillate is a function of the layout and source
impedance of the circuit employed. Poor layout and
larger source impedance will increase the minimum
slew-rate requirement.
Figure 1 shows a high-speed receiver application with
50Ω input and output termination. With this configuration, in which a ground plane and microstrip PC board
are used, the minimum slew rate for clean output
switching is 1V/µs.
In many applications, adding regenerative feedback
will assist the input signal through the linear region,
which will lower the minimum slew-rate requirement
considerably. For example, with the addition of positive
feedback components, Rf = 1kΩ and Cf = 10pF, the
minimum slew-rate requirement can be reduced by a
factor of four.
PROPAGATION DELAY
MAX9691/3-11
V
IN
200mV/div
TIME (1 ns/div)
Q OUT - Q OUT
200mV/div
VIN = 100mV
V
OD
= 10mV
100MHz OUTPUT RESPONSE
MAX9691/3-12
-1.0
Q OUT
200mV/div
Q OUT
200mV/div
-1.8
-1.8
-1.0
TIME (1ns/div)
Figure 1. Regenerative Feedback—High-Speed Receiver with
50Ω Input and Output Termination
V
IN
50Ω
50Ω
Q
Q
LE
C
R
f
f
50Ω
-2V
50Ω
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
6 _______________________________________________________________________________________
As high-speed receivers, the MAX9691/MAX9692/
MAX9693 are capable of processing signals in excess
of 600MHz. Figure 2 is a 100MHz example with an
input signal level of 14mV
RMS
.
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions. The top line of the diagram illus-
trates two latch-enable pulses. Each pulse is high for
the compare function and low for the latch function. The
first pulse demonstrates the compare function; part of
the input action takes place during the compare mode.
The second pulse demonstrates a compare function
interval during which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude, small-overdrive pulse) switches the
comparator after time interval tpd. Output Q and Q transistors are similar in timing. The input signal must occur
at time tsbefore the latch falling edge, and must be
maintained for time thafter the edge to be acquired.
After th, the output is no longer affected by the input status until the latch is again strobed. A minimum latch
pulse width of t
pw(LE)
is needed for the strobe opera-
tion, and the output transitions occur after a time t
LE(±)
.
The MAX9691/MAX9692/MAX9693 will not false trip
(i.e., output invert) if one of the inputs is in the valid
common-mode range while the other input is outside
the common-mode range.
Figure 2. Signal Processed at 100MHz with Input Signal Level
of 14mV
RMS
Figure 3. Timing Diagram
INPUT
20mV/div
OUTPUT
500mV/div
2ns/div
0
-0.9V
-1.7V
COMPARE
LATCH
ENABLE
LATCH
DIFFERENTIAL
INPUT
VOLTAGE
V
IN
Q
Q
t
s
t
h
V
OD
t
pd
t
pw(LE)
t
LE(+)
50%
V
OS
50%
50%
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________ 7
Definition of Terms
V
OS
Input Offset Voltage. The voltage required
between the input terminals to obtain 0V differential at the output.
V
IN
Input Voltage Pulse Amplitude
V
OD
Input Voltage Overdrive
t
pd+
Input to Output High Delay. The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output low-to-high transition.
t
pd-
Input to Output Low Delay. The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output high-to-low transition.
t
LE(+)
Latch-Enable to Output High Delay. The propagation delay measured from the 50% point of
the latch-enable signal low-to-high transition
to the 50% point of an output low-to-high transition.
t
LE(-)
Latch-Enable to Output Low Delay. The propagation delay measured from the 50% point of
the latch-enable signal low-to-high transition
to the 50% point of an output high-to-low transition.
t
pw
(LE)
Latch-Enable Pulse Width. The minimum time
the latch-enable signal must be high to acquire
and hold an input signal.
t
s
Setup Time. The minimum time before the
negative transition of the latch-enable pulse
that an input signal must be present to be acquired and held at the outputs.
t
h
Hold Time.The minimum time after the negative transition of the latch-enable signal that
an input signal must remain unchanged to be
acquired and held at the output.
∆
pd
Propagation Delay Skew.The difference in
propagation delay between the Q and Q outputs crossing each other in both directions.
P
DSP
Propagation Delay Dispersion.The change in
propagation delay as a result of the overdrive
of the input signal varying.
t
pdm
Propagation Delay Match (MAX9693 only).The
difference in propagation delay between two
separate channels.
Chip Information
TRANSISTOR COUNT: MAX9691:106
MAX9692:106
MAX9693: 207
Ordering Information (continued)
PART
MAX9692EUB -40°C to +85°C 10 µMAX
MAX9692ESE -40°C to +85°C 16 Narrow SO
MAX9692EPE -40°C to +85°C 16 PDIP
MAX9693EEE -40°C to +85°C 16 Narrow SO
MAX9693ESE -40°C to +85°C 16 QSOP
MAX9693EPE -40°C to +85°C 16 PDIP
TEMP.
RANGE
PIN-PACKAGE
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
8 _______________________________________________________________________________________
Pin Configurations
DIP/SO/µMAX
MAX9691
Q OUT
Q OUTV
EE
1
2
87GND1
GND2IN+
IN-
V
CC
3
4
6
5
TOP VIEW
µMAX
MAX9692
1
2
3
4
5
10
9
8
7
6
GND1
GND2
Q OUT
Q OUTN.C.
IN-
IN+
V
CC
V
EE
LE
PDIP/SO
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GND1 GND2
N.C.
N.C.
N.C.
Q OUT
N.C.
N.C.
V
CC
IN+
LE
IN-
N.C.
N.C.
V
EE
MAX9692
TOP VIEW
MAX9693
DIP/SO/QSOP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Q OUT Q OUT
Q OUT
GND
LEB
LEB
V
CC
INB-
INB+
Q OUT
GND
V
EE
LEA
LEA
INA-
INA+
TOP VIEW
Q OUT
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________ 9
Package Information
MAX9691/MAX9692/MAX9693
8LUMAXD.EPS
10LUMAX.EPS
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
QSOP.EPS
Package Information (continued)
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