Rainbow Electronics MAX9671 User Manual

General Description

The MAX9670/MAX9671 dual SCART matrices route audio and video signals between a set-top box decoder chip and two external SCART connectors under I

C control. Operating from a 3.3V supply and a 12V supply, the MAX9670/MAX9671 consume 70mW during quiescent operation and 471mW during average operation when driving typical signals into typical loads. Video input detection, video load detection, and a 2.5mW standby mode facilitate the design of intelligent, low-power set-top boxes.

The MAX9670/MAX9671 audio section contains a buffered crosspoint to route audio inputs to audio outputs and programmable volume control from -62dB to 0dB in 2dB steps. The DirectDrive

output amplifiers

create a 2V

RMS

full-scale audio signal biased around ground, eliminating the need for bulky output capacitors and reducing click-and-pop noise. The zero-cross detection circuitry also further reduces clicks and pops by enabling audio sources to switch only during a zerocrossing. The MAX9671 offers TV left and right audio inputs.

The MAX9670/MAX9671 video section contains a buffered crosspoint to route video inputs to video outputs. The standard-definition video signals from the settop box decoder chip are lowpass filtered to remove out-of-band artifacts.

The MAX9670/MAX9671 also support slow-switching and fast-switching signals. An interrupt signal from the MAX9670/MAX9671 informs the microcontroller when the system status has changed.

Applications

Set-Top Boxes

TVs

DVD Players

Features

o 70mW Quiescent Power Consumption

o 2.5mW Standby Mode Consumption

o Programmable Audio Gain Control of -62dB to

0dB (TV Audio Outputs)

o Clickless, Popless, DirectDrive Audio

o Video Input and Video Load Detection

o Video Reconstruction Filter with 10MHz Passband

and 52dB Attenuation at 27MHz

o 3.3V and 12V Supply Voltages

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

________________________________________________________________

Maxim Integrated Products

19-4653; Rev 0; 7/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad.

DirectDrive is a registered trademark of Maxim Integrated Products, Inc.

Typical Application Circuit appears at end of data sheet.

System Block Diagram

PART TEMP RANGE

PINPACKAGE

MAX9670CTL+ 0°C to +70°C 40 TQFN-EP* No

MAX9671CTH+ 0°C to +70°C 44 TQFN-EP* Yes

TV R+L

AUDIO

INPUTS

STB CHIP

µC

VIDEO

ENCODER

I2C

INTERRUPT

OUTPUT

RGB, Y/C, CVBS

12V 3.3V3.3V

MAX9670/MAX9671

I2C INTERFACE

REGISTERS AND

ACTIVITY MONITOR

VIDEO FILTERS AND

CROSSPOINT

AUD

VID

RGB, Y/C, CVBS

CVBS

L/R AUDIO

(MAX9671 ONLY)

L/R AUDIO

(MAX9670 ONLY)

SLOW SWITCHING

FAST SWITCHING

SCART

Y/C, CVBS

RGB, Y/C, CVBS

L/R AUDIO

SLOW SWITCHING

FAST SWITCHING

VCR

SCART

STEREO

AUDIO

DAC

SINGLE-ENDED R/L

STEREO AUDIO

AUDIO CROSSPOINT

WITH DIRECTDRIVE OUTPUTS, VOLUME

CONTROL

SLOW SWITCHING

FAST SWITCHING

CHARGE PUMP

EP GNDVID

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(V12= 12V, V

VID

= V

AUD

= 3.3V, V

GNDVID

= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VID

to GNDVID........................................................-0.3V to +4V

to EP.................................................................-0.3V to +14V

AUD

to EP ...............................................................-0.3V to +4V

EP to GNDVID .......................................................-0.1V to +0.1V

All Video Inputs, VCRIN_FS to GNDVID...................-0.3V to +4V

All Audio Inputs to EP .........................................-1V to (EP + 1V)

SDA, SCL, DEV_ADDR, INT to GNDVID ..................-0.3V to +4V

TV_SS, VCR_SS to EP .................................-0.3V to (V

+ 0.3V)

Current

All Video/Audio Inputs ...................................................±20mA

C1P, C1N, CPVSS .........................................................±50mA

Output Short-Circuit Current Duration

Video and Fast-Switching Outputs to V

VID

GNDVID.................................................................Continuous

Audio Outputs to V

AUD

, EP .....................................Continuous

TV_SS, VCR_SS to V

, EP......................................Continuous

Continuous Power Dissipation (T

= +70°C) 40-Pin TQFN-EP (derate 26.3mW/°C above +70°C) ...2105.3mW 44-Pin TQFN-EP (derate 26.3mW/°C above +70°C)...2222.2mW

Operating Temperature Range...............................0°C to +70°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Video Supply Voltage Range V

Audio Supply Voltage Range V

V12 Supply Voltage Range V

Quiescent Supply Current I

VID

Quiescent Supply Current I

AUD

V12 Quiescent Supply Current I

VIDEO CHARACTERISTICS

DC-COUPLED INPUT

Input Current I

Input Resistance R

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VID_Q

AUD_Q

VID

AUD

12_Q

Inferred from video PSRR test at 3V and

3.6V

Inferred from audio PSRR test at 3V and

3.6V

Inferred from slow-switching levels 11.4 12 12.6 V

Normal operation; all video output amplifiers are enabled and muted (Note 2)

Standby mode, slow switch inputs low 1500

Shutdown 35

Normal operation (Note 2) 3.2 6 mA

Shutdown 35 µA

Slow-switching output

Normal operation (Note 2)

Shutdown, TA = +25°C 10 µA

RL = 75Ω to GNDVID or 150Ω to V

/2; inferred

VID

from gain test

VIN = 0.3V, TA = +25°C 1 2 µA

set to low-level

Slow-switching output set to medium-level

= 3V 1.15

VID

= 3.135V 1.15Input Voltage Range V

VID

= 3.3V 1.3

VID

3 3.3 3.6 V

16 30 mA

0.3 100

475

300 kΩ

µA

P-P

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(V12= 12V, V

VID

= V

AUD

= 3.3V, V

GNDVID

= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

AC-COUPLED INPUT

Sync-Tip Clamp Level V

Sync Crush

Input Clamping Current Sync-tip clamp, VIN = 0.3V, TA = +25°C 1 2 µA

Maximum Input Source Resistance

Input Voltage

Input Resistance

DC CHARACTERISTICS

DC Voltage Gain Av Guaranteed by output voltage swing 1.95 2 2.05 V/V

DC Gain Mismatch Among R, G, and B Outputs

Output Level

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLP

Sync-tip clamp -13 -4 +6 mV

S ync- ti p cl am p ; p er centag e r ed ucti on i n sync p ul se ( 0.3V cl am p i ng cur r ent m easur em ent, T

) ; g uar anteed b y i np ut

P - P

= + 25° C

Input sync-tip circuit must be stable even if the source resistance is as high as 300Ω

300 Ω

Bias circuit 0.57 0.6 0.63

High-impedance input circuit

0.3 x V

VID

0.36 x V

VID

Bias circuit 10

High-impedance input circuit 222

Guaranteed by output voltage swing of TV_R/C_OUT, TV_G_OUT, and TV_B_OUT; first input signal set is VCR_R/C_IN, VCR_G_IN, and VCR_B_IN; second signal

-2 +2 %

set is ENC_R/C_IN, ENC_G_IN, and ENC_B_IN

Sync-tip clamp (VIN = V

) 0.1 0.30 0.51

CLP

Bias circuit 1.3 1.5 1.78

Sync-tip clamp, measured at output, V

= 3V, VIN = V

VID

= 150Ω to V

to (V

CLP

/2, RL = 75Ω to GNDVID

VID

CLP

+1.15V),

2.3

kΩ

Output Voltage Swing

Measured at output, V

to (V

CLP

/2, RL = 75Ω to GNDVID

VID

+ 1.15V), RL = 150Ω to

CLP

Bias circuit, measured at output, V V

= (V

= 150Ω to V

- 0.575V) to (V

BIAS

VID

Measured at output, V

= (V

= 150Ω to V

- 0.575V) to (V

BIAS

VID

= 3.135V, VIN =

VID

= 3V,

VID

+ 0.575V),

BIAS

/2, RL = 75Ω to GNDVID

= 3.135V,

VID

+ 0.575V),

BIAS

/2, RL = 75Ω to GNDVID

2.243 2.3 2.358

2.3

2.243 2.3 2.358

P-P

Output Short-Circuit Current 100 mA

Output Resistance R

OUT

0.5 Ω

Output Leakage Current Output disabled (load detection not active) 170 µA

Power-Supply Rejection Ratio 3V ≤ V

≤ 3.6V 35 dB

VID

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V12= 12V, V

VID

= V

AUD

= 3.3V, V

GNDVID

= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

AC CHARACTERISTICS

Filter Passband Flatness V

Filter Attenuation

Slew Rate V

Settling Time V

Differential Gain DG 5-step modulated staircase, f = 4.43MHz 0.15 %

Differential Phase DP 5-step modulated staircase, f = 4.43MHz 0.5 Degrees

2T Pulse-to-Bar K Rating

2T Pulse Response 2T = 200ns 0.2 K%

2T Bar Response

Nonlinearity 5-step staircase 0.1 % Group Delay Distortion 100kHz ≤ f ≤ 5MHz, outputs are 2V

Glitch Impulse Caused by Charge-Pump Switching

Peak Signal to RMS Noise 100kHz ≤ f ≤ 5MHz 70 dB

Power-Supply Rejection Ratio f = 100kHz, 100mV

Output Impedance f = 5MHz 2 Ω

Video Crosstalk f = 4.43MHz -80 dB

Reverse Isolation

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

= 2V

OUT

= 2V

OUT

attenuation is referred to 100kHz

= 2V

OUT

= 2V

OUT

2T = 200ns, bar time is 18µs, the beginning

2.5% and the ending 2.5% of the bar time is ignored

2T = 200ns, bar time is 18µs, the beginning

2.5% and the ending 2.5% of the bar time is ignored

Measured at outputs 100 pV-s

VCR SCART inputs to encoder inputs, full-power mode with VCR being looped through to TV, f = 4.43MHz

, f = 100kHz to 5.5MHz -1 dB

P-P

, no filter in video path 60 V/µs

P-P

, settle to 0.1% (Note 3) 400 ns

P-P

f = 9.5MHz 3

f = 27MHz 40

f = 54MHz 55

P-P

0.3 K%

0.2 K%

11 ns

47 dB

92 dB

Pulldown Resistance

AUDIO CHARACTERISTICS

Voltage Gain VIN = -0.707V to +0.707V 3.95 4 4.05 V/V

Gain Mismatch VIN = -0.707V to +0.707V -1.5 +1.5 %

Flatness f = 20Hz to 20kHz, 0.25V

Frequency Bandwidth

Capacitive Drive

Enable VCR_R/C_OUT pulldown through

C interface

input 0.006 dB

RMS

0.25V

-3dB referenced to 1kHz

No sustained oscillations; 75Ω series resistor on output

input, frequency where output is

RMS

4.4 7.5 Ω

230 kHz

300 pF

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(V12= 12V, V

VID

= V

AUD

= 3.3V, V

GNDVID

= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

Input Resistance VIN = -0.707V to +0.707V 10 MΩ

Input Bias Current VIN = 0, TA = +25°C 500 nA

Input Signal Amplitude f = 1kHz, THD < 1% 0.5 V

Output DC Level No input signal, VIN grounded -4 +4 mV

Power-Supply Rejection Ratio

Signal-to-Noise Ratio f = 1kHz, 0.25V

Total Harmonic Distortion Plus Noise

Output Impedance f = 1kHz 0.4 Ω

Volume Control Attenuation Step

Volume Control Minimum Attenuation

Volume Control Maximum Attenuation

Mute Suppression f = 1kHz, 0.25V

Audio Crosstalk f = 1kHz, 0.25V

VIDEO-TO-AUDIO INTERACTION

Crosstalk

CHARGE PUMP

Switching Frequency 570 kHz

FAST SWITCHING

Input Low 0.4 V

Input High Level 1V

Input Current TA = +25°C 10 µA

Output Low Voltage I

Output High Voltage I

Output Resistance 7 Ω

Rise Time 143Ω to GNDVID 12 ns

Fall Time 143Ω to GNDVID 10 ns

SLOW SWITCHING

Input Low Voltage 2V

Input Medium Voltage 4.5 7 V

Input High Voltage 9.5 V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

RMS

DC 75 100

f = 1kHz 90

input, 20Hz to 20kHz 96 dB

RMS

RL = 3.33kΩ, f = 1kHz, 0.25V

= 3.33kΩ, f = 1kHz, 0.5V

Programmable gain to TV SCART volume control from -62dB to 0

input 110 dB

RMS

input 100 dB

RMS

Video input: f = 15kHz, 1V Audio input: f = 15kHz, 0.5V

= 0.5mA 0.1 V

= 0.5mA

input 0.002

RMS

input 0.001

RMS

signal

P-P

signal

RMS

VID

0.1

2dB

0dB

62 dB

92 dB

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V12= 12V, V

VID

= V

AUD

= 3.3V, V

GNDVID

= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

Input Current 70 100 µA

Output Low Voltage 10kΩ to EP, 11.4V ≤ V

Output Medium Voltage 10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V 5 6.5 V

Output High Voltage 10kΩ to EP, 11.4V ≤ V

DIGITAL INTERFACE

Input High Voltage V

Input Low Voltage V

Input Hysteresis V

Input Leakage Current IIH, I

Input Capacitance 6pF

Input Current

Output Low Voltage SDA V

Serial-Clock Frequency f

Bus Free Time Between a STOP and a START Condition

Hold Time, (Repeated) START Condition

Low Period of the SCL Clock t

High Period of the SCL Clock t

Setup Time for a Repeated START Condition

Data Hold Time t

Data Setup Time t

Fall Time of SDA Transmitting t

Setup Time for STOP Condition t

Pulse Width of Spike Suppressed t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

≤ 12.6V 1.5 V

≤ 12.6V 10 V

HYS

0.7 x V

VID

0.06 x V

VID

TA = +25°C -1 +1 µA

< SDA < 3.3V,

0.1V

VID

0.1V

< SCL < 3.3V

VID

I/O pins of fast-mode devices must not

-10 +10 µA

0.3 x V

VID

obstruct the SDA and SCL lines if V+ is

= +25°C

and tF measured between

VID

0 400 kHz

1.3 µs

0.6 µs

1.3 µs

0.6 µs

100 ns

0.6 µs

050ns

SCL

BUF

HD, STA

LOW

HIGH

SU, STA

HD, DAT

SU, STO

switched off, T

= 6mA 0.4 V

SINK

(Note 4) 0 0.9 µs

≤ 6mA, CB = total capacitance of one

SINK

bus line in pF, t

and 0.7V

0.3V

VID

Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(V12= 12V, V

VID

= V

AUD

= 3.3V, V

GNDVID

= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

Note 1: All devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by design. Note 2: Normal operation mode is full power with input video and load detection active. Note 3: The settling time is measured from the 50% of the input swing to the 0.1% of the final value of the output. Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V

of the SCL signal) to bridge

the undefined region of SCL’s falling edge.

Typical Operating Characteristics

VID

= V

AUD

= 3.3V, V12= 12V, V

GNDVID

= VEP= 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, TA= +25°C, unless

otherwise noted.)

OTHER DIGITAL I/O

DEV_ADDR Low Level

DEV_ADDR High Level

DEV_ADDR Input Current TA = +25°C -1 +1 µA

Interrupt Output Low Voltage I Interrupt Output Leakage Current INT high impedance, TA = +25°C 10 µA

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

0.3 x V

VID

0.7 x V

VID

= 0.5mA 0.1 V

SMALL-SIGNAL GAIN

vs. FREQUENCY

-10

-20

GAIN (dB)

-30

-40

-50

-60 100k 1G

FREQUENCY (Hz)

FILTER

OUT

= 100mV

100M10M1M

P-P

NO FILTER

MAX9670 toc01

SMALL-SIGNAL GAIN FLATNESS

vs. FREQUENCY

-1

-2

-3

GAIN (dB)

-4

-5

-6

-7

-8 1M 100M

FILTER

FREQUENCY (Hz)

10M

OUT

= 100mV

P-P

NO FILTER

MAX9670 toc02

LARGE-SIGNAL GAIN

vs. FREQUENCY

-10

-20

GAIN (dB)

-30

-40

-50

-60 100k 1G

FILTER

100M10M1M

FREQUENCY (Hz)

= 2V

OUT

NO FILTER

P-P

MAX9670 toc03

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

VID

= V

AUD

= 3.3V, V12= 12V, V

GNDVID

= VEP= 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, TA= +25°C, unless

otherwise noted.)

LARGE-SIGNAL GAIN FLATNESS

vs. FREQUENCY

MAX9670 toc04

FREQUENCY (Hz)

GAIN (dB)

10M

-7

-6

-5

-4

-3

-2

-1

-8 1M 100M

NO FILTER

FILTER

GROUP DELAY

vs. FREQUENCY

FILTER

NO FILTER

-20

-40

-60

DELAY (ns)

-80

-100

VIDEO CROSSTALK

vs. FREQUENCY

OUT

ALL HOSTILE

= 100mV

MAX9670 toc05

140

120

100

DELAY (ns)

P-P

= 2V

OUT

P-P

MAX9670 toc06

VIDEO POWER-SUPPLY REJECTION RATIO

-5

-10

-15

-20

-25

PSRR (dB)

-30

-35

-40

-45

-50 100k

DIFFERENTIAL GAIN AND PHASE

0.3

0.2

0.1 0

-0.1

-0.2

-0.3

DIFFERENTIAL GAIN (%)

0.6

0.4

0.2 0

-0.2

-0.4

-0.6

DIFFERENTIAL PHASE (deg)

102345

vs. FREQUENCY

FILTER

NO FILTER

10M1M

FREQUENCY (Hz)

100M

-120 100k

2.04

2.03

MAX9670 toc07

2.02

2.01

2.00

1.99

OUTPUT VOLTAGE (V)

1.98

1.97

1.96

0.3

0.2

0.1

MAX9670 toc10

-0.1

-0.2

-0.3

DIFFERENTIAL GAIN (%)

0.6

0.4

0.2 0

-0.2

-0.4

-0.6

DIFFERENTIAL PHASE (deg)

10M1M

FREQUENCY (Hz)

VIDEO VOLTAGE GAIN

vs. TEMPERATURE

INPUT VOLTAGE (V)

5025

DIFFERENTIAL GAIN AND PHASE

102345

1023

100M

100k

FREQUENCY (Hz)

10M1M

100M

VIDEO OUTPUT VOLTAGE

vs. INPUT VOLTAGE

3.5

3.0

MAX9670 toc08

2.5

2.0

1.5

OUTPUT VOLTAGE (V)

1.0

0.5

MAX9670 toc11

INPUT VOLTAGE (V)

2T WITH FILTER

80ns/div

1.20.80.4

MAX9670 toc12

MAX9670 toc09

1.6

VIDEO INPUT 200mV/div

VIDEO OUTPUT 500mV/div

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

VID

= V

AUD

= 3.3V, V12= 12V, V

GNDVID

= VEP= 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, TA= +25°C, unless

otherwise noted.)

2T NO FILTER

80ns/div

12.5T NO FILTER

MAX9670 toc13

MAX9670 toc15

VIDEO INPUT 200mV/div

VIDEO OUTPUT 500mV/div

VIDEO INPUT 200mV/div

12.5T WITH FILTER

1µs/div

NTC7 WITH FILTER

MAX9670 toc14

MAX9670 toc16

VIDEO INPUT 200mV/div

VIDEO OUTPUT 500mV/div

VIDEO INPUT 500mV/div

1µs/div

NTC7 NO FILTER

10µs/div

MAX9670 toc17

VIDEO OUTPUT 500mV/div

VIDEO INPUT 500mV/div

VIDEO OUTPUT 1V/div

10µs/div

FIELD SQUARE WAVE

2ms/div

MAX9670 toc18

VIDEO OUTPUT 1V/div

VIDEO INPUT 500mV/div

VIDEO OUTPUT 1V/div

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

VID

= V

AUD

= 3.3V, V12= 12V, V

GNDVID

= VEP= 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, TA= +25°C, unless

otherwise noted.)

VIDEO INPUT SYNC-TIP CLAMP VOLTAGE

-1

-2

-3

-4

INPUT CLAMP VOLTAGE (mV)

-5

-6 0

VIDEO INPUT SYNC-TIP CLAMP CURRENT

1.4

1.3

1.2

1.1

1.0

0.9

0.8

INPUT CLAMP CURRENT (mA)

0.7

0.6 0

vs. TEMPERATURE

5025

TEMPERATURE (°C)

vs. TEMPERATURE

5025

TEMPERATURE (°C)

MAX9670 toc19

MAX9670 toc21

VIDEO INPUT BIAS VOLTAGE

vs. TEMPERATURE

620

615

610

605

600

595

INPUT BIAS VOLTAGE (mV)

590

585

580

TEMPERATURE (°C)

5025

VIDEO INPUT SYNC-TIP CLAMP CURRENT

vs. INPUT VOLTAGE

INPUT CLAMP CURRENT (µA)

0 1.00.5 1.5 2.0 2.5 3.0 3.5

INPUT VOLTAGE (V)

MAX9670 toc20

MAX9670 toc22

VIDEO OUTPUT BIAS VOLTAGE

vs. TEMPERATURE

1.50

1.49

1.48

1.47

1.46

1.45

OUTPUT BIAS VOLTAGE (V)

1.44

1.43

1.42 0

TEMPERATURE (°C)

MAX9670 toc23

-5

GAIN (dB)

-10

-15

5025

-20

AUDIO LARGE-SIGNAL GAIN

vs. FREQUENCY

100k10k1k100

FREQUENCY (Hz)

MAX9670 toc24

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________

Typical Operating Characteristics (continued)

VID

= V

AUD

= 3.3V, V12= 12V, V

GNDVID

= VEP= 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, TA= +25°C, unless

otherwise noted.)

AUDIO CROSSTALK

vs. FREQUENCY

-20

-40

-60

CROSSTALK (dB)

-80

-100

-120 10

FREQUENCY (Hz)

POWER-SUPPLY REJECTION RATIO

AUD

(INPUT REFERRED) vs. FREQUENCY

-20

-40

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

= 3.3V + 100mV

AUD

0.1

MAX9670 toc25

0.01 TVIN TO

TVOUT

THD+N (%)

0.001

10k1k100

100k

0.0001 10 100k

FREQUENCY (Hz)

QUIESCENT SUPPLY CURRENT

VID

vs. TEMPERATURE

P-P

MAX9670 toc27

VIN = 0.25V

TVIN TO VCROUT

10k1k100

RMS

MAX9670 toc26

MAX9670 toc28

-60

PSRR (dB)

-80

-100

-120 10 100k

FREQUENCY (Hz)

QUIESCENT SUPPLY CURRENT

AUD

vs. TEMPERATURE

CURRENT (mA)

0255075

TEMPERATURE (°C)

CURRENT (mA)

10k1k100

0255075

TEMPERATURE (°C)

V12 QUIESCENT SUPPLY CURRENT

vs. TEMPERATURE

800

MAX9670 toc29

700

600

500

400

CURRENT (nA)

300

200

100

TEMPERATURE (°C)

MAX9670 toc30

5025

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

12 ______________________________________________________________________________________

Pin Description

MAX9670 MAX9671

1 1 SDA Bidirectional I2C Data I/O. Output is open drain and tolerates up to 3.6V.

2 2 SCL I2C Clock Input

3 3 DEV_ADDR Device Address Set Input. Connect to GNDVID, V

44 INT

NAME FUNCTION

Interrupt Output. This is an open-drain output that pulls down to GNDVID to indicate a change in the VCR slow switching or fast switching input, the activity status of the composite video inputs, or the load status of the composite video outputs.

, SDA or SCL. See Table 3.

VID

55 V

6 6 C1P

7 7 C1N

8 8 CPVSS C har g e- P um p N eg ati ve P ow er S up p l y. Byp ass w i th a 1µF cer am i c cap aci tor to E P .

9 9 ENC_INL Encoder Left-Channel Audio Input

10 10 ENC_INR Encoder Right-Channel Audio Input

— 11 TV_INL TV SCART Left-Channel Audio Input

— 12 TV_INR TV SCART Right-Channel Audio Input

11 13 VCR_INL VCR SCART Left-Channel Audio Input

12 14 VCR_INR VCR SCART Right-Channel Audio Input

13 15 TV_OUTL TV SCART Left-Channel Audio Output

14 16 VCR_OUTL VCR SCART Left-Channel Audio Output

15 17 VCR_OUTR VCR SCART Right-Channel Audio Output

16 18 TV_OUTR TV SCART Right-Channel Audio Output

17 19 TV_SS TV SCART Bidirectional Slow-Switch Signal

18 20 V

19 21 VCR_SS VCR SCART Bidirectional Slow-Switch Signal

20 22 TVOUT_FS TV SCART Fast-Switching Logic Output

— 23, 44 N.C. No Connection. Leave unconnected.

21 24 VCRIN_FS VCR SCART Fast-Switching Logic Input

22 25 ENC_B_IN Encoder Blue Video Input

23 26 ENC_G_IN Encoder Green Video Input

24 27 VCR_B_IN VCR SCART Blue Video Input

25 28 VCR_G_IN VCR SCART Green Video Input

26 29 TV_B_OUT TV SCART Blue Video Output

27 30 TV_G_OUT TV SCART Green Video Output

AUD

Audio Supply. Connect to a 3.3V supply. Bypass with a 10µF aluminum electrolytic capacitor and a 0.47µF ceramic capacitor to EP.

Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47µF capacitor from C1P to C1N.

Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47µF capacitor from C1P to C1N.

+12V Supply for the Slow Switching Circuit. Bypass with a 10µF + 0.47µF ceramic capacitor to EP.

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 13

Detailed Description

The MAX9670/MAX9671 represents Maxim’s third generation of SCART audio/video (A/V) switches. Under I2C control, these devices route audio, video, and control information between the set-top box decoder chip and two SCART connectors. The audio signals are left audio and right audio. The video signals are composite video with blanking and sync (CVBS) and component video (red, green, blue). S-video (Y/C) can be transported across the SCART interface if CVBS is reassigned to luma (Y) and red is reassigned to chroma (C). Support for S-video is optional. The slow-switch signal and the fast-switch signal carry control information. The slowswitch signal is a 12V, three-level signal that indicates whether the picture aspect ratio is 4:3 or 16:9 or causes the television to use an internal A/V source such as an antenna. The fast-switch signal indicates whether the television should display CVBS or RGB signals.

CVBS, left audio, and right audio are full duplex. All the other signals are half duplex. Therefore, one device on the link must be designated as the transmitter, and the other device must be designated as the receiver.

The low power consumption and the advanced monitoring functions of the MAX9670/MAX9671 enable the cre-

ation of lower power set-top boxes, televisions, and DVD players. Unlike competing SCART ICs, the audio and video circuits of the MAX9670/MAX9671 operate entirely from 3.3V rather than from 5V and 12V. Only the slow-switch circuit of the MAX9670/MAX9671 requires a 12V supply. The MAX9670/MAX9671 also have circuits that detect activity on the CVBS inputs, loads on the CVBS outputs, and the level of the slow-switch signals. The INT signal informs the microcontroller if there are any changes so that the microcontroller can intelligently decide whether to power up or power down the equipment.

In addition, the MAX9670/MAX9671 have DirectDrive audio circuitry to eliminate click-and-pop noise. With DirectDrive, the DC bias of the audio line outputs is always at ground, no matter whether the MAX9670/ MAX9671 are being powered up or powered down. Conventional audio line output drivers that operate from a single supply require series AC-coupling capacitors. During power-up, the DC bias on the AC-coupling capacitor moves from ground to a positive voltage, and during power-down, the opposite occurs. The changing DC bias usually causes an audible transient.

Pin Description (continued)

MAX9670 MAX9671

28 31 GNDVID Video Ground

29 32 VCR_R/C_IN VCR SCART Red/Chroma Video Input

30 33 V

31 34 ENC_C_IN Encoder Chroma Video Input

32 35 ENC_R/C_IN Encoder Red/Chroma Video Input

33 36 TV_R/C_OUT TV SCART Red/Chroma Video Output

34 37 VCR_R/C_OUT VCR SCART Red/Chroma Video Output

35 38 VCR_Y/CVBS_OUT VCR SCART Luma/Composite Video Output

36 39 TV_Y/CVBS_OUT TV SCART Luma/Composite Video Output

37 40 VCR_Y/CVBS_IN VCR SCART Luma/Composite Video Input

38 41 TV_Y/CVBS_IN TV SCART Luma/Composite Video Input

39 42 ENC_Y_IN Encoder Luma Video Input

40 43 ENC_Y/CVBS_IN Encoder SCART Luma/Composite Video Input

—— EP

NAME FUNCTION

Video and Digital Supply. Connect to a 3.3V supply. Bypass with parallel 1µF and

VID

0.1µF ceramic capacitors to GNDVID. V

C interface.

Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and charge pump. A low-impedance connection between ground and EP is required for proper isolation.

also serves as a digital supply for the

VID

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

14 ______________________________________________________________________________________

Audio Section

The MAX9670 audio circuit is essentially a stereo, 2-by-2, nonblocking, audio crosspoint with output drivers. The encoder (stereo audio DAC) and the VCR are the two input sources, and the two outputs go to the TV SCART connector and the VCR SCART connector. See Figure 1. The MAX9671 audio circuit is similar to that of the MAX9670 except that it is a stereo, 3-by-2,

nonblocking audio crosspoint with TV as the third input source.

The integrated charge pump inverts the +3.3V supply to create a -3.3V supply. The audio circuit operates from bipolar supplies so the audio signal is always biased to ground.

Figure 1. MAX9670/MAX9671 Audio Section Functional Diagram

ZCD

MUTE

ENC_INL

VCR_INL

*TV_INL

(0.5V

RMS

MUTE

FULL-SCALE INPUT)

MUTE

VOLUME

CONTROL

0dB TO -62dB

VOLUME

CONTROL

0dB TO -62dB

MUTE

FULL-SCALE OUTPUT)

(2V

RMS

TV_OUTL

TV_OUTR

ENC_INR

VCR_INR

*TV_INR

SCL

SDA

DEV_ADDR

AUD

C1P

C1N

CPVSS

*MAX9671 ONLY.

MUTE

VCR_OUTL

VCR_OUTR

CHARGE

PUMP

FULL-SCALE OUTPUT)

(2V

RMS

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 15

Clickless Switching

The TV audio channel incorporates a zero-crossing detect (ZCD) circuit that minimizes click noise due to abrupt signal level changes that occur when switching between audio signals at an arbitrary moment.

To implement the zero-crossing function when switching audio signals, set the ZCD bit high (Audio Control register 00h, bit 6). Then set the mute bit high (Audio Control register 00h, bit 0). Next, wait for a sufficient period of time for the audio signal to cross zero. This period is a function of the audio signal path’s low-frequency 3dB corner (f

L3dB

). Thus, if f

L3dB

= 20Hz, the time period to wait for a zero-crossing detect is 1/20Hz or 50ms.

After the wait period, select a new audio source for the TV audio channel by writing to bits 1 and 0 of TV Audio Control register (01h). Finally, clear mute (Audio Control register, 00h, bit 0), but leave ZCD (Audio Control register 00h, bit 6) high. The MAX9670/MAX9671 switches the signal out of mute at the next zero crossing. See Tables 12 and 13.

Audio Outputs

The MAX9670/MAX9671 audio output amplifiers feature Maxim’s patented DirectDrive architecture, thereby eliminating the need for output-coupling capacitors required by conventional single-supply audio line drivers. An internal charge pump inverts the positive supply (V

AUD

), creating a negative supply (CPVSS). The audio output amplifiers operate from these bipolar supplies with their outputs biased about audio ground (Figure 2). The benefit of this audio ground bias is that the amplifier outputs do not have a DC component. The DC-blocking capacitors required with conventional audio line drivers are unnecessary, conserving board space, reducing system cost, and improving frequency response.

Conventional single-supply audio line drivers have their outputs biased about a nominal DC voltage (typically half the supply) for maximum dynamic range. Large coupling capacitors are needed to block this DC bias. Clicks and pops are created when the coupling capacitors are charged during power-up and discharged during power-down.

The MAX9670/MAX9671 features a low-noise charge pump that requires only two small ceramic capacitors. The 580kHz switching frequency is well beyond the audio range and does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients.

The SCART standard specifies 2V

RMS

as the full-scale

for audio signals. As the audio circuits process

0.5V

RMS

full-scale audio signals internal to the MAX9670/MAX9671, the gain-of-4 output amplifiers restore the audio signals to a full-scale of 2V

RMS

To select which audio input source is routed to the TV SCART connector, write to bits 1 and 0 of the TV Audio Control register (01h). To select which audio input source is routed to the VCR SCART connector, write to bits 3 and 2 of the TV Audio Control register (01h). The power-on default is for the TV and VCR audio outputs to be muted (the inputs of the output amplifiers are connected to audio ground). See Tables 10 and 13.

Volume Control

Volume control is programmable from -62dB to 0dB in 2dB steps through I2C interface. The block consists of a resistive ladder network to generate 31 2dB volume control steps, a unity gain buffer to isolate the input from the resistive ladder, switches (MPLx and MNLx) that select 1 of 32 nodes on the resistive ladder, and logic to decode the the I2C volume control value. See Table 12.

Figure 2. Conventional Driver Output Waveform vs. MAX9670/ MAX9671 Output Waveform.

VDD/2

GND

CONVENTIONAL DRIVER-BIASING SCHEME

GND

-V

DirectDrive BIASING SCHEME

OUT

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

16 ______________________________________________________________________________________

Video Section

The video circuit routes different video formats between the set-top box decoder, the TV SCART connector, and

the VCR SCART connector. It also routes slow-switch and fast-switch control information. See Figure 3.

Figure 3. MAX9670/MAX9671 Video Section Function Diagram

ACTIVITY DETECT

TV_Y/CVBS_IN

VCR_Y/CVBS_IN CLAMP

ENC_Y/CVBS_IN CLAMP

ENC_Y_IN CLAMP

CLAMP

ACTIVITY DETECT

LPF

MUTE

MAX9670/MAX9671

LOAD SENSE

AV = 2V/V

LOAD SENSE

TV_Y/CVBS_OUT

VCR_R/C_IN CLAMP/BIAS

ENC_R/C_IN CLAMP/BIAS

ENC_C_IN CLAMP/BIAS

MUTE

VCR_G_IN CLAMP

ENC_G_IN CLAMP

MUTE

VCR_B_IN CLAMP

ENC_B_IN CLAMP

MUTE

VCRIN_FS

0.7V

TO I2C

AV = 2V/V

LPF

VID

GNDVID

+6V

AV = 2V/V

AV = 1V/V

VCR_Y/CVBS_OUT

TV_R/C_OUT

VCR_R/C_OUT

TV_G_OUT

TV_B_OUT

TVOUT_FS

TV_SS

VCR_SS

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 17

Video Inputs

Whether the incoming video signal is AC-coupled or DC-coupled into the MAX9670/MAX9671 depends upon the origin, format, and voltage range of the video signal. Table 1 below shows the recommended connections. Always AC-couple an external video signal through a 0.1µF capacitor because its voltage is not well defined (see the

Typical Application Circuit

). For example, the video transmitter circuit might have a different ground than the video receiver, thereby level shifting the DC bias. 60Hz power line hum might cause the video signal to change DC bias slowly.

Internal video signals that are between 0 and 1V can be DC-coupled. Most video DACs generate video signals between 0 and 1V because the video DAC sources current into a ground-referenced resistor. For the minority of video DACs that generate video signals between

2.3V and 3.3V because the video DAC sinks current from a V

VID

-referenced resistor, AC-couple the video

signal to the MAX9670/MAX9671.

The MAX9670/MAX9671 restore the DC level of incoming, AC-coupled video signals with either transparent sync-tip clamps or bias circuits. When using an ACcoupled input, the transparent sync-tip clamp automatically clamps the input signal minimum to ground, preventing it from going lower. A small current of 1µA pulls down on the input to prevent an AC-coupled signal from drifting outside the input range of the part. Use sync-tip clamps with CVBS, RGB, and luma signals.

The transparent sync-tip clamp is transparent when the incoming video signal is DC-coupled and at or above ground. Under such conditions, the clamp never activates. Therefore, the outputs of video DACs that generate signals between 0 and 1V can be directly connected to the MAX9670/MAX9671 inputs.

The bias circuit accepts AC-coupled chroma, which is a subcarrier with the color information modulated onto it. The bias voltage of the bias circuits is around 600mV.

ENC_R/C_IN and VCR_R/C_IN can receive either a red video signal or a chroma video signal. Set the input configuration by writing to bits 7 and 3 of the VCR Video Input Control register (08h). See Tables 10 and 16.

The MAX9670/MAX9671 also have video input detection. When activated, activity detect circuits check if sync is present on incoming CVBS signals. If so, then there is a valid video signal. Read bits 2, 3, 4, and 5 of the Video Activity Status register (0Fh) to determine the status of the CVBS inputs. See Table 21.

In high-impedance mode, the inputs to the MAX9670/ MAX9671 do not distort the video signal in case the outputs of the video DAC are also connected to another video circuit such as a high-definition video filter amplifier. See the

SCART Set-Top Box with Analog HD Outputs

section. The inputs in high-impedance mode are biased at V

VID

/3, which is sufficiently above ground so that the ESD diodes never forward biases as the video signal changes. The input resistance is 222kΩ, which presents negligible loading on the video current DAC.

Video Reconstruction Filter

The video DAC outputs of the set-top box decoder chip need to be lowpass-filtered to reject the out-of-band noise. The MAX9670/MAX9671 integrate sixth-order, Butterworth filters. The filter passband (±1dB) is typically 5.5MHz, and the attenuation at 27MHz is 52dB. The filters are suited for standard-definition video.

Video Outputs

The video output amplifiers can both source and sink load current, allowing output loads to be DC- or ACcoupled. The amplifier output stage needs around 300mV of headroom from either supply rail. For video signals with a sync pulse, the sync tip is typically at 300mV, as shown in Figure 4. For a chroma signal, the blank level is typically at 1.5V, as shown in Figure 5.

If the supply voltage is greater than 3.135V (5% below a 3.3V supply), each amplifier can drive two DC-coupled video loads to ground. If the supply is less than

3.135V, each amplifier can drive only one DC-coupled or AC-coupled video load.

The SCART standard allows for video signals to have a superimposed DC component within 0 and 2V. Therefore, most video signals are DC-coupled at the output. In the unlikely event that the video signal needs to be AC-coupled, the coupling capacitors should be 220µF or greater to keep the highpass filter formed by the 37.5Ω equivalent resistance of the video transmission line to a corner frequency of 4.8Hz or below to keep it well below the 25Hz frame rate of the PAL standard.

The CVBS outputs have load sense circuits. If enabled, each load sense circuit checks for a load eight times per second by connecting an internal 15kΩ pullup resistor to the output for 1ms. If the output is pulled up, no load is present. If the output stays low, a load is connected. Read bits 1 and 3 to determine load status. See Table 21.

The selection of video sources that are sent to the TV SCART connector are controlled by bits 0 to 4 of the TV

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

18 ______________________________________________________________________________________

Video Input Control register (06h) while the selection of video sources that are sent to the VCR SCART connector are controlled by bits 0 to 2 of the VCR Video Input Control register (08h). See Tables 10, 14, and 16. The video outputs can be enabled or disabled by bits 2 through 7 of the Output Enable register (0Dh). See Table 18.

Slow Switching

The MAX9670/MAX9671 support the IEC 933-1, Amendment 1, three-level slow switching that selects the aspect ratio for the display (TV). Under I2C control, the MAX9670/MAX9671 set the slow-switching output voltage level. Table 2 shows the valid input levels of the slow-switching signal and the corresponding operating modes of the display device.

Two bidirectional ports are available for slow-switching signals for the TV and VCR. The slow-switching input status is continuously read and stored in the Status register (0Eh). The slow-switching outputs can be set to a logic level or high impedance by writing to the TV Video Output Control register (07h) and the VCR Video Output Control register (09h). When enabled, INT becomes active low if the voltage level changes on TV_SS or VCR_SS. See Tables 10, 15, 17, and 20.

Fast Switching

The fast-switching signal was originally used to switch between CVBS and RGB signals on a pixel-by-pixel basis so that on-screen display (OSD) information could be inserted. Since modern set-top box decoder chips have integrated OSD circuitry, there is no need to create OSD information using the older technique. Now,

the fast-switching signal is just used to switch between CVBS and RGB signal sources.

Set the source of the fast-switching signal by writing to bits 4 and 3 of the TV Video Output Control register (07h). The fast-switching signal to the TV SCART connector can be enabled or disabled by bit 1 of the Output Enable register (0Dh). See Tables 10, 15, and 18.

I2C Serial Interface

The MAX9670/MAX9671 feature an I2C/SMBus™-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9670/ MAX9671 and the master at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9670/ MAX9671 by transmitting a START (S) condition, the proper slave address with the R/W bit set to 0, followed by the register address and then the data word. Each transmit sequence is framed by a START and a STOP (P) condition. Each word transmitted to the MAX9670/MAX9671 is 8 bits long and is followed by an acknowledge clock pulse. A master reads from the MAX9670/MAX9671 by transmitting the slave address with the R/W bit set to 0, the register address of the register to be read, a REPEATED START (Sr) condition, the slave address with the R/W bit set to 1, followed by a series of SCL pulses. The MAX9670/MAX9671 transmit data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or

Figure 4. MAX9670/MAX9671 Video Output with CVBS Signal, Multiburst Video Test Signal Shown

Figure 5. MAX9670/MAX9671 Video Output with Chroma (C) Signal, Multiburst Video Test Signal Shown

MAX9670 fig04

INPUT 500mV/div

OUTPUT 500mV/div

20µs/div

10µs/div

MAX9670 fig05

INPUT 200mV/div

OUTPUT 200mV/div

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 19

REPEATED START (Sr) condition, an acknowledge or a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500Ω, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500Ω, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9670/MAX9671 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the

START and STOP

Conditions

section). SDA and SCL idle high when the

I2C bus is not busy.

START and STOP Conditions

SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START (S) condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 7). A START condition from the master signals the beginning of a transmission to the MAX9670/MAX9671. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition.

Early STOP Conditions

The MAX9670/MAX9671 recognize a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition.

Slave Address

The slave address is defined as the 7 most significant bits (MSBs) followed by the read/write (R/W) bit. Set the R/W bit to 1 to configure the MAX9670/MAX9671 to read mode. Set the R/W bit to 0 to configure the MAX9670/MAX9671 to write mode. The slave address is always the first byte of information sent to the MAX9670/MAX9671 after a START or a REPEATED START condition. The MAX9670/MAX9671 slave address is configurable with DEV_ADDR. Table 3 shows the possible slave addresses for the MAX9670/MAX9671.

Figure 6. I2C Serial-Interface Timing Diagram

Figure 7. START, STOP, and REPEATED START Conditions

SDA

SU, DAT

LOW

SCL

HD, STA

START

CONDITION

HIGH

HD, DAT

SU, STA

REPEATED

START CONDITION

HD, STA

BUF

SU, STO

STOP

CONDITION

START

CONDITION

SSrP

SCL

SDA

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

20 ______________________________________________________________________________________

Acknowledge

The acknowledge bit (ACK) is a clocked 9th bit that the MAX9670/MAX9671 use to handshake receipt of each byte of data when in write mode (see Figure 8). The MAX9670/MAX9671 pull down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when

the MAX9670/MAX9671 are in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9670/MAX9671, followed by a STOP (P) condition.

Write Data Format

A write to the MAX9670/MAX9671 consists of transmitting a START condition, the slave address with the R/W bit set to 0, one data byte to configure the internal register address pointer, one or more data bytes, and a STOP condition. Figure 9 illustrates the proper frame format for writing one byte of data to the MAX9670/MAX9671. Figure 10 illustrates the frame format for writing n bytes of data to the MAX9670/ MAX9671.

The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9670/ MAX9671. The MAX9670/MAX9671 acknowledge receipt of the address byte during the master-generated ninth SCL pulse.

The second byte transmitted from the master configures the MAX9670/MAX9671’s internal register address pointer. The pointer tells the MAX9670/MAX9671 where to write the next byte of data. An acknowledge pulse is sent by the MAX9670/MAX9671 upon receipt of the address pointer data.

Figure 8. Acknowledge

Figure 9. Writing a Byte of Data to the MAX9670/MAX9671

Figure 10. Writing n Bytes of Data to the MAX9670/MAX9671

CLOCK PULSE FOR

ACKNOWLEDGMENT

CONDITION

SCL

START

289

NOT ACKNOWLEDGE

SDA

ACKNOWLEDGE

ACKNOWLEDGE FROM MAX9670/MAX9671

S AA

ACKNOWLEDGE FROM MAX9670/MAX9671

SLAVE ADDRESS

ACKNOWLEDGE FROM MAX9670/MAX9671

R/W

0SLAVE ADDRESS REGISTER ADDRESS DATA BYTE

R/W

ACKNOWLEDGE FROM MAX9670/MAX9671

ACKNOWLEDGE FROM

MAX9670/MAX9671

B1 B0B3 B2B5 B4B7 B6

DATA BYTE 1

1 BYTE

AUTOINCREMENT INTERNAL

1 BYTE

ACKNOWLEDGE FROM

MAX9670/MAX9671

DATA BYTE n

B1 B0B3 B2B5 B4B7 B6

1 BYTE

B1 B0B3 B2B5 B4B7 B6

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 21

The third byte sent to the MAX9670/MAX9671 contains the data that is written to the chosen register. An acknowledge pulse from the MAX9670/MAX9671 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential register address locations within one continuous frame. The master signals the end of transmission by issuing a STOP (P) condition.

Read Data Format

The master presets the address pointer by first sending the MAX9670/MAX9671’s slave address with the R/W bit set to 0 followed by the register address after a START (S) condition. The MAX9670/MAX9671 acknowledges receipt of its slave address and the register address by pulling SDA low during the ninth SCL clock pulse. A REPEATED START (Sr) condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9670/MAX9671 transmits the contents of the specified register. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from the register address location set by the previous transaction and not 00h and subsequent reads autoincrement the address pointer until the next STOP condition. Attempting to read from register

addresses higher than 01h results in repeated reads from a dummy register containing FFh data. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figures 11 and 12 illustrate the frame format for reading data from the MAX9670/MAX9671.

Interrupt Output

When interrupt is enabled in modes 1 and 2, INT, which is an open-drain output, pulls low under the following conditions: slow-switch signals change value, CVBS input signals are detected or disappear, and CVBS output loads are added or removed.

When interrupt is enabled in mode 3, INT pulls low only when the slow-switch signal changes value.

Enable INT by writing a 1 into bit 4 of register 01h. See Table 13.

The interrupt can be cleared by reading register 0Eh and 0Fh.

Applications Information

Audio Inputs

The maximum full-scale audio signal that can be applied to the audio inputs is 0.5V

RMS

biased at ground. The recommended application circuit to attenuate and bias an incoming audio signal is shown in Figure 13.

Figure 11. Reading One Indexed Byte of Data from the MAX9670/MAX9671

Figure 12. Reading n Bytes of Indexed Data from the MAX9670/MAX9671

ACKNOWLEDGE FROM

MAX9670/MAX9671

ACKNOWLEDGE FROM

MAX9670/MAX9671

R/W

ACKNOWLEDGE FROM

MAX9670/MAX9671

ACKNOWLEDGE FROM

MAX9670/MAX9671

REPEATED START

Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE

ACKNOWLEDGE FROM

MAX9670/MAX9671

Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE

ACKNOWLEDGE FROM

MAX9670/MAX9671

R/WREPEATED START

R/W

NOT ACKNOWLEDGE FROM MASTER

1 BYTE

AUTOINCREMENT INTERNAL

1 BYTE

AUTOINCREMENT INTERNAL

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

22 ______________________________________________________________________________________

The audio path has a gain of 4V/V so that the full scale of the audio output signal is 2V

RMS

. If less than 2V

RMS

, full scale is desired at the audio outputs, and the full scale of the audio input signal should be proportionately decreased below 0.5V

RMS

Operating Modes

The MAX9670/MAX9671 has four operating modes, which can be set by writing to bits 6 and 7 of register 10h. See Table 19.

Shutdown

All circuitry is shutdown in the MAX9670/MAX9671 except for the I2C interface, which is designed with static CMOS logic. Except for register 10h, which sets the operating mode, the values in all of the other I2C registers are preserved while entering, during, and leaving shutdown mode.

Standby Mode

In standby mode, the MAX9670/MAX9671 monitor the slow-switch signals and decide whether to loop through the audio/video signals. If the VCR slow switch input has activity (6V or 12V at the input), the audio/video signals are looped through from the VCR SCART to the TV SCART. If the TV slow-switch input has activity, the audio/video signals are looped through from the TV SCART to the VCR SCART. If neither the VCR slowswitch input nor the TV slow switch input show activity, i.e., both inputs are at ground, no signals are looped through. If both the VCR slow-switch input and the TV slow-switch input have activity, the MAX9670/MAX9671

considers this condition to be illegal and does not loop through any signals.

A finite state machine (Figure 14) controls the operation of the MAX9670/MAX9671. State 0 is always the initial state when the MAX9670/MAX9671 enter standby mode. Table 4 shows the values of the I

C registers in state 0. The state machine sets the other I2C registers to the correct values to loop through the audio/video signals in states 1 and 2 (see Tables 5 and 6). When the MAX9670/MAX9671 leaves standby mode, the values in all of the I2C registers except register 10h are preserved so that the operation is not disturbed. For example, if in standby mode, the MAX9670 is looping through the audio/video signals from VCR SCART to TV SCART, and if the microcontroller changes the operating mode from standby mode to full-power mode, the audio/video signals continue to be looped through during and after the mode change. The user does not experience any disruption in audio or video service.

The microcontroller can be turned off in standby mode because the MAX9670/1 operate autonomously. Upon power-up, the default operating mode is standby mode.

Full-Power Mode with Video Input Detection

and Video Load Detection

In this mode, the MAX9670/MAX9671 are fully on. If interrupt is enabled, INT goes active low whenever the slow-switch signal changes; a CVBS signal appears or disappears; or a CVBS load appears or disappears. The microcontroller can decide whether to change the routing configuration or operating mode of the MAX9670/MAX9671.

Full-Power Mode Without Video Input Detection

and Video Load Detection

This mode is similar to the above mode except that video input detection and video load detection are not active. If interrupt is enabled, INT goes active low only when the slow-switch signal changes.

Power Consumption

The quiescent power consumption and average power consumption of the MAX9670/MAX9671 are very low because of 3.3V operation and low-power circuit design. Quiescent power consumption is defined when the MAX9670/MAX9671 are operating without loads and without any audio or video signals. Table 7 shows the quiescent power consumption in all 4 operating modes.

Average power consumption is defined when the MAX9670/MAX9671 drives typical signals into typical loads. Table 6 shows the average power consumption in full-power mode and Table 9 shows the input and output conditions.

Figure 13. Application circuit to connect audio source to audio inputs. The 1µF capacitor connected to the ground-referenced resistors biases the audio signal at ground. The resistors attenuate the audio signal.

STEREO

AUDIO

DACS

*R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53kΩ, 1% DAC = PCM1742: R1 = 5.57kΩ, 1%

1µF

6.65kΩ

R1*

6.65kΩ

R1*

MAX9670

ENC_INL

ENC_INR

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 23

S-Video

The MAX9670/MAX9671 support S-video from the settop box to the TV, set-top box to the VCR, and VCR to the set-top box. S-video was not included in the original SCART specifications but was added afterwards. As a consequence, the luma (Y) signal of S-video shares the same SCART pin as the CVBS signal. Likewise, the chroma (C) signal shares the same SCART pin as the

red signal. The pins that can carry both CVBS and luma have Y/CVBS in their names, and the pins that can carry red and chroma have R/C in their names.

Now, the Y/CVBS signals are full duplex while the R/C signals are half duplex. Therefore, S-video is limited to being half duplex. The MAX9670/MAX9671 have to transmit a chroma signal and receive a chroma signal

Figure 14. Standby mode finite state machine. TV_SS is active when either 6V or 12V are present. VCR_SS is active when either 6V or 12V are present.

TV_SS NOT ACTIVE

VCR_SS NOT ACTIVE

SLOW SWITCH: LISTENING FOR ACTIVITY

STATE 0 SEARCH

AUDIO: INACTIVE VIDEO: INACTIVE

FAST SWITCH: INACTIVE

TV_SS ACTIVE

VCR_SS ACTIVE

TV_SS NOT ACTIVE

VCR_SS ACTIVE

TV_SS ACTIVE

VCR_SS ACTIVE

TV_SS ACTIVE

VCR_SS NOT ACTIVE

TV-TO-VCR

AUDIO: TV TO VCR

VIDEO: TV TO VCR

SLOW SWITCH: TV TO VCR

FAST SWITCH: NOT APPLICABLE

STATE 1

TV_SS NOT ACTIVE

VCR_SS NOT ACTIVE

TV_SS ACTIVE

VCR_SS NOT ACTIVE

TV_SS NOT ACTIVE

VCR_SS NOT ACTIVE

SLOW SWITCH: VCR TO TV

FAST SWITCH: VCR TO TV

TV_SS NOT ACTIVE

VCR_SS ACTIVE

TV_SS NOT ACTIVE

VCR_SS ACTIVE

STATE 2

VCR-TO-TV

AUDIO: VCR TO TV VIDEO: VCR TO TV

TV_SS ACTIVE

VCR_SS NOT ACTIVE

TV_SS ACTIVE

VCR_SS ACTIVE

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

24 ______________________________________________________________________________________

on the same SCART pin, but not at the same time. The 75Ω resistor connected to VCR_R/C_OUT must act as a back termination resistor when the MAX9670/MAX9671 is transmitting chroma signal and as an input termination resistor when it is receiving a chroma signal. Figure 15 shows how the MAX9670/MAX9671 transmits a chroma signal to the VCR SCART connector while Figure 16 shows how the MAX9670/MAX9671 receives a chroma from the VCR SCART connector.

Write a 0 into bit 2 of register 09h to open the pulldown switch at VCR_R/C_OUT. To close the pulldown switch, write a 0 into bit 6 of register 0Dh to turn off the output amplifier, and then write a 1 into register 09h. See Tables 17 and 18.

Figure 15. Gain-of-2 amplifier on VCR_R/C_OUT outputs chroma signal to VCR SCART connector. Notice that the pulldown switch on VCR_R/C_OUT is open.

Figure 16. VCR_R/C_IN receives chroma signal from VCR SCART connector. Notice that the pulldown switch on VCR_R/C_OUT is closed and that the gain-of-2 amplifier is off. The chroma signal from VCR SCART is looped through to the TV SCART in the above configuration.

0.1µF VCR_R/C_IN

ENC_R/C_IN

ENC_C_IN

BIAS

LPF

AV = 2V/V

TV_R/C_OUT

75Ω

SCART

75Ω

VCR

SCART

MAX9670/MAX9671

AV = 2V/V

VCR_R/C_OUT

0.1µF VCR_R/C_IN

ENC_R/C_IN

ENC_C_IN

BIAS

LPF

MAX9670/MAX9671

AV = 2V/V

OFF

TV_R/C_OUT

VCR_R/C_OUT

75Ω

SCART

VCR

SCART

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 25

Interfacing to an RF Modulator

If the set-top box modulates CVBS and mono audio onto an RF carrier (for example, channel 3), a simple application circuit can provide the needed signals (see Figure 17). 10kΩ resistor summer circuit between TV_OUTR and TV_OUTL creates the mono audio signal. The resistor-divider to ground on TV_Y/CVBS_OUT creates a video signal with normal amplitude. The unique feature of the MAX9670/MAX9671 that facilitates this application circuit is that the audio and video output amplifiers of the MAX9670/MAX9671 can drive multiple loads if V

AUD

and V

VID

are both greater than

3.135V.

Floating-Chassis Discharge Protection

and ESD

Some set-top boxes have a floating chassis problem in which the chassis is not connected to earth ground. As a result, the chassis can charge up to 500V. When a SCART cable is connected to the SCART connector, the charged chassis can discharge through a signal pin. The equivalent circuit is a 2200pF capacitor charged to 311V connected through less than 0.1Ω to a signal pin. The MAX9670/MAX9671 are soldered on the PCB when it experiences such a discharge. Therefore, the current spike flows through both external and internal ESD protection devices and is absorbed by the supply bypass capacitors, which have high capacitance and low ESR.

To better protect the MAX9670/MAX9671 against excess voltages during the cable discharge condition or ESD events, add series resistors to all inputs and outputs to the SCART connector if series resistors are not already present in the application circuit. Also, add external ESD protection diodes (for example, BAV99) on all inputs and outputs to the SCART connector.

SCART Set-Top Box

with Analog HD Outputs

In set-top boxes with SCART connectors and cinch connectors for high-definition YPbPr outputs, a triplevideo DAC usually outputs either standard-definition RGB signals that are routed to the MAX9670/MAX9671 or high-definition YPbPr signals that are routed through a high-definition filter amplifier like the MAX9653 (see Figure 19). The set-top box devices have a limited number of video DACs, and hence, one bank of triple-video DACs switches video format depending upon whether standard-definition RGB or high-definition YPbPr signals are required.

When RGB signals are desired, the high-definition filter amplifier should be turned off so that the RGB signals do not appear on the YPbPr connectors. The MAX9653/MAX9654 are well-suited for this application because their video inputs are in high-impedance mode when in shutdown.

Figure 17. Application Circuit to Connect CVBS and Mono Audio from TV SCART to RF Modulator

TV_OUTR

10kΩ

MAX9670/MAX9671

TV_OUTL

TV_Y/CVBS_OUT

MONO AUDIO

10kΩ

75Ω OR GREATER

75Ω

SCART

75Ω OR GREATER

MODULATOR

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

26 ______________________________________________________________________________________

Figure 18. Application Circuit to Connect Series Resistors and External ESD Protection Diodes at MAX9670/MAX9671 Outputs

+3.3 V

STB CHIP

MICRO-

CONTROLLER

VIDEO ENCODER

STEREO

AUDIO DACS

*R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53kΩ ±1% DAC = PCM1742: R1 = 5.57kΩ ±1%

75Ω

1µF

6.65kΩ

R1*

1µF

6.65kΩ

R1*

12V 3.3V

0.1µF

SDA

SCL

INT

DEV_ADDR

ENC_Y/CVBS_IN

ENC_R/C_IN

ENC_G_IN

ENC_B_IN

ENC_Y_IN

ENC_C_IN

ENC_INL

ENC_INR

1µF

MAX9670 MAX9671

C1NC1P CPVSS

VID

3.3V

0.1µF

AUD

(MAX9671 ONLY)

TV_OUTR

TV_OUTL

TV_B_OUT

TV_G_OUT

TV_R/C_OUT

TVOUT_FS

TV_Y/CVBS_OUT

TV_Y/CVBS_IN

VCR_OUTR

VCR_INR

VCR_OUTL

VCR_INL

VCR_B_IN

VCR_G_IN

VCR_R/C_IN

VCR_R/C_OUT

VCRIN_FS

VCR_Y/CVBS_OUT

VCR_Y/CVBS_IN

1µF

TV_INL

TV_INR

TV_SS

GNDVID

VCR_SS

0.1µF

7.68kΩ

2.55kΩ

7.68kΩ

2.55kΩ

75Ω

7.68kΩ

2.55kΩ

75Ω

7.68kΩ

2.55kΩ

75Ω

GNDVID

75Ω

AUD

1µF

CPVSS

AUD

1µF

AUD

CPVSS

AUD

CPVSS

GNDVID

1µF

VID

GNDVID

VID

GNDVID

SCART

VCR

SCART

GNDVID

VID

0.1µF

GNDVID

CPVSS

VID

GNDVID

VID

0.1µF

GNDVID

75Ω

AUD

CPVSS

AUD

CPVSS

0.1µF

75Ω

VID

0.1µF

75Ω

VID

GNDVID

VID

0.1µF

75Ω

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 27

Similarly, when YPbPr signals are desired, ENC_R/C_IN, ENC_G_IN, and ENC_B_IN of the MAX9670/MAX9671 should be set to high-impedance mode by setting bit 4 in register 08h to high if those video inputs are AC-coupled. The high-impedance mode has higher priority whether ENC_R/C_IN is in sync-tip clamp or bias circuit mode (set by bit 3 in register 08h). If ENC_R/C_IN, ENC_G_IN, and ENC_B_IN are DC-coupled, the inputs should be left in sync-tip clamp mode. The RGB outputs of the MAX9670 should be muted or shut down.

In either case, the inactive device should not distort the video signals generated by the DACs.

Power-Supply Bypassing

The MAX9670/MAX9671 feature single 3.3V and 12V supply operation and require no negative supply. The 12V supply V12is for the SCART switching function. For V12, place a 0.1µF bypass capacitor as close as possible. Connect all V

AUD

pins together to 3.3V and bypass

with a 10µF electrolytic capacitor in parallel with a

0.1µF ceramic capacitor to audio ground. Bypass each V

VID

to video ground with a 0.1µF ceramic capacitor.

Using a Digital Supply

The MAX9670/MAX9671 are designed to operate from noisy digital supplies. The high PSRR (49dB at 100kHz) allows the MAX9670/MAX9671 to reject the noise from the digital power supplies (see the

Typical Operating

Characteristics

). If the digital power supply is very noisy

and stripes appear on the television screen, increase the supply bypass capacitance. An additional, smaller capacitor in parallel with the main bypass capacitor can reduce digital supply noise because the smaller capacitor has lower equivalent series resistance (ESR) and equivalent series inductance (ESL).

Layout and Grounding

For optimal performance, use controlled-impedance traces for video signal paths and place input termination resistors and output back-termination resistors close to the MAX9670/MAX9671. Avoid routing video traces parallel to high-speed data lines.

The MAX9670/MAX9671 provide separate ground connections for video and audio supplies. For best performance, use separate ground planes for each of the ground returns and connect all ground planes together at a single point. See the MAX9670/MAX9671 evaluation kit for a proven circuit board layout example.

If the MAX9670/MAX9671 are mounted using flow soldering or wave soldering, the ground via(s) for the EP pad should have a finished hole size of at least 14mils to insure adequate wicking of soldering onto the exposed pad. If the MAX9670/MAX9671 are mounted using solder mask technique, the via requirement does not apply. In either case, a good connection between the exposed pad and ground is required to minimize noise from coupling onto the outputs.

Figure 19. Triple DAC is connected to both a MAX9670 and a MAX9653/MAX9654 high-definition video-filter amplifier. (A) The MAX9670/MAX9671 are transmitting standard-definition RGB signals while the MAX9653/MAX9654 are in shutdown mode. (B) The MAX9670/MAX9671 are not transmitting RGB signals, but the MAX9653/MAX9654 are transmitting high-definition YPbPr signals.

0.1µF

3.3V

MAX9670/MAX9671MAX9670/MAX9671

TV_R/C_OUT

ENC_R/C_IN

ENC_G_IN

ENC_B_IN

INPUTS SET TO HIGH IMPEDANCEINPUTS SET TO SYNC-TIP CLAMP

MAX9653 MAX9654

YIN

PBIN

PRIN

SHDN

(B)

TV_G_OUT

TV_B_OUT

YOUT

PBOUT

PROUT

75Ω

SCART CONNECTOR

YPbPr OUTPUTS

SET-TOP BOX

CHIP

DAC

0.1µF

3.3V

0.1µF

(A)

ENC_R/C_IN

ENC_G_IN

ENC_B_IN

YIN

PBIN

PRIN

SHDN

MAX9653 MAX9654

OFF

TV_R/C_OUT

TV_G_OUT

TV_B_OUT

YOUT

PBOUT

PROUT

75Ω

SCART

75Ω

CONNECTOR

YPbPr OUTPUTS

SET-TOP BOX

CHIP

DAC

3.3V

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

28 ______________________________________________________________________________________

Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit Configuration*

Use a 0.1µF capacitor to AC-couple a video signal into the MAX9670/MAX9671.

Table 2. Slow-Switching Modes

VIDEO ORIGIN FORMAT VOLTAGE RANGE COUPLING INPUT CIRCUIT CONFIGURATION

External CVBS Unknown AC Transparent sync-tip clamp

External RGB Unknown AC Transparent sync-tip clamp

External Y Unknown AC Transparent sync-tip clamp

External C Unknown AC Bias circuit

Internal CVBS 0 to 1V DC Transparent sync-tip clamp

Internal R, G, B 0 to 1V DC Transparent sync-tip clamp

Internal Y, C 0 to 1V DC Transparent sync-tip clamp

Internal Y, Pb, Pr 0 to 1V DC Transparent sync-tip clamp

Internal CVBS 2.3V to 3.3V AC Transparent sync-tip clamp

Internal R, G, B 2.3V to 3.3V AC Transparent sync-tip clamp

Internal Y 2.3V to 3.3V AC Transparent sync-tip clamp

Internal C 2.3V to 3.3V AC Bias circuit

SLOW-SWITCHING

SIGNAL VOLTAGE

(V)

0 to 2

4.5 to 7.0

9.5 to 12.6

Display device uses an internal source such as a built-in tuner to provide a video signal.

Display device uses a video signal from the SCART connector and sets the display to 16:9 aspect ratio.

Display device uses a signal from the SCART connector and sets the display to 4:3 aspect ratio.

MODE

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 29

Table 3. Slave Address

Table 4. I2C Register Values in State 0*

Table 5. I2C Register Values in State 1*

Table 6. I2C Register Values in State 2*

u indicates that the bit is unchanged from its previous state.

u indicates that the bit is unchanged from its previous state;

MM = Register 0Eh (bit 0, bit 1)

u indicates that the bit is unchanged from its previous state;

NN = Register 0Eh (bit 3, bit 2)

DEV_ADDR B7 B6 B5 B4 B3 B2 B1 B0

GNDVID 1 0 01010 R/W 94h 95h

VID

SCL 1001100 R/W 98h 99h SDA 1001101 R/W 9Ah 9Bh

(hexadecimal)

00h uuuu uuuu

01h uuuu 1111

06h uuuu uuuu

07h uuuu uu10

08h uuuu uuuu

09h uuuu u010

0Dh 0000 000u

1001011 R/W 96h 97h

VALUE (binary)

(hexadecimal)

WRITE ADDRESS

(hex)

00h uuuu uuu0

01h uuuu 1011

06h uuuu uuuu

07h uuu0 0u10

08h uuuu u011

09h uuuu u0MM

0Dh 1100 001u

READ ADDRESS

(hex)

VALUE (binary)

(hexadecimal)

00h uuuu uuu0

01h uuuu 1101

06h uuu0 1010

07h uuu0 0uNN

08h uuuu uuuu

09h uuuu u110

0Dh 0011 111u

VALUE (binary)

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

30 ______________________________________________________________________________________

Table 7. Quiescent Power Consumption

Table 8. Average Power Consumption

Table 9. Conditions for Average Power Consumption Measurement

OPERATING MODE

Shutdown 0.13

Standby mode with no video activity (i.e., TV slow-switch and VCR slow-switch inputs are at ground). Standby mode is the power-on default.

Full-power mode with input video detection and video load detection active.

Full-power mode without input video detection and video load detection active.

POWER CONSUMPTION

(mW)

2.83

OPERATING MODE

Full-power mode with input video detection and video load detection active.

Full-power mode without input video detection and video load detection active.

PIN (MAX9670) NAME TYPE SIGNAL LOAD

9 ENC_INL Input 0.25V

10 ENC_INR Input 0.25V

11 VCR_INL Input None N/A

12 VCR_INR Input None N/A

13 TV_OUTL Output 1V

14 VCR_OUTL Output 1V

15 VCR_OUTR Output 1V

16 TV_OUTR Output 1V

17 TV_SS Output 12V 10kΩ to ground

18 V

19 VCR_SS Input 0 N/A

20 TVOUT_FS Output 3.3V 150Ω to ground

21 VCRIN_FS Input 0 N/A

22 ENC_B_IN Input 50% flat field N/A

23 ENC_G_IN Input 50% flat field N/A

24 VCR_B_IN Input None N/A

25 VCR_G_IN Input None N/A

26 TV_B_OUT Output 50% flat field 150Ω to ground

27 TV_G_OUT Output 50% flat field 150Ω to ground

28 GNDVID Supply 0 N/A

29 VCR_R/C_IN Input None N/A

30 V

AUD

VID

Supply 3.3V N/A

RMS

Supply 12V N/A

Supply 3.3V N/A

POWER CONSUMPTION

(mW)

300

, 1kHz N/A

RMS

, 1kHz N/A

RMS

, 1kHz 10kΩ to ground

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 31

Table 9. Conditions for Average Power Consumption Measurement (continued)

Table 10. Data Format for Write Mode

PIN (MAX9670) NAME TYPE SIGNAL LOAD

31 ENC_C_IN Input None N/A

32 ENC_R/C_IN Input 50% flat field N/A

33 TV_R/C_OUT Output 50% flat field 150Ω to ground

34 VCR_R/C_OUT Output 50% flat field 150Ω to ground

35 VCR_Y/CVBS_OUT Output 50% flat field 150Ω to ground

36 TV_Y/CVBS_OUT Output 50% flat field 150Ω to ground

37 VCR_Y/CVBS_IN Input None N/A

38 TV_Y/CVBS_IN Input None N/A

39 ENC_Y_IN Input None N/A

40 ENC_Y/CVBS_IN Input 50% flat field N/A

ADDRESS (hex)

00h Not used TV ZCD TV volume control

01h Not used

02h Not used 03h Not used 04h Not used 05h Not used 06h Not used TV G and B video switch TV video switch 07h Not used Set TV fast switching Not used Set TV slow switching

08h

09h Not used

0Ah Not used 0Bh Not used

0Ch Not used

0Dh

10h Operating mode Not used

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

VCR_R/C_IN

clamp

VCR_Y/

CVBS_OUT

enable

VCR_R/

C_OUT

enable

Not used

TV_R/

C_OUT

enable

Interrupt

enable

ENC R/G/B

high-

impedance

bias

TV_G_OUT

enable

VCR audio selection TV audio selection

ENC_R/C_IN

clamp

TV_B_OUT

enable

VCR_R/C_OUT

CVBS_OUT

enable

ground

TV_Y/

VCR video switch

Set VCR slow

TVOUT_FS

enable

TV audio

output mute

switching

Not used

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

32 ______________________________________________________________________________________

Table 11. Data Format for Read Mode

Table 12. Register 00H: Audio Control

Table 13. Register 01H: TV Audio

ADDRESS (hex)

0Eh Not used

0Fh Not used

DESCRIPTION

TV Audio Mute

TV Volume Control

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

Power-on

reset

76543210

. . .

Not used

BIT

. . .

ENC_Y/

CVBS_IN

input video

detection

. . .

ENC_Y_IN

input video

detection

0 0 0 0 0 0dB gain (power-on default)

0 0 0 0 1 -2dB gain

0 0 0 1 0 -4dB gain

0 0 0 1 1 -6dB gain

0 0 1 0 0 -8dB gain

0 0 1 0 1 -10dB gain

. . .

VCR slow-switch input

status

VCR CVBS output load

0Off

1 On (power-on default)

. . .

VCR CVBS input video

detection

. . .

TV slow switch input

TV CVBS

output load

COMMENTS

. . .

status

TV CVBS

input video

detection

1 1 1 1 0 -60dB gain

1 1 1 1 1 -62dB gain

TV Zero-Crossing Detector

0Off

1 On (power-on default)

DESCRIPTION

Input Source for TV Audio

Input Source for VCR Audio

Interrupt Enable

76543210

BIT

0 0 Encoder audio

0 1 VCR audio

1 0 TV audio (MAX9671 only)

1 1 Mute (power-on default)

0 0 Encoder audio

0 1 VCR audio

1 0 TV audio (MAX9671 only)

1 1 Mute (power-on default)

0 Disabled (power-on default)

1 Enabled

COMMENTS

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 33

Table 14. Register 06H: TV Video Input Control

Table 15. Register 07H: TV Video Output Control

DESCRIPTION

Input Sources for TV Video

Input Sources for TV_G_OUT and TV_B_OUT

76543210

BIT

0 0 ENC_G_IN ENC_B_IN

0 1 VCR_G_IN VCR_B_IN

1 0 Mute Mute

DESCRIPTION

Set TV Slow Switching

Set TV Fast Switching

76543210

BIT

0 0 GNDVID (power-on default)

0 1 Not used

1 0 Same level as VCR_FB_IN

11 V

COMMENTS

TV_Y/CVBS_OUT TV_R/C_OUT

0 0 0 ENC_Y/CVBS_IN ENC_R/C_IN

0 0 1 ENC_Y_IN ENC_C_IN

0 1 0 VCR_Y/CVBS_IN VCR_R/C_IN

0 1 1 TV_Y/CVBS_IN

1 0 0 Not used Not used

1 0 1 Mute Mute

1 1 0 Mute Mute

111

0 0 Low (< 2V) internal source

1 0 High impedance (power-on default)

Mute (power-on

default)

TV_G_OUT TV_B_OUT

Mute (power-on

default)

COMMENTS

Medium (4.5V to 7V); external SCART source with 16:9 aspect ratio

High (> 9.5V); external SCART source with 4:3 aspect ratio

VID

Mute (power-on

default)

Mute (power-on

default)

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

34 ______________________________________________________________________________________

Table 16. Register 08H: ENC and VCR Video Input/Output Control

DESCRIPTION

Input Sources for VCR Video

ENC_R/C_IN Clamp/Bias

ENC R/C, G, and B inputs high-impedance bias (in HD application)

76543210

BIT

VCR_Y/CVBS_OUT VCR_R/C_OUT

0 0 0 ENC_Y/CVBS_IN ENC_R/C_IN

0 0 1 ENC_Y_IN ENC_C_IN

0 1 0 VCR_Y/CVBS_IN VCR_R/C_IN

0 1 1 TV_Y/CVBS_IN Mute

1 0 0 Not used Not used

1 0 1 Mute Mute

1 1 0 Mute Mute

111

1 Chrominance bias applied at input

Mute (power-on default)

DC restore clamp active at input (power-on default)

High-impedance bias off (power-on default)

Biases the R/C, G, and B inputs to high impedance (overwrites the ENC_R/C_IN clamp and bias bit)

COMMENTS

Mute (power-on default)

VCR_R/C_IN Clamp/Bias

1 Chrominance bias applied at input

DC restore clamp active at input (power-on default)

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 35

Table 17. Register 09H: VCR Video Output Control

Table 18. Register 0DH: Output Enable

DESCRIPTION

Set VCR Function Switching

VCR_R/C_OUT Ground

76543210

BIT

DESCRIPTION

TVOUT_FS Enable

TV_Y/CVBS_OUT Enable

TV_B_OUT Enable

TV_G_OUT Enable

TV_R/C_OUT Enable

VCR_R/C_OUT Enable

VCR_Y/CVBS_OUT Enable

76543210

0 Off (power-on default)

1On

0 Off (power-on default)

1On

BIT

0 Off (power-on default)

1On

0 Off (power-on default)

1On

0 Off (power-on default)

1On

COMMENTS

0 0 Low (< 2V) internal source

1 0 High impedance (power-on default)

0 Off (power-on default)

1On

0 Off (power-on default)

1On

Medium (4.5V to 7V); external SCART source with 16:9 aspect ratio

High (> 9.5V); external SCART source with 4:3 aspect ratio

Normal operation; pulldown on VCR_R/C_OUT is off (power-on default)

Ground; pulldown on VCR_R/C_OUT is on; the output amplifier driving VCR_R/C_OUT is off

COMMENTS

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

36 ______________________________________________________________________________________

Table 19. Register 10H: Operating Modes

Table 20. Register 0EH: Status

DESCRIPTION

Operating Mode

76543210

0 0 Shutdown

BIT

COMMENTS

Standby mode (power-on default). Input video detection circuits are active. Audio circuitry is off unless video is detected. Once slow switch is detected, the signal paths between the VCR and TV SCART are connected.

Full-power mode with input video detection and video-load detection active.

Full-power mode without input video detection and video-load detection active.

DESCRIPTION

TV Slow-Switching Input Status

VCR Slow-Switching Input Status

Power-On Reset

BIT

76543210

0 0 0 to 2V; internal source

1 0 Not used

0 0 0 to 2V; internal source

1 0 Not used

COMMENTS

4.5V to 7V; external source with 16:9 aspect ratio

9.5V to 12.6V; external source with 4:3 aspect ratio

4.5V to 7V; external source with 16:9 aspect ratio

9.5V to 12.6V; external source with 4:3 aspect ratio

is too low for digital logic to

VID

operate

is high enough for digital logic to

VID

operate

The temperature is below the thermal shutdown limit

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 37

Table 21. Register 0Fh: Video Activity Status

DESCRIPTION

TV CVBS Input Video Detection

TV CVBS Output Load

VCR CVBS Input Video Detection

VCR CVBS Output Load

ENC_Y/CVBS Input Video Detection

ENC_Y_IN Input Video Detection

76543210

0 No video detected.

1 Video detected.

BIT

0 No video detected.

1 Video detected.

0 No video detected.

1 Video detected.

0 No video detected.

1 Video detected.

0 No load connected.

1 Load connected.

0 No video detected.

1 Video detected.

COMMENTS

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

38 ______________________________________________________________________________________

Typical Application Circuit

12V 3.3V

3.3V

+3.3 V

STB CHIP

MICRO-

CONTROLLER

VIDEO ENCODER

STEREO

AUDIO DACS

*R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53kΩ ±1% DAC = PCM1742: R1 = 5.57kΩ ±1%

75Ω

1µF

6.65kΩ

R1*

1µF

6.65kΩ

R1*

SDA

SCL

INT

DEV_ADDR

ENC_Y/CVBS_IN

ENC_R/C_IN

ENC_G_IN

ENC_B_IN

ENC_Y_IN

ENC_C_IN

ENC_INL

ENC_INR

1µF

0.1µF

C1NC1P CPVSS

VID

MAX9670 MAX9671

1µF

0.1µF

AUD

TV_INL

(MAX9671 ONLY)

TV_INR

(MAX9671 ONLY)

TV_OUTR

TV_OUTL

TV_SS

TV_B_OUT

TV_G_OUT

TV_R/C_OUT

TVOUT_FS

TV_Y/CVBS_OUT

TV_Y/CVBS_IN

GNDVID

VCR_OUTR

VCR_INR

VCR_OUTL

VCR_INL

VCR_SS

VCR_B_IN

VCR_G_IN

VCR_R/C_IN

VCR_R/C_OUT

VCRIN_FS

VCR_Y/CVBS_OUT

VCR_Y/CVBS_IN

0.1µF

7.68kΩ

2.55kΩ

7.68kΩ

2.55kΩ

75Ω

7.68kΩ

2.55kΩ

75Ω

7.68kΩ

2.55kΩ

75Ω

SCART

1µF

VCR

SCART

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 39

Pin Configurations

Chip Information

PROCESS: BiCMOS

TOP VIEW

ENC_C_IN

ENC_R/C_IN

TV_R/C_OUT

VCR_R/C_OUT

VCR _Y/CVBS_OUT

TV_Y/CVBS_OUT

VCR_Y/CVBS_IN

TV_Y/CVBS_IN

ENC_Y_IN

ENC_Y/CVBS_IN

EP* = EXPOSED PAD

TOP VIEW

VID

1 2

SDA

TV_G_OUT

GNDVID

VCR_R/C_IN

TV_B_OUT

27282930 26 24 23 22

MAX9670

4567

INT

SCL

DEV_ADDR

40 TQFN

AUD

VCR_G_IN

C1P

VCR_B_IN

ENC_G_IN

*EP

8910

C1N

CPVSS

VCRIN_FS

ENC_B_IN

ENC_INL

ENC_INR

TVOUT_FS

VCR_SS

TV_SS

TV_OUTR

VCR_OUTR

VCR_OUTL

TV_OUTL

VCR_INR

VCR_INL

ENC_C_IN

ENC_R/C_IN

TV_R/C_OUT

VCR_R/C_OUT

VCR_Y/CVBS_OUT

TV _Y/CVBS_OUT

VCR_Y/CVBS_IN

TV_Y/CVBS_IN

ENC_Y_IN

ENC_Y/CVBS_IN

N.C.

EP* = EXPOSED PAD

VID

GNDVID

TV_G_OUT

TV_B_OUT

MAX9671

INT

44 TQFN

DEV_ADDR

AUD

VCR_G_IN

C1P

VCR_R/C_IN

3332313029282726252423

123456789

SCL

SDA

VCR_B_IN

ENC_G_IN

C1N

CPVSS

ENC_B_IN

VCRIN_FS

*EP

ENC_INL

ENC_INR

N.C.

TV_INL

TVOUT_FS VCR_SS V

TV_SS TV_OUTR VCR_OUTR VCR_OUTL TV_OUTL VCR_INR VCR_INL TV_INR

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

40 ______________________________________________________________________________________

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

40 TQFN T4066+3

21-0141

44 TQFN T4477+2

21-0144

QFN THIN.EPS

MAX9670/MAX9671

Low-Power Audio/Video Switch with Audio

Volume Control for Dual SCART Connectors

______________________________________________________________________________________ 41

Package Information (continued)

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

Package Information (continued)

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors

MAX9670/MAX9671

Rainbow Electronics MAX9671 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual