Rainbow Electronics MAX9489 User Manual

General Description

The MAX9489 clock generator provides multiple clock outputs, ideal for network routers. The MAX9489 provides 15 buffered clock outputs, each independently programmable to any of 10 individual frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz,

62.5MHz, 50MHz, 33MHz, or 25MHz. All of the outputs are single-ended LVCMOS. The MAX9489 is controlled through its I2C™ interface.

At power-up, the frequency of output CLK1 is set by the tri-level input SEL to 100MHz, 125MHz, or 133MHz, while all other outputs are logic low. All outputs are then programmable to any available frequency through the I2C interface. Additionally, all output frequencies are adjustable up or down, by a margin of 5% or 10%, through the I

C interface.

The MAX9489 requires a 25MHz reference that can be either a crystal or an external clock signal. The MAX9489 requires a +3.0V to +3.6V power supply and is available in a 32-pin thin QFN package with an exposed pad for heat removal.

Applications

Network Routers

Telecom/Networking Equipment

Storage Area Networks/Network Attached Storage

Features

♦ 15 LVCMOS Outputs with 10 Independently

Programmable Frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz, 33MHz, and 25MHz

♦ 25MHz Crystal or Clock Input Reference

♦ Programmable Through I

C Interface

♦ Programmable Output Frequency Margin of ±5%

or ±10%

♦ Pin-Selectable Power-Up Frequency for CLK1

Output: 100MHz, 125MHz, or 133MHz

♦ Low Output Period Jitter: < 48ps

RMS

♦ Output-to-Output Skew < 200ps

♦ Available in 32-Lead, 5mm x 5mm x 0.8mm,

Thin QFN Package

♦ Operates from +3.0V to +3.6V Power Supply

♦ Power Dissipation 450mW (typ)

♦ Extended Temperature Range: -40°C to +85°C

MAX9489

Multiple-Output Network Clock Generator

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3385; Rev 0; 8/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration

MAX9489

25MHz

10pF

SDA

0.1µF

SCL

SA0

SA1

SEL

AGND

GND

CLK15

CLK1

+3.3V +3.3V

SERIAL

INTERFACE

CLOCK OUTPUTS

0.1µF x 5

Typical Operating Circuit

I2C is a trademark of Philips Corp. Purchase of I

C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I

C Patent Rights to use these compo-

nents in an I

C system, provided that the system conforms to the

C Standard Specification as defined by Philips.

*EP = Exposed pad.

TOP VIEW

SA131SA030GND29V

CLK1527CLK1426CLK13

PART TEMP RANGE PIN-PACKAGE

MAX9489ETJ -40°C to +85°C

32 Thin QFN-EP* 5mm x 5mm x 0.8mm

GND 1

SCL

SDA

SEL

AGND

MAX9489

EXPOSED PAD (GND)

CLK413CLK514CLK6

CLK19CLK210CLK3

THIN QFN-EP

CLK12

CLK11

CLK10

CLK9

CLK8

CLK7

MAX9489

Multiple-Output Network Clock Generator

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VDD= AVDD= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= AVDD= +3.3V, TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND ..............................................…….….-0.3V to +4.0V

AGND to GND .............................................……...-0.3V to +0.3V

All Other Pins to GND.................................-0.3V to (V

+ 0.3V)

Short-Circuit Duration for all CLK_ Outputs ...............Continuous

Continuous Power Dissipation (T

= +70°C)

32-Pin Thin QFN (derate 21.3mW/°C above +70°C) ....1702mW

Storage Temperature Range .............................-65°C to +150°C

Maximum Junction Temperature .....................................+150°C

Operating Temperature Range ...........................-40°C to +85°C

ESD Rating (Human Body Model) .......................................±2kV

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLOCK INPUT (X1)

Input High Level V

Input Low Level V

Input Current I

CLOCK OUTPUTS (CLK_)

Output High Level V

Output Low Level V

Output Short-Circuit Current I

Output Capacitance C

TRI-LEVEL INPUTS (SEL, SA0, SA1)

Input High Level V

Input Low Level V

Input Open Level V

Input Current I

SERIAL INTERFACE (SCL, SDA) (Note 3)

Input High Level V

Input Low Level V

Input leakage Current IIH, I

Low-Level Output V

Input Capacitance Ci (Note 2) 10 pF

IL1

IL2

IH1

IL1

, I

IH1 VX

IH2

IL2

IO2

, I

IH2

_ = 0 to V

IOH = -100µA

IOH = -4mA 2.4

IOH = -8mA 2.1

IOL = 100µA 0.2

IOL = 4mA 0.4

IOL = 8mA 0.75

CLK_ = VDD or GND 45 mA

(Note 2) 5 pF

= 0 or V

IL2

= 4mA 0 0.4 V

SINK

2.0 V

0.8 V

-5 +5 µA

0.2

2.5 V

0.8 V

1.35 1.90 V

IH2

= V

-10 +10 µA

0.7 x V

0.3 x V

-1 +1 µA

MAX9489

Multiple-Output Network Clock Generator

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VDD= AVDD= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= AVDD= +3.3V, TA= +25°C.) (Note 1)

AC ELECTRICAL CHARACTERISTICS

(VDD= AVDD= +3.0V to +3.6V, CL= 10pF, unless otherwise noted. Typical values are at VDD= AVDD= +3.3V, TA= +25°C, with all CLK_ outputs at 133MHz.) (Note 2)

POWER SUPPLIES

Digital Power-Supply Voltage V

Analog Power-Supply Voltage AV

Total Supply Current C L = 10p f ( w i th al l C LK_ outp uts at 133M H z) 134 160 mA

Total Power-Down Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

All clock registers = 0x00 38 47 mA

3.0 3.6 V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OUTPUTS (CLK_)

Crystal Frequency Tolerance ∆f

Output-to-Output Skew t

Rise Time t

Fall Time t

Duty Cycle 40 60 %

Output Period Jitter J

Power-Up Time t

PLL Lockup Time t

Margin Accuracy Select ±5% or ±10% margin -1 +1 %

SKO

Lock

Any two CLK_ outputs 200 ps

20% VDD to 80% V

80% VDD to 20% V

RMS 53 ps

VDD > 2.8V to PLL lock 2 ms

PLL dividing ratio set to PLL lock 20 µs

-50 +50 ppm

1.8 2.5 ns

MAX9489

Multiple-Output Network Clock Generator

4 _______________________________________________________________________________________

Note 1: All DC parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design.

Note 3: No high output level is specified but only the output resistance to the bus. For I

C, the high-level voltage is provided by

pullup resistors on the bus.

Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V

of the SCL signal) to bridge

the undefined region of SCL’s falling edge.

Note 5: C

= total capacitance of one bus line in pF. tRand tFmeasured between 0.3(VDD) and 0.7(VDD).

Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

SERIAL INTERFACE TIMING

(VDD= AVDD= +3.3V, TA= -40°C to +85°C.) (Note 1, Figure 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Serial Clock f

Bus Free Time Between STOP and START Conditions

Hold Time, Repeated START Condition

Repeated START Condition Setup Time

STOP Condition Setup Time t

Data Hold Time Master t

Data Hold Time Slave t

Data Setup Time t

SCL Clock Low Period t

SCL Clock High Period t

Rise Time of SDA and SCL, Receiving

Fall Time of SDA and SCL, Receiving

Fall Time of SDA, Transmitting t

Pulse Width of Spike Suppressed t

Capacitive Load for Each Bus Line

SCL

BUF

HD,STA

SU,STA

SU,STO

HD,DAT

SU,DAT

LOW

HIGH

F,TX

1.3 µs

0.6 µs

(Note 4) 15 900 ns

100 ns

1.3 µs

0.7 µs

(Notes 2, 5)

(Notes 2, 6) 0 50 ns

(Note 2) 400 pF

20 +

0.1C

20 +

0.1C

20 +

0.1C

400 kHz

300 ns

250 ns

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