Rainbow Electronics MAX9452 User Manual

19-0547; Rev 0; 5/06

High-Precision Clock Generators

with Integrated VCXO

General Description

The MAX9450/MAX9451/MAX9452 clock generators provide high-precision clocks for timing in SONET/SDH systems or Gigabit Ethernet systems. The MAX9450/ MAX9451/MAX9452 can also provide clocks for the highspeed and high-resolution ADCs and DACs in 3G base stations. Additionally, the devices can also be used as a jitter attenuator for generating high-precision CLK signals.

The MAX9450/MAX9451/MAX9452 feature an integrated VCXO. This configuration eliminates the use of an external VCXO and provides a cost-effective solution for generating high-precision clocks. The MAX9450/MAX9451/ MAX9452 feature two differential inputs and clock outputs. The inputs accept LVPECL, LVDS, differential signals, and LVCMOS. The input reference clocks range from 8kHz to 500MHz.

The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL, and LVDS outputs, respectively. The output range is up to 160MHz, depending on the selection of crystal. The input and output frequency selection is implemented through the I2C* or SPI™ interface. The MAX9450/ MAX9451/MAX9452 feature clock output jitter less than

0.8ps RMS (in a 12kHz to 20MHz band) and phasenoise attenuation greater than -130dBc/Hz at 100kHz. The phase-locked loop (PLL) filter can be set externally, and the filter bandwidth can vary from 1Hz to 20kHz.

The MAX9450/MAX9451/MAX9452 feature an input clock monitor with a hitless switch. When a failure is detected at the selected reference clock, the device can switch to the other reference clock. The reaction to the recovery of the failed reference clock can be revertive or nonrevertive. If both reference clocks fail, the PLL retains its nominal frequency within a range of ±20ppm at +25°C.

The MAX9450/MAX9451/MAX9452 operate from a 2.4V to

3.6V supply and are available in 32-pin TQFP packages with exposed pads.

Applications

SONET/SDH Systems

10 Gigabit Network Routers and Switches

3G Cellular Phone Base Stations

General Jitter Attenuation

*Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I ponents in an I

C Standard Specification as defined by Philips.

the I

SPI is a trademark of Motorola, Inc.

C system, provided that the system conforms to

C Patent Rights to use these com-

Features

♦ Integrated VCXO Provides a Cost-Effective

Solution for High-Precision Clocks

♦ 8kHz to 500MHz Input Frequency Range ♦ 15MHz to 160MHz Output Frequency Range ♦ I2C or SPI Programming for the Input and Output

Frequency Selection

♦ PLL Lock Range > ±60ppm ♦ Two Differential Outputs with Three Types of

Signaling: LVPECL, LVDS, or HSTL

♦ Input Clock Monitor with Hitless Switch ♦ Internal Holdover Function within ±20ppm of the

Nominal Frequency

♦ Low Output CLK Jitter: < 0.8ps RMS in the 12kHz

to 20MHz Band

♦ Low Phase Noise > -130dBc at 100kHz

Ordering Information

PART PIN-PACKAGE OUTPUT PKG CODE

MAX9450EHJ+ 32 TQFP-EP** LVPECL H32E-6

MAX9451EHJ+† 32 TQFP-EP** HSTL H32E-6

MAX9452EHJ+† 32 TQFP-EP** LVDS H32E-6

Note: All devices are specified over the -40°C to +85°C temperature range.

+Denotes lead-free package. **EP = Exposed pad.

†Future product—contact factory for availability.

Pin Configuration

TOP VIEW

DDA

LP1

LP2

GNDA

25V

32RJ

DDQ

CLK1+

CLK1-

MAX9450 MAX9451 MAX9452

EXPOSED PAD

SEL0

SEL1

GND

212223

(GND)

IN0+

TQFP

24 20

LOCK

(5mm x 5mm)

CLK0+

IN0-

CLK0-

DDQ

CMON

AD1

AD0

SDA

SCL

GND/CS

INT

834

IN1-

IN1+

MAX9450/MAX9451/MAX9452

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

MAX9450/MAX9451/MAX9452

High-Precision Clock Generators with Integrated VCXO

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

DDA

= VDD= V

DDQ

= 2.4V to 3.6V, and V

DDQ

= 1.4V to 1.6V for MAX9451, TA= -40°C to +85°C. Typical values at V

DDA

= VDD=

DDQ

= 3.3V, and V

DDQ

= 1.5V for MAX9451, TA= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND...........................................................-0.3V to +4.0V

DDA

to GNDA ......................................................-0.3V to +4.0V

All Other Pins to GND ...................................-0.3V to V

+ 0.3V

Short-Circuit Duration (all pins) ..................................Continuous

Continuous Power Dissipation (T

= +85°C)

32-Pin TQFP (derate 27.8mW/°C above +70°C)........2222mW

Storage Temperature Range .............................-65°C to +165°C

Maximum Junction Temperature .....................................+150°C

Operating Temperature Range ...........................-40°C to +85°C

Lead Temperature (soldering, 10s) .................................+300°C

ESD Protection

Human Body Model (R

= 1.5kΩ, CS= 100pF) ..............±2kV

PARAMETER

CONDITIONS

UNITS

LVCMOS INPUT (SEL_, CMON, OE, MR)

Input High Level V

IH1

2.0

Input Low Level V

IL1

0 0.8 V

Input Current I

IN1

VIN = 0V to V

-50 +50 µA

LVCMOS OUTPUT (INT, LOCK)

Output High Level V

OH1IOH1

= -4mA

Output Low Level V

OL1IOL1

= 4mA 0.4 V

THREE-LEVEL INPUT (AD0, AD1)

Input High Level V

IH2

1.8 V

Input Low Level V

IL2

0.8 V

Input Open Level V

IO2

Measured at the opened inputs

Input Current

IL2

= 0V or V

IH2

= V

-15 +15 µA

DIFFERENTIAL INPUTS (IN0, IN1)

Differential Input High Threshold V

IDH

= V

IN+

- V

IN-

50 mV

Differential Input Low Threshold V

IDL

= V

IN+

- V

IN-

-50 mV

Common-Mode Input-Voltage Range V

COM

= V

IN+ - VIN-

2.4 V

Input Current

-1 +1 µA

MAX9450 OUTPUTS (CLK0, CLK1) (LVPECL)

Output High Voltage V

OH2

50Ω load connected to V

DDQ

- 2.0V

Output Low Voltage V

OL2

50Ω load connected to V

DDQ

- 2.0V

SYMBOL

MIN TYP MAX

- 0.4

IL2, IIH2

IN+, IIN-

1.05 1.35

/ 2|

D D Q

- |V

- 1.42

D D Q

- 2.15

D D Q

- 1.00

D D Q

- 2.15

/ 2|

MAX9450/MAX9451/MAX9452

High-Precision Clock Generators

with Integrated VCXO

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

DDA

= VDD= V

DDQ

= 2.4V to 3.6V, and V

DDQ

= 1.4V to 1.6V for MAX9451, TA= -40°C to +85°C. Typical values at V

DDA

= VDD=

DDQ

= 3.3V, and V

DDQ

= 1.5V for MAX9451, TA= +25°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SERIAL INTERFACE INPUT, OUTPUT (SCL, SDA, CS)

Input High Level V

Input Low Level V

Input Leakage Current I

±1 µA

Output Low Level V

3mA sink current 0.4 V

Input Capacitance C

10 pF

POWER CONSUMPTION

VDD and V

DDA

Supply Current I

CC1

Output clock frequency = 155MHz 55 85 mA

DDQ

Supply Current I

CC2

Output clock frequency = 155MHz (MAX9450)

55 80 mA

AC ELECTRICAL CHARACTERISTICS

DDA

= VDD= V

DDQ

= 2.4V to 3.6V, and V

DDQ

= 1.4V to 1.6V for MAX9451, TA= -40°C to +85°C. |VID| = 200mV, V

COM

= |VID/ 2| to

2.4 - |V

/ 2|. Typical values at V

DDA

= VDD= V

DDQ

= 3.3V and V

DDQ

= 1.5V for MAX9451, TA= +25°C. CL= 10pF, clock output =

155.5MHz and clock input = 19.44MHz, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

CLK OUTPUTS (CLK0, CLK1)

Reference Input Frequency f

Measured at IN0 or IN1

500

MHz

Output Frequency f

OUT

Measured at CLK0 or CLK1 15 160

MHz

VCXO Pulling Range CL = 8pF (Note 2) ±50

ppm

Output-to-Output Skew t

SKO

Skew between CLK0 and CLK1 90 ps

Rise Time t

20% to 80% of output swing 0.4

Fall Time t

80% to 20% of output swing 0.4

Duty Cycle 44 56 %

Period Jitter (RMS) T

0.8 ps

1kHz offset -70

dBc/Hz

10kHz offset

dBc/Hz

Phase Noise

100kHz offset

dBc/Hz

SYMBOL

0.7

x V

0.3

x V

MIN TYP MAX

0.008

Measured at the band 12kHz to 20MHz

-110

-130

0.585

Note 1: All timing AC electrical characteristics and timing specifications are guaranteed by design and not production tested. Note 2: The VCXO tracks the input clock frequency by ±50ppm. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined regions of SCL’s

falling edge.

Note 4: C

= total capacitance of one bus line in pF. Tested with CB= 400pF.

Note 5: Input filters on SDA and SCL suppress noise spikes less than 50ns.

PARAMETER

CONDITIONS

UNITS

Serial-Clock Frequency f

SCL

MHz

CS Fall to CLK Rise Setup Time t

CSS

DIN Setup Time t

DIN Hold Time t

0ns

CLK High to CS High t

CSH

0ns

CS Pulse-High Time t

CSW

20 ns

SERIAL SPI INTERFACE TIMING CHARACTERISTICS

(VDD= 2.4V to 3.6V, TA= -40°C to +85°C. See Figure 7 for the timing parameters definition.)

MAX9450/MAX9451/MAX9452

High-Precision Clock Generators with Integrated VCXO

4 _______________________________________________________________________________________

PARAMETER

CONDITIONS

UNITS

Serial Clock f

SCL

400

kHz

Bus Free Time Between STOP and START Conditions

BUF

1.3 µs

Rep eated H ol d Ti m e S TART C ond i ti on

0.6 µs

STOP Condition Setup Time

0.6 µs

Data Hold Time

(Note 3) 100 ns

Data Setup Time

100 ns

SCL Clock-Low Period t

LOW

1.3 µs

SCL Clock-High Period t

HIGH

0.7 µs

300 ns

(Note 4)

300 ns

Minimum Receive SCL/SDA Fall Time t

(Note 4)

Fall Time of SDA, Transmitting t

F,TX

(Note 4)

250 ns

Pulse Width of Suppressed Spike t

(Note 5) 0 50 ns

Capacitive Load for Each Bus Line C

(Note 4) 400 pF

SERIAL I2C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS

(VDD= 2.4V to 3.6V, TA= -40°C to +85°C. See Figure 4 for the timing parameters definition.)

Rep eated S TART C ond i ti on S etup Ti m et

Maximum Receive SCL/SDA Rise Time

SYMBOL

HD,STA

SU,STA

SU,STO

HD,DAT

SU,DAT

MIN TYP MAX

Minimum Receive SCL/SDA Rise Time

Maximum Receive SCL/SDA Fall Time

SYMBOL

+ 0.1 x C

+ 0.1C

MIN TYP MAX

12.5

MAX9450/MAX9451/MAX9452

High-Precision Clock Generators

with Integrated VCXO

_______________________________________________________________________________________ 5

VDD AND V

DDA

SUPPLY CURRENT

vs. VOLTAGE

MAX9450 toc01

VOLTAGE (V)

(mA)

3.43.33.23.1

3.0 3.63.5

TA = -40°C

TA = +25°C

TA = +85°C

DDQ

SUPPLY CURRENT

vs. VOLTAGE

MAX9450 toc02

VOLTAGE (V)

(mA)

3.43.33.23.1

3.0 3.63.5

TA = -40°C

TA = +25°C

TA = +85°C

OUTPUT FREQUENCY CHANGE

vs. TEMPERATURE

MAX9450 toc04

TEMPERATURE (°C)

OUTPUT FREQUENCY CHANGE (ppm)

6035-15 10

-30

-20

-10

-50

-40

-40 85

PHASE NOISE

vs. FREQUENCY

MAX9450 toc05

PHASE NOISE (dB)

100k

FREQUENCY (Hz)

1M 10M10k1k

-20

-40

-60

-80

-100

-120

-140

-160

OUTPUT RMS JITTER

vs. TEMPERATURE

MAX9450 toc03

TEMPERATURE (°C)

RMS JITTER (ps)

603510-15

-40 85

OUTPUT CLOCK SYNCHRONIZED

TO INPUT REFERENCE

MAX9450 toc06

153.13mV/div 100mV/div

10ns/div

INPUT REFERENCE = 19.44MHz OUTPUT CLOCK = 155.52 MHz

Typical Operating Characteristics

(VDD= V

DDA

= V

DDQ

= 3.3V. TA= +25°C, unless otherwise noted.)

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