General Description
The MAX9394/MAX9395 consist of a 2:1 multiplexer
and a 1:2 demultiplexer with loopback. The multiplexer
section (channel B) accepts two low-voltage differential
signaling (LVDS) inputs and generates a single LVDS
output. The demultiplexer section (channel A) accepts
a single LVDS input and generates two parallel LVDS
outputs. The MAX9394/MAX9395 feature a loopback
mode that connects the input of channel A to the output
of channel B and connects the selected input of channel B to the outputs of channel A.
Three LVCMOS/LVTTL logic inputs control the internal
connections between inputs and outputs, one for the
multiplexer portion of channel B (BSEL), and the other
two for loopback control of channels A and B (LB_SELA
and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility.
Fail-safe circuitry forces the outputs to a differential low
condition for undriven inputs or when the commonmode voltage exceeds the specified range. The
MAX9394 provides high-level input fail-safe detection
for HSTL, LVDS, and other GND-referenced differential
inputs. The MAX9395 provides low-level fail-safe detection for CML, LVPECL, and other VCC-referenced differential inputs.
Ultra low 91ps
P-P
(max) pseudorandom bit sequence
(PRBS) jitter ensures reliable communications in highspeed links that are highly sensitive to timing error,
especially those incorporating clock-and-data recovery,
or serializers and deserializers. The high-speed switching performance guarantees 1.5GHz operation and less
than 87ps (max) skew between channels.
LVDS inputs and outputs are compatible with the
TIA/EIA-644 LVDS standard. The LVDS outputs drive
100Ω loads. The MAX9394/MAX9395 are offered in 32pin TQFP and 28-pin thin QFN packages and operate
over the extended temperature range (-40°C to +85°C).
Applications
High-Speed Telecom/Datacom Equipment
Central Office Backplane Clock Distribution
DSLAM
Protection Switching
Fault-Tolerant Systems
Features
♦ Guaranteed 1.5GHz Operation with 250mV
Differential Output Swing
♦ Simultaneous Loopback Control
♦ 2ps
(RMS)
(max) Random Jitter
♦ AC Specifications Guaranteed for 150mV
Differential Input
♦ Signal Inputs Accept Any Differential Signaling
Standard
♦ LVDS Outputs for Clock or High-Speed Data
♦ High-Level Input Fail-Safe Detection (MAX9394)
♦ Low-Level Input Fail-Safe Detection (MAX9395)
♦ +3.0V to +3.6V Supply Voltage Range
♦ LVCMOS/LVTTL Logic Inputs
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
0.1µF 0.01µF
+3.0V TO
+3.6V
OUTA0
OUTA0
LVDS
RECEIVER
INA
INA
ENA0
ENA1
ENB
GNDGND GNDGND
OUTA1
OUTA1
OUTB
OUTB
LVCMOS/LVTTL
LOGIC INPUTS
LB_SELA
LB_SELB
BSEL
INB0
INB0
100Ω
Z0 = 50Ω
Z0 = 50Ω
MAX9394
MAX9395
V
CC
INB1
INB1
Z0 = 50Ω
Z0 = 50Ω
100Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Typical Operating Circuit
19-2878; Rev 0; 7/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*Future product—contact factory for availability.
Pin Configurations and Functional Diagram appear at end
of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX9394EHJ -40°C to +85°C 32 TQFP
MAX9394ETI* -40°C to +85°C 28 Thin QFN
MAX9395EHJ -40°C to +85°C 32 TQFP
MAX9395ETI* -40°C to +85°C 28 Thin QFN
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.1V
IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, _SEL, LB_SEL_
to GND........................................................-0.3V to (V
CC
+ 0.3V)
IN_ _ to IN_ _..........................................................................±3V
Short-Circuit Duration (OUT_ _, OUT_ _) ...................Continuous
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFP (derate 13.1mW/°C above +70°C)........1047mW
28-Pin 5mm x 5mm Thin QFN
(derate 20.8mW/°C above +70°C).............................1667mW
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin TQFP............................................................+76.4°C/W
28-Pin 5mm x 5mm Thin QFN....................................+48°C/W
Junction-to-Case Thermal Resistance
28-Pin 5mm x 5mm Thin QFN......................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection (Human Body Model)
(IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, SEL_, LB_SEL_) ..±2kV
Soldering Temperature (10s) ...........................................+300°C
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, RL= 100Ω ±1%, EN_ _ = VCC, VCM= +0.05V to (VCC- 0.6V) (MAX9394), VCM= +0.06V to (VCC- 0.05V)
(MAX9395), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, |VID| = 0.2V, VCM= +1.2V, TA= +25°C.)
(Notes 1, 2, and 3)
LVCMOS/LVTTL INPUTS (EN_ _, BSEL, LB_SEL_)
Input High Voltage V
Input Low Voltage V
Input High Current I
Input Low Current I
DIFFERENTIAL INPUTS (IN_ _, IN_ _)
Differential Input Voltage V
Input Common-Mode Range V
Input Current
LVDS OUTPUTS (OUT_ _, OUT_ _)
Differential Output Voltage V
Change in Magnitude of V
Between Complementary Output
States
Offset Common-Mode Voltage V
Change in Magnitude of V
Between Complementary Output
States
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
OD
OS
IH
IL
IH
IL
ID
CM
,
I
IN_ _
I
IN_ _ MAX9395 |V
OD
∆V
OD
OS
∆V
OS
VIN = +2.0V to V
VIN = 0V to +0.8V 0 10 µA
V
> 0V and V
ILD
MAX9394 0.05
MAX9395 0.6
MAX9394 |VID| < 3.0V -75 10
RL = 100Ω, Figure 2 250 350 450 mV
Figure 2 1.0 50 mV
Figure 2 1.125 1.25 1.375 V
Figure 2 1.0 50 mV
2.0 V
0 0.8 V
CC
< VCC, Figure 1 0.1 3.0 V
IHD
| < 3.0V -10 100
ID
020µA
V
CC
0.6
V
CC
0.05
CC
-
-
V
V
µA
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
_______________________________________________________________________________________ 3
Note 1: Measurements obtained with the device in thermal equilibrium. All voltages referenced to GND except VID, VOD, and ∆VOD.
Note 2: Current into the device defined as positive. Current out of the device defined as negative.
Note 3: DC parameters production tested at T
A
= +25°C and guaranteed by design and characterization for TA= -40°C to +85°C.
Note 4: Current through either output.
Note 5: Guaranteed by design and characterization. Limits set at ±6 sigma.
Note 6: t
SKEW
is the magnitude difference of differential propagation delays for the same output over the same condtions. t
SKEW
=
|t
PHL
- t
PLH
|.
Note 7: Measured between outputs of the same device at the signal crossing points for a same-edge transition under the same con-
ditions. Does not apply to loopback mode.
Note 8: Device jitter added to the differential input signal.
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, RL= 100Ω ±1%, EN_ _ = VCC, VCM= +0.05V to (VCC- 0.6V) (MAX9394), VCM= +0.06V to (VCC- 0.05V)
(MAX9395), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, |VID| = 0.2V, VCM= +1.2V, TA= +25°C.)
(Notes 1, 2, and 3)
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, fIN< 1.34GHz, t
R_IN
= t
F_IN
= 125ps, RL= 100Ω ±1%, |VID| ≥ 150mV, VCM= +0.075V to (VCC- 0.6V)
(MAX9394 only), V
CM
= +0.6V to (VCC- 0.075V) (MAX9395 only), EN_ _ = VCC, TA= -40°C to +85°C, unless otherwise noted. Typical
values are at V
CC
= +3.3V, |VID| = 0.2V, VCM= +1.2V, fIN= 1.34GHz, TA= +25°C.) (Note 5)
(
)
Output Short-Circuit Current
(Output(s) Shorted to GND)
Output Short-Circuit Current
(Outputs Shorted Together)
SUPPLY CURRENT
Supply Current I
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
V
V
= ±100mV
|I
|I
OS
OSB
ID
|
(Note 4)
|VID = ±100mV, V
RL = 100Ω, EN_ _ = V
CC
RL = 100Ω, EN_ _ = VCC, switching at
670MHz (1.34Gbps)
V
V
OUT_ _
OUT_ _
OUT_ _
OUT_ _
= V
CC
or V
=
= 0V
OUT_ _
= 0V 30 40
OUT_ _
17 24
(Note 4) 5 12 mA
53 65
53 65
mA
mA
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
SEL to Switched Output t
SWITCH
Disable Time to Differential
Output Low
Enable Time to Differential Output
High
Switching Frequency f
Low-to-High Propagation Delay t
High-to-Low Propagation Delay t
Pulse Skew |t
PLH
– t
|t
PHL
Output Channel-to-Channel Skew t
Output Low-to-High Transition
Time (20% to 80%)
Output High-to-Low Transition
Time (80% to 20%)
Added Random Jitter t
Added Deterministic Jitter t
t
PHD
t
PDH
MAX
PLH
PHL
SKEW
CCS
t
R
t
F
RJ
DJ
Figure 3 1.1 ns
Figure 4 1.7 ns
Figure 4 1.7 ns
VOD > 250mV 1.5 2.2 GHz
Figures 1, 5 340 567 720 ps
Figures 1, 5 340 562 720 ps
Figures 1, 5 (Note 6) 12.4 86 ps
Figure 6 (Note 7) 16 87 ps
f
= 100MHz, Figures 1, 5 112 154 187 ps
IN_ _
f
= 100MHz, Figures 1, 5 112 152 187 ps
IN_ _
f
= 1.34GHz, clock pattern (Note 8) 2 ps
IN_ _
1.34Gbps, 223 - 1 PRBS (Note 8) 60 91 ps
RMS
P-P
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VCC= +3.3V, |VID| = 0.2V, VCM= +1.2V, TA= +25°C, fIN= 1.34GHz, Figure 5.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9394/95 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
6035-15 10
35
40
45
50
55
60
65
70
30
-40 85
VCC = +3.3V
VCC = +3.6V
VCC = +3.0V
OUTPUT AMPLITUDE vs. FREQUENCY
MAX9394/95 toc02
FREQUENCY (GHz)
OUTPUT AMPLITUDE (mV)
2.00.4 1.2 1.60.8
50
100
150
200
250
300
350
400
0
02.4
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9394/95 toc03
TEMPERATURE (°C)
RISE/FALL TIME (ps)
603510-15
130
140
150
160
170
180
120
-40 85
t
R
t
F
fIN = 100MHz
PROPAGATION DELAY
vs. TEMPERATURE
MAX9394/95 toc04
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
603510-15
510
520
530
540
550
560
570
580
590
600
500
-40 85
MAX9394 DIFFERENTIAL INPUT CURRENT
vs. TEMPERATURE
MAX9394/95 toc05
TEMPERATURE (°C)
INPUT CURRENT (µA)
603510-15
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
-50
-40 85
V
IN_ _
= 3.0V
V
IN_ _
= 0.1V
V
IN_ _
= 0V
MAX9395 DIFFERENTIAL INPUT CURRENT
vs. TEMPERATURE
MAX9394/95 toc06
TEMPERATURE (°C)
INPUT CURRENT (µA)
6035-15 10
10
20
30
40
50
60
70
80
0
-40 85
V
IN_ _
= V
CC
V
IN_ _
= (VCC - 0.1V)
V
IN_ _
= (VCC - 3.0V)
MAX9394
DIFFERENTIAL INPUT CURRENT vs. V
IHD
MAX9394/95 toc07
V
IHD
(V)
INPUT CURRENT (µA)
3.02.40.6 1.2 1.8
-35
-30
-25
-20
-15
-10
-5
0
5
-40
03.6
IN_ _ OR
IN_ _ = GND
VCC = +3V
VCC = +3.6V
MAX9395
DIFFERENTIAL INPUT CURRENT vs. V
ILD
MAX9394/95 toc08
V
ILD
(V)
INPUT CURRENT (µA)
3.02.40.6 1.2 1.8
0
10
20
30
40
50
60
70
80
-10
03.6
IN_ _ OR
IN_ _ = V
CC
VCC = +3.6V
VCC = +3V
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
_______________________________________________________________________________________ 5
Pin Description
PIN
TQFP QFN
1, 2, 3, 30,
31, 32
4, 9, 20, 25 3, 8, 18, 23 GND Ground
5 4 ENB
6 5 OUTB
76OUTB
8, 13, 24, 29 7, 22, 27 V
10 9 INB0
11 10 INB0
12 11 LB_SELB
1, 2, 28 N.C. No Connection. Not internally connected.
NAME FUNCTION
Channel B Output Enable. Drive ENB high to enable the LVDS outputs for channel B.
An internal 435kΩ resistor to GND pulls ENB low when unconnected.
Channel B LVDS Noninverting Output. Connect a 100Ω termination resistor between
OUTB and OUTB at the receiver inputs to ensure proper operation.
Channel B LVDS Inverting Output. Connect a 100Ω termination resistor between
OUTB and OUTB at the receiver inputs to ensure proper operation.
Power-Supply Input. Bypass each VCC to GND with a 0.1µF and 0.01µF ceramic
CC
capacitor. Install both bypass capacitors as close to the device as possible, with the
0.01µF capacitor closest to the device.
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Inverting Input. An internal
128kΩ pullup resistor to V
internal 68kΩ resistor to GND pulls the input low when unconnected (MAX9395).
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Noninverting Input. An internal
128kΩ pullup resistor to VCC pulls the input high when unconnected (MAX9394). An
internal 68kΩ resistor to GND pulls the input low when unconnected (MAX9395).
Loopback Select for Channel B Output. Connect LB_SELB to GND or leave
unconnected to reproduce the INB_ (INB_) differential inputs at OUTB (OUTB).
Connect LB_SELB to V
(OUTB). An internal 435kΩ resistor to GND pulls LB_SELB low when unconnected.
pulls the input high when unconnected (MAX9394). An
CC
to loop back the INA (INA) differential inputs to OUTB
CC
14 12 INB1
15 13 INB1
16 14 BSEL
17 15 ENA1
18 16 OUTA1
19 17 OUTA1
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Inverting Input. An internal
128kΩ pullup resistor to V
internal 68kΩ resistor to GND pulls the input low when unconnected (MAX9395).
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Noninverting Input. An internal
128kΩ pullup resistor to VCC pulls the input high when unconnected (MAX9394). An
internal 68kΩ resistor to GND pulls the input low when unconnected (MAX9395).
Channel B Multiplexer Control Input. Selects the differential input to reproduce at the
B channel differential output. Connect BSEL to GND or leave unconnected to select
the INB0 (INB0) set of inputs. Connect BSEL to V
inputs. An internal 435kΩ resistor to GND pulls BSEL low when unconnected.
Channel A1 Output Enable. Drive ENA1 high to enable the A1 LVDS outputs. An
internal 435kΩ resistor to GND pulls the ENA1 low when unconnected.
Channel A1 LVDS Inverting Output. Connect a 100Ω termination resistor between
OUTA1 and OUTA1 at the receiver inputs to ensure proper operation.
Channel A1 LVDS Noninverting Output. Connect a 100Ω termination resistor between
OUTA1 and OUTA1 at the receiver inputs to ensure proper operation.
pulls the input high when unconnected (MAX9394). An
CC
to select the INB1 (INB1) set of
CC
MAX9394/MAX9395
Detailed Description
The LVDS interface standard provides a signaling
method for point-to-point communication over a controlled-impedance medium as defined by the ANSI
TIA/EIA-644 standard. LVDS utilizes a lower voltage
swing than other communication standards, achieving
higher data rates with reduced power consumption,
while reducing EMI emissions and system susceptibility
to noise.
The MAX9394/MAX9395 high-speed, low-power 2:1
multiplexers and 1:2 demultiplexers with loopback provide signal redundancy switching in telecom and storage applications. These devices select one of two
remote signal sources for local input and buffer a single
local output signal to two remote receivers.
The multiplexer section (channel B) accepts two differential inputs and generates a single LVDS output. The
demultiplexer section (channel A) accepts a single differential input and generates two parallel LVDS outputs. The
MAX9394/MAX9395 feature a loopback mode that connects the input of channel A to the output of channel B
and connects the selected input of channel B to the outputs of channel A. LB_SELA and LB_SELB provide independent loopback control for each channel.
Three LVCMOS/LVTTL logic inputs control the internal
connections between inputs and outputs, one for the
multiplexer portion of channel B (BSEL), and the other
two for loopback control of channels A and B (LB_SELA
and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility.
Input Fail-Safe
The differential inputs of the MAX9394/MAX9395 possess internal fail-safe protection. Fail-safe circuitry
forces the outputs to a differential-low condition for
undriven inputs or when the common-mode voltage
exceeds the specified range. The MAX9394 provides
high-level input fail-safe detection for LVDS, HSTL, and
other GND-referenced differential inputs. The MAX9395
provides low-level input fail-safe detection for LVPECL,
CML, and other VCC-referenced differential inputs.
Select Function
BSEL selects the differential input pair to transmit
through OUTB (OUTB) for LB_SELB = GND or through
OUTA_ (OUTA_) for LB_SELA = VCC. LB_SEL_ controls
the loopback function for each channel. Connect
LB_SEL_ to GND to select the normal inputs for each
channel. Connect LB_SEL_ to VCCto enable the loop-
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
6 _______________________________________________________________________________________
Pin Description (continued)
PIN
TQFP QFN
21 19 ENA0
22 20 OUTA0
23 21 OUTA0
26 24 INA
27 25 INA
28 26 LB_SELA
——EP Exposed Paddle. Connect to GND for optimal thermal and EMI characteristics.
NAME FUNCTION
Channel A0 Output Enable. Drive ENA0 high to enable the A0 LVDS outputs. An
internal 435kΩ resistor to GND pulls ENA0 low when unconnected.
Channel A0 LVDS Inverting Output. Connect a 100Ω termination resistor between
OUTA0 and OUTA0 at the receiver inputs to ensure proper operation.
Channel A0 LVDS Noninverting Output. Connect a 100Ω termination resistor between
OUTA0 and OUTA0 at the receiver inputs to ensure proper operation.
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Noninverting Input. An internal
128kΩ pullup resistor to VCC pulls the input high when unconnected (MAX9394). An
internal 68kΩ resistor to GND pulls the input low when unconnected (MAX9395).
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Inverting Input. An internal
128kΩ pullup resistor to V
internal 68kΩ resistor to GND pulls the input low when unconnected (MAX9395).
Loopback Select for Channel A Output. Connect LB_SELA to GND or leave
unconnected to reproduce the INA (INA) differential inputs at OUTA_ (OUTA_).
Connect LB_SELA to V
(OUTA_). An internal 435kΩ resistor to GND pulls LB_SELA low when unconnected.
pulls the input high when unconnected (MAX9394). An
CC
to loop back the INB_ (INB_) differential inputs to OUTA_
CC
back function. The loopback function routes the input of
channel A to the output of channel B, and the inputs of
channel B to the outputs of channel A. See Tables 1
and 2 for a summary of the input/output routing
between channels.
Enable Function
The EN_ _ logic inputs enable and disable each set of
differential outputs. Connect EN_ 0 to VCCto enable the
OUT_0/OUT_0 differential output pair. Connect EN_0 to
GND to disable the OUT_0/OUT_0 differential output
pair. The differential output pairs assert to a differential
low condition when disabled.
Applications Information
Differential Inputs
The MAX9394/MAX9395 inputs accept any differential
signaling standard within the specified common-mode
voltage range. The fail-safe feature detects commonmode input signal levels and generates a differential
output low condition for undriven inputs or when the
common-mode voltage exceeds the specified range
(VCM≥ VCC- 0.6V, MAX9394; VCM≤ 0.6V, MAX9395).
Leave unused inputs unconnected or connect to V
CC
for the MAX9394 or to GND for the MAX9395.
Power-Supply Bypassing
Bypass each VCCto GND with high-frequency surfacemount ceramic 0.1µF and 0.01µF capacitors in parallel
as close to the device as possible. Install the 0.01µF
capacitor closest to the device.
Differential Traces
Input and output trace characteristics affect the performance of the MAX9394/MAX9395. Connect each input
and output to a 50Ω characteristic impedance trace.
Maintain the distance between differential traces and
eliminate sharp corners to avoid discontinuities in differential impedance and maximize common-mode
noise immunity. Minimize the number of vias on the differential input and output traces to prevent impedance
discontinuities. Reduce reflections by maintaining the
50Ω characteristic impedance through connectors and
across cables. Minimize skew by matching the electrical length of the traces.
Output Termination
Terminate LVDS outputs with a 100Ω resistor between
the differential outputs at the receiver inputs. LVDS outputs require 100Ω termination for proper operation.
Ensure that the output currents do not exceed the current limits specified in the Absolute Maximum Ratings.
Observe the total thermal limits of the MAX9394/
MAX9395 under all operating conditions.
Cables and Connectors
Use matched differential impedance for transmission
media. Use cables and connectors with matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables.
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
_______________________________________________________________________________________ 7
Figure 1. Output Transition Time and Propagation Delay Timing
Diagram
Figure 2. Test Circuit for VODand V
OS
V
V
V
OUT_ _
V
OUT_ _
IN_ _
IN_ _
= 0V
V
ID
t
PLH
50% V
20%
V
VOD = V
= 0V
V
ID
t
PHL
= 0V
V
OD
80%
= 0V
OD
t
R
= V
- V
ID
IN_ _
- V
OUT_ _
80%
50%
IN_ _
OUT_ _
V
OD
V
OD
t
F
20%
= 0V
= 0V
V
IHD
V
ILD
OUT_ _
V
OD
V
OS
/2
IN_ _
IN_ _
EN_ _ = HIGH
VID = V
MAX9394/MAX9395
RL/2
R
L
- V
IN_ _
IN_ _
∆VOD = VOD - VOD* RL = 100Ω ±1%
= VOS - VOS*
∆V
OS
AND V
V
OD
V
OD
ARE MEASURED WITH VID = +100mV.
OS
* AND VOS* ARE MEASURED WITH VID = -100mV.
OUT_ _
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
8 _______________________________________________________________________________________
Figure 3. Input to Rising/Falling Edge Select and Mux Switch Timing Diagram
Figure 4. Output Active-to-Disable and Disable-to-Active Test Circuit and Timing Diagram
V
INB0
INB0
INB1
INB1
BSEL
= 0V
V
ID
= 0V
V
ID
1.5V
1.5V
IHD
V
ILD
V
IHD
V
ILD
V
IH
V
IL
OUT_ _
INB0
OUT_ _
t
SWITCH
EN_0 = EN_1 = HIGH
V
= V
- V
ID
IN_ _
IN_ _
MAX9394/MAX9395
IN_ _
IN_ _
PULSE
GENERATOR
V
EN_ _
EN_ _
50Ω
1.5V
C
C
L
L
VOD = 0V
RL/2
R
/2
L
OUT_ _
OUT_ _
INB1
1.5V
+1.25V
R
C
= 100Ω ±1%
L
= 1.0pF
L
OD
= 0V
t
SWITCH
3V
0V
INB0
V
WHEN VID = +100mV
V
OUT_ _
WHEN VID = -100mV
V
OUT_ _
V
WHEN VID = -100mV
OUT_ _
V
WHEN VID = +100mV
OUT_ _
t
t
PHD
PHD
50%
50%
VID = V
IN_ _
- V
IN_ _
t
PDH
50%
50%
t
PDH
Balanced cables such as twisted pair offer superior
signal quality and tend to generate less EMI due to
canceling effects.
Board Layout
Use a four-layer printed circuit (PC) board providing
separate signal, power, and ground planes for highspeed signaling applications. Bypass VCCto GND as
close to the device as possible. Install termination
resistors as close to receiver inputs as possible. Match
the electrical length of the differential traces to minimize
signal skew.
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
_______________________________________________________________________________________ 9
Table 1. Input Select Truth Table
LB_SEL_ OUT_ _
GND or open Normal inputs selected.
V
CC
Loopback inputs selected.
Table 2. Loopback Select Truth Table
Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit
X = Don’t care.
LOGIC INPUTS DIFFERENTIAL OUTPUTS
LB_SELA LB_SELB BSEL OUTA_ / OUTA_ OUTB / OUTB
0 0 0 INA selected INB0 selected
0 0 1 INA selected INB1 selected
0 1 X INA selected INA selected
1 0 0 INB0 selected INB0 selected
1 0 1 INB1 selected INB1 selected
1 1 0 INB0 selected INA selected
1 1 1 INB1 selected INA selected
LB_SELA
MAX9394
MAX9395
0
LB
C
L
C
L
C
L
R
OUTA0
L
OUTA0
OUTA1
PULSE
GENERATOR
50Ω
50Ω
INA
INA
FROM
CHANNEL B
C
L
R
L
C
ENA0 = ENA1 = HIGH
1 CHANNEL SHOWN.
L
R
L
OUTA1
= 100Ω ±1%
= 1.0pF
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
10 ______________________________________________________________________________________
Figure 6. Output Channel-to-Channel Skew
0
LB
LB
0
OUTA1
ENA1
ENA0
LB_SELA
BSEL
OUTA1
OUTA0
OUTA0
INA
INA
MAX9394
MAX9395
INB0
INB0
INB1
INB1
ENB
LB_SELB
OUTB
OUTB
1
0
Functional Diagram
V
OUTA0
V
OUTA0
V
OUTA1
V
OUTA1
VOD = 0V
t
CCS
VOD = V
V
= 0V VOD = 0V
OD
- V
OUT_ _
OUT_ _
VOD = 0V
t
CCS
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
______________________________________________________________________________________ 11
Pin Configurations
Chip Information
TRANSISTOR COUNT: 1565
PROCESS: Bipolar
TOP VIEW
1N.C.
2
N.C.
3
N.C.
4
GND
5
ENB
6
OUTB
7
OUTB
8V
CC
N.C.
N.C.
N.C.
32 28
VCCLB_SELA
293031
MAX9394
MAX9395
10
9
GND
INB0
INB0
LB_SELB
TQFP
INA
INA
GND
26
25
27
24 V
CC
OUTA0
23
OUTA0
22
ENA0
21
GND
20
OUTA1
19
OUTA1
18
ENA1
17
14
15
13
CC
V
INB1
INB1
1611 12
BSEL
TOP VIEW
OUTB
OUTB
N.C.
VCCLB_SELA
INA
26
25 24 23 22
27
MAX9394
MAX9395
*EXPOSED PADDLE
10
11 12
98
INB0
INB0
LB_SELB
N.C.
N.C.
GND
ENB
V
28
1
2
3
4
5
6
7
CC
GND
THIN QFN
*CONNECT EXPOSED PADDLE TO GND.
INA
INB1
CC
GND
V
21
OUTA0
OUTA0
20
ENA0
19
18
GND
OUTA1
17
OUTA1
16
15
ENA1
14
13
INB1
BSEL
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
12 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D
PIN # 1
I.D.
D/2
C
COMMON DIMENSIONS
A1
0.15 C A
E/2
A3
D2
b
0.10 M
PIN # 1 I.D.
0.35x45
E2/2
C
k
L
DOCUMENT CONTROL NO.
21-0140
C A B
QFN THIN.EPS
E2
L
CC
L
L
REV.
1
C
2
C
L
D2/2
0.15
C B
E
0.10
C
A
0.08 C
(NE-1) X e
DETAIL A
k
e
(ND-1) X e
L
L
e e
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
21-0140
REV.DOCUMENT CONTROL NO.APPROVAL
2
C
2
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
32L TQFP, 5x5x01.0.EPS
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