Rainbow Electronics MAX9217 User Manual

General Description

The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable input determines when the video or control data is serialized.

The MAX9217 pairs with the MAX9218 deserializer to form a complete digital video serial link. Interconnect can be controlled-impedance PC board traces or twistedpair cable. Proprietary data encoding reduces EMI and provides DC balance. DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The LVDS output is internally terminated with 100Ω.

ESD tolerance is specified for ISO 10605 with ±10kV contact discharge and ±30kV air discharge.

The MAX9217 operates from a +3.3V core supply and features a separate input supply for interfacing to 1.8V to 3.3V logic levels. This device is available in 48-lead Thin QFN and TQFP packages and is specified from

-40°C to +85°C.

Applications

Navigation System Display

In-Vehicle Entertainment System

Video Camera

LCD Displays

Features

♦ Proprietary Data Encoding for DC Balance and

Reduced EMI

♦ Control Data Sent During Video Blanking

♦ Five Control Data Inputs Are Single-Bit-Error

Tolerant

♦ Programmable Phase-Shifted LVDS Signaling

Reduces EMI

♦ Output Common-Mode Filter Reduces EMI

♦ Greater than 10m STP Cable Drive

♦ Wide ±2% Reference Clock Tolerance

♦ ISO 10605 ESD Protection

♦ Separate Input Supply Allows Interface to 1.8V to

3.3V Logic

♦ +3.3V Core Supply

♦ Space-Saving Thin QFN and TQFP Packages

♦ -40°C to +85°C Operating Temperature

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

________________________________________________________________ Maxim Integrated Products 1

Pin Configurations

Ordering Information

19-3558; Rev 1; 4/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*EP = Exposed pad.

PART TEMP RANGE

PINPACKAGE

MAX9217ECM -40°C to +85°C 48 TQFP C48-5

MAX9217ETM -40°C to +85°C 48 Thin QFN-EP* T4866-1

PKG

CODE

TOP VIEW

GND

CCIN

RGB_IN10 RGB_IN11 RGB_IN12 RGB_IN13 RGB_IN14 RGB_IN15 RGB_IN16 RGB_IN17 CNTL_IN0 CNTL_IN1

RGB_IN9

RGB_IN8

RGB_IN7

RGB_IN6

RGB_IN5

RGB_IN4

4847464544434241403938

1314151617181920212223

GND

CNTL_IN3

CNTL_IN2

MAX9217

CNTL_IN4

CNTL_IN5

TQFP

RGB_IN3

RGB_IN2

CNTL_IN6

CNTL_IN7

RGB_IN1

RGB_IN0

DE_IN

CNTL_IN8

VCCGND

MOD0

PCLK_IN

RNG0 RNG1 V

CCLVDS

OUT+ OUTLVDS GND LVDS GND CMF PWRDWN V

CCPLL

PLL GND MOD1

GND

CCIN

RGB_IN10 RGB_IN11 RGB_IN12 RGB_IN13 RGB_IN14 RGB_IN15 RGB_IN16 RGB_IN17 CNTL_IN0 CNTL_IN1

RGB_IN9

RGB_IN8

RGB_IN7

RGB_IN6

RGB_IN5

RGB_IN4

4847464544434241403938

1314151617181920212223

GND

CNTL_IN3

CNTL_IN2

THIN QFN-EP

MAX9217

CNTL_IN4

CNTL_IN5

RGB_IN3

RGB_IN2

CNTL_IN6

CNTL_IN7

RGB_IN1

RGB_IN0

DE_IN

CNTL_IN8

VCCGND

MOD0

PCLK_IN

RNG0 RNG1 V

CCLVDS

OUT+ OUTLVDS GND LVDS GND CMF PWRDWN V

CCPLL

PLL GND MOD1

MAX9217

27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

CC_

= +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at

CC_

= +3.3V, TA= +25°C.) (Notes 1, 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CC_

to _GND........................................................-0.5V to +4.0V

Any Ground to Any Ground...................................-0.5V to +0.5V

OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V

OUT+, OUT- Short Circuit to LVDS GND

or V

CCLVDS

.............................................................Continuous

RGB_IN[17:0], CNTL_IN[8:0], DE_IN,

RNG0, RNG1, MOD0, MOD1, PCLK_IN,

PWRDWN, CMF to GND......................-0.5V to (V

CCIN

+ 0.5V)

Continuous Power Dissipation (T

= +70°C) 48-Lead Thin QFN (derate 37mW/°C above +70°C) .2963mW

48-Lead TQFP (derate 20.8mW/°C above +70°C) ....1667mW

ESD Protection

Human Body Model (R

= 1.5kΩ, CS= 100pF)

All Pins to GND.................................................................±2kV

ISO 10605 (R

= 2kΩ, CS= 330pF)

Contact Discharge (OUT+, OUT-) to GND.....................±10kV

Air Discharge (OUT+, OUT-) to GND.............................±30kV

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_, MOD_)

= 1.71V to <3V 0.65V

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I

Input Clamp Voltage V

LVDS OUTPUTS (OUT+, OUT-)

Differential Output Voltage V

Change in VOD Between Complementary Output States

Common-Mode Voltage V

Change in VOS Between Complementary Output States

Output Short-Circuit Current I

Magnitude of Differential Output Short-Circuit Current

Output High-Impedance Current I

∆V

OSD

CCIN

= 1.71V to <3V -0.3 0.3V

CCIN

VIN = -0.3V to (V V

= 1.71V to 3.6V,

CCIN

PWRDWN = high or low

ICL = -18mA -1.5 V

Figure 1 250 335 450 mV

Figure 1 20 mV

Figure 1 1.125 1.29 1.375 V

Figure 1 20 mV

or V

OUT+

= 0 5.5 15 mA

PWRDWN = low or V

= 0

CC_

CCIN

-0.3 +0.8

+ 0.3V),

CCIN

= 0 or 3.6V -15 ±8 +15 mA

OUT-

OUT+ = 0, OUT- = 3.6V

OUT+ = 3.6V, OUT- = 0

-70 +70 µA

-1 +1 µA

CCIN

+ 0.3

CCIN

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

CC_

= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values

are at V

CC_

= +3.3V, TA= +25°C.) (Note 4)

DC ELECTRICAL CHARACTERISTICS (continued)

CC_

= +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at

CC_

= +3.3V, TA= +25°C.) (Notes 1, 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential Output Resistance R

Worst-Case Supply Current

Power-Down Supply Current I

CCW

CCZ

RL = 100Ω ± 1%, C

= 5pF,

continuous 10 transition words, modulation off

(Note 3) 50 µA

3MHz 15 25

5MHz 18 25

10MHz 23 28

20MHz 33 39

35MHz 50 70

78 110 147 Ω

PCLK_IN TIMING REQUIREMENTS

Clock Period t

Clock Frequency f

Clock Frequency Difference from Deserializer Reference Clock

Clock Duty Cycle DC t

Clock Transition Time tR, t

SWITCHING CHARACTERISTICS

Output Rise Time t

Output Fall Time t

Input Setup Time t

Input Hold Time t

Serializer Delay t

PLL Lock Time t

Power-Down Delay t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Figure 2 28.57 333.00 ns

CLK

∆f

CLK

RISE

FALL

SET

HOLD

LOCK

or t

HIGH/tT

Figure 2 2.5 ns

20% to 80%, VOD ≥ 250mV, modulation off, Figure 3

80% to 20%, VOD ≥ 250mV, modulation off, Figure 3

Figure 4 3 ns

Figure 5

Figure 6

Figure 7 1 µs

Figure 2 35 50 65 %

LOW/tT,

3 35 MHz

-2 +2 %

215 350 ps

206 350 ps

3.15 x t

3.2 x t

16385 x

WORST-CASE PATTERN

SUPPLY CURRENT vs. FREQUENCY

MAX9217 toc01

FREQUENCY (MHz)

SUPPLY CURRENT (mA)

3127231915117

335

Typical Operating Characteristics

(TA= +25°C, V

CC_

= +3.3V, RL= 100Ω, modulation off, unless otherwise noted.)

MAX9217

27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

CC_

= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values

are at V

CC_

= +3.3V, TA= +25°C.) (Note 4)

Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground

except V

, ∆VOD, and ∆VOS.

Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production

tested at T

= +25°C.

Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V

CCIN

- 0.3V. PWRDWN is ≤ 0.3V.

Note 4: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.

Peak-to-Peak Output Offset Voltage

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OSp-p

700Mbps data rate, CMF open, Figure 8

700Mbps data rate, CMF 0.1µF to ground, Figure 8

22 70

12 50

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

_______________________________________________________________________________________ 5

Pin Description

PIN NAME FUNCTION

1, 13, 37 GND Input Buffer Supply and Digital Supply Ground

3–10,

39–48

11, 12, 15–21 CNTL_IN[8:0]

14, 38 V

22 DE_IN

23 PCLK_IN

24 MOD0

25 MOD1

26 PLL GND PLL Supply Ground

27 V

28 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.

29 CMF

30, 31 LVDS GND LVDS Supply Ground

32 OUT- Inverting LVDS Serial Data Output

33 OUT+ Noninverting LVDS Serial Data Output

34 V

35 RNG1

36 RNG0

EP GND Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PC board GND.

CCIN

RGB_IN[17:0]

CCPLL

CCLVDS

Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.

LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to GND.

LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN when DE_IN is low. Internally pulled down to GND.

Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.

LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally pulled down to GND.

LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL reference clock. Internally pulled down to GND.

LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled down to GND.

PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.

Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter common-mode switching noise.

LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.

LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.

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