Rainbow Electronics MAX9217 User Manual

General Description

The MAX9217 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reduc­ing the serial data rate. The data enable input determines
when the video or control data is serialized.

The MAX9217 pairs with the MAX9218 deserializer to
form a complete digital video serial link. Interconnect
can be controlled-impedance PC board traces or twisted­pair cable. Proprietary data encoding reduces EMI and
provides DC balance. DC balance allows AC-coupling,
providing isolation between the transmitting and receiv­ing ends of the interface. The LVDS output is internally
terminated with 100Ω.

ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.

The MAX9217 operates from a +3.3V core supply and
features a separate input supply for interfacing to 1.8V
to 3.3V logic levels. This device is available in 48-lead
Thin QFN and TQFP packages and is specified from

-40°C to +85°C.

Applications

Navigation System Display

In-Vehicle Entertainment System

Video Camera

LCD Displays

Features

♦ Proprietary Data Encoding for DC Balance and

Reduced EMI

♦ Control Data Sent During Video Blanking

♦ Five Control Data Inputs Are Single-Bit-Error

Tolerant

♦ Programmable Phase-Shifted LVDS Signaling

Reduces EMI

♦ Output Common-Mode Filter Reduces EMI

♦ Greater than 10m STP Cable Drive

♦ Wide ±2% Reference Clock Tolerance

♦ ISO 10605 ESD Protection

♦ Separate Input Supply Allows Interface to 1.8V to

3.3V Logic

♦ +3.3V Core Supply

♦ Space-Saving Thin QFN and TQFP Packages

♦ -40°C to +85°C Operating Temperature

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

________________________________________________________________ Maxim Integrated Products 1

Pin Configurations

Ordering Information

19-3558; Rev 1; 4/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*EP = Exposed pad.

PART TEMP RANGE

PIN­PACKAGE

MAX9217ECM -40°C to +85°C 48 TQFP C48-5

MAX9217ETM -40°C to +85°C 48 Thin QFN-EP* T4866-1

PKG

CODE

TOP VIEW

GND

V

CCIN

RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
RGB_IN17
CNTL_IN0
CNTL_IN1

RGB_IN9

RGB_IN8

RGB_IN7

RGB_IN6

RGB_IN5

RGB_IN4

4847464544434241403938

1

2

3

4

5

6

7

8

9

10

11

12

1314151617181920212223

GND

CC

V

CNTL_IN3

CNTL_IN2

MAX9217

CNTL_IN4

CNTL_IN5

TQFP

RGB_IN3

RGB_IN2

CNTL_IN6

CNTL_IN7

RGB_IN1

RGB_IN0

DE_IN

CNTL_IN8

VCCGND

37

24

MOD0

PCLK_IN

36

35

34

33

32

31

30

29

28

27

26

25

RNG0
RNG1
V

CCLVDS

OUT+
OUT­LVDS GND
LVDS GND
CMF
PWRDWN
V

CCPLL

PLL GND
MOD1

GND

V

CCIN

RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
RGB_IN17
CNTL_IN0
CNTL_IN1

RGB_IN9

RGB_IN8

RGB_IN7

RGB_IN6

RGB_IN5

RGB_IN4

4847464544434241403938

1

2

3

4

5

6

7

8

9

10

11

12

1314151617181920212223

GND

CC

V

CNTL_IN3

CNTL_IN2

THIN QFN-EP

MAX9217

CNTL_IN4

CNTL_IN5

RGB_IN3

RGB_IN2

CNTL_IN6

CNTL_IN7

RGB_IN1

RGB_IN0

DE_IN

CNTL_IN8

VCCGND

37

24

MOD0

PCLK_IN

36

35

34

33

32

31

30

29

28

27

26

25

RNG0
RNG1
V

CCLVDS

OUT+
OUT­LVDS GND
LVDS GND
CMF
PWRDWN
V

CCPLL

PLL GND
MOD1

MAX9217

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(V

CC_

= +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at

V

CC_

= +3.3V, TA= +25°C.) (Notes 1, 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

V

CC_

to _GND........................................................-0.5V to +4.0V

Any Ground to Any Ground...................................-0.5V to +0.5V

OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V

OUT+, OUT- Short Circuit to LVDS GND

or V

CCLVDS

.............................................................Continuous

RGB_IN[17:0], CNTL_IN[8:0], DE_IN,

RNG0, RNG1, MOD0, MOD1, PCLK_IN,

PWRDWN, CMF to GND......................-0.5V to (V

CCIN

+ 0.5V)

Continuous Power Dissipation (T

A

= +70°C)
48-Lead Thin QFN (derate 37mW/°C above +70°C) .2963mW

48-Lead TQFP (derate 20.8mW/°C above +70°C) ....1667mW

ESD Protection

Human Body Model (R

D

= 1.5kΩ, CS= 100pF)

All Pins to GND.................................................................±2kV

ISO 10605 (R

D

= 2kΩ, CS= 330pF)

Contact Discharge (OUT+, OUT-) to GND.....................±10kV

Air Discharge (OUT+, OUT-) to GND.............................±30kV

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_, MOD_)

V

= 1.71V to <3V 0.65V

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I

Input Clamp Voltage V

LVDS OUTPUTS (OUT+, OUT-)

Differential Output Voltage V

Change in VOD Between
Complementary Output States

Common-Mode Voltage V

Change in VOS Between
Complementary Output States

Output Short-Circuit Current I

Magnitude of Differential Output
Short-Circuit Current

Output High-Impedance Current I

∆V

∆V

I

OSD

IH

IL

IN

CL

OD

OD

OS

OS

OS

OZ

CCIN

V

= 1.71V to <3V -0.3 0.3V

CCIN

VIN = -0.3V to (V
V

= 1.71V to 3.6V,

CCIN

PWRDWN = high or low

ICL = -18mA -1.5 V

Figure 1 250 335 450 mV

Figure 1 20 mV

Figure 1 1.125 1.29 1.375 V

Figure 1 20 mV

V

or V

OUT+

V

= 0 5.5 15 mA

OD

PWRDWN = low
or
V

= 0

CC_

V

CCIN

2V

-0.3 +0.8

+ 0.3V),

CCIN

= 0 or 3.6V -15 ±8 +15 mA

OUT-

OUT+ = 0,
OUT- = 3.6V

OUT+ = 3.6V,
OUT- = 0

-70 +70 µA

-1 +1 µA

CCIN

CCIN

+ 0.3

+ 0.3

CCIN

V

V

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(V

CC_

= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values

are at V

CC_

= +3.3V, TA= +25°C.) (Note 4)

DC ELECTRICAL CHARACTERISTICS (continued)

(V

CC_

= +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at

V

CC_

= +3.3V, TA= +25°C.) (Notes 1, 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential Output Resistance R

Worst-Case Supply Current

Power-Down Supply Current I

I

O

CCW

CCZ

RL = 100Ω ± 1%,
C

= 5pF,

L

continuous 10
transition words,
modulation off

(Note 3) 50 µA

3MHz 15 25

5MHz 18 25

10MHz 23 28

20MHz 33 39

35MHz 50 70

78 110 147 Ω

PCLK_IN TIMING REQUIREMENTS

Clock Period t

Clock Frequency f

Clock Frequency Difference from
Deserializer Reference Clock

Clock Duty Cycle DC t

Clock Transition Time tR, t

SWITCHING CHARACTERISTICS

Output Rise Time t

Output Fall Time t

Input Setup Time t

Input Hold Time t

Serializer Delay t

PLL Lock Time t

Power-Down Delay t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Figure 2 28.57 333.00 ns

T

CLK

∆f

CLK

RISE

FALL

SET

HOLD

SD

LOCK

PD

or t

HIGH/tT

Figure 2 2.5 ns

F

20% to 80%, VOD ≥ 250mV,
modulation off, Figure 3

80% to 20%, VOD ≥ 250mV,
modulation off, Figure 3

Figure 4 3 ns

Figure 4 3 ns

Figure 5

Figure 6

Figure 7 1 µs

Figure 2 35 50 65 %

LOW/tT,

3 35 MHz

-2 +2 %

215 350 ps

206 350 ps

3.15 x
t

T

3.2 x
t

T

16385 x

t

T

mA

ns

ns

WORST-CASE PATTERN

SUPPLY CURRENT vs. FREQUENCY

MAX9217 toc01

FREQUENCY (MHz)

SUPPLY CURRENT (mA)

3127231915117

10

20

30

40

50

60

0

335

Typical Operating Characteristics

(TA= +25°C, V

CC_

= +3.3V, RL= 100Ω, modulation off, unless otherwise noted.)

MAX9217

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(V

CC_

= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values

are at V

CC_

= +3.3V, TA= +25°C.) (Note 4)

Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground

except V

OD

, ∆VOD, and ∆VOS.

Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production

tested at T

A

= +25°C.

Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V

CCIN

- 0.3V. PWRDWN is ≤ 0.3V.

Note 4: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.

Peak-to-Peak Output Offset
Voltage

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

OSp-p

700Mbps data rate,
CMF open, Figure 8

700Mbps data rate,
CMF 0.1µF to ground, Figure 8

22 70

12 50

mV

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

_______________________________________________________________________________________ 5

Pin Description

PIN NAME FUNCTION

1, 13, 37 GND Input Buffer Supply and Digital Supply Ground

2V

3–10,

39–48

11, 12, 15–21 CNTL_IN[8:0]

14, 38 V

22 DE_IN

23 PCLK_IN

24 MOD0

25 MOD1

26 PLL GND PLL Supply Ground

27 V

28 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.

29 CMF

30, 31 LVDS GND LVDS Supply Ground

32 OUT- Inverting LVDS Serial Data Output

33 OUT+ Noninverting LVDS Serial Data Output

34 V

35 RNG1

36 RNG0

EP GND Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PC board GND.

CCIN

RGB_IN[17:0]

CC

CCPLL

CCLVDS

Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.

LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.

LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.

Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.

LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.

LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.

LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled
down to GND.

LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled
down to GND.

PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.

Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.

LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.

LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.

LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.

MAX9217

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

6 _______________________________________________________________________________________

Functional Diagram

Figure 1. LVDS DC Output Load and Parameters

OUT-

RGB_IN

CNTL_IN

DE_IN

PCLK_IN

RNG0
RNG1

PWRDWN

(-) VOS(+)

V

OS

1

INPUT LATCH

0

PLL

DC BALANCE/

ENCODE

TIMING AND CONTROL

OUT+

OUT-

PAR-TO-SER

MAX9217

/ 2

R

L

V

/ 2

R

L

((OUT+) + (OUT-)) / 2

OUT+

OUT-

CMF

MOD0

MOD1

OD

V

OS

GND

V

(-)

OS

OUT+

= |VOS(+) - VOS(-)|

∆V

OS

VOD(+)

V

(-)

OD

(OUT+) - (OUT-)

∆VOD = |VOD(+) - VOD(-)|

V

= 0V

OD

(-)

V

OD

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

_______________________________________________________________________________________ 7

PCLK_IN

Figure 2. Parallel Clock Requirements

Figure 3. Output Rise and Fall Times

Figure 4. Synchronous Input Timing

t

T

V

V

IHmin

ILmax

t

HIGH

t

F

(OUT+) - (OUT-)

80%

t

R

OUT+

OUT-

C

L

t

RISE

t

LOW

R

L

C

L

80%

20%20%

t

FALL

PCLK_IN

RGB_IN[17:0]

CNTL_IN[8:0]

DE_IN

V

V

IHmin

ILmax

V

IHmin

V

ILmax

t

SET

t

HOLD

V

V

IHmin

ILmax

MAX9217

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

8 _______________________________________________________________________________________

Figure 5. Serializer Delay

Figure 6. PLL Lock Time

Figure 7. Power-Down Delay

EXPANDED TIME SCALE

RGB_IN

CNTL_IN

PCLK_IN

OUT_

PWRDWN

(OUT+) - (OUT-)

N

N + 1

HIGH-Z

N + 2

V

ILmax

N - 1

t

SD

t

LOCK

N + 3

N

BIT 0 BIT 19

N + 4

V

OD

= 0V

PCLK_IN

PWRDWN

V

ILmax

t

PD

(OUT+) - (OUT-)

PCLK_IN

HIGH-Z

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

_______________________________________________________________________________________ 9

Detailed Description

The MAX9217 DC-balanced serializer operates at a
parallel clock frequency of 3MHz to 35MHz, serializing
18 bits of parallel video data RGB_IN[17:0] when the
data enable input DE_IN is high, or 9 bits of parallel
control data CNTL_IN[8:0] when DE_IN is low. The
RGB video input data are encoded using 2 overhead
bits, EN0 and EN1, resulting in a serial word length of
20 bits (Table 1). Control inputs are mapped to 19 bits
and encoded with 1 overhead bit, EN0, also resulting in
a 20-bit serial word. Encoding reduces EMI and main-

tains DC balance across the serial cable. Two transition
words, which contain a unique bit sequence, are insert­ed at the transition boundaries of video-to-control and
control-to-video phases.

Control data inputs C0 to C4 are mapped to 3 bits each
in the serial control word (Table 2). At the deserializer,
2 or 3 bits at the same state determine the state of the
recovered bit, providing single bit-error tolerance for
C0 to C4. Control data that may be visible if an error
occurs, such as VSYNC and HSYNC, can be connect­ed to these inputs. Control data inputs C5 to C8 are
mapped to 1 bit each.

Figure 8. Peak-to-Peak Output Offset Voltage

Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.

Table 1. Serial Video Phase Word Format

Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.

Table 2. Serial Control Phase Word Format

OUT-

OUT+

((OUT+) + (OUT-)) / 2

V

OS(P-P)

V

OS(P-P)

012345678910111213141516171819

EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17

012345678910111213141516171819

E N 0C0C0C0C1C1C1C2C2C2C3C3C3C4C4C4C5C6C7C8

MAX9217

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

10 ______________________________________________________________________________________

Transition Timing

The transition words require interconnect bandwidth
and displace control data. Therefore, control data is not
sampled (see Figure 9):

• Two clock cycles before DE_IN goes high.

• During the video phase.

• Two clock cycles after DE_IN goes low.

The last sampled control data are latched at the deserial­izer control data outputs during the transition and video
phases. Video data are latched at the deserializer RGB
data outputs during the transition and control phases.

Applications Information

AC-Coupling Benefits

AC-coupling increases the common-mode voltage to
the voltage rating of the capacitor. Two capacitors are
sufficient for isolation, but four capacitors—two at the
serializer output and two at the deserializer input—pro­vide protection if either end of the cable is shorted to a
high voltage. AC-coupling blocks low-frequency
ground shifts and common-mode noise. The MAX9217
serializer can also be DC-coupled to the MAX9218
deserializer.

Figure 10 shows an AC-coupled serializer and deserial­izer with two capacitors per link, and Figure 11 is the
AC-coupled serializer and deserializer with four capaci­tors per link.

Selection of AC-Coupling Capacitors

See Figure 12 for calculating the capacitor values for
AC-coupling, depending on the parallel clock frequen­cy. The plot shows capacitor values for two- and four­capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.125µF capacitors.

Frequency-Range Setting RNG[1:0]

The RNG[1:0] inputs select the operating frequency
range of the MAX9217 serializer. An external clock with­in this range is required for operation. Table 3 shows
the selectable frequency ranges and corresponding
data rates for the MAX9217.

Figure 9. Transition Timing

CONTROL

PHASE

PCLK_IN

CNTL_IN

DE_IN

RGB_IN

= NOT SAMPLED BY PCLK_IN

TRANSITION

PHASE

VIDEO PHASE

TRANSITION

PHASE

CONTROL

PHASE

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

______________________________________________________________________________________ 11

Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link

Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link

V

CC

130Ω

RGB_IN

CNTL_IN

DE_IN

PCLK_IN

RNG0
RNG1

PWRDWN

1

0

INPUT LATCH

PLL

ENCODE

DC BALANCE/

TIMING AND

CONTROL

PAR-TO-SER

OUT

CMF

MOD0

MOD1

*

*

82Ω 82Ω

RNG0

RNG1

MAX9217

CERAMIC RF SURFACE-MOUNT CAPACITOR

*CAPACITORS CAN BE AT EITHER END.

V

CC

130Ω

IN

PLL

TIMING AND

CONTROL

100Ω DIFFERENTIAL STP CABLE

DECODE

DC BALANCE/

MAX9218

1

0

SER-TO-PAR

R/F
OUTEN

RGB_OUT

CNTL_OUT

DE_OUT

PCLK_OUT

REF_IN

PWRDWN

LOCK

130Ω

RGB_IN

CNTL_IN

DE_IN

PCLK_IN

RNG0
RNG1

PWRDWN

1

0

INPUT LATCH

PLL

ENCODE

DC BALANCE/

TIMING AND

CONTROL

PAR-TO-SER

OUT

CMF

MOD0

MOD1

82Ω 82Ω

RNG0

RNG1

MAX9217

CERAMIC RF SURFACE-MOUNT CAPACITOR

130Ω

IN

PLL

TIMING AND

CONTROL

100Ω DIFFERENTIAL STP CABLE

DECODE

DC BALANCE/

MAX9218

1

0

SER-TO-PAR

R/F
OUTEN

RGB_OUT

CNTL_OUT

DE_OUT

PCLK_OUT

REF_IN

PWRDWN

LOCK

MAX9217

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

12 ______________________________________________________________________________________

Phase-Modulation Setting MOD[1:0]

The serial output edges can be phase shifted (modulated)
to reduce EMI. Table 4 shows the available settings for
phase modulation. Two shift amplitudes are available. The
parallel clock frequency should be 10MHz or higher for
the highest amplitude (MOD1 = 1, MOD0 = 0).

Termination

The MAX9217 has an integrated 100Ω output-termina-
tion resistor. This resistor damps reflections from
induced noise and mismatches between the transmis­sion line impedance and termination resistors at the
deserializer input. With PWRDWN = low or with the sup­ply off, the output termination is switched out and the
LVDS output is high impedance.

Common-Mode Filter

The integrated 100Ω output termination is made up of
two 50Ω resistors in series. The junction of the resistors
is connected to the CMF pin for connecting an optional
common-mode filter capacitor. Connect the filter
capacitor to ground close to the MAX9217 as shown in
Figure 13. The capacitor shunts common-mode switch­ing current to ground to reduce EMI.

Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 35MHz

Table 3. Parallel Clock Frequency Range
Select

Table 4. Modulation Rate Function Table

Figure 13. Common-Mode Filter Capacitor Connection

AC-COUPLING CAPACITOR VALUE

vs. PARALLEL CLOCK FREQUENCY

140

125

110

95

80

65

CAPACITOR VALUE (nF)

50

35

20

18 36

FOUR CAPACITORS PER LINK

TWO CAPACITORS PER LINK

333021 24 27

PARALLEL CLOCK FREQUENCY (MHz)

MAX9217 fig12

RNG0 RNG1

0 0 3 to 5 60 to 100

0 1 5 to10 100 to 200

1 0 10 to 20 200 to 400

1 1 20 to 35 400 to 700

PARALLEL

CLOCK (MHz)

SERIAL DATA RATE

(Mbps)

MOD1 MOD0

0 0 0 (off)

0 1 2.5

1 0 4.5

1 1 (reserved)

SIMULATED PEAK POWER

REDUCTION (dB)

OUT+

/ 2

R

O

CMF

R

/ 2

O

OUT-

C

CMF

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

______________________________________________________________________________________ 13

Power-Down and Power-Off

Driving PWRDWN low stops the PLL, switches out the
integrated 100Ω output termination, and puts the output
in high impedance to ground and differentially. With

PWRDWN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or
≥ V

CCIN

- 0.3V, supply current is reduced to 50µA or less.

Driving PWRDWN high starts PLL lock to PCLK_IN and
switches in the 100Ω output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100Ω differen-
tial. The 100Ω integrated termination pulls OUT+ and
OUT- together while the PLL is locking so that VOD= 0V.

If VCC= 0, the output resistor is switched out and the LVDS
outputs are high impedance to ground and differentially.

PLL Lock Time

The PLL lock time is set by an internal counter. The lock
time is 16,385 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.

Input Buffer Supply

The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNG0, RNG1, MOD0, MOD1, PCLK_IN, and
PWRDWN) are powered from V

CCIN

. V

CCIN

can be
connected to a 1.71V to 3.6V supply, allowing logic
inputs with a nominal swing of V

CCIN

. If no power is

applied to V

CCIN

when power is applied to VCC, the

inputs are disabled and PWRDWN is internally driven
low, putting the device in the power-down state.

Power-Supply Circuits and Bypassing

The MAX9217 has isolated on-chip power domains. The
digital core supply (VCC) and single-ended input supply
(V

CCIN

) are isolated but have a common ground (GND).

The PLL has separate power and ground (V

CCPLL

and

V

CCPLL

GND) and the LVDS input also has separate

power and ground (V

CCLVDS

and V

CCLVDS

GND). The
grounds are isolated by diode connections. Bypass each
VCC, V

CCIN

, V

CCPLL

, and V

CCLVDS

pin with high-frequen­cy, surface-mount ceramic 0.1µF and 0.001µF capacitors
in parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.

LVDS Output

The LVDS output is a current source. The voltage swing
is proportional to the termination resistance. The output
is rated for a differential load of 100Ω±1%.

Cables and Connectors

Interconnect for LVDS typically has a differential imped­ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.

Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel­ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.

MAX9217

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

14 ______________________________________________________________________________________

Board Layout

Separate the LVTTL/LVCMOS inputs and LVDS output to
prevent crosstalk. A four-layer PC board with separate
layers for power, ground, and signals is recommended.

ESD Protection

The MAX9217 ESD tolerance is rated for Human Body
Model and ISO 10605. ISO 10605 specifies ESD toler­ance for electronic systems. The Human Body Model
discharge components are CS= 100pF and RD=

1.5kΩ (Figure 14). The ISO 10605 discharge compo­nents are CS= 330pF and RD= 2kΩ (Figure 15).

Chip Information

TRANSISTOR COUNT: 16,608

PROCESS: CMOS

Figure 14. Human Body ESD Test Circuit

Figure 15. ISO 10605 Contact-Discharge ESD Test Circuit

R

D

S

1.5kΩ

DISCHARGE

RESISTANCE

STORAGE
CAPACITOR

DEVICE
UNDER

1MΩ

CHARGE-CURRENT-

DC

LIMIT RESISTOR

C

100pF

HIGH-

VOLTAGE

SOURCE

TEST

R

D

S

2kΩ

DISCHARGE

RESISTANCE

STORAGE
CAPACITOR

DEVICE
UNDER

TEST

50Ω TO 100Ω

CHARGE-CURRENT-

DC

LIMIT RESISTOR

C

330pF

HIGH-

VOLTAGE

SOURCE

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

______________________________________________________________________________________ 15

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages

.)

32L/48L,TQFP.EPS

PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm

21-0054

1

E

2

PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm

21-0054

2

E

2

MAX9217

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages

.)

48L THIN QFN.EPS

PACKAGE OUTLINE, 48L THIN QFN
6x6x0.8mm BODY / 0.4mm LEAD PITCH

NOTE :

1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES.

2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08mm.

3. WARPAGE SHALL NOT EXCEED 0.10 mm.

4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC. (S)

5. REFER TO JEDEC MO-220.

6. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012.
DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

7. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

S

A

A1

A2

b

D

e

E

k

k1

L

L1

N

ND

NE

COMMON DIMENSIONS

O

MIN. NOM. MAX.

S

L

BMY

0.700 0.750 0.800

0.000 -- -- 0.050

0.150 0.200 0.250

5.900 6.000 6.100

5.900 6.000 6.050

0.250 0.350 0.450

0.350 0.450 0.550

0.400 0.500 0.600

0.300 0.400 0.500

0.200 REF.

0.400 TYP.

48

12

12

PKG.
CODE

T4866-1

EXPOSED PAD VARIATONS

D2

MIN. NOM. MAX. MIN. NOM. MAX.

PACKAGE OUTLINE, 48L THIN QFN
6x6x0.8mm BODY / 0.4mm LEAD PITCH

21-0160

E2

4.404.304.204.404.304.20

21-0160

1

A

2

2

A

2