General Description
The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 deserialize three LVDS serial data inputs into
21 single-ended LVCMOS/LVTTL outputs. A parallel rate
LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.
The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 feature programmable DC balance, which
allows isolation between a serializer and deserializer
using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215
serializer.
The MAX9210/MAX9212/MAX9214/MAX9216 have rising-edge output strobes, and when DC balance is not
programmed, are compatible with non-DC-balanced
21-bit deserializers such as the DS90CR216A and
DS90CR218A. The MAX9220/MAX9222 have fallingedge output strobes.
Two frequency versions and two DC balance default conditions are available for maximum replacement flexibility
and compatibility with popular non-DC-balanced deserializers. The transition time of the single-ended outputs is
increased on the low-frequency version parts (MAX9210/
MAX9212/MAX9220) for reduced EMI.
The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 are available in TSSOP and space-saving QFN
packages, and operate over the -40°C to +85°C temperature range.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Features
♦ Programmable DC Balance or Non-DC Balance
♦ DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
♦ As Low as 8MHz Operation
(MAX9210/MAX9212/MAX9220)
♦ Falling-Edge Output Strobe (MAX9220/MAX9222)
♦ Slower Output Transitions for Reduced EMI
(MAX9210/MAX9212/MAX9220)
♦ High-Impedance Outputs when PWRDWN is Low
Allow Output Busing
♦ Pin Compatible with DS90CR216A/DS90CR218A
(MAX9210/MAX9212/MAX9214/MAX9216)
♦ Fail-Safe Inputs in Non-DC-Balanced Mode
♦ 5V Tolerant PWRDWN Input
♦ PLL Requires No External Components
♦ Up to 1.785Gbps Throughput
♦ Separate Output Supply Pins Allow Interface to
1.8V, 2.5V, 3.3V, and 5V Logic
♦ LVDS Inputs Meet IEC 61000-4-2 Level 4 ESD
Requirements
♦ LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS
Standard
♦ Low-Profile 48-Lead TSSOP and Space-Saving
QFN Packages
♦ +3.3V Main Power Supply
♦ -40°C to +85°C Operating Temperature Range
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2864; Rev 1; 8/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*Future product—contact factory for availability.
**EP = Exposed pad.
Functional Diagram and Pin Configurations appear at end
of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX9210ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9210EUM* -40°C to +85°C 48 TSSOP
MAX9212ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9212EUM* -40°C to +85°C 48 TSSOP
MAX9214ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9214EUM -40°C to +85°C 48 TSSOP
MAX9216ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9216EUM* -40°C to +85°C 48 TSSOP
MAX9220ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9220EUM* -40°C to +85°C 48 TSSOP
MAX9222ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9222EUM -40°C to +85°C 48 TSSOP
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, V
CCO
= +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage VID = 0.05V to
1.2V, input common-mode voltage V
CM
= VID/2 to 2.4V - VID/2, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at V
CC
= V
CCO
= +3.3V, VID = 0.2V, VCM= 1.25V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.5V to +4.0V
V
CCO
to GND.........................................................-0.5V to +6.0V
RxIN_, RxCLK IN_ to GND ....................................-0.5V to +4.0V
PWRDWN to GND .................................................-0.5V to +6.0V
DCB/NC to GND.........................................-0.5V to (V
CC
+ 0.5V)
RxOUT_, RxCLK OUT to GND .................-0.5V to (V
CCO
+ 0.5V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TSSOP (derate 16mW/
°
C above +70°C)........ 1282mW
48-Lead Thin QFN
(derate 26.3mW/
°
C above +70°C) ................................2105mW
Storage Temperature Range..............................-65
°
C to +150°C
Junction Temperature ......................................................+150
°
C
ESD Protection
Human Body Model (R
D
= 1.5kΩ, CS= 100pF)
All Pins to GND ................................................................±5kV
IEC 61000-4-2 (R
D
= 330Ω, CS= 150pF) Level 4
Contact Discharge LVDS Inputs (RxIN_, RxCLK IN_)
to GND .............................................................................±8kV
Air Discharge LVDS Inputs (RxIN_, RxCLK IN_)
to GND ...........................................................................±15kV
Lead Temperature (soldering, 10s) .................................+300
°
C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (PWRDWN, DCB/NC)
High-Level Input Voltage V
Low-Level Input Voltage V
Input Current I
Input Clamp Voltage V
SINGLE-ENDED OUTPUTS (RxOUT_, RxCLK OUT)
High-Level Output Voltage V
Low-Level Output Voltage V
High-Impedance Output Current I
Output Short-Circuit Current
Note: Short one output at a time.
LVDS INPUTS
Differential Input High Threshold V
Differential Input Low Threshold V
PWRDWN 2.0 5.5
IH
DCB/NC 2.0
IL
VIN = high or low, PWRDWN = high or low -20 +20 µA
IN
ICL = -18mA -1.5 V
CL
IOH = -100µA
OH
IOH = -2mA
IOL = 100µA 0.1
OL
IOL = 2mA 0.2
PWRDWN = low, V
OZ
I
OS
TH
TL
+ 0.3V)
(V
CCO
V
= 3.0V to 3.6V, V
CCO
V
= 4.5V to 5.5V, V
CCO
V
+
CC
0.3
-0.3 +0.8 V
V
-
CCO
0.1
V
-
CCO
0.25
= -0.3V to
OUT_
= 0V -10 -40
OUT
= 0V -28 -75
OUT
-20 +20 µA
50 mV
-50 mV
V
V
V
mA
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, V
CCO
= +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage VID = 0.05V to
1.2V, input common-mode voltage V
CM
= VID/2 to 2.4V - VID/2, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at V
CC
= V
CCO
= +3.3V, VID = 0.2V, VCM= 1.25V, TA= +25°C.) (Notes 1, 2)
AC ELECTRICAL CHARACTERISTICS
(VCC= V
CCO
= +3.0V to 3.6V, 100mV
P-P
at 200kHz supply noise, CL= 8pF, PWRDWN = high, DCB/NC = high or low, differential
input voltage V
ID
= 0.1V to 1.2V, input common-mode voltage VCM= VID/2 to 2.4V - VID/2, TA= -40°C to +85°C, unless other-
wise noted. Typical values are at V
CC
= V
CCO
= +3.3V, VID = 0.2V, VCM= 1.25V, TA= 25°C.) (Notes 3, 4, 5)
Input Current I
Power-Off Input Current
Input Resistor 1 R
Input Resistor 2 R
POWER SUPPLY
Worst-Case Supply Current I
Power-Down Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IN+, IIN-
I
INO+,
I
INO-
CCW
CCZ
PWRDWN = high or low -25 +25 µA
VCC = V
DCB/NC, PWRDWN = 0V or open
PWRDWN = high or low (Figure 1)
IN1
VCC = V
PWRDWN = high or low (Figure 1)
IN2
VCC = V
CL = 8pF, worst-case
pattern, DC-balanced
mode; V
3.0V to 3.6V, Figure 2
CL = 8pF, worst-case
pattern, non-DCbalanced mode;
= V
V
CC
3.6V, Figure 2
PWRDWN = low 50 µA
= 0V or open,
CCO
= 0V or open (Figure 1)
CCO
= 0V or open (Figure 1)
CCO
CC
CCO
= V
=
CCO
= 3.0V to
-25 +25 µA
42 78 kΩ
246 410 kΩ
16MHz 52 63
34MHz 86 106
66MHz 152 177
20MHz 53 64
33MHz 72 85
40MHz 81 99
66MHz 127 149
85MHz 159 186
mA
Output Rise Time CLHT 0.1 x V
Output Fall Time CHLT 0.9 x V
RxIN Skew Margin RSKM
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC-balanced mode,
Figure 4 (Note 6)
Non-DC-balanced mode,
Figure 4 (Note 6)
CCO
CCO
to 0.9 x V
to 0.1 x V
, Figure 3 2.2 3.15 3.9 ns
CCO
, Figure 3 1.3 2.12 2.9 ns
CCO
16MHz 2560 3137
34MHz 900 1327
66MHz 330 685
20MHz 2500 3300
40MHz 960 1448
85MHz 330 685
ps
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
MAX9210 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
65503520
60
80
100
120
140
160
40
580
MAX9214
DC-BALANCED MODE
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
MAX9210 toc02
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
75 9060
30
45
60
80
100
120
160
40
15
140
MAX9214
NON-DC-BALANCED MODE
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
CCO
)
MAX9210 toc03
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
4.54.03.53.0
2
3
4
5
1
2.5 5.0
MAX9214
NON-DC-BALANCED MODE
t
F
t
R
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC= V
CCO
= +3.0V to 3.6V, 100mV
P-P
at 200kHz supply noise, CL= 8pF, PWRDWN = high, DCB/NC = high or low, differential
input voltage V
ID
= 0.1V to 1.2V, input common-mode voltage VCM= VID/2 to 2.4V - VID/2, TA= -40°C to +85°C, unless other-
wise noted. Typical values are at V
CC
= V
CCO
= +3.3V, VID = 0.2V, VCM= 1.25V, TA= 25°C.) (Notes 3, 4, 5)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
and VTL.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 4: C
L
includes probe and test jig capacitance.
Note 5: RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP.
Note 6: RSKM measured with
≤
150ps cycle-to-cycle jitter on RxCLK IN.
Typical Operating Characteristics
(VCC= V
CCO
= +3.3V, CL= 8pF, PWRDWN = high, differential input voltage VID = 0.2V, input common-mode voltage VCM= 1.2V,
T
A
= +25°C, unless otherwise noted.)
RxCLK OUT High Time RCOH Figures 5a, 5b
RxCLK OUT Low Time RCOL Figures 5a, 5b
RxOUT Setup to RxCLK OUT RSRC Figures 5a, 5b
RxOUT Hold from RxCLK OUT RHRC Figures 5a, 5b
RxCLK IN to RxCLK OUT Delay RCCD Figures 6a, 6b 4.9 6.17 8.1 ns
Deserializer Phase-Locked
Loop Set
Deserializer Power-Down Delay RPDD Figure 8 100 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RPLLS Figure 7
0.35 x
RCOP
0.35 x
RCOP
0.30 x
RCOP
0.45 x
RCOP
0.4 x
RCOP
0.44 x
RCOP
0.35 x
RCOP
0.48 x
RCOP
32800 x
RCIP
ns
ns
ns
ns
ns
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________ 5
Pin Description
PIN
TSSOP QFN
NAME FUNCTION
1, 2, 4, 5, 45, 46, 47
RxOUT14–
RxOUT20
Channel 2 Single-Ended Outputs
3, 25, 32, 38, 44 19, 26, 32, 38, 45 GND Ground
6 48 DCB/NC
LVTTL/LVCMOS DC-Balance Programming Input:
MAX9210: pulled up to V
CC
MAX9212: pulled down to GND
MAX9214: pulled up to V
CC
MAX9216: pulled down to GND
MAX9220: pulled up to V
CC
MAX9222: pulled up to V
CC
See Table 1.
7, 13, 18 1, 7, 12 LVDS GND LVDS Ground
8 2 RxIN0- Inverting Channel 0 LVDS Serial Data Input
9 3 RxIN0+ Noninverting Channel 0 LVDS Serial Data Input
10 4 RxIN1- Inverting Channel 1 LVDS Serial Data Input
11 5 RxIN1+ Noninverting Channel 1 LVDS Serial Data Input
12 6 LVDS V
CC
LVDS Supply Voltage
14 8 RxIN2- Inverting Channel 2 LVDS Serial Data Input
15 9 RxIN2+ Noninverting Channel 2 LVDS Serial Data Input
16 10 RxCLK IN- Inverting LVDS Parallel Rate Clock Input
17 11 RxCLK IN+ Noninverting LVDS Parallel Rate Clock Input
19, 21 13, 15 PLL GND PLL Ground
20 14 PLL V
CC
PLL Supply Voltage
22 16 PWRDWN
5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally
pulled down to GND. Outputs are high impedance when
PWRDWN = low or open.
23 17 RxCLK OUT
Parallel Rate Clock Single-Ended Output.
MAX9210/MAX9212/MAX9214/MAX9216, rising edge
strobe. MAX9220/MAX9222, falling edge strobe.
24, 26, 27, 29, 30, 31, 33
RxOUT0–
RxOUT6
Channel 0 Single-Ended Outputs
28, 36, 48 22, 30, 42 V
CCO
Output Supply Voltage
34, 35, 37, 39, 40, 41, 43
RxOUT7–
RxOUT13
Channel 1 Single-Ended Outputs
42 36 V
CC
Digital Supply Voltage
— EP EP Exposed Paddle. Solder to ground.
39, 40, 41, 43, 44, 46, 47
18, 20, 21, 23, 24, 25, 27
28, 29, 31, 33, 34, 35, 37
Detailed Description
The MAX9210/MAX9212/MAX9220 operate at a parallel
clock frequency of 8MHz to 34MHz in DC-balanced
mode and 10MHz to 40MHz in non-DC-balanced
mode. The MAX9214/MAX9216/MAX9222 operate at a
parallel clock frequency of 16MHz to 66MHz in DC-balanced mode and 20MHz to 85MHz in non-DC-balanced mode. The transition times of the single-ended
outputs are increased on the MAX9210/MAX9212/
MAX9220 for reduced EMI.
DC-balanced or non-DC-balanced operation is controlled by the DCB/NC pin (see Table 1 for DCB/NC
default settings and operating modes). In non-DC-balanced mode, each channel deserializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are deserialized every clock cycle (7 data bits + 2 DCbalance bits). The highest data rate in DC-balanced
mode for the MAX9214, MAX9216, and MAX9222 is
66MHz x 9 = 594Mbps. In non-DC-balanced mode, the
maximum data rate is 85MHz x 7 = 595Mbps.
DC Balance
Data coding by the MAX9209/MAX9211/MAX9213/
MAX9215 serializers (which are companion devices to
the MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 deserializers) limits the imbalance of ones
and zeros transmitted on each channel. If +1 is assigned
to each binary 1 transmitted and -1 is assigned to each
binary 0 transmitted, the variation in the running sum of
assigned values is called the digital sum variation
(DSV). The maximum DSV for the data channels is 10.
At most, 10 more zeros than ones, or 10 more ones than
zeros, are transmitted. The maximum DSV for the clock
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
6 _______________________________________________________________________________________
Figure 1. LVDS Input Circuits
Table 1. DC-Balance Programming
Figure 2. Worst-Case Test Pattern
DEVICE DCB/NC
MAX9210
MAX9212
MAX9214
MAX9216
MAX9220
MAX9222
High or open DC balanced 8 to 34
Low
High DC balanced 8 to34
Low or open
High or open DC balanced 16 to 66
Low
High DC balanced 16 to 66
Low or open
High or open DC balanced 8 to 34
Low
High or open DC balanced 16 to 66
Low
OUTPUT STROBE
EDGE
Rising
Rising
Rising
Rising
Falling
Falling
OPERATING MODE
Non-DC balanced 10 to 40
Non-DC balanced 10 to 40
Non-DC balanced 20 to 85
Non-DC balanced 20 to 85
Non-DC balanced 10 to 40
Non-DC balanced 20 to 85
V
CC
OPERATING
FREQUENCY (MHz)
RIN2
RCIP
RxIN_ + OR
RxCLK IN+
RIN1
RIN1
RxIN_ - OR
RxCLK IN-
RxIN_ + OR
RxCLK IN+
RIN1
RIN1
RxIN_ - OR
RxCLK IN-
NON-DC-BALANCED MODE DC-BALANCED MODE
RxCLK OUT
ODD RxOUT
EVEN RxOUT
RISING EDGE STROBE SHOWN.
VCC - 0.3V
1.2V
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________ 7
Figure 4. LVDS Receiver Input Skew Margin
Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times
Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times
Figure 6a. Rising-Edge Clock-IN to Clock-OUT Delay
Figure 6b. Falling-Edge Clock-IN to Clock-OUT Delay
RxOUT_ OR
Figure 3. Output Load and Transition Times
Figure 7. Phase-Locked Loop Set Time
RxCLK OUT
8pF
RxOUT_ OR
RxCLK OUT
90%90%
10%10%
CHLTCLHT
IDEAL SERIAL BIT TIME
RSKM RSKM
IDEAL
MIN MAX
INTERNAL STROBE
IDEAL
1.3V
1.1V
RCIP
RxCLK OUT
RxOUT_
2.0V
2.0V
SETUP
2.0V
0.8V 0.8V
RCOHRCOL
RHRCRSRC
2.0V
HOLD
2.0V
RCIP
RxCLK OUT
RxOUT_
2.0V 2.0V
0.8V 0.8V 0.8V
RCOH RCOL
RHRCRSRC
2.0V
SETUP
2.0V
HOLD
RxCLK IN
RxCLK OUT
VID = 0
RCCD
1.5V
+
RxCLK IN
-
RxCLK OUT
VID = 0
RCCD
1.5V
2V
PWRDWN
3V
V
CC
RxCLK IN
RxCLK OUT
HIGH-Z
RPLLS
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
8 _______________________________________________________________________________________
channel is five. Limiting the DSV and choosing the correct coupling capacitors maintains differential signal
amplitude and reduces jitter due to droop on AC-coupled links.
To obtain DC balance on the data channels, the serializer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel input data bits to indicate to the MAX9210/
MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
deserializers whether the data bits are inverted (see
Figures 9 and 10). The deserializer restores the original
state of the parallel data. The LVDS clock signal alternates duty cycles of 4/9 and 5/9, which maintain DC
balance.
Figure 9. Deserializer Serial Input in Non-DC-Balanced Mode
Figure 10. Deserializer Serial Input in DC-Balanced Mode
Figure 8. Power-Down Delay
PWRDWN
RxCLK IN
RxOUT_
RxCLK OUT
+
RxCLK IN
TxIN14TxIN15
RxIN2
TxIN7TxIN8
RxIN1
0.8V
RPDD
HIGH-Z
TxIN9TxIN13 TxIN10TxIN11TxIN12
CYCLE N + 1CYCLE NCYCLE N - 1
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN7TxIN8
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN7TxIN8TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN1
TxIN0
RxIN0
TxIN_ IS DATA FROM THE SERIALIZER.
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN0TxIN1
TxIN0TxIN1TxIN2TxIN6 TxIN3TxIN4TxIN5
+
RxCLK IN
CYCLE N + 1CYCLE NCYCLE N - 1
DCB2DCA2
RxIN2
DCB1DCA1
RxIN1
DCA0
DCB0
RxIN0
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN7TxIN8
TxIN0TxIN1
TxIN16TxIN17TxIN18DCA2 TxIN19TxIN20DCB2
TxIN15
TxIN14
TxIN9TxIN10TxIN11DCA1 TxIN12TxIN13DCB1
TxIN8
TxIN7
TxIN2TxIN3TxIN4DCA0 TxIN5TxIN6DCB0
TxIN1
TxIN0
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________ 9
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be eliminated by increasing the receiver common-mode voltage
range by AC-coupling. AC-coupling increases the common-mode voltage range of an LVDS receiver to nearly
the voltage rating of the capacitor. The typical LVDS driver output is 350mV centered on an offset voltage of
1.25V, making single-ended output voltages of 1.425V
and 1.075V. An LVDS receiver accepts signals from 0V
to 2.4V, allowing approximately ±1V common-mode difference between the driver and receiver on a DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V - 0V =
1.075V). Common-mode voltage differences may be
due to ground potential variation or common-mode
noise. If there is more than ±1V of difference, the receiver is not guaranteed to read the input signal correctly
and may cause bit errors. AC-coupling filters low-frequency ground shifts and common-mode noise and
passes high-frequency data. A common-mode voltage
difference up to the voltage rating of the coupling
capacitor (minus half the differential swing) is tolerated.
DC-balanced coding of the data is required to maintain
the differential signal amplitude and limit jitter on an ACcoupled link. A capacitor in series with each output of
the LVDS driver is sufficient for AC-coupling. However,
two capacitors—one at the serializer output and one at
the deserializer input—provide protection in case either
end of the cable is shorted to a high voltage.
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
causes signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
Figure 11. DC-Coupled Link, Non-DC-Balanced Mode
MAX9209
MAX9211
MAX9213
MAX9215
TxOUT
MAX9210
MAX9212
MAX9214
MAX9216
TRANSMISSION LINE
RxIN
MAX9220
MAX9222
TxIN
PWRDWN
TxCLK IN
7
7
7
7 : 1
7 : 1
7 : 1
PLL
21:3 SERIALIZER 3:21 DESERIALIZER
TxCLK OUT
100Ω
100Ω
100Ω
100Ω
RxCLK IN
1 : 7
1 : 7
1 : 7
PLL
7
7
7
RxOUT
PWRDWN
RxCLK OUT
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
10 ______________________________________________________________________________________
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (RT), the LVDS driver
output resistor (RO), and the series AC-coupling capacitors (C). The RC time constant for two equal-value
series capacitors is (C x (RT + RO))/2 (Figure 12). The
RC time constant for four equal-value series capacitors
is (C x (RT + RO))/4 (Figure 13).
RTis required to match the transmission line impedance (usually 100Ω) and ROis determined by the LVDS
driver design (the minimum differential output resistance of 78Ω for the MAX9209/MAX9211/MAX9213/
MAX9215 serializers is used in the following example).
This leaves the capacitor selection to change the system time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = - (2 x t
B
x DSV) / (ln (1 - D) x (RT+ RO)) (Eq 1)
where:
C = AC-coupling capacitor (F)
t
B
= bit time (s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
RT= termination resistor (Ω)
RO= output resistance (Ω)
Equation 1 is for two series capacitors (Figure 12). The
bit time (tB) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capacitors (Figure 13).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = - (2 x t
B
x DSV) / (ln (1 - D) x (RT+ RO))
C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.0773µF
Figure 12. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
TxIN
PWRDWN
TxCLK IN
MAX9209
MAX9211
MAX9213
MAX9215
7
(7 + 2):1
7
(7 + 2):1
7
(7 + 2):1
PLL
21:3 SERIALIZER 3:21 DESERIALIZER
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
SERIALIZER INSTEAD OF THE DESERIALIZER.
TxOUT
100Ω
100Ω
100Ω
100Ω
TxCLK OUT
RxCLK IN
RxIN
MAX9210
MAX9212
MAX9214
MAX9216
MAX9220
MAX9222
1:(9 - 2)
1:(9 - 2)
1:(9 - 2)
PLL
7
7
7
RxOUT
PWRDWN
RxCLK OUT
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
______________________________________________________________________________________ 11
Jitter due to droop is proportional to the droop and
transition time:
tJ= tTx D (Eq 2)
where:
tJ= jitter (s)
tT= transition time (s) (0% to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
tJ= 1ns x 0.02
tJ= 20ps
The transition time in a real system depends on the frequency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 13) is:
C = - (4 x tBx DSV) / (ln (1 - D) x (RT+ RO)) (Eq 3)
Fail-Safe
The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 have fail-safe LVDS inputs in non-DC-balanced mode (Figure 1). Fail-safe drives the outputs low
when the corresponding LVDS input is open, undriven
and shorted, or undriven and parallel terminated. The
fail-safe on the LVDS clock input drives all outputs low.
Fail-safe does not operate in DC-balanced mode.
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting
LVDS inputs are internally connected to +1.2V through
42kΩ (min) to provide biasing for AC-coupling (Figure 1).
A frequency-detection circuit on the clock input detects
when the input is not switching, or is switching at low
frequency. In this case, all outputs are driven low. To
prevent switching due to noise when the clock input is
not driven, bias the clock input to differential +15mV by
connecting a 10kΩ ±1% pullup resistor between the
noninverting input and VCC, and a 10kΩ ±1% pulldown
resistor between the inverting input and ground. These
MAX9209
Figure 13. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
MAX9211
MAX9213
MAX9215
MAX9210
MAX9212
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
TxOUT
RxIN
MAX9214
MAX9216
MAX9220
MAX9222
7
(7 + 2):1
7
TxIN
PWRDWN
TxCLK IN
(7 + 2):1
7
(7 + 2):1
PLL
21:3 SERIALIZER 3:21 DESERIALIZER
TxCLK OUT
100Ω
100Ω
100Ω
100Ω
RxCLK IN
1:(9 - 2)
1:(9 - 2)
1:(9 - 2)
PLL
7
7
7
RxOUT
PWRDWN
RxCLK OUT
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
12 ______________________________________________________________________________________
bias resistors, along with the 100Ω ±1% tolerance termination resistor, provide +15mV of differential input.
However, the +15mV bias causes degradation of
RSKM proportional to the slew rate of the clock input.
For example, if the clock transitions 250mV in 500ps,
the slew rate of 0.5mV/ps reduces RSKM by 30ps.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data
inputs open. In non-DC balanced mode, the input failsafe circuit drives the corresponding outputs low and no
pullup or pulldown resistors are needed. In DC-balanced
mode, at each unused LVDS data input, pull the inverting
input up to V
CC
using a 10kΩ resistor, and pull the nonin-
verting input down to ground using a 10kΩ resistor. Do
not connect a termination resistor. The pullup and pulldown resistors drive the corresponding outputs low and
prevent switching due to noise.
PWRDWN
Driving PWRDWN low puts the outputs in high impedance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs controlled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid contention of the bused outputs.
Input Clock and PLL Lock Time
There is no required timing sequence for the application or reapplication of the parallel rate clock (RxCLK
IN) relative to PWRDWN, or to a power-supply ramp for
proper PLL lock. The PLL lock time is set by an internal
counter. The maximum time to lock is 32,800 clock
periods. Power and clock should be stable to meet the
lock time specification. When the PLL is locking, the
outputs are low.
Power-Supply Bypassing
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
VCC, V
CCO
, PLL VCC, and LVDS VCCpin with high-frequency, surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the
supply pin.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input signals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended.
IEC 61000-4-2 Level 4 ESD Protection
The IEC 61000-4-2 standard specifies ESD tolerance
for electronic systems. The IEC 61000-4-2 model
(Figure 14) specifies a 150pF capacitor that is discharged into the device through a 330Ω resistor. The
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 LVDS inputs are rated for IEC 61000-4-2
level 4 (±8kV contact discharge and ±15kV air discharge). IEC 61000-4-2 discharges higher peak current
and more energy than the HBM due to the lower series
resistance and larger capacitor. The HBM (Figure 15)
specifies a 100pF capacitor that is discharged into the
device through a 1.5kΩ resistor. All pins are rated for
±5kV HBM.
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 15. Human Body ESD Test Circuit
R1
50Ω TO 100ΩR2330kΩ
R1
1MΩ
R2
1.5kΩ
HIGH-
DC
CHARGE-CURRENT-
LIMIT RESISTOR
100pF
CHARGE-CURRENT-
DC
LIMIT RESISTOR
150pF
HIGH-
VOLTAGE
SOURCE
C
S
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
VOLTAGE
SOURCE
C
S
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
5V Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
GND. DCB/NC is not 5V tolerant. The input voltage
range for DCB/NC is nominally ground to VCC.
Normally, DCB/NC is connected to VCCor ground.
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degradation of the serial data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
V
CCO
Output Supply and Power Dissipation
The outputs have a separate supply (V
CCO
) for interfacing to systems with 1.8V to 5V nominal input logic levels.
The DC Electrical Characteristics table gives the maxi-
mum supply current for V
CCO
= 3.6V with 8pF load at
several switching frequencies with all outputs switching in
the worst-case switching pattern. The approximate incremental supply current for V
CCO
other than 3.6V with the
same 8pF load and worst-case pattern can be calculated
using:
II= CTVI 0.5fCx 21 (data outputs)
+ CTVIfCx 1 (clock output)
where:
II= incremental supply current
CT= total internal (C
INT
) and external (CL) load capacitance
VI= incremental supply voltage
fC= output clock switching frequency
The incremental current is added to (for V
CCO
> 3.6V)
or subtracted from (for V
CCO
< 3.6V) the DC Electrical
Characteristics table maximum supply current. The
internal output buffer capacitance is C
INT
= 6pF. The
worst-case pattern switching frequency of the data outputs is half the switching frequency of the output clock.
In the following example, the incremental supply current is
calculated for V
CCO
= 5.5V, fC= 34MHz, and CL= 8pF:
VI= 5.5V - 3.6V = 1.9V
CT= C
INT
+ CL= 6pF + 8pF = 14pF
where:
I
I
= CTVI 0.5FCx 21 (data outputs) + CTVIfCx 1 (clock
output)
II= (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x
34MHz)
II= 9.5mA + 0.9mA = 10.4mA
The maximum supply current in DC-balanced mode for
V
CC
= V
CCO
= 3.6V at fC= 34MHz is 106mA (from the
DC Electrical Characteristics table). Add 10.4mA to get
the total approximate maximum supply current at V
CCO
= 5.5V and VCC= 3.6V.
If the output supply voltage is less than V
CCO
= 3.6V,
the reduced supply current can be calculated using the
same formula and method.
At high switching frequency, high supply voltage, and
high capacitive loading, power dissipation can exceed
the package power dissipation rating. Do not exceed
the maximum package power dissipation rating. See
the Absolute Maximum Ratings for maximum package
power dissipation capacity and temperature derating.
Rising- or Falling-Edge Output Strobe
The MAX9210/MAX9212/MAX9214/MAX9216 have a
rising-edge output strobe, which latches the parallel
output data into the next chip on the rising edge of
RxCLK OUT. The MAX9220/MAX9222 have a fallingedge output strobe, which latches the parallel output
data into the next chip on the falling edge of RxCLK
OUT. The deserializer output strobe polarity does not
need to match the serializer input strobe polarity. A
deserializer with rising or falling edge output strobe can
be driven by a serializer with a rising edge input strobe.
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
______________________________________________________________________________________ 13
Functional Diagram
DATA
CHANNEL 0
SERIAL-TO-
PARALLEL
CONVERTER
DATA
CHANNEL 1
SERIAL-TO-
PARALLEL
CONVERTER
DATA
CHANNEL 2
SERIAL-TO-
PARALLEL
CONVERTER
REFERENCE
CLOCK
GENERATOR
RxOUT0–6
RxOUT7–13
RxOUT14–20
RxCLK OUT
RxIN0+
RxIN0-
RxIN1+
RxIN1-
RxIN2+
RxIN2-
RxCLK IN+
RxCLK IN-
DCB/NC
PWRDWN
LVDS DATA
RECEIVER 0
LVDS DATA
RECEIVER 1
LVDS DATA
RECEIVER 2
LVDS CLOCK
RECEIVER
STROBE
STROBE
STROBE
7x/9x
PLL
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
14 ______________________________________________________________________________________
Pin Configurations
Chip Information
MAX9210 TRANSISTOR COUNT: 10,248
MAX9212 TRANSISTOR COUNT: 10,248
MAX9214 TRANSISTOR COUNT: 10,248
MAX9216 TRANSISTOR COUNT: 10,248
MAX9220 TRANSISTOR COUNT: 10,248
MAX9222 TRANSISTOR COUNT: 10,248
PROCESS: CMOS
TOP VIEW
RxOUT17
RxOUT18
GND
RxOUT20
DCB/NC
LVDS GND
RxIN0+
RxIN1+
LVDS V
LVDS GND
RxIN2-
RxIN2+
RxCLK IN-
RxCLK IN+
LVDS GND
PLL GND
PLL V
PLL GND
PWRDWN
RxCLK OUT
RxOUT0
1
2
3
4
5
6
7
8
9
MAX9210
10
MAX9212
MAX9214
11
MAX9216
MAX9220
12
CC
CC
MAX9222
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CCO
RxOUT16
RxOUT15
RxOUT14RxOUT19
GND
RxOUT13
V
CC
RxOUT12RxIN0-
RxOUT11
RxOUT10RxIN1-
GND
RxOUT9
V
CCO
RxOUT8
RxOUT7
RxOUT6
GND
RxOUT5
RxOUT4
RxOUT3
V
CCO
RxOUT2
RxOUT1
GND
LVDS GND
RxIN0-
RxIN0+
RxIN1-
RxIN1+
LVDS V
LVDS GND
RxIN2-
RxIN2+
RxCLK INRxCLK IN+
LVDS GND
RxOUT20
RxOUT19
CC
PLL V
GND
PLL GND
PWRDWN
DCB/NC
4847464544434241403938
1
2
3
4
5
6
CC
7
8
9
10
11
12
1314151617181920212223
PLL GND
CCO
RxOUT18
RxOUT17
V
MAX9210
MAX9212
MAX9214
MAX9216
MAX9220
MAX9222
EXPOSED PAD
GND
RxOUT0
RxCLK OUT
RxOUT16
RxOUT15
RxOUT1
RxOUT2
RxOUT14
GND
CCO
V
RxOUT3
RxOUT13
37
36
35
34
33
32
31
30
29
28
27
26
25
24
RxOUT4
V
CC
RxOUT12
RxOUT11
RxOUT10
GND
RxOUT9
V
CCO
RxOUT8
RxOUT7
RxOUT6
GND
RxOUT5
QFN
TSSOP
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
______________________________________________________________________________________ 15
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
23 1
N
TOP VIEW
b
e
D
SIDE VIEW
0.25
HE
BOTTOM VIEW
SEE DETAIL A
A1
A2
(;)
A
SEATING PLANE
DETAIL A
PARTING
LINE
C
L
END VIEW
c
WITH PLATING
BASE METAL
;
b
b1
SECTION C-C
c1
c
48L TSSOP.EPS
NOTES:
1.
DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH.
2.
MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE.
3.
CONTROLLING DIMENSION: MILLIMETERS.
4.
THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED.
5.
"N" REFERS TO NUMBER OF LEADS.
6.
THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO
PARALLEL PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE
SPECIFIED DISTANCE FROM (-C-) IN THE DIRECTION INDICATED.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 48L TSSOP, 6.1mm
BODY
21-0155
REV.DOCUMENT CONTROL NO.APPROVAL
A
1
2
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
16 ______________________________________________________________________________________
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
D/2
D2
C
L
k
D2/2
b
D
A1AA2
E/2
E
(NE-1) X e
DETAIL A
e
(ND-1) X e
C
L
L
e
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0144
E2/2
C
E2
L
k
L
C
L
L
e
REV.
B
32, 44, 48L QFN .EPS
1
2
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED.
TOTAL NUMBER OF LEADS ARE 44.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
DOCUMENT CONTROL NO.APPROVAL
21-0144
REV.
2
B
2
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