Rainbow Electronics MAX8760 User Manual

General Description
The MAX8760 is a dual-phase, Quick-PWM™, step­down controller for 6-bit VID AMD Mobile Turion™ 64 CPU core supplies. Dual-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. The quick-PWM control scheme provides instantaneous response to fast-load current steps. The MAX8760 includes active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output capacitance requirements.
The MAX8760 is intended for two different notebook CPU core applications: stepping down the battery directly or stepping down the 5V system supply to create the core voltage. The single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage con­version (stepping down the 5V system supply instead of the battery) at a higher switching frequency provides the minimum possible physical size.
The MAX8760 complies with AMD’s desktop and mobile CPU specifications. The switching regulator features soft­start and power-up sequencing, and soft-shutdown. The MAX8760 also features independent four-level logic inputs for setting the suspend voltage (S0, S1).
The MAX8760 includes output undervoltage protection, thermal protection, and voltage regulator power-OK (VROK) output. When any of these protection features detect a fault, the controller shuts down.
The MAX8760 is available in a low-profile, 40-pin 6mm x 6mm thin QFN package. For other CPU platforms, refer to the pin-to-pin compatible MAX1544, MAX1519/MAX1545, and MAX1532/MAX1546/MAX1547 data sheets.
Applications
6-Bit VID AMD Mobile Turion 64 CPU
Multiphase CPU Core Supply
Voltage-Positioned Step-Down Converters
Servers/Desktop Computers
Features
Dual-Phase, Quick-PWM Controller
±0.75% V
OUT
Accuracy Over Line, Load, and
Temperature (1.3V)
Active Voltage Positioning with Adjustable Gain
and Offset
6-Bit On-Board DAC: 0.375V to 1.55V Output
Adjust Range
Selectable 100kHz/200kHz/300kHz/550kHz
Switching Frequency
4V to 28V Battery Input Voltage Range
Adjustable Slew-Rate Control
Drives Large Synchronous Rectifier MOSFETs
Undervoltage and Thermal-Fault Protection
Power Sequencing and Timing
Selectable Suspend Voltage
Soft-Start and Soft-Shutdown
Selectable Single- or Dual-Phase Pulse Skipping
D4 D5
OAIN+ OAIN-
GNDS
CCV GND
FB CCI
DHS
LXS
BSTS
CMP CMN
CSN
12345678910
30 29 28 27 26 25 24
23 22 21
CSP
DLS
PGND
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
S1
OFS
REF
ILIM
V
CC
S0
SUS
TON
TIME
DLM
DHM
LXM
BSTM
VROKD0D1D2D3
V
DD
THIN QFN
MAX8760
TOP VIEW
V+
SKIP
SHDN
Pin Configuration
Ordering Information
PART
PIN-PACKAGE
MAX8760ETL
40 Thin QFN 6mm x 6mm
MAX8760ETL+
40 Thin QFN 6mm x 6mm
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
________________________________________________________________ Maxim Integrated Products 1
19-3721; Rev 0; 5/05
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
Turion is a trademark of AMD.
+Denotes lead-free package.
TEMP RANGE
-40°C to +100°C
-40°C to +100°C
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND ..............................................................-0.3V to +30V
V
CC
to GND..............................................................-0.3V to +6V
V
DD
to PGND............................................................-0.3V to +6V
SKIP, SUS, D0–D5 to GND.......................................-0.3V to +6V
ILIM, FB, OFS, CCV, CCI, REF, OAIN+,
OAIN- to GND.........................................-0.3V to (V
CC
+ 0.3V)
CMP, CSP, CMN, CSN, GNDS to GND ......-0.3V to (V
CC
+ 0.3V)
TON, TIME, VROK, S0–S1 to GND..............-0.3V to (V
CC
+ 0.3V)
SHDN to GND (Note 1)...........................................-0.3V to +18V
DLM, DLS to PGND....................................-0.3V to (V
DD
+ 0.3V)
BSTM, BSTS to GND ..............................................-0.3V to +36V
DHM to LXM ...........................................-0.3V to (V
BSTM
+ 0.3V)
LXM to BSTM............................................................-6V to +0.3V
DHS to LXS..............................................-0.3V to (V
BSTS
+ 0.3V)
LXS to BSTS .............................................................-6V to +0.3V
GND to PGND .......................................................-0.3V to +0.3V
REF Short-Circuit Duration .........................................Continuous
Continuous Power Dissipation (T
A
= +70°C)
40-Pin 6mm
6mm Thin QFN
(derate 23.2mW/°C above +70°C)...............................1.860W
Operating Temperature Range .........................-40°C to +100°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, VCC= VDD= V
SHDN
= V
SKIP
= VS0= VS1= 5V, VFB= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS =
SUS = GNDS = D0–D5 = GND, T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Battery voltage, V+ 4 28
Input Voltage Range
V
CC
, V
DD
4.5 5.5
V
DAC codes ≥ 1V -10
DC Output Voltage Accuracy (Note 2)
V+ = 4.5V to 28V, includes load regulation error
DAC codes from
0.375V to 1V
-15
mV
Line Regulation Error VCC = 4.5V to 5.5V, V+ = 4.5V to 28V 5 mV
FB, GNDS -2 +2
Input Bias Current
I
OFS
OFS
µA
OFS Input Range 02V
V
OUT
/V
OFS;
V
OFS
= V
OFS, VOFS
= 0 to 1V
OFS Gain A
OFS
V
OUT
/V
OFS;
V
OFS
= V
OFS
- V
REF, VOFS
= 1V to 2V
V/V
GNDS Input Range -20
mV
GNDS Gain A
GNDS
V
OUT
/V
GNDS
V/V
1000kHz nominal, R
TIME
= 15k
500kHz nominal, R
TIME
= 30k
250kHz nominal, R
TIME
= 60k
TIME Frequency Accuracy f
TIME
Startup and shutdown, R
TIME
= 30k
kHz
Note 1: SHDN may be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables
fault protection and overlapping operation.
+10
+15
IFB, I
GNDS
-0.1 +0.1
-0.129 -0.125 -0.117
-0.129 -0.125 -0.117
0.97 0.99 1.01
900 1000 1100
460 500 540
225 250 275
125
+200
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC= VDD= V
SHDN
= V
SKIP
= VS0= VS1= 5V, VFB= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS =
SUS = GNDS = D0–D5 = GND, T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TON = GND (550kHz)
TON = REF (300kHz)
TON = open (200kHz)
On-Time (Note 3) t
ON
V+ = 12V, V
FB
= V
CCI
= 1.2V
TON = V
CC
(100kHz)
ns
TON = GND
Minimum Off-Time (Note 3)
)
TON = VCC, open, or REF
ns
BIAS AND REFERENCE
Quiescent Supply Current (VCC)I
CC
Measured at VCC, FB forced above the
mA
Quiescent Supply Current (VDD)I
DD
Measured at VDD, FB forced above the regulation point
<1 5 µA
Quiescent Battery Supply Current (V+)
I
V+
Measured at V+ 25 40 µA
Shutdown Supply Current (VCC) Measured at VCC, SHDN = GND 4 10 µA
Shutdown Supply Current (VDD) Measured at VDD, SHDN = GND <1 5 µA
Shutdown Battery Supply Current (V+)
Measured at V+, SHDN = GND, V
CC
= VDD = 0V or 5V
<1 5 µA
Reference Voltage V
REF
V
CC
= 4.5V to 5.5V, I
REF
= 0
V
Reference Load Regulation ∆V
REFIREF
= -10µA to 100µA -10
mV
FAULT PROTECTION
Output Overvoltage Protection Threshold
V
OVP
V
Output Overvoltage Propagation Delay
t
OVP
FB forced 2% above trip threshold 10 µs
Output Undervoltage Protection Threshold
V
UVP
Measured at FB with respect to unloaded output voltage
67 70 73 %
Output Undervoltage Propagation Delay
t
UVP
FB forced 2% below trip threshold 10 µs
Lower threshold (undervoltage)
-12 -10 -8
VROK Threshold
Measured at FB with respect to unloaded output voltage
Upper threshold (overvoltage) SKIP = V
CC
+8
%
t
OFF(MIN
regulation point, OAIN- = FB, V
= 1.3V
OAI N +
155 180 205
320 355 390
475 525 575
920 1000 1140
1.990 2.000 2.010
300 375
400 480
1.70 3.20
2.00
+10 +12
+10
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC= VDD= V
SHDN
= V
SKIP
= VS0= VS1= 5V, VFB= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS =
SUS = GNDS = D0–D5 = GND, T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Undervoltage Fault and VROK Transition Blanking Time
t
BLANK
Measured from the time when FB reaches the voltage set by the DAC code; clock speed set by R
TIME
(Note 4)
24 Clks
VROK Startup Delay
Measured from the time when FB first reaches the voltage set by the DAC code after startup
357ms
VROK Delay t
VROK
FB forced 2% outside the VROK trip threshold
10 µs
VROK Output Low Voltage I
SINK
= 3mA 0.4 V
VROK Leakage Current High state, VROK forced to 5.5V 1 µA
VCC Undervoltage Lockout Threshold
)
Rising edge, hysteresis = 90mV, PWM disabled below this level
4.0
4.4 V
Thermal-Shutdown Threshold T
SHDN
Hysteresis = 10°C
°C
CURRENT LIMIT AND BALANCE
Current-Limit Threshold Voltage (Positive, Default)
V
LIMIT
CMP - CMN, CSP - CSN; ILIM = V
CC
28 30 32 mV
V
ILIM
= 0.2V 8 10 12
Current-Limit Threshold Voltage (Positive, Adjustable)
V
LIMIT
V
ILIM
= 1.5V 73 75 77
mV
Current-Limit Threshold Voltage (Negative)
)
CMP - CMN, CSP - CSN; ILIM = VCC, SKIP = V
CC
-41 -36 -31 mV
Current-Limit Threshold Voltage (Zero Crossing)
V
ZERO
CMP - CMN, CSP - CSN; SKIP = GND 1.5 mV
CMP, CMN, CSP, CSN Input Ranges
02V
CMP, CMN, CSP, CSN Input Current
V
CSP
= V
CSN
= 0 to 5V -2 +2 µA
Secondary Driver-Disable Threshold
V
CSP
3
VCC -
0.4
V
ILIM Input Current I
ILIM
V
ILIM
= 0 to 5V 0.1
nA
Current-Limit Default Switchover Threshold
V
ILIM
3
VCC -
0.4
V
Current-Balance Offset
)
(V
CMP
- V
CMN
) - (V
CSP
- V
CSN
); I
CCI
= 0,
-20mV < (V
CMP
- V
CMN
) < 20mV,
1.0V < V
CCI
< 2.0V
-2 +2 mV
V
UVLO(VCC
4.25
+160
CMP - CMN, CSP - CSN
V
LIMIT(NEG
V
OS(IBAL
VCC - 1
VCC - 1
200
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC= VDD= V
SHDN
= V
SKIP
= VS0= VS1= 5V, VFB= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS =
SUS = GNDS = D0–D5 = GND, T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Current-Balance Transconductance
)
µS
GATE DRIVERS
DH_ Gate-Driver On-Resistance R
ON(DH)
BST_ - LX_ forced to 5V 1.0 4.5
High state (pullup) 1.0 4.5
DL_ Gate-Driver On-Resistance R
ON(DL)
Low start (pulldown) 0.4 2
DH_ Gate-Driver Source/Sink Current
I
DH
DH_ forced to 2.5V, BST_ - LX_ forced to 5V
1.6 A
DL_ Gate-Driver Sink Current
)
DL_ forced to 5V 4 A
DL_ Gate-Driver Source Current
)
DL_ forced to 2.5V 1.6 A
DL_ rising 35
Dead Time t
DEAD
DH_ rising 26
ns
VOLTAGE-POSITIONING AMPLIFIER
Input Offset Voltage V
OS
-1 +1 mV
Input Bias Current I
BIAS
OAIN+, OAIN- 0.1
nA
Op Amp Disable Threshold V
OAIN-
3
VCC -
0.4
V
Common-Mode Input Voltage Range
V
CM
Guaranteed by CMRR test 0 2.5 V
Common-Mode Rejection Ratio CMRR V
OAIN+
= V
OAIN-
= 0 to 2.5V 70
dB
Power-Supply Rejection Ratio PSRR VCC = 4.5V to 5.5V 75
dB
Large-Signal Voltage Gain A
OA
RL = 1k to VCC/2 80
dB
VCC - V
FBH
77
Output Voltage Swing
|V
OAIN+
- V
OAIN-
| 10mV,
R
L
= 1k to VCC/2
V
FBL
47
mV
Input Capacitance 11 pF
Gain-Bandwidth Product 3
MHz
Slew Rate 0.3 V/µs
Capacitive-Load Stability No sustained oscillations
pF
LOGIC AND I/O
SHDN Input High Voltage V
IH
0.8 V
SHDN Input Low Voltage V
IL
0.4 V
SHDN No-Fault Threshold V
SHDN
To enable no-fault mode 12 15 V
High 2.7 REF 1.2 2.3Three-Level Input Logic Levels SUS, SKIP
Low 0.8
V
Logic Input Current SHDN, SKIP, SUS -1 +1 µA
D0–D5 Logic Input High Voltage
1.6 V
G
m(IBAL
I
DL(SINK
I
DL(SOURCE
400
VCC - 1
115
100
112
400
200
300
200
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC= VDD= V
SHDN
= V
SKIP
= VS0= VS1= 5V, VFB= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS =
SUS = GNDS = D0–D5 = GND, T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
D0–D5 Logic Input Low Voltage 0.8 V
D0–D5 Input Current D0–D5 -2 +2 µA
High
V
CC
-
0.4
Open
REF
Four-Level Input Logic Levels TON, S0 and S1
Low 0.4
V
Four-Level Input Current TON, S0 and S1 forced to GND or V
CC
-3 +3 µA
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, VCC= VDD= V
SHDN
= V
SKIP
= VS0= VS1= 5V, VFB= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS =
SUS = GNDS = D0–D5 = GND, T
A
= -40°C to +100°C, unless otherwise specified.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
PWM CONTROLLER
Battery voltage, V+ 4 28
Input Voltage Range
V
CC
, V
DD
4.5 5.5
V
DAC codes ≥ 1V -13
DC Output Voltage Accuracy (Note 2)
V+ = 4.5V to 28V, includes load regulation error
DAC codes from
0.375V to 1V
-20
mV
OFS Input Range 02V
V
OUT
/V
OFS;
V
OFS
= V
OFS, VOFS
= 0 to 1V
OFS GAIN A
OFS
V
OUT
/V
OFS;
V
OFS
= V
OFS
- V
REF, VOFS
= 1V to 2V
V/V
GNDS Gain A
GNDS
V
OUT
/V
GNDS
V/V
1000kHz nominal, R
TIME
= 15k
500kHz nominal, R
TIME
= 30k
TIME Frequency Accuracy f
TIME
250kHz nominal, R
TIME
= 60k
kHz
TON = GND (550kHz)
TON = REF (300kHz)
TON = open (200kHz)
On-Time (Note 3) t
ON
V+ = 12V, V
FB
= V
CCI
= 1.2V
TON = V
CC
(100kHz)
ns
TON = GND
Minimum Off-Time (Note 3)
)
TON = VCC, open, or REF
ns
3.15 3.85
1.65 2.35
t
OFF(MIN
-0.131 -0.115
-0.131 -0.115
0.94 1.01
880 1120
450 550
220 280
150 210
315 395
470 580
910 1150
+13
+20
380
490
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC= VDD= V
SHDN
= V
SKIP
= VS0= VS1= 5V, VFB= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS =
SUS = GNDS = D0–D5 = GND, T
A
= -40°C to +100°C, unless otherwise specified.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
BIAS AND REFERENCE
Quiescent Supply Current (VCC)
I
CC
Measured at VCC, FB forced above the
3.2 mA
Quiescent Supply Current (VDD)
I
DD
Measured at VDD, FB forced above the regulation point
20 µA
Quiescent Battery Supply Current (V+)
I
V+
Measured at V+ 50 µA
Shutdown Supply Current (VCC)
Measured at VCC, SHDN = GND 20 µA
Shutdown Supply Current (VDD)
Measured at VDD, SHDN = GND 20 µA
Shutdown Battery Supply Current (V+)
Measured at V+, SHDN = GND, V
CC
= VDD = 0V or 5V
20 µA
Reference Voltage V
REF
VCC = 4.5V to 5.5V, I
REF
= 0
V
FAULT PROTECTION
Output Undervoltage Protection Threshold
V
UVP
Measured at FB with respect to unloaded output voltage
67 73 %
Lower threshold (undervoltage)
-13 -7
VROK Threshold
Measured at FB with respect to unloaded output voltage
Upper threshold (overvoltage), SKIP = V
CC
+7
%
VROK Startup Delay
Measured from the time when FB first reaches the voltage set by the DAC code after startup
3ms
VCC Undervoltage Lockout Threshold
)
Rising edge, hysteresis = 90mV, PWM disabled below this level
V
CURRENT LIMIT AND BALANCE
Current-Limit Threshold Voltage (Positive, Default)
V
LIMIT
CMP - CMN, CSP - CSN; ILIM = V
CC
27 33 mV
V
ILIM
= 0.2V 7 13
Current-Limit Threshold Voltage (Positive, Adjustable)
V
LIMIT
CMP - CMN, CSP - CSN
V
ILIM
= 1.5V 72 78
mV
Current-Limit Threshold Voltage (Negative)
)
CMP - CMN, CSP - CSN; ILIM = VCC, SKIP = V
CC
-30 -42 mV
Current-Balance Offset
)
(V
CMP
- V
CMN
) - (V
CSP
- V
CSN
); I
CCI
= 0,
-20mV < (V
CMP
- V
CMN
) < 20mV,
1.0V < V
CCI
< 2.0V
-3 +3 mV
GATE DRIVERS
DH_ Gate-Driver On-Resistance
)
BST_ - LX_ forced to 5V 4.5
regulation point, OAIN- = FB, V
V
UVLO(VCC
V
LIMIT(NEG
V
OS(IBAL
R
ON(DH
OAI N +
= 1.3V
1.985 2.015
+13
3.90 4.45
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC= VDD= V
SHDN
= V
SKIP
= VS0= VS1= 5V, VFB= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS =
SUS = GNDS = D0–D5 = GND, T
A
= -40°C to +100°C, unless otherwise specified.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
High state (pullup) 4.5
DL_ Gate-Driver On-Resistance R
ON(DL)
Low start (pulldown) 2
VOLTAGE-POSITIONING AMPLIFIER
Input Offset Voltage V
OS
mV
Common-Mode Input Voltage Range
V
CM
Guaranteed by CMRR test 0 2.5 V
VCC - V
FBH
300
Output Voltage Swing
|V
OAIN+
- V
OAIN-
| 10mV,
R
L
= 1k to VCC/2
V
FBL
200
mV
LOGIC AND I/O
SHDN Input High Voltage V
IH
0.8 V
SHDN Input Low Voltage V
IL
0.4 V
High 2.7 REF 1.2 2.3Tri-Level Input Logic Levels SUS, SKIP
Low 0.8
V
D0–D5 Logic Input High Voltage
1.6 V
D0–D5 Logic Input Low Voltage 0.8 V
High
V
CC
-
0.4
Open
REF
Four-Level Input Logic Levels TON, S0 and S1
Low 0.4
V
Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. When pulse skipping, the output slightly rises
(<0.5%) when transitioning from continuous conduction to no load.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DHM and DHS pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in­circuit times may be different due to MOSFET switching speeds.
Note 4: The output fault-blanking time is measured from the time when FB reaches the regulation voltage set by the DAC code.
During normal operation (SUS = GND), the regulation voltage is set by the VID DAC inputs (D0–D5). During suspend mode (SUS = REF or high), the regulation voltage is set by the suspend DAC inputs (S0 and S1).
Note 5: Specifications to T
A
= -40°C and +100°C are guaranteed by design and are not production tested.
-2.0 +2.0
3.15 3.85
1.65 2.35
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
_______________________________________________________________________________________ 9
OUTPUT VOLTAGE vs. LOAD CURRENT
(V
OUT
= 1.30V)
MAX8760 toc01
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
302010
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.18 040
VIN = 12V SKIP = V
CC
OR REF
EFFICIENCY vs. LOAD CURRENT
(V
OUT
= 1.30V)
MAX8760 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
101
60
70
80
90
100
50
0.01 100
VIN = 7V
VIN = 12V
VIN = 20V
SKIP = REF SKIP = V
CC
OUTPUT VOLTAGE vs. LOAD CURRENT
(V
OUT
= 1.00V)
MAX8760 toc03
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
302010
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
0.88 040
VIN = 12V SKIP = V
CC
OR REF
EFFICIENCY vs. LOAD CURRENT
(V
OUT
= 1.00V)
MAX8760 toc04
LOAD CURRENT (A)
EFFICIENCY (%)
101
60
70
80
90
100
50
0.01 100
VIN = 7V
VIN = 12V
VIN = 20V
SKIP = REF SKIP = V
CC
OUTPUT VOLTAGE vs. LOAD CURRENT
(V
OUT
= 0.80V)
MAX8760 toc05
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
15105
0.76
0.78
0.80
0.82
0.84
0.74 020
VIN = 12V SKIP = REF or GND
EFFICIENCY vs. LOAD CURRENT
(V
OUT
= 0.80V)
MAX8760 toc06
LOAD CURRENT (A)
EFFICIENCY (%)
101
60
70
80
90
100
50
0.01 100
VIN = 7V
VIN = 20V
SKIP = REF SKIP = GND
SWITCHING FREQUENCY
vs. LOAD CURRENT
MAX8760 toc07
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)
3010 20
100
200
300
400
0
040
V
OUT
= 1V (NO LOAD)
SKIP MODE (SKIP = REF)
FORCED-PWM (SKIP = VCC)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (FORCED-PWM MODE)
MAX8760 toc08
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
20 255 1510
30
60
90
120
150
0
030
I
IN
SKIP = V
CC
ICC + I
DD
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (PULSE SKIPPING)
MAX8760 toc09
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
20 255 1510
0.5
1.0
1.5
2.0
2.5
3.0
0
030
IIN
SKIP = REF
ICC + I
DD
Typical Operating Characteristics
(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D5 set for 1.5V (SUS = GND), S0 and S1 set for 1V (SUS = V
CC
), OFS = GND, TA= +25°C, unless otherwise specified.)
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
10 ______________________________________________________________________________________
OUTPUT OFFSET VOLTAGE
vs. OFS VOLTAGE
MAX8760 toc10
OFS VOLTAGE (V)
OUTPUT OFFSET VOLTAGE (mV)
1.50.5 1.0
-100
-50
0
50
100
150
-150 0 2.0
UNDEFINED REGION
REFERENCE VOLTAGE
DISTRIBUTION
MAX8760 toc11
REFERENCE VOLTAGE (V)
SAMPLE PERCENTAGE (%)
2.0051.995
2.000
10
20
30
40
50
0
1.990 2.010
SAMPLE SIZE = 100
CURRENT-BALANCE OFFSET
VOLTAGE DISTRIBUTION
MAX8760 toc12
OFFSET VOLTAGE (mV)
SAMPLE PERCENTAGE (%)
1.25-1.25
0
10
20
30
40
50
0
-2.50 2.50
SAMPLE SIZE = 100
CURRENT-LIMIT THRESHOLD
DISTRIBUTION
MAX8760 toc13
CURRENT LIMIT (mV)
SAMPLE PERCENTAGE (%)
10.59.5
10.0
10
20
30
40
50
0
9.0 11.0
V
ILIM
= 0.20V
SAMPLE SIZE = 100
60
-40
0.1 10 100 1k1 10k
VOLTAGE-POSITIONING AMPLIFIER
GAIN AND PHASE vs. FREQUENCY
-20
-10
0
-30
MAX8760 toc14
FREQUENCY (Hz)
GAIN (dB)
PHASE (DEGREES)
10
20
30
40
50
180
-180
-108
-72
-36
-144
0
36
72
108
144
GAIN
PHASE
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D5 set for 1.5V (SUS = GND), S0 and S1 set for 1V (SUS = V
CC
), OFS = GND, TA= +25°C, unless otherwise specified.)
VPS AMPLIFIER OFFSET VOLTAGE
vs. COMMON-MODE VOLTAGE
MAX8760 toc15
COMMON-MODE VOLTAGE (V)
34
1 205
OFFSET VOLTAGE (µV)
20
40
60
80
100
120
140
160
180
0
VPS AMPLIFIER
DISABLED
INDUCTOR CURRENT DIFFERENCE
vs. LOAD CURRENT
MAX8760 toc16
LOAD CURRENT (A)
30 40
10
20
050
I
L(CS)
- I
L(CM)
(A)
0.2
0.4
0.6
0.8
1.0
0
R
SENSE
= 1m
SKIP = REF
SKIP = V
CC
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 11
POWER-UP SEQUENCE
MAX8760 toc17
0
3.3V
0
0
0
1.46V
0
B
C
D
E
A
2ms/div
A. SHDN, 5V/div B. VROK, 5V/div C. 1.5V OUTPUT, 1V/div
R
LOAD
= 75m
D. I
L1
, 10A/div
E. I
L2
, 10A/div
SOFT-SHUTDOWN WAVEFORMS
MAX8760 toc19
3.3V
10A
10A
1.46V
B
C
D
A
200µs/div
A. SHDN, 5V/div B. 1.5V OUTPUT, 500mV/div C. I
L1
, 10A/div
D. I
L2
, 10A/div
R
LOAD
= 75m
1.30V LOAD TRANSIENT (10A TO 30A LOAD)
MAX8760 toc20
15A
1.48A
1.44V
5A
5A
15A
B
C
A
20µs/div
A. I
L1
, 10A/div
B. I
L2
, 10A/div
C. OUTPUT VOLTAGE, 20mV/div
OFFSET TRANSITION
MAX8760 toc21
0.2V
5A
5A
0
1.5V
B
C
D
A
20µs/div
A. V
OFS
= 0 TO 200mV, 0.2V/div
B. V
OUT
= 1.500V TO 1.475V, 20mV/div
C. I
L1
, 10A/div
D. I
L2
, 10A/div
10A LOAD
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D5 set for 1.5V (SUS = GND), S0 and S1 set for 1V (SUS = V
CC
), OFS = GND, TA= +25°C, unless otherwise specified.)
SOFT-START
MAX8760 toc18
3.3V
0
0
0
0
B
C
D
A
200µs/div
A. SHDN, 5V/div B. 1.5V OUTPUT, 500mV/div C. I
L1
, 10A/div
D. I
L2
, 10A/div
R
LOAD
= 75m
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D5 set for 1.5V (SUS = GND), S0 and S1 set for 1V (SUS = V
CC
), OFS = GND, TA= +25°C, unless otherwise specified.)
SUSPEND TRANSITION
(DUAL-PHASE PWM OPERATION)
MAX8760 toc22
3.3V
2.5A
2.5A
0
1.5V
1.0V
B
C
D
A
40µs/div
A. SUS, 5V/div B. V
OUT
= 1.5V TO 1.0V, 0.5V/div
C. I
L1
, 10A/div
D. I
L2
, 10A/div
5A LOAD, SKIP = V
CC
, R
TIME
= 64.9k
SUSPEND TRANSITION
(SINGLE-PHASE SKIP OPERATION)
MAX8760 toc23
3.3V
0
10A
0
10A
0
1.5V
1.0V
B
C
D
A
100µs/div
A. SUS, 5V/div B. V
OUT
= 1.5V TO 1.0V, 0.5V/div
C. I
L1
, 10A/div
D. I
L2
, 10A/div
5A LOAD, C
OUT
= (4) 680µF, SKIP = SUS, R
TIME
= 64.9k
SINGLE-PHASE SKIP TO DUAL-PHASE
PWM TRANSITION
MAX8760 toc24
5V
0
0
1.5V
B
C
D
A
20µs/div
A. SKIP = V
CC
TO GND, 5V/div B. 1.5V OUTPUT, 50mV/div C. I
L1
, 10A/div
D. I
L2
, 10A/div
2A LOAD
DUAL-PHASE SKIP TO DUAL-PHASE
PWM TRANSITION
MAX8760 toc25
5V 2V
0
0
1.5V
B
C
D
A
20µs/div
A. SKIP = V
CC
TO REF, 5V/div B. 1.5V OUTPUT, 50mV/div C. I
L1
, 10A/div
D. I
L2
, 10A/div
2A LOAD
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 13
100mV DAC CODE TRANSITION
MAX8760 toc26
3.3V
0
5A
5A
1.5V
1.4V
B
C
D
A
20µs/div
A. D1, 5V/div B. V
OUT
= 1.50V TO 1.40V, 100mV/div
C. I
L1
, 10A/div
D. I
L2
, 10A/div
10A LOAD
400mV DAC CODE TRANSITION
MAX8760 toc27
3.3V
0
1.5V
1.1V
B
C
D
A
40µs/div
A. D3, 5V/div B. V
OUT
= 1.50V TO 1.10V, 0.5V/div
C. I
L1
, 10A/div
D. I
L2
, 10A/div
10A LOAD
5A
5A
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D5 set for 1.5V (SUS = GND), S0 and S1 set for 1V (SUS = V
CC
), OFS = GND, TA= +25°C, unless otherwise specified.)
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
14 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 TIME
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 150k to 15k resistor sets the clock from 100kHz to 1MHz, f
SLEW
= 500kHz x 30k/R
TIME
. During
startup and shutdown, the internal slew-rate clock operates at 1/4 the programmed rate.
2 TON
On-Time Selection Control Input. This four-level input sets the K-factor value used to determine the DH_ on-time (see the On-Time One-Shot (TON) section): GND = 550kHz, REF = 300kHz, OPEN = 200kHz, V
CC
= 100kHz
3 SUS
Suspend Input. SUS is a tri-level logic input. When the controller detects on-transition on SUS, the controller slews the output voltage to the new voltage level determined by SUS, S0, S1, and D0–D5. The controller blanks VROK during the transition and another 24 R
TIME
clock cycles after the new DAC code
is reached. Connect SUS as follows to select which multiplexer sets the nominal output voltage:
3.3V or V
CC
(high) = Suspend mode; S0, S1 low-range suspend code (Table 5) REF = Suspend mode; S0, S1 high-range suspend code (Table 5) GND = Normal operation; D0–D5 VID DAC code (Table 4)
4, 5 S0, S1
Suspend-Mode Voltage-Select Inputs. S0, S1 are four-level digital inputs that select the suspend mode VID code (Table 5) for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered to the DAC (see the Internal Multiplexers section), overriding any other voltage setting (Figure 3).
6 SHDN
S hutd ow n C ontr ol Inp ut. Thi s i np ut cannot w i thstand the b atter y vol tag e. C onnect to V
C C
for nor m al op er ati on. C onnect to g r ound to p ut the IC i nto i ts 1µA ( typ ) shutd ow n state. D ur i ng the tr ansi ti on fr om nor m al op er ati on to shutd ow n, the outp ut vol tag e r am p s d ow n at 4 ti m es the outp ut- vol tag e sl ew r ate p r og r am m ed b y the TIM E p i n. In shutd ow n m od e, D LM and D LS ar e for ced to V
D D
to cl am p the outp ut to g r ound . For ci ng SH DN to 12V
~ 15V d i sab l es b oth over vol tag e p r otecti on and und er vol tag e p r otecti on ci r cui ts, d i sab l es over l ap op er ati on, and cl ear s the faul t l atch. D o not connect SH DN to > 15V .
7 OFS
Voltage-Divider Input for Offset Control. For 0 < V
OFS
< 0.8V, 0.125 times the voltage at OFS is
subtracted from the output. For 1.2V < V
OFS
< 2V, 0.125 times the difference between REF and OFS is
added to the output. Voltages in the 0.8V < V
OFS
< 1.2V range are undefined. The controller disables the
offset amplifier during suspend mode (SUS = REF or high).
8 REF
2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor. The reference can source 100µA for external loads. Loading REF degrades output voltage accuracy according to the REF load regulation error.
9 ILIM
Current-Limit Adjustment. The current-limit threshold defaults to 30mV if ILIM is connected to V
CC
. In
adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM over a
0.2V to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately V
CC
-
10 V
CC
Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V) with a series 10 resistor. Bypass to GND with a 1µF or greater ceramic capacitor, as close to the IC as possible.
11 GND Analog Ground. Connect the MAX8760’s exposed pad to analog ground.
12 CCV
Voltage Integrator Capacitor Connection. Connect a 47pF to 1000pF (150pF typ) capacitor from CCV to analog ground (GND) to set the integration time constant.
13 GNDS
Ground Remote-Sense Input. Connect GNDS directly to the CPU ground-sense pin. GNDS internally connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the regulator ground to the load ground.
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 15
PIN NAME FUNCTION
14 CCI
Current Balance Compensation. Connect a 470pF capacitor between CCI and FB. See the Current Balance Compensation section.
15 FB
Feedback Input. FB is internally connected to both the feedback input and the output of the voltage­positioning op amp. See the Setting Voltage Positioning section to set the voltage-positioning gain.
16 OAIN-
Op Amp Inverting Input and Op Amp Disable Input. When using the internal op amp for additional voltage-positioning gain, connect to the negative terminal of current-sense resistor through a resistor as described in the Setting Voltage Positioning section. Connect OAIN- to V
CC
to disable the op amp. The
logic threshold to disable the op amp is approximately V
CC
- 1V.
17 OAIN+
Op Amp Noninverting Input. When using the internal op amp for additional voltage-positioning gain, connect to the positive terminal of current-sense resistor through a resistor as described in the Setting Voltage Positioning section.
18 SKIP
Pulse-Skipping Select Input. When pulse skipping, the controller blanks the VROK upper threshold:
3.3V or V
CC
(high) = Dual-phase forced-PWM operation REF = Dual-phase pulse-skipping operation GND = Single-phase pulse-skipping operation
19–24 D5–D0
Low-Voltage VID DAC Code Inputs. The D0–D5 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the output voltage is set by the VID code indicated by the logic-level voltages on D0–D5. In suspend mode (Table 5, SUS = REF or high), the decoded state of the four-level S0, S1 inputs sets the output voltage.
25 VROK
Open-Drain Power-Good Output. After output voltage transitions, except during power-up and power­down, if OUT is in regulation then VROK is high impedance. The controller blanks VROK whenever the slew-rate control is active (output voltage transitions). VROK is forced low in shutdown. A pullup resistor on VROK causes additional finite shutdown current. During power-up, VROK includes a 3ms (min) delay after the output reaches the regulation voltage.
26 BSTM
Main Boost Flying Capacitor Connection. An optional resistor in series with BSTM allows the DHM pullup current to be adjusted.
27 LXM Main Inductor Connection. LXM is the internal lower supply rail for the DHM high-side gate driver.
28 DHM Main High-Side Gate-Driver Output. Swings LXM to BSTM.
29 DLM
M ai n Low - S i d e G ate- D r i ver O utp ut. D LM sw i ng s fr om P GN D to V
D D
. D LM i s for ced hi g h after the M AX 8760
p ow er s d ow n.
30 V
DD
Supply Voltage Input for the DLM and DLS Gate Drivers. Connect to the system supply voltage (4.5V to
5.5V). Bypass V
DD
to PGND with a 2.2µF or greater ceramic capacitor as close to the IC as possible.
31 PGND Power Ground. Ground connection for low-side gate drivers DLM and DLS.
Pin Description (continued)
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
16 ______________________________________________________________________________________
Detailed Description
Dual 180° Out-of-Phase Operation
The two phases in the MAX8760 operate 180° out-of­phase (SKIP = REF or high) to minimize input and output filtering requirements, reduce electromagnetic interfer­ence (EMI), and improve efficiency. This effectively low­ers component count—reducing cost, board space, and component power requirements—making the MAX8760 ideal for high-power, cost-sensitive applications.
Typically, switching regulators provide transfer power using only one phase instead of dividing the power among several phases. In these applications, the input capacitors must support high-instantaneous current requirements. The high-RMS ripple current can lower efficiency due to I
2
R power loss associated with the input capacitor’s effective series resistance (ESR). Therefore, the system typically requires several low-ESR input capacitors in parallel to minimize input voltage ripple, to reduce ESR-related power losses, and to meet the nec­essary RMS ripple current rating.
With the MAX8760, the controller shares the current between two phases that operate 180° out-of-phase, so the high-side MOSFETs never turn on simultaneously during normal operation. The instantaneous input cur­rent of either phase is effectively cut in half, resulting in reduced input voltage ripple, ESR power loss, and RMS ripple current (see the Input Capacitor Selection sec­tion). As a result, the same performance can be achieved with fewer or less-expensive input capacitors. Table 1 lists component selection for standard multi­phase selections and Table 2 is a list of component suppliers.
Transient Overlap Operation
When a transient occurs, the response time of the con­troller depends on how quickly it can slew the inductor current. Multiphase controllers that remain 180 degrees out-of-phase when a transient occurs actually respond slower than an equivalent single-phase controller. To provide fast transient response, the MAX8760 supports a phase-overlap mode, which allows the dual regula­tors to operate in-phase when heavy-load transients are detected, reducing the response time. After either high­side MOSFET turns off, if the output voltage does not exceed the regulation voltage when the minimum off­time expires, the controller simultaneously turns on both high-side MOSFETs during the next on-time cycle. This maximizes the total inductor current slew rate. The phases remain overlapped until the output voltage exceeds the regulation voltage after the minimum off­time expires.
After the phase-overlap mode ends, the controller auto­matically begins with the opposite phase. For example, if the secondary phase provided the last on-time pulse before overlap operation began, the controller starts switching with the main phase when overlap operation ends.
Power-Up Sequence
The MAX8760 is enabled when SHDN is driven high (Figure 2). The reference powers up first. Once the ref­erence exceeds its UVLO threshold, the PWM controller evaluates the DAC target and starts switching.
Pin Description (continued)
PIN NAME FUNCTION
32 DLS
S econd ar y Low - S i d e G ate- D r i ver O utp ut. D LS sw i ng s fr om P GN D to V
D D
. D LS i s for ced hi g h after the
M AX 8760 p ow er s d ow n.
33 DHS Secondary High-Side Gate-Driver Output. Swings LXS to BSTS.
34 LXS Secondary Inductor Connection. LXS is the internal lower supply rail for the DHS high-side gate driver.
35 BSTS
Secondary Boost Flying Capacitor Connection. An optional resistor in series with BSTS allows the DHS pullup current to be adjusted.
36 V+
Battery Voltage-Sense Connection. Used only for PWM one-shot timing. DH_ on-time is inversely proportional to input voltage over a 4V to 28V range.
37 CMP Main Inductor Positive Current-Sense Input
38 CMN Main Inductor Negative Current-Sense Input
39 CSN Secondary Inductor Positive Current-Sense Input
40 CSP Secondary Inductor Negative Current-Sense Input
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 17
For the MAX8760, the slew-rate controller ramps up the output voltage in 12.5mV increments to the proper oper­ating voltage (see Tables 3 and 4) set by either D0–D5 (SUS = GND) or S0, S1 (SUS = REF or high). The ramp rate is set with the R
TIME
resistor (see the Output Voltage
Transition Timing section).
The ramp rate is 1/4 the rate set by the R
TIME
resistor (see the Output Voltage Transition Timing section). The controller pulls VROK low until at least 3ms after the MAX8760 reaches the target DAC code.
Shutdown
When SHDN goes low, the MAX8760 enters low-power shutdown mode. VROK is pulled low immediately, and the output voltage ramps down to 0V in LSB increments at 4 times the clock rate set by R
TIME
:
where f
SLEW
= 500kHz 30k/R
TIME
, V
DAC
is the DAC setting when the controller begins the shutdown sequence, and V
LSB
= 12.5mV is the DAC’s smallest voltage increment. Slowly discharging the output capac­itors by slewing the output over a long period of time (4/f
SLEW
) keeps the average negative inductor current
low (damped response), thereby eliminating the nega­tive output voltage excursion that occurs when the con­troller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output voltage excursion. When the DAC reaches the 0V setting, DL_ goes high, DH_ goes low, the reference turns off, and the supply current drops to about 1µA. When a fault condition—out­put undervoltage lockout, output overvoltage lockout, or thermal shutdown—activates the shutdown sequence, the controller sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle V
CC
power below 1V.
When SHDN goes high, the reference powers up. Once the reference voltage exceeds its UVLO threshold, the controller evaluates the DAC target and starts switching. The slew-rate controller ramps up from 0V in LSB increments to the currently selected output-voltage set­ting at 1/4 the slew rate set by the R
TIME
resistor (see the Power-Up Sequence section). There is no traditional soft­start (variable current-limit) circuitry, so full output current is available immediately.
t
f
V V
SHDN
SLEW
DAC
LSB
 
 
4
MAX8760 AMD MOBILE COMPONENTS
DESIGNATION
Circuit of Figure 1
Input Voltage Range 7V to 24V
VID Output Voltage (D5–D0)
1.3V
(D5–D0 = 001010)
Suspend Voltage (SUS, S0, S1)
Not used
(SUS = GND)
Maximum Load Current 30A Number of Phases (η
TOTAL
) Two phases
Inductor (per Phase) 0.56µH Panasonic ETQP4LR56WFC
Switching Frequency 300kHz (TON = REF)
High-Side MOSFET (NH, per phase) Siliconix (1) Si7886DP
Low-Side MOSFET (NL, per phase) Siliconix (2) Si7356DP
Total Input Capacitance (CIN)
(4) 10µF, 25V
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
Total Output Capacitance (C
OUT
)
(4) 330µF, 2.5V
Sanyo 2R5TPE330M9
Current-Sense Resistor (R
SENSE
, per Phase)
1m
Panasonic ERJM1WTJ1M0U
Table 1. Component Selection for Standard Multiphase Applications
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
18 ______________________________________________________________________________________
INPUT* 7V TO 24V
OUTPUT
V
CC
VROK
SHDN
OFS
POWER
GOOD
OFF
ON
DAC INPUTS
SUSPEND INPUTS
(FOUR-LEVEL LOGIC)
L1
C
BST1
0.22µF
N
H1
N
H2
N
L1
C
IN
C2
1µF
C
REF
0.22µF
R13
10
R12
100k
C
CCV
47pF
C
CCI
470pF
C
BST2
0.22µF
R7 0
C3
OPEN
R10
2k
±1%
R1 2k ±1%
5V BIAS SUPPLY
C1
2.2µF
C
OUT
C
OUT
*LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.
BST DIODES
SUS
TIME
CCV
SKIP
R
SENSE1
1.0m
N
L2
R6 OPEN
R8
100k
±1%
R4
1k
±1%
R5 1k ±1%
POWER GROUND
ANALOG GROUND
MAX8760
C
IN
REF
TON
REF
R2
1k
±1%
R3 1k ±1%
R
TIME
30.1k
D0 D1 D2 D3 D4
S0 S1
L2
R
SENSE2
1.0m
BSTM
DHM
LXM
DLM
PGND
GND
CMN CMP
V+
OAIN+
OAIN-
REF (300kHz)
FB
CCI
CSP CSN
BSTS
DHS
LXS
DLS
GNDS
V
DD
ILIM
R9
49.9k ±1%
SKIP
PWM
D5
Figure 1. Standard Two-Phase AMD Mobile 30A Application Circuit
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 19
Internal Multiplexers
The MAX8760 has a unique internal DAC input multiplexer (MUXes) that selects one of three different DAC code settings for different processor states (Figure 3). On startup, the MAX8760 selects the DAC code from the D0–D5 (SUS = GND) or S0, S1 (SUS = REF or high) input decoders.
DAC Inputs (D0–D5)
During normal forced-PWM operation (SUS = GND), the digital-to-analog converter (DAC) programs the output voltage using the D0–D5 inputs. Do not leave D0–D5
unconnected. D0–D5 can be changed while the MAX8760 is active, initiating a transition to a new output voltage level. Change D0–D5 together, avoiding greater than 1µs skew between bits. Otherwise, incorrect DAC readings can cause a partial transition to the wrong volt­age level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with AMD K9 voltage specifications (Table 4).
MANUFACTURER PHONE WEBSITE
BI Technologies
714-447-2345 (USA) www.bitechnologies.com
Central Semiconductor
631-435-1110 (USA) www.centralsemi.com
Coilcraft
800-322-2645 (USA) www.coilcraft.com
Coiltronics
561-752-5000 (USA) www.coiltronics.com
Fairchild Semiconductor
888-522-5372 (USA) www.fairchildsemi.com
International Rectifier
310-322-3331 (USA) www.irf.com
Kemet
408-986-0424 (USA) www.kemet.com
Panasonic
847-468-5624 (USA) www.panasonic.com
Sanyo
65-6281-3226 (Singapore) www.secc.co.jp
Siliconix (Vishay)
203-268-6261 (USA) www.vishay.com
Sumida
408-982-9660 (USA) www.sumida.com
Taiyo Yuden
03-3667-3408 (Japan)
408-573-4150 (USA)
www.t-yuden.com
TDK
847-803-6100 (USA)
81-3-5201-7241 (Japan)
www.component.tdk.com
TOKO
858-675-8013 (USA) www.tokoam.com
Table 2. Component Suppliers
VID (D0–D5)
SHDN
V
CORE
t
VROK(START)
5ms (TYP)
SOFT-SHUTDOWN 1 LSB PER 4 R
TIME
CYCLES
SOFT-START
1 LSB PER 4 R
TIME
CYCLES
VROK
DO NOT CARE
Figure 2. Power-Up and Shutdown Sequence Timing Diagram
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
20 ______________________________________________________________________________________
Four-Level Logic Inputs
TON and S0, S1 are four-level logic inputs. These inputs help expand the functionality of the controller without adding an excessive number of pins. The four-level inputs are intended to be static inputs. When left open, an internal resistive voltage-divider sets the input volt­age to approximately 3.5V. Therefore, connect the four­level logic inputs directly to V
CC
, REF, or GND when selecting one of the other logic levels. See the Electrical Characteristics table for exact logic level voltages.
Suspend Mode
When the processor enters low-power suspend mode, it sets the regulator to a lower output voltage to reduce power consumption. The MAX8760 includes independent suspend-mode output voltage codes set by the four-level S0, S1 inputs and the tri-level SUS input. When the CPU suspends operation (SUS = REF or high), the controller disables the offset amplifier and overrides the 5-bit VID DAC code set by either D0–D5 (normal operation). The master controller slews the output to the selected sus­pend-mode voltage. During the transition, the MAX8760 blanks VROK and the UVP fault protection until 24 R
TIME
clock cycles after the slew-rate controller reaches the suspend-mode voltage.
SUS is a tri-level logic input: GND, REF, or high. This expands the functionality of the controller without adding an additional pin. This input is intended to be driven by a dedicated open-drain output with the pullup resistor connected either to REF (or a resistive divider from VCC) or to a logic-level bias supply (3.3V or greater). When pulled up to REF, the MAX8760 selects the upper suspend voltage range. When pulled high (2.7V or greater), the controller selects the lower sus­pend voltage range. See the Electrical Characteristics table for exact logic-level voltages.
Output Voltage Transition Timing
The MAX8760 is designed to perform mode transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest pos­sible peak currents for a given output capacitance.
At the beginning of an output voltage transition, the MAX8760 blanks the VROK output, preventing it from changing states. VROK remains blanked during the transition and is enabled 24 clock cycles after the slew-rate controller has set the final DAC code value. The slew-rate clock frequency (set by resistor R
TIME
) must be set fast enough to ensure that the transition is completed within the maximum allotted time.
SHDN SUS SKIP OFS
OUTPUT
OPERATING MODE
GND x x x GND
Low-Power Shutdown Mode. DL_ is forced high, DH_ is forced low, and the PWM controller is disabled. The supply current drops to 1µA (typ).
V
CC
GND V
CC
D0–D5
(no offset)
N or m al Op er ati on. The no- l oad outp ut vol tag e i s d eter m i ned b y the sel ected V ID D AC cod e ( D 0–D 5, Tab l e 4) .
V
CC
x
GND
or
REF
D0–D5
(no offset)
Pulse-Skipping Operation. When SKIP is pulled low, the MAX8760 immediately enters pulse-skipping operation allowing automatic PWM/PFM switchover under light loads. The VROK upper threshold is blanked.
V
CC
GND x
0 to 0.8V
or
1.2V to 2V
D0–D5
Deep-Sleep Mode. The no-load output voltage is determined by the selected VID DAC code (D0–D5, Table 4) plus the offset voltage set by OFS.
V
CC
REF
or
High
xx
(no offset)
Suspend Mode. The no-load output voltage is determined by the selected suspend code (SUS, S0, S1, Table 5), overriding all other active modes of operation.
V
CC
xx x GND
Fault Mode. The fault latch has been set by either UVP, OVP, or thermal shutdown. The controller remains in FAULT mode until V
CC
power is cycled or SHDN toggled.
Table 3. Operating Mode Truth Table
VOLTAGE
GND or REF
GND or REF
(plus offset)
SUS, S0–S1
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 21
The slew-rate controller transitions the output voltage in
12.5mV steps during soft-start, soft-shutdown, and sus­pend-mode transitions. The total time for a transition depends on R
TIME
, the voltage difference, and the accuracy of the MAX8760’s slew-rate clock, and is not dependent on the total output capacitance. The greater the output capacitance, the higher the surge current required for the transition. The MAX8760 automatically controls the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less than the current limit set by ILIM. The transition time is given by:
where f
SLEW
= 500kHz 30k/ R
TIME
, V
OLD
is the
original DAC setting, V
NEW
is the new DAC setting, and
V
LSB
= 12.5mV is the DAC’s smallest voltage incre­ment. The additional two clock cycles on the falling edge time are due to internal synchronization delays. See TIME Frequency Accuracy in the Electrical Characteristics table for f
SLEW
limits.
The practical range of R
TIME
is 15kto 150kΩ, corre-
sponding to 1.0µs to 10µs per 12.5mV step. Although the DAC takes discrete steps, the output filter makes the transitions relatively smooth. The average inductor current required to make an output voltage transition is:
IC V f
L OUT LSB SLEW
≅××
t
f
VV
V
for V ri g
t
f
VV
V
for V falling
SLEW
SLEW
OLD NEW
LSB
OUT
SLEW
SLEW
OLD NEW
LSB
OUT
 
 
 
 
+
 
 
1
1
2
sin
S0 S1
S0, S1
DECODER
IN
SEL
SUS
SUSPEND
MUX
OUT
1
0
SEL
DAC
1.0V
2.5V SUS 3-LEVEL
DECODER
OUT
D0–D5
DECODER
OUT
IN
D3 D4
D1 D2
D0
D5
Figure 3. Internal Multiplexers Functional Diagram
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
22 ______________________________________________________________________________________
Fault Protection
Output Overvoltage Protection
The OVP circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX8760 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the fixed 2.0V (typ) threshold. When the OVP circuit detects an overvoltage fault, it immediately sets the fault latch, turns off the high-side MOSFETs, and forces DL high.
This action discharges the output filter capacitor and forces the output to ground. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCCpower supply below 1V.
The OVP is disabled when the controller is in the no-fault test mode (see the No-Fault Test Mode section).
Output Undervoltage Shutdown
The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX8760 output voltage is under 70% of the nominal value, the controller activates the shutdown sequence and sets the fault latch.
Once the controller ramps down to the 0V DAC code setting, it forces the DL_ low-side gate driver high and pulls the DH_ high-side gate driver low. Toggle SHDN or cycle the V
CC
power supply below 1V to clear the
fault latch and reactivate the controller. UVP is ignored during output voltage transitions and remains blanked for an additional 24 clock cycles after the controller reaches the final DAC code value.
UVP can be disabled through the no-fault test mode (see the No-Fault Test Mode section).
Thermal-Fault Protection
The MAX8760 features a thermal-fault protection circuit. When the junction temperature rises above +160°C, a thermal sensor activates the fault latch and the soft­shutdown sequence. Once the controller ramps down to the 0V DAC code setting, it forces the DL_ low-side gate driver high, and pulls the DH_ high-side gate driver low. Toggle SHDN or cycle the V
CC
power supply below 1V to clear the fault latch and reactivate the con­troller after the junction temperature cools by 15°C.
Thermal shutdown can be disabled through the no-fault test mode (see the No-Fault Test Mode section).
No-Fault Test Mode
The latched-fault protection features and overlap mode can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a no­fault test mode is provided to disable the fault protection (overvoltage protection, undervoltage protection, and thermal shutdown) and overlap mode. Additionally, the test mode clears the fault latch if it has been set. The no­fault test mode is entered by forcing 12V to 15V on SHDN.
SUS
V
DAC
TIME
CLOCK
VROK
VROK BLANKING
VROK BLANKING
OUTPUT SET BY SUS AND S0, S1
OUTPUT SET BY D0–D4
1 LSB PER R
TIME
CYCLE
t
SLEW
t
BLANK
= 24 CLKSt
SLEW
t
BLANK
= 24 CLKS
Figure 4. Suspend Transition
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 23
D5
OUTPUT
VOLTAGE (V)
000000 1.5500
000001 1.5250
000010 1.5000
000011 1.4750
000100 1.4500
000101 1.4250
000110 1.4000
000111 1.3750
001000 1.3500
001001 1.3250
001010 1.3000
001011 1.2750
001100 1.2500
001101 1.2250
001110 1.2000
001111 1.1750
010000 1.1500
010001 1.1250
010010 1.1000
010011 1.0750
010100 1.0500
010101 1.0250
010110 1.0000
010111 0.9750
011000 0.9500
011001 0.9250
011010 0.9000
011011 0.8750
011100 0.8500
011101 0.8250
011110 0.8000
011111 0.7750
Table 4. Output Voltage ID DAC Codes (SUS = GND)
D4 D3 D2 D1 D0
D5 D4 D3 D2 D1 D0
100000 0.7625
100001 0.7500
100010 0.7375
100011 0.7250
100100 0.7125
100101 0.7000
100110 0.6875
100111 0.6750
101000 0.6625
101001 0.6500
101010 0.6375
101011 0.6250
101100 0.6125
101101 0.6000
101110 0.5875
101111 0.5750
110000 0.5625
110001 0.5500
110010 0.5375
110011 0.5250
110100 0.5125
110101 0.5000
110110 0.4875
110111 0.4750
111000 0.4625
111001 0.4500
111010 0.4375
111011 0.4250
111100 0.4125
111101 0.4000
111110 0.3875
111111 0.3750
OUTPUT
VOLTAGE (V)
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
24 ______________________________________________________________________________________
LOWER SUSPEND CODES
SUS S1 S0
OUTPUT
VOLTAGE (V)
HIGH GND GND 0.800
HIGH GND REF 0.775
HIGH GND OPEN 0.750
HIGH GND V
CC
0.725
HIGH REF GND 0.700
HIGH REF REF 0.675
HIGH REF OPEN 0.650
HIGH REF V
CC
0.625
HIGH OPEN GND 0.600
HIGH OPEN REF 0.575
HIGH OPEN OPEN 0.550
HIGH OPEN V
CC
0.525
HIGH V
CC
GND 0.500
HIGH V
CC
REF 0.475
HIGH V
CC
OPEN 0.450
HIGH V
CC
V
CC
0.425
Table 5. Suspend Mode DAC Codes
*Connect the tri-level SUS input to a 2.7V or greater supply (3.3V or VCC) for an input logic level high.
Multiphase Quick-PWM
5V Bias Supply (VCCand VDD)
The Quick-PWM controller requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook’s 95%-efficient 5V system sup­ply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V bias supply can be generated with an external linear regulator.
The 5V bias supply must provide VCC(PWM controller) and VDD(gate-drive power), so the maximum current drawn is:
I
BIAS
= ICC+ fSW(Q
G(LOW)
+ Q
G(HIGH)
)
where ICCis provided in the Electrical Characteristics table, fSWis the switching frequency, and Q
G(LOW)
and
Q
G(HIGH)
are the MOSFET data sheet’s total gate-charge
specification limits at VGS= 5V.
V+ and VDDcan be connected together if the input power source is a fixed 4.5V to 5.5V supply. If the 5V bias supply is powered up prior to the battery supply,
the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup.
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
The quick-PWM control architecture is a pseudofixed-fre­quency, constant-on-time, current-mode regulator with input voltage feed-forward (Figure 5). This architecture relies on the output filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage pro­vides the PWM ramp signal. The control algorithm is sim­ple: the high-side switch on-time is determined solely by a one-shot with a period inversely proportional to input voltage, and directly proportional to output voltage or the difference between the main and secondary inductor currents (see the On-Time One-Shot (TON) section). Another one-shot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley current-limit threshold, and the minimum off-time one-shot times out. The controller maintains 180° out-of­phase operation by alternately triggering the main and secondary phases after the error comparator drops below the output voltage set point.
SUS S1 S0
REF GND GND 1.200
REF GND REF 1.175
REF GND OPEN 1.150
REF GND V
REF REF GND 1.100
REF REF REF 1.075
REF REF OPEN 1.050
REF REF V
REF OPEN GND 1.000
REF OPEN REF 0.975
REF OPEN OPEN 0.950
REF OPEN V
REF V
REF V
REF V
REF V
UPPER SUSPEND CODES
CC
CC
CC
CC
CC
CC
CC
GND 0.900
REF 0.875
OPEN 0.850
V
CC
OUTPUT
VOLTAGE (V)
1.125
1.025
0.925
0.825
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 25
CSN
CSP
CMP
CMN
V
CC
REF
GND
CCV
OFS
FB
OAIN+
OAIN-
GNDS
1.0V
TIME
ILIM
19R
R
REF
(2.0V)
SHDN
REF
T = 1T
T = 0
Gm
Gm
R-2R
DAC
INTERNAL MULTIPLEXERS, MODE
CONTROL, AND SLEW-RATE CONTROL
S[0:1] D[0:5]
SUS
SKIP
Q
Q
T
CMP
CMN
SKIP
FAULT
1.5mV
S
R
Q
R
S
Q
ON-TIME
ONE-SHOT
TRIGQ
ON-TIME
ONE-SHOT
TRIG
Q
BSTM
TON
V+
CCI
DHM
LXM
V
DD
DLM
PGND
MAIN PHASE
DRIVERS
TRIG
Q
ONE-SHOT
MINIMUM OFF-TIME
SECONDARY PHASE
DRIVERS
FB
Gm
Gm
CMP
CSP
CMN
CSN
BSTS
DHS
LXS
DLS
Gm
MAX8760
Figure 5. Dual-Phase Quick-PWM Functional Diagram
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
26 ______________________________________________________________________________________
On-Time One-Shot (TON)
The core of each phase contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFETs on-time. The one-shot for the main phase varies the on­time in response to the input and feedback voltages. The main high-side switch on-time is inversely propor­tional to the input voltage as measured by the V+ input, and proportional to the feedback voltage (VFB):
where K is set by the TON pin-strap connection (Table 6) and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch.
The one-shot for the secondary phase varies the on-time in response to the input voltage and the difference between the main and secondary inductor currents. Two identical transconductance amplifiers integrate the difference between the master and slave current-sense signals. The summed output is internally connected to CCI, allowing adjustment of the integration time constant with a compensation network connected between CCI and FB.
The resulting compensation current and voltage are determined by the following equations:
where Z
CCI
is the impedance at the CCI output. The secondary on-time one-shot uses this integrated signal (V
CCI
) to set the secondary high-side MOSFETs on-time. When the main and secondary current-sense signals (V
CM
= V
CMP
- V
CMN
and VCS= V
CSP
- V
CSM
) become unbalanced, the transconductance amplifiers adjust the secondary on-time, which increases or decreases the secondary inductor current until the current-sense signals are properly balanced:
This algorithm results in a nearly constant switching frequency and balanced inductor currents, despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive
regions such as the 455kHz IF band; second, the induc­tor ripple-current operating point remains relatively con­stant, resulting in easy design methodology and predictable output-voltage ripple. The on-time one-shots have good accuracy at the operating points specified in the Electrical Characteristics table. On-times at operating points far removed from the conditions specified in the Electrical Characteristics table can vary over a wider range. For example, the 300kHz setting typically runs about 3% slower with inputs much greater than 12V due to the very short on-times required.
On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics table are influenced by switching delays in the external high-side MOSFET. Resistive losses, including the induc­tor, both MOSFETs, output capacitor ESR, and PC board copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reduc­ing the switching frequency. It occurs only during forced­PWM operation and dynamic output voltage transitions when the inductor current reverses at light- or negative­load currents. With reversed inductor current, the induc­tor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time.
For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency (per phase) is:
where V
DROP1
is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous recti­fier, inductor, and PC board resistances; V
DROP2
is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PC board resistances; and tONis the on-time as determined above.
f
SW
VV
tVV V
OUT DROP
ON IN DROP DROP
=
+
()
+
()
1
12
-
.
.
( ) (
)
()
tK
VV
V
K
VV
V
K
IZ
V
Main on time Secondary Current
Balance Correction
ON ND
CCI
IN
FB
IN
CCI CCI
IN
2
0 075
0 075
=
+
 
 
=
+
 
 
+
 
 
=+
IGVVGVV
VVIZ
CCI M CMP CMN M CSP CSN
CCI FB CCI CCI
=
()()
=
+
-- -
t
ON MAIN
KV V
V
FB
IN
()
.
=
+
()
0 075
Table 6. Approximate K-Factor Errors
TON
CONNECTION
FREQUENCY
SETTING
(kHz)
K-FACTOR
(µs)
MAX
K-FACTOR
ERROR
(%)
V
CC
100 10 ±10
Float 200 5 ±10
REF 300 3.3 ±10
GND 550 1.8 ±12.5
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 27
Current Balance
Without active current-balance circuitry, the current matching between phases depends on the MOSFET’s on-resistance (R
DS(ON)
), thermal ballasting, on-/off-time matching, and inductance matching. For example, vari­ation in the low-side MOSFET on-resistance (ignoring thermal effects) results in a current mismatch that is proportional to the on-resistance difference:
However, mismatches between on-times, off-times, and inductor values increase the worst-case current imbal­ance, making it impossible to passively guarantee accurate current balancing.
The multiphase quick-PWM controller integrates the dif­ference between the current-sense voltages and adjusts the on-time of the secondary phase to maintain current balance. The current balance now relies on the accuracy of the current-sense resistors instead of the inaccurate, thermally sensitive on-resistance of the low­side MOSFETs.
With active current balancing, the current mismatch is determined by the current-sense resistor values and the offset voltage of the transconductance amplifiers:
where V
OS(IBAL)
is the current balance offset specifica-
tion in the Electrical Characteristics table.
The worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches, resulting in different di/dt for the two phases. The time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency.
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier
The multiphase quick-PWM controllers include an inde­pendent operational amplifier for adding gain to the volt­age-positioning sense path. The voltage-positioning gain allows the use of low-value current-sense resistors to minimize power dissipation. This 3MHz gain-bandwidth amplifier was designed with low offset voltage (70µV typ) to meet the IMVP output-accuracy requirements.
The inverting (OAIN-) and noninverting (OAIN+) inputs are used to differentially sense the voltage across the voltage-positioning sense resistor. The op amp’s output is internally connected to the regulator’s feedback input (FB). The op amp should be configured as a noninvert­ing, differential amplifier, as shown in Figure 10. The voltage-positioning slope is set by properly selecting the feedback resistor connected from FB to OAIN- (see the Setting Voltage Positioning section). For applications using a slave controller, additional differential input resistors (summing configuration) can be connected to the slave’s voltage-positioning sense resistor. Summing together both the master and slave current-sense signals ensures that the voltage-positioning slope remains con­stant when the slave controller is disabled.
The controller also uses the amplifier for remote output sensing (FBS) by summing in the remote-sense voltage into the positive terminal of the voltage-positioning amplifier (Figure 10).
In applications that do not require voltage-positioning gain, the amplifier can be disabled by connecting the OAIN- pin directly to V
CC
. The disabled amplifier’s out­put becomes high impedance, guaranteeing that the unused amplifier does not corrupt the FB input signal. The logic threshold to disable the op amp is approxi­mately VCC- 1V.
Integrator Amplifier
A feedback amplifier forces the DC average of the feedback voltage to equal the VID DAC setting. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 5), allowing accurate DC output voltage regulation regardless of the output ripple voltage. The feedback amplifier has the ability to shift the output voltage. The differential input voltage range is at least ±80mV total, including DC offset and AC ripple. The integration time constant can be set easily with an external compensation capacitor at the CCV pin. Use a capacitor value of 47pF to 1000pF (150pF typ).
Differential Remote Sense
The multiphase quick-PWM controllers include differen­tial remote-sense inputs to eliminate the effects of volt­age drops down the PC board traces and through the processor’s power pins. The remote output sense (FBS) is accomplished by summing in the remote-sense volt­age into the positive terminal of the voltage-positioning amplifier (Figure 10). The controller includes a dedicat­ed input and internal amplifier for the remote ground sense. The GNDS amplifier adds an offset directly to the feedback voltage, adjusting the output voltage to counteract the voltage drop in the ground path.
III
V
R
OS IBAL LM LS
OS IBAL
SENSE
()
()
== -
II I
R
R
MAIN ND MAIN
MAIN
ND
--
2
2
1=
 
 
 
 
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
28 ______________________________________________________________________________________
Together, the feedback-sense resistor (R
FBS
) and GNDS input sum the remote-sense voltages with the feedback signals that set the voltage-positioned output, enabling true differential remote sense of the processor voltage. Connect the feedback-sense resistor (R
FBS
) and ground-sense input (GNDS) directly to the proces­sor’s core supply remote-sense outputs as shown in the Standard Applications Circuit.
Offset Amplifier
The multiphase quick-PWM controllers include a third amplifier used to add small offsets to the voltage-posi­tioned load line. The offset amplifier is summed directly with the feedback voltage, making the offset gain inde­pendent of the DAC code. This amplifier has the ability to offset the output by ±100mV.
The offset is adjusted using resistive voltage-dividers at the OFS input. For inputs from 0 to 0.8V, the offset amplifier adds a negative offset to the output that is equal to 1/8 the voltage appearing at the selected OFS input (V
OUT
= V
DAC
- 0.125 x V
OFS
). For inputs from
1.2V to 2V, the offset amplifier adds a positive offset to the output that is equal to 1/8th the difference between the reference voltage and the voltage appearing at the selected OFS input (V
OUT
= V
DAC
+ 0.125 x (V
REF
-
V
OFS
)). With this scheme, the controller supports both positive and negative offsets with a single input. The piecewise linear transfer function is shown in the Typical Operating Characteristics. The regions of the transfer function below zero, above 2V, and between
0.8V and 1.2V are undefined. OFS inputs are disal­lowed in these regions, and the respective effects on the output are not specified.
The controller disables the offset amplifier during sus­pend mode (SUS = REF or high).
Forced-PWM Operation (Normal Mode)
During normal mode, when the CPU is actively running (SKIP = high, Table 7), the quick-PWM controller oper­ates with the low-noise forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gate-drive waveform to be constantly the complement of the high-side gate­drive waveform. This keeps the switching frequency fairly constant and allows the inductor current to reverse under light loads, providing fast, accurate neg­ative output voltage transitions by quickly discharging the output capacitors.
Forced-PWM operation comes at a cost: the no-load 5V bias supply current remains between 10mA to 60mA per phase, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light-load conditions, the processor may switch the controller to a low-power pulse-skipping control scheme after entering suspend mode.
Table 7.
SSKKIIPP
Settings*
SKIP
CONNECTION
MODE OPERATION
High
(3.3V or V
CC
)
Two-phase
forced PWM
The controller operates with a constant switching frequency, providing low-noise forced-PWM operation. The controller disables the zero-crossing comparators, forcing the low-side gate­drive waveform to be constantly the complement of the high-side gate-drive waveform.
REF
Two-phase
The controller automatically switches over to PFM operation under light loads. The controller keeps both phases active and uses the automatic pulse-skipping control scheme, alternating between the primary and secondary phases with each cycle.
GND
One-phase
The controller automatically switches over to PFM operation under light loads. Only the main phase is active. The secondary phase is disabled, DLS and DHS are pulled low, so LXS is high impedance.
*Settings for a dual 180° out-of-phase controller.
-200
-100
0
100
200
0 1.00.5
0.8 1.2
1.5 2.0
OFS VOLTAGE (V)
OUTPUT OFFSET VOLTAGE (mV)
UNDEFINED REGION
Figure 6. Offset Voltage
pulse skipping
pulse skipping
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 29
Low-Power Pulse Skipping
During pulse-skipping override mode (SKIP = REF or GND, Table 7), the multiphase quick-PWM controllers use an automatic pulse-skipping control scheme. When SKIP is pulled low, the controller uses the automatic pulse-skipping control scheme, overriding forced-PWM operation, and blanks the upper VROK threshold.
SKIP is a three-level logic input—GND, REF, or high. This input is intended to be driven by a dedicated open-drain output with the pullup resistor connected either to REF (or a resistive divider from VCC) or to a logic-level high-bias supply (3.3V or greater).
When driven to GND, the multiphase Quick-PWM controller disables the secondary phase (DLS = PGND and DHS = LXS) and the primary phase uses the auto­matic pulse-skipping control scheme. When pulled up to REF, the controller keeps both phases active and uses the automatic pulse-skipping control scheme— alternating between the primary and secondary phases with each cycle.
Automatic Pulse-Skipping Switchover
In skip mode (SKIP = REF or GND), an inherent automatic switchover to PFM takes place at light loads (Figure 7). A comparator that truncates the low-side switch on-time at the inductor current’s zero crossing affects this switch­over. The zero-crossing comparator senses the inductor current across the current-sense resistors. Once VC_P­VC_Ndrops below the zero-crossing comparator thresh­old (see the Electrical Characteristics table), the com­parator forces DL low (Figure 5). This mechanism causes the threshold between pulse-skipping PFM and nonskip­ping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current of each phase is equal to 1/2 the peak-to­peak ripple current, which is a function of the inductor value (Figure 7). For a battery input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. The total load current at the PFM/PWM crossover threshold (I
LOAD(SKIP)
) is approximately:
where η
TOTAL
is the number of active phases, and K is
the on-time scale factor (Table 6).
The switching waveforms may appear noisy and asyn­chronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Varying the inductor value makes trade-offs between PFM noise and light-load
efficiency. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels.
Current-Limit Circuit
The current-limit circuit employs a unique “valley” current­sensing algorithm that uses current-sense resistors between the current-sense inputs (C_P to C_N) as the cur­rent-sensing elements. If the current-sense signal of the selected phase is above the current-limit threshold, the PWM controller does not initiate a new cycle (Figure 8) until the inductor current of the selected phase drops below the valley current-limit threshold. When either phase trips the current limit, both phases are effectively current limited since the interleaved controller does not initiate a cycle with either phase.
I
K
LOAD SKIP
TOTAL
()
=
 
 
 
 
η
V
L
V-V
V
OUT IN OUT
IN
INDUCTOR CURRENT
I
LOAD
= I
PEAK
/2
ON-TIME0 TIME
I
PEAK
L
V
BATT
- V
OUT
it
=
Figure 7. Pulse-Skipping/Discontinuous Crossover Point
INDUCTOR CURRENT
I
LIMIT(VALLEY)
= I
LOAD(MAX)
2 - LIR
2η
()
TIME
0
I
PEAK
I
LOAD
I
LIMIT
Figure 8. “Valley” Current-Limit Threshold Point
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
30 ______________________________________________________________________________________
Since only the valley current is actively limited, the actu­al peak current is greater than the current-limit thresh­old by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. When combined with the undervoltage protec­tion circuit, this current-limit method is effective in almost every circumstance.
There is also a negative current limit that prevents excessive reverse inductor currents when V
OUT
is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted. When a phase drops below the negative current limit, the controller immediately activates an on­time pulse—DL turns off, and DH turns on—allowing the inductor current to remain above the negative cur­rent threshold.
The current-limit threshold is adjusted with an external resistive voltage-divider at ILIM. The current-limit threshold voltage adjustment range is from 10mV to 75mV. In the adjustable mode, the current-limit thresh­old voltage is precisely 1/20 the voltage seen at ILIM. The threshold defaults to 30mV when ILIM is connected to VCC. The logic threshold for switchover to the 30mV default value is approximately VCC- 1V.
Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the cur­rent-sense signals seen by the current-sense inputs (C_P, C_N).
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving moder­ately sized, high-side and larger, low-side power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment, where a large VIN- V
OUT
differential exists. An adaptive dead-time circuit monitors the DL output and prevents the high­side FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the quick-PWM controller interprets the MOSFET gate as “off” while there is actually charge still left on the gate. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the device). The dead time at the other edge (DH turning off) is determined by a fixed 35ns internal delay.
The internal pulldown transistor that drives DL low is robust, with a 0.4(typ) on-resistance. This helps pre­vent DL from being pulled up due to capacitive coupling
from the drain to the gate of the low-side MOSFETs when LX switches from ground to VIN. Applications with high input voltages and long, inductive DL traces may require additional gate-to-source capacitance to ensure fast-ris­ing LX edges do not pull up the low-side MOSFET’s gate voltage, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-to-drain capacitance (C
RSS
), gate-to-source capac-
itance (C
ISS
- C
RSS
), and additional board parasitics
should not exceed the minimum threshold voltage:
Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Typically, adding 4700pF between DL and power ground (CNLin Figure 9), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays.
Alternatively, shoot-through currents may be caused by a combination of fast high-side MOSFETs and slow low­side MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5in series with BST slows down the high-side MOSFET turn-on time, elimi­nating the shoot-through currents without degrading the turn-off time (R
BST
in Figure 9). Slowing down the high­side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise.
Power-On Reset
VV
C
C
GS TH IN
RSS
ISS
()
>
 
 
V
DD
BST
DH
LX
(R
BST
)*
(CNL)*
D
BST
C
BST
C
BYP
INPUT (V
IN
)
N
H
L
V
DD
DL
PGND
N
L
(R
BST
)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 9. Optional Gate-Driver Circuitry
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 31
Power-on reset (POR) occurs when VCCrises above approximately 2V, resetting the fault latch, activating boot mode, and preparing the PWM for operation. V
CC
undervoltage lockout (UVLO) circuitry inhibits switch­ing, and forces the DL gate driver high (to enforce out­put overvoltage protection). When VCCrises above
4.25V, the DAC inputs are sampled and the output volt­age begins to slew to the target voltage.
For automatic startup, the battery voltage should be present before VCC. If the quick-PWM controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. Toggle the SHDN pin to reset the fault latch.
Input Undervoltage Lockout
During startup, the VCCUVLO circuitry forces the DL gate driver high and the DH gate driver low, inhibiting switching until an adequate supply voltage is reached. Once VCCrises above 4.25V, valid transitions detected at the trigger input initiate a corresponding on-time pulse (see the On-Time One-Shot (TON) section). If the VCCvoltage drops below 4.25V, it is assumed that there is not enough supply voltage to make valid deci­sions. To protect the output from overvoltage faults, the controller activates the shutdown sequence.
Multiphase Quick-PWM
Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switch­ing frequency and inductor operating point, and the fol­lowing four factors dictate the rest of the design:
• Input voltage range: The maximum value (V
IN(MAX)
) must accommodate the worst-case high
AC adapter voltage. The minimum value (V
IN(MIN)
) must account for the lowest input voltage after drops due to connectors, fuses, and battery-selector switches. If there is a choice at all, lower input volt­ages result in better efficiency.
• Maximum load current: There are two values to consider. The peak load current (I
LOAD(MAX)
) deter­mines the instantaneous component stresses and fil­tering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load cur­rent (I
LOAD
) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing com­ponents. Modern notebook CPUs generally exhibit I
LOAD
= I
LOAD(MAX)
x 80%.
For multiphase systems, each phase supports a fraction of the load, depending on the current bal­ancing. When properly balanced, the load current is evenly distributed among each phase:
where η
TOTAL
is the total number of active phases.
• Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and V
IN
2
. The opti­mum frequency is also a moving target, due to rapid improvements in MOSFET technology that are mak­ing higher frequencies more practical.
• Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values pro­vide better transient response and smaller physical size, but also result in lower efficiency and higher out­put noise due to increased ripple current. The mini­mum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current.
Inductor Selection
The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows:
where η
TOTAL
is the total number of phases.
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (I
PEAK
):
I
I LIR
PEAK
LOAD MAX
TOTAL
=
+
 
 
()
η
1
2
L
VV
fI LIRVV
TOTAL
IN OUT
SW LOAD MAX
OUT
IN
()
=
 
 
 
 
η
I
I
LOAD PHASE
LOAD
TOTAL
()
=
η
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
32 ______________________________________________________________________________________
Transient Response
The inductor ripple current impacts transient-response performance, especially at low VIN- V
OUT
differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty fac­tor, which can be calculated from the on-time and mini­mum off-time. For a dual-phase controller, the worst-case output sag voltage can be determined by:
where t
OFF(MIN)
is the minimum off-time (see the
Electrical Characteristics table) and K is from Table 6.
The amount of overshoot due to stored inductor energy can be calculated as:
where η
TOTAL
is the total number of active phases.
Setting the Current Limit
The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The val­ley of the inductor current occurs at I
LOAD(MAX)
minus
half the ripple current; therefore:
where η
TOTAL
is the total number of active phases, and
I
LIMIT(LOW)
equals the minimum current-limit threshold
voltage divided by the current-sense resistor (R
SENSE
). For the 30mV default setting, the minimum current-limit threshold is 28mV.
Connect ILIM to VCCfor the default current-limit thresh­old (see the Electrical Characteristics table). In adjustable mode, the current-limit threshold is precisely 1/20 the voltage seen at ILIM. For an adjustable thresh­old, connect a resistive divider from REF to GND with ILIM connected to the center tap. When adjusting the current limit, use 1% tolerance resistors with approxi­mately 10µA of divider current to prevent a significant increase of errors in the current-limit tolerance.
Output Capacitor Selection
The output filter capacitor must have low enough effec­tive series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements.
In CPU V
CORE
converters and other applications where the output is subject to large-load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:
In non-CPU applications, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci­tor’s ESR. When operating multiphase systems out-of­phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. For 3- or 4-phase operation, the maximum ESR to meet ripple requirements is:
where
η
TOTAL
is the total number of active phases, t
ON
is the calculated on-time per phase, and t
TRIG
is the trig­ger delay between the master’s DH rising edge and the slave’s DH rising edge. The trigger delay must be less than 1/(f
SW
x
η
TOTAL
) for stable operation. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usual­ly selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types).
When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V
SAG
and V
SOAR
from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the V
SAG
and V
SOAR
equations
in the Transient Response section).
R
VL
VVt Vt
ESR
RIPPLE
IN
TOTAL
OUT ON
TOTAL
OUT TRIG
−−()2 ηη
R
V
I
ESR
STEP
LOAD MAX
()
I
I LIR
LIMIT LOW
LOAD MAX
TOTAL
()
()
>
 
 
η
1
2
V
IL
CV
SOAR
LOAD MAX
TOTAL
OUT OUT
()
()
2
2η
V
LI
VK
V
t
CV
VVK
V
t
I
C
VK
V
t
SAG
LOAD MAX
OUT
IN
OFF MIN
OUT OUT
IN OUT
IN
OFF MIN
LOAD MAX
OUT
OUT
IN
OFF MIN
=
 
 
 
 
+
 
 
+
 
 
 
 
+
 
 
()
()
() ()
()
()
()
2
2
2
2
2
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 33
Output Capacitor Stability Considerations
For quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching fre­quency. The boundary of instability is given by the fol­lowing equation:
where:
and:
where C
OUT
is the total output capacitance, R
ESR
is the
total equivalent-series resistance, R
SENSE
is the
current-sense resistance, A
VPS
is the voltage-positioning
gain, and R
PCB
is the parasitic board resistance
between the output capacitors and sense resistors.
For a standard 300kHz application, the ESR zero fre­quency must be well below 95kHz, preferably below 50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP capacitors in widespread use at the time of publication have typical ESR-zero frequencies below 50kHz. For example, the ESR needed to support a 30mV
P-P
ripple
in a 40A design is 30mV/(40A x 0.3) = 2.5m. Four 330µF/2.5V Panasonic SP (type XR) capacitors in paral­lel provide 2.5m(max) ESR. Their typical combined ESR results in a zero at 40kHz.
Ceramic capacitors have a high ESR-zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. Do not put high-value ceramic capacitors directly across the output without verifying that the circuit contains enough voltage positioning and series PC board resistance to ensure stability. When only using ceramic output capacitors, output overshoot (V
SOAR
) typically deter­mines the minimum output capacitance requirement. Their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load con­ditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. The efficiency penalty for operating at 550kHz is about 5% when compared to the 300kHz circuit, primarily due to the high-side MOSFET switching losses.
Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased out­put ripple. However, it can indicate the possible pres­ence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits.
The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over­shoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (I
RMS
) imposed by the switching currents. The multiphase quick-PWM controllers operate out-of­phase, while the quick-PWM slave controllers provide selectable out-of-phase or in-phase on-time triggering. Out-of-phase operation reduces the RMS input current by dividing the input current between several stag­gered stages. For duty cycles less than 100%/η
OUTPH
per phase, the I
RMS
requirements can be determined
by the following equation:
where η
OUTPH
is the total number of out-of-phase switch­ing regulators. The worst-case RMS current requirement occurs when operating with VIN= 2η
OUTPHVOUT
. At this
point, the above equation simplifies to I
RMS
= 0.5 x
I
LOAD/ηOUTPH
.
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON™) are preferred due to their resis­tance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than 10°C temperature rise at the RMS input current for optimal cir­cuit longevity.
I
I
V
VV V
RMS
LOAD
OUTPH IN
OUTPH OUT IN OUTPH OUT
=
 
 
η
ηη()
RR AR R
EFF ESR VPS SENSE PCB
=+ +
f
RC
ESR
EFF OUT
=
1
2π
f
f
ESR
SW
π
OS-CON is a trademark of Sanyo.
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
34 ______________________________________________________________________________________
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-cur­rent applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V
IN(MIN)
and V
IN(MAX)
. Calculate both of these sums.
Ideally, the losses at V
IN(MIN)
should be roughly equal to
losses at V
IN(MAX)
, with lower losses in between. If the
losses at V
IN(MIN)
are significantly higher than the losses
at V
IN(MAX)
, consider increasing the size of NH(reducing
R
DS(ON)
but with higher C
GATE
). Conversely, if the losses
at V
IN(MAX)
are significantly higher than the losses at
V
IN(MIN)
, consider reducing the size of NH(increasing
R
DS(ON)
to lower C
GATE
). If VINdoes not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible on-resistance (R
DS(ON)
), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Ensure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur (see the MOSFET Gate Driver section).
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worst­case power dissipation due to resistance occurs at the minimum input voltage:
where η
TOTAL
is the total number of phases.
Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the R
DS(ON)
required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (R
DS(ON)
) losses. High­side switching losses do not usually become an issue until the input is greater than approximately 15V.
Calculating the power dissipation in high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout
characteristics. The following switching-loss calculation provides only a very rough estimate and is no substi­tute for breadboard evaluation, preferably including verification using a thermocouple mounted on N
H
:
where C
RSS
is the reverse transfer capacitance of N
H
and I
GATE
is the peak gate-drive source/sink current
(1A typ).
Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied due to the squared term in the C x V
IN
2
x fSWswitching-loss equation. If the high-side
MOSFET chosen for adequate R
DS(ON)
at low battery voltages becomes extraordinarily hot when biased from V
IN(MAX)
, consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage:
The worst-case for MOSFET power dissipation occurs under heavy overloads that are greater than I
LOAD(MAX)
but are not quite high enough to exceed the current limit and cause the fault latch to trip. To pro­tect against this possibility, you can “overdesign” the circuit to tolerate:
where I
VALLEY(MAX)
is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good-size heatsink to handle the overload power dissipation.
Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. As a gen­eral rule, select a diode with a DC current rating equal to 1/3 of the load current-per-phase. This diode is optional and can be removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (C
BST
) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic capacitors work well for low-power applications driving
II
I
I
I LIR
LOAD
TOTAL
VALLEY MAX
INDUCTOR
TOTAL
VALLEY MAX
LOAD MAX
=+
 
 
=+
 
 
η
η
()
()
()
2
2
PD N RESISTIVE
V
V
I
R
L
OUT
IN MAX
LOAD
TOTAL
DS ON
()
()
()
=−
 
 
1
2
η
PD N SWITCHING V
CfII
HINMAX
RSS SW
GATE
LOAD
TOTAL
()()
()
=
 
 
2
η
PD N RESISTIVE
V
V
I
R
H
OUT
IN
LOAD
TOTAL
DS ON
()
()
=
 
 
η
2
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 35
medium-sized MOSFETs. However, high-current appli­cations driving large, high-side, MOSFETs require boost capacitors larger than 0.1µF. For these applica­tions, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the high-side MOSFET’s gates:
where N is the number of high-side MOSFETs used for one regulator, and Q
GATE
is the gate charge specified in the MOSFET’s data sheet. For example, assume two IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS= 5V). Using the above equation, the required boost capacitance would be:
Selecting the closest standard value, this example requires a 0.22µF ceramic capacitor.
Current-Balance Compensation (CCI)
The current-balance compensation capacitor (C
CCI
) inte­grates the difference between the main and secondary current-sense voltages. The internal compensation resis­tor (R
CCI
= 20k) improves transient response by
increasing the phase margin. This allows the dynamics of the current-balance loop to be optimized. Excessively large capacitor values increase the integration time con­stant, resulting in larger current differences between the phases during transients. Excessively small capacitor val­ues allow the current loop to respond cycle-by-cycle but can result in small DC current variations between the phases. Likewise, excessively large resistor values can also cause DC current variations between the phases. Small resistor values reduce the phase margin, resulting in marginal stability in the current-balance loop. For most applications, a 470pF capacitor from CCI to the switching regulator’s output works well.
Connecting the compensation network to the output (V
OUT
) allows the controller to feed-forward the output voltage signal, especially during transients. To reduce noise pickup in applications that have a widely distrib­uted layout, it is sometimes helpful to connect the com­pensation network to the quiet analog ground rather than V
OUT
.
Setting Voltage Positioning
Voltage positioning dynamically lowers the output volt­age in response to the load current, reducing the processor’s power dissipation. When the output is loaded, an operational amplifier (Figure 5) increases the signal fed back to the quick-PWM controller’s feed­back input. The adjustable amplification allows the use of standard, current-sense resistor values, and signifi­cantly reduces the power dissipated since smaller cur­rent-sense resistors can be used. The load transient response of this control loop is extremely fast, yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guidelines.
The voltage-positioned circuit determines the load current from the voltage across the current-sense resistors (R
SENSE
= RCM= RCS) connected between the inductors and output capacitors, as shown in Figure 10. The voltage drop can be determined by the following equation:
where η
SUM
is the number of phases summed together
for voltage-positioning feedback, and η
TOTAL
is the total number of active phases. When the slave controller is disabled, the current-sense summation maintains the proper voltage-positioned slope. Select the positive input summing resistors so R
FBS
= RFand RA= RB.
Minimum Input Voltage Requirements
and Dropout Performance
The nonadjustable minimum off-time one-shot and the number of phases restrict the output voltage adjustable range for continuous-conduction operation. For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K factor. This error is greater at higher fre­quencies (Table 6). Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the V
SAG
equation in the
Design Procedure section).
The absolute point of dropout is when the inductor cur­rent ramps down during the minimum off-time (∆I
DOWN
)
as much as it ramps up during the on-time (∆IUP). The ratio h = ∆I
UP
/I
DOWN
is an indicator of the ability to
VAIR
A
R
R
VPS VPS LOAD SENSE
VPS
SUM
F
TOTAL
B
=
=
η
η
C
xnC
mV
F
BST
==
224
200
024. µ
C
NxQ
mV
BST
GATE
=
200
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
36 ______________________________________________________________________________________
slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V
SAG
greatly increases
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting this up or down allows tradeoffs between V
SAG
, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as:
where η
OUTPH
is the total number of out-of-phase switch-
ing regulators, V
VPS
is the voltage-positioning droop,
V
DROP1
and V
DROP2
are the parasitic voltage drops in the discharge and charge paths (see the On-Time One- Shot (TON) section), t
OFF(MIN)
is from the Electrical Characteristics table, and K is taken from Table 6. The absolute minimum input voltage is calculated with h = 1.
If the calculated V
IN(MIN)
is greater than the required min­imum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable V
SAG
.
If operation near dropout is anticipated, calculate V
SAG
to
be sure of adequate transient response.
Dropout design example:
VFB= 1.4V
K
MIN
= 3µs for fSW= 300kHz
t
OFF(MIN)
= 400ns
V
VPS
= 3mV/A × 30A = 90mV
V
DROP1
= V
DROP2
= 150mV (30A load)
h = 1.5 and η
OUTPH
= 2
Calculating again with h = 1 gives the absolute limit of dropout:
Therefore, V
IN
must be greater than 4.1V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 5V.
Vx
VmV mV
xsx s
mV mV mV V
IN MIN()
.
(. . / .
.
=
+
 
 
++=
2
14 90 150
12 04 10 30
150 150 90 4 07
-
-
-
µµ
Vx
VmV mV
xsx s
mV mV mV V
IN MIN()
.
(. . / .
.
=
+
 
 
++=
2
14 90 150
12 04 15 30
150 150 90 4 96
-
-
-
µµ
V
VV V
hxt
K
VVV
IN MIN
OUTPH
FB VPS DROP
OUTPH
OFF MIN
DROP DROP VPS
()
()
=
+
 
 
   
   
++
η
η--
-
1
21
1
MAIN
PHASE
SECOND
PHASE
PC BOARD TRACE RESISTANCE
ERROR
COMPARATOR
R
F
R
A
R
A
R
B
R
B
OAIN+
OAIN-
FB
PC BOARD TRACE RESISTANCE
CPU SENSE POINT
CMP
CMN
CSP CSN
L1
R
SENSE
R
FBS
L2
R
SENSE
MAX8760
Figure 10. Voltage-Positioning Gain
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
______________________________________________________________________________________ 37
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 11). If possible, mount all the power compo­nents on the top side of the board with their ground ter­minals flush against one another. Follow these guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitter-free operation.
2) Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the quick-PWM controller. This includes the V
CC
bypass capacitor, REF and GNDS bypass capaci­tors, compensation (CC_) components, and the resistive dividers connected to ILIM and OFS.
3) Each slave controller should also have a separate analog ground. Return the appropriate noise-sen­sitive slave components to this plane. Since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in the master to the analog ground in the slave to prevent ground offsets. A low-value (10) resistor is sufficient to link the two grounds.
4) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be ap­proached in terms of fractions of centimeters, where a single mof excess trace resistance causes a measurable efficiency penalty.
5) Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents.
6) C_P, C_N, OAIN+, and OAIN- connections for cur­rent limiting and voltage positioning must be made using Kelvin-sense connections to guarantee the current-sense accuracy.
7) When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the
inductor and the low-side MOSFET or between the inductor and the output filter capacitor.
8) Route high-speed switching nodes away from sensitive analog areas (REF, CCV, CCI, FB, C_P, C_N, etc). Make all pin-strap control input connec­tions (SHDN, ILIM, SKIP, SUS, S_, TON) to analog ground or VCCrather than power ground or VDD.
Layout Procedure
Place the power components first, with ground termi­nals adjacent (low-side MOSFET source, CIN, C
OUT
, and D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas.
1) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC).
2) Group the gate-drive components (BST diodes
and capacitors, VDDbypass capacitor) together near the controller IC.
3) Make the DC-to-DC controller ground connections
as shown in the Standard Application Circuits. This diagram can be viewed as having four sepa­rate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin and VDDbypass capacitor go; the master’s analog ground plane, where sensitive analog components, the master’s GND pin, and VCCbypass capacitor go; and the slave’s analog ground plane, where the slave’s GND pin and VCCbypass capacitor go. The mas­ter’s GND plane must meet the PGND plane only at a single point directly beneath the IC. Similarly, the slave’s GND plane must meet the PGND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the high-power output ground with a short metal trace from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal.
4) Connect the output power planes (V
CORE
and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-to-DC converter circuit as close to the CPU as is practical.
Chip Information
TRANSISTOR COUNT: 11,015
PROCESS: BiCMOS
MAX8760
Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies
38 ______________________________________________________________________________________
MAIN PHASE
INDUCTOR
POWER
GROUND
OUTPUT
SECONDARY PHASE
INPUT
CPU
KELVIN SENSE VIAS UNDER
THE SENSE RESISTOR
(REFER TO EVALUATION KIT)
C
OUT
CINCINC
IN
CINCINC
IN
C
OUTCOUTCOUTCOUTCOUT
INDUCTOR
R
SENSE
R
SENSE
VIAS TO POWER
GROUND
CONNECT THE
EXPOSED PAD TO
ANALOG GND
CONNECT GND
AND PGND TO THE
CONTROLLER AT ONE POINT
ONLY AS SHOWN
PLACE CONTROLLER ON
BACK SIDE WHEN POSSIBLE,
USING THE GROUND PLANE
TO SHIELD THE IC FROM EMI
POWER GROUND
(2ND LAYER)
ANALOG GROUND
(2ND LAYER)
VIA TO ANALOG
GROUND
Figure 11. PC Board Layout Example
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 39
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages
.)
QFN THIN 6x6x0.8.EPS
e e
LL
A1 A2
A
E/2
E
D/2
D
E2/2
E2
(NE-1) X e
(ND-1) X e
e
D2/2
D2
b
k
k
L
C
L
C
L
C L
C
L
E
1
2
21-0141
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
L1
L
e
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
3. N IS THE TOTAL NUMBER OF TERMINALS.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
NOTES:
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
E
2
2
21-0141
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
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